TWI564945B - Cleaning method of semiconductor manufacturing process - Google Patents
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本發明是有關於一種清潔方法，且特別是有關於一種避免接觸透孔內壁呈現凹凸不平之現象的清潔方法。 The present invention relates to a cleaning method, and more particularly to a cleaning method for avoiding the phenomenon that the inner wall of the through-hole is uneven.
在積體電路的製作過程中，常因製程需要而進行元件表面之清潔。在常見的乾式清洗技術(dry clean)中，例如物理性離子轟擊(physical bombardment)，多使用氬氣游離成之氬離子來去除半導體元件表面之氧化物。但隨著半導體元件和其上透孔的尺寸逐漸縮小，使用物理性離子轟擊，會造成副產物再次沉積在透孔內使得透孔變小，以及若透孔底部為矽，則有因離子轟擊造成透孔底部不平整有漏電和電阻值升高等問題。 In the fabrication process of the integrated circuit, the surface of the component is often cleaned due to the needs of the process. In a typical dry clean technique, such as physical bombardment, argon ions freed from argon are used to remove oxides on the surface of the semiconductor device. However, as the size of the semiconductor element and the through-hole thereof is gradually reduced, the use of physical ion bombardment causes the by-product to be deposited again in the through-hole to make the through-hole smaller, and if the bottom of the through-hole is 矽, there is ion bombardment. The bottom of the through hole is uneven, and there are problems such as leakage and increase in resistance.
有鑑於此，本發明的目的就是提供一種半導體製程中的清潔方法，其可避免接觸透孔內壁呈現凹凸不平之現象。本發明提出一種半導體製程中的清潔方法，應用於半導體基板，半導體基板中具有複數種材料層，該等材料層中有一開口，而該開口暴露出一側壁，該側壁至少包含第一材料層與第二材料層，清潔方法包含下列步驟，進行第一清潔步驟，直到那些材料層損失程度相等時停止，清除第一清潔步驟於側壁上所產生之副產物。 In view of the above, an object of the present invention is to provide a cleaning method in a semiconductor process which can avoid the phenomenon that the inner wall of the contact through-hole is uneven. The invention provides a cleaning method in a semiconductor process, which is applied to a semiconductor substrate having a plurality of material layers, wherein the material layers have an opening therein, and the opening exposes a sidewall, the sidewall comprising at least a first material layer and The second material layer, the cleaning method comprises the steps of performing the first cleaning step until the loss of the material layers is equal, and removing the by-products generated on the sidewalls in the first cleaning step.
在本發明之一實施例中，上述側壁為接觸透孔之側壁，第一材料層與第二材料層分別為氧化矽層與氮化矽層。 In an embodiment of the invention, the sidewall is a sidewall of the contact via, and the first material layer and the second material layer are respectively a ruthenium oxide layer and a tantalum nitride layer.
在本發明之一實施例中，上述清潔方法更包括於清除 副產物後，進行第二清潔步驟，直到該等材料層損失程度相等時停止。 In an embodiment of the invention, the cleaning method is further included in the cleaning After the by-product, a second cleaning step is performed until the levels of loss of the material layers are equal.
在本發明之一實施例中，上述第一清潔步驟、清除副產物步驟、第二清潔步驟皆係於同一機台中完成。 In an embodiment of the invention, the first cleaning step, the cleaning by-product step, and the second cleaning step are all performed in the same machine.
在本發明之一實施例中，上述第二清潔步驟為化學式清洗法。上述第一清潔步驟為化學式清洗法，用以清洗接觸透孔底部之氧化矽。 In an embodiment of the invention, the second cleaning step is a chemical cleaning method. The first cleaning step is a chemical cleaning method for cleaning the ruthenium oxide contacting the bottom of the through hole.
在本發明之一實施例中，上述清潔方法在進行第一清潔步驟之前更包括進行物理式清潔方法，其包含通入第一反應氣體，以清除部分氧化矽，其中第一反應氣體包含氬氣。 In an embodiment of the present invention, the cleaning method further includes performing a physical cleaning method, including introducing a first reactive gas to remove a portion of the cerium oxide, wherein the first reactive gas comprises argon gas before performing the first cleaning step .
在本發明之一實施例中，上述化學式清洗法可為以氟為基礎的化學式清洗法。 In an embodiment of the invention, the chemical cleaning method may be a fluorine-based chemical cleaning method.
在本發明之一實施例中，上述以氟為基礎的化學式清洗法之第二反應氣體包含有氨氣和三氟化氮，溫度低於50℃，且氨氣和三氟化氮流量分別為5立方公分/分和20立方公分/分，在小於17秒時，對氧化矽層之蝕刻厚度大於對氮化矽層之蝕刻厚度，並於進行17秒後趨近相等。 In an embodiment of the present invention, the second reaction gas of the fluorine-based chemical cleaning method comprises ammonia gas and nitrogen trifluoride, the temperature is lower than 50 ° C, and the ammonia gas and the nitrogen trifluoride flow rate are respectively 5 cubic centimeters per minute and 20 cubic centimeters per minute. At less than 17 seconds, the etched layer of the yttrium oxide layer is thicker than the etched layer of the tantalum nitride layer and approaches approximately equal after 17 seconds.
在本發明之一實施例中，上述副產物係為(NH4)2SiF6，而清除副產物之方法可為對半導體基板進行熱製程。 In one embodiment of the present invention, the by-product is (NH 4 ) 2 SiF 6 , and the method of removing by-products may be a thermal process of the semiconductor substrate.
在本發明之一實施例中，上述熱製程包含下列步驟，提供溫度為180℃之熱源，將半導體基板接近熱源，使副產物到達其昇華溫度而完成清除。 In one embodiment of the invention, the thermal process comprises the steps of providing a heat source having a temperature of 180 ° C, bringing the semiconductor substrate close to the heat source, and causing the byproduct to reach its sublimation temperature to complete the removal.
在本發明之一實施例中，於進行該第一清潔步驟之前 更包括進行加熱除氣步驟。 In an embodiment of the invention, prior to performing the first cleaning step It also includes a heating and degassing step.
本發明之清潔方法包含至少一個清潔步驟，每個清潔步驟，都以側壁各材料層損失程度相等時間當做終止點。如此可避免至少包含第一材料層與第二材料層的側壁，因被蝕刻厚度的不同而呈現凹凸不平整之問題。 The cleaning method of the present invention comprises at least one cleaning step, each cleaning step being treated as a termination point with the same degree of loss of the material layers of the side walls. In this way, it is possible to avoid the problem that at least the sidewalls of the first material layer and the second material layer are included, and the unevenness of the etching is caused by the thickness of the etching.
在本發明之一實施例中，上述半導體製程中的清潔方法，更包含進行複數個清潔步驟，各清潔步驟直到各材料層損失程度相等時停止，清除複數個清潔步驟於側壁上所產生之副產物。 In an embodiment of the present invention, the cleaning method in the semiconductor process further includes performing a plurality of cleaning steps, each cleaning step is stopped until the loss of each material layer is equal, and the plurality of cleaning steps are eliminated on the sidewall. product.
本發明再提出一種半導體製程中的清潔方法，應用於具有透孔之半導體基板，其包含先進行物理式清潔方法，移除透孔底部於半導體製程中產生之部分氧化物，進行化學式清潔方法，直到移除透孔中之剩餘氧化物時停止。 The invention further provides a cleaning method in a semiconductor process, which is applied to a semiconductor substrate having a through hole, which comprises a physical cleaning method, which removes a part of oxides generated in the bottom of the through hole in the semiconductor process, and performs a chemical cleaning method. Stop until the remaining oxide in the through hole is removed.
在本發明之一實施例中，上述物理式清潔方法，其包含先通入第一反應氣體，清除部分氧化物，其中第一反應氣體包含氬氣。 In an embodiment of the invention, the physical cleaning method comprises first introducing a first reactive gas to remove a portion of the oxide, wherein the first reactive gas comprises argon.
在本發明之一實施例中，上述透孔具有側壁，側壁至少包含第一材料層與第二材料層，第一材料層與第二材料層分別為氧化矽層與氮化矽層。 In an embodiment of the invention, the through hole has a sidewall, and the sidewall includes at least a first material layer and a second material layer, and the first material layer and the second material layer are respectively a ruthenium oxide layer and a tantalum nitride layer.
在本發明之一實施例中，上述化學式清潔方法，其包含先進行第一清潔步驟，直到第一材料層與第二材料層損失程度相等時停止，以及清除第一清潔步驟於側壁上所產生之副產物。 In an embodiment of the present invention, the chemical cleaning method includes performing a first cleaning step until the first material layer and the second material layer are equal in degree of loss, and removing the first cleaning step on the sidewall. By-product.
在本發明之一實施例中，上述化學式清潔方法，其包含進行複數個清潔步驟，各清潔步驟直到各材料層損失程 度相等時停止，以及清除複數個清潔步驟於側壁上所產生之副產物。 In an embodiment of the invention, the above chemical cleaning method comprises performing a plurality of cleaning steps, each cleaning step until each material layer loss process Stop when the degrees are equal, and remove by-products generated on the sidewalls by a plurality of cleaning steps.
在本發明之一實施例中，上述化學式清洗法可為以氟為基礎的化學式清洗法。 In an embodiment of the invention, the chemical cleaning method may be a fluorine-based chemical cleaning method.
在本發明之一實施例中，上述以氟為基礎的化學式清洗法之第二反應氣體包含氨氣和三氟化氮，溫度低於50℃，且氨氣和三氟化氮流量分別為5立方公分/分和100立方公分/分，在小於17秒時，對氧化矽層之蝕刻厚度大於對氮化矽層之蝕刻厚度，並於進行17秒後趨近相等。 In an embodiment of the present invention, the second reaction gas of the fluorine-based chemical cleaning method comprises ammonia gas and nitrogen trifluoride, the temperature is lower than 50 ° C, and the flow rates of ammonia gas and nitrogen trifluoride are respectively 5 Cubic centimeters per minute and 100 cubic centimeters per minute, at less than 17 seconds, the etched thickness of the yttria layer is greater than the etched thickness of the tantalum nitride layer and approaches approximately equal after 17 seconds.
在本發明之一實施例中，上述副產物可為(NH4)2SiF6，而清除副產物之方法可為對半導體基板進行熱製程。 In one embodiment of the present invention, the by-product may be (NH 4 ) 2 SiF 6 , and the method of removing by-products may be a thermal process of the semiconductor substrate.
在本發明之一實施例中，上述熱製程包含下列步驟，先提供溫度為180℃之熱源，將半導體基板接近熱源，使副產物到達其昇華溫度而完成清除。 In an embodiment of the invention, the thermal process comprises the steps of first providing a heat source having a temperature of 180 ° C, bringing the semiconductor substrate close to the heat source, and causing the by-product to reach its sublimation temperature to complete the removal.
在本發明之一實施例中，上述半導體製程中的清潔方法，在進行第一清潔方法之前更包括進行加熱除氣步驟。 In an embodiment of the invention, the cleaning method in the semiconductor process further includes performing a heating and degassing step before performing the first cleaning method.
為讓本發明之上述和其他目的、特徵和優點能更明顯易懂，下文特舉較佳實施例，並配合所附圖式，作詳細說明如下。 The above and other objects, features and advantages of the present invention will become more <RTIgt;
為能改善副產物沉積在透孔內和電阻值升高的問題，申請人便採用以氟為基礎的化學清洗來取代以氬離子進行轟擊的物理性清洗，如此便可有效改善副產物沉積在透孔內和以及若透孔底部因氬離子轟擊而凹凸不平，造成 電阻值升高的問題。然而，使用化學清洗會因等向性蝕刻使透孔擴大，因此本發明提出一種半導體製程中的清潔方法，可應用於半導體基板，降低透孔電阻值和減輕擴孔現象。本發明之方法的應用範圍很廣，例如可應用在多晶矽閘極之電晶體製程或是金屬閘極之電晶體製程。以下為方便闡述，本實施例皆以半導體元件中常見的多晶矽閘極金氧半電晶體為例進行說明。圖1為本發明方法可運用其上之金氧半電晶體的剖面示意圖。金氧半電晶體100主要具有通道區域110、源/汲極結構101、閘極結構102、金屬矽化物層106、間隙壁結構105、接觸蝕刻中止層103(Contact Etch Stop Layer，簡稱CESL)以及內層介電層104(Inter layer dielectric，簡稱ILD)等結構，內層介電層104通常是一複合材料層，其可包含低介電常數材料或硼磷玻璃(BPSG)、未摻雜矽玻璃(USG)或四乙基正矽酸鹽之氧化矽(TEOS oxide)或氮碳化矽(SiCN)或碳化矽(SiC)或上述的任意組合。為能和外部電路完成電性連接，可形成接觸透孔107從金氧半電晶體100表面穿過內層介電層104以及接觸蝕刻中止層103連通到源/汲極101表面之金屬矽化物層106，並於接觸透孔107內形成導體和外界電路完成電性連接。 In order to improve the deposition of by-products in the through-holes and the increase in resistance, the applicant used a fluorine-based chemical cleaning instead of physical cleaning with argon ions for bombardment, thus effectively improving by-product deposition. Inside and outside the through hole, and if the bottom of the through hole is bumped by argon ion bombardment, resulting in unevenness The problem of increased resistance. However, the use of chemical cleaning causes the through holes to be enlarged by the isotropic etching. Therefore, the present invention proposes a cleaning method in a semiconductor process which can be applied to a semiconductor substrate to reduce the through-hole resistance value and reduce the hole expansion phenomenon. The method of the present invention has a wide range of applications, such as a transistor process for a polysilicon gate or a transistor process for a metal gate. Hereinafter, for convenience of explanation, the present embodiment is described by taking a polycrystalline germanium gate MOS transistor which is common in semiconductor devices as an example. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a schematic cross-sectional view of a gold oxide semi-electrode on which the method of the present invention can be applied. The MOS transistor 100 mainly has a channel region 110, a source/drain structure 101, a gate structure 102, a metal telluride layer 106, a spacer structure 105, and a contact Etch Stop Layer (CESL). The inner dielectric layer 104 is usually a composite material layer, which may comprise a low dielectric constant material or a borophosphosilicate glass (BPSG), which is not doped. Glass (USG) or TEOS oxide of tetraethyl orthosilicate or lanthanum carbide (SiCN) or lanthanum carbide (SiC) or any combination of the above. In order to be electrically connected to the external circuit, the contact via 107 may be formed from the surface of the MOS transistor 100 through the inner dielectric layer 104 and the metal mash of the contact etch stop layer 103 to the source/drain 101 surface. The layer 106 is formed in the contact through hole 107 to form a conductor and the external circuit to complete the electrical connection.
但於蝕刻形成接觸透孔107後，接觸透孔107底部的金屬矽化物層106表面容易堆積副產物而影響導電性。在本實施例中，可將蝕刻後形成之接觸透孔107先進行加熱除氣處理，以清除蝕刻製程所殘留的蝕刻液和高分子化合物等，接著進行物理性清潔方法，清除半導體製程中所產生之氧化物等副產物，氧化物可能為氧化矽等。物理性清 潔方法可以是以氬離子進行轟擊的物理性清洗，其包含通入第一反應氣體，第一反應氣體可為氬氣，而此物理性清洗只移除部分氧化矽後就停止，因此氬離子並無直接轟擊接觸透孔107底部的矽，亦不會造成接觸透孔107底部不平整，避免將來完成之金屬接觸結構因表面不平而導致漏電和電阻值升高的問題。 However, after etching forms the contact via 107, the surface of the metal telluride layer 106 contacting the bottom of the via 107 is likely to accumulate by-products and affect conductivity. In this embodiment, the contact via 107 formed after the etching may be subjected to a heating degassing treatment to remove the etching liquid and the polymer compound remaining in the etching process, and then a physical cleaning method is performed to remove the semiconductor process. A by-product such as an oxide which is produced, and the oxide may be ruthenium oxide or the like. Physical clear The cleaning method may be a physical cleaning by bombardment with argon ions, which comprises introducing a first reaction gas, and the first reaction gas may be argon gas, and the physical cleaning stops only after removing part of the cerium oxide, so the argon ion There is no direct impact on the bottom of the through-hole 107, nor does it cause the bottom of the contact through-hole 107 to be uneven, which avoids the problem of leakage and increased resistance due to uneven surface of the metal contact structure completed in the future.
然後，再進行化學式清潔方法，直到移除側壁上和接觸透孔107底部之剩餘氧化矽。化學式清洗方法可為以氟為基礎的化學式清洗法，於溫度低於50℃，通入之第二反應氣體可包含有氨氣和三氟化氮，並再清除第二反應氣體和氧化物作用後產生之副產物，例如是(NH4)2SiF6。當然，本發明在此不做任何限定，化學式清潔方法可為任何移除剩餘氧化物之方法。 Then, a chemical cleaning method is performed until the remaining yttrium oxide on the sidewall and the bottom of the contact via 107 is removed. The chemical cleaning method may be a fluorine-based chemical cleaning method, and the second reaction gas introduced at a temperature lower than 50 ° C may contain ammonia gas and nitrogen trifluoride, and then remove the second reaction gas and oxide. A by-product produced later is, for example, (NH 4 ) 2 SiF 6 . Of course, the invention is not limited herein, and the chemical cleaning method can be any method of removing residual oxide.
另一方面，請參照圖1，由於接觸透孔107貫穿內層介電層104以及接觸蝕刻中止層103等複數個材料層，內層介電層104通常為氧化矽，而接觸蝕刻中止層103可為氮化矽。在使用上述以氟為基礎的化學式清洗法，卻又存在側壁因複數種材料的蝕刻選擇率不同，而呈現接觸透孔107側壁凹凸不平整之問題。為了清潔在形成接觸透孔107製程中，接觸透孔107底部產生的氧化矽，且避免接觸透孔107側壁108因為第一材料層104與第二材料層103，於蝕刻時因蝕刻選擇率的不同而呈現凹凸不平整情形，造成接觸透孔107內填入材料時之困難度，因此，本發明提出一種清潔方法，可改善上述問題。首先，可將蝕刻後形成之接觸透孔107進行加熱除氣處理，以清除蝕刻製程所殘留 的蝕刻液等。但由於稍後移除副產物時也需進行退火製程，故此處除氣處理僅為一選擇性步驟，也可合併至後面之熱製程中一起完成。 On the other hand, referring to FIG. 1, since the contact via 107 penetrates the inner dielectric layer 104 and the plurality of material layers such as the contact etch stop layer 103, the inner dielectric layer 104 is usually yttrium oxide, and the contact etch stop layer 103 is contacted. It can be tantalum nitride. In the above-mentioned fluorine-based chemical cleaning method, there is a problem in that the sidewall has different etching selectivity of the plurality of materials, and the unevenness of the sidewall of the contact via 107 is uneven. In order to clean the yttrium oxide generated at the bottom of the contact via 107 during the process of forming the contact via 107, and avoiding contacting the sidewall 108 of the via 107 due to the first material layer 104 and the second material layer 103, the etching selectivity is selected during etching. The unevenness is uneven, which causes difficulty in filling the material into the through-hole 107. Therefore, the present invention proposes a cleaning method which can solve the above problems. First, the contact through hole 107 formed after the etching can be heated and degassed to remove the residue of the etching process. Etching solution, etc. However, since the annealing process is also required when the by-product is removed later, the degassing treatment here is only an optional step, and may be incorporated into the subsequent thermal process.
接著，對接觸透孔107進行第一清潔步驟，清除其底部表面上之氧化矽，直到第一材料層104與第二材料層103損失程度相等時停止。在本實施例中，為達成第一清潔步驟，可將金氧半電晶體100送入反應機台，反應機台可使用美商應用材料(Applied Materials)所推出之“Siconi Preclean chamber”設備，其和氬電漿離子轟擊不同，本案進行一種以氟為基礎的化學清洗，而且金氧半電晶體100進行清洗後，於本案之反應機台中一直處於高真空環境下，可避免接觸透孔107表面再度被氧化。為清除接觸透孔107底部表面上之氧化矽，於本案之反應機台通入第二反應氣體，其包含氨氣和三氟化氮，藉由氨氣和三氟化氮之蝕刻，可清除接觸透孔107底部的氧化矽，圖2為本發明之一實施例中蝕刻第一材料層與第二材料層之厚度和蝕刻時間之對應關係圖，由圖2可知，一開始，當第一清潔步驟溫度低於50度，且氨氣和三氟化氮流量比為5立方公分/分(sccm)：100立方公分/分(sccm)時，氨氣和三氟化氮對內層介電層104(氧化矽層)之蝕刻厚度大於對接觸蝕刻中止層103(氮化矽層)之蝕刻厚度，但於進行17秒後，第二反應氣體對上述兩者的蝕刻厚度逐漸趨近相等，此時停止第一清潔步驟。第一清潔步驟其反應式如下：NF 3 +NH 3 → NH 4 F+NH 4 F ． HF Next, the contact via 107 is subjected to a first cleaning step to remove yttrium oxide on the bottom surface thereof until the first material layer 104 and the second material layer 103 are equal in degree of loss. In this embodiment, in order to achieve the first cleaning step, the MOS transistor 100 can be sent to the reaction machine, and the reaction machine can use the "Siconi Preclean chamber" device introduced by Applied Materials. Different from the argon plasma ion bombardment, the present invention performs a fluorine-based chemical cleaning, and after the gold-oxygen semi-crystal 100 is cleaned, it is always in a high vacuum environment in the reaction machine of the present case, and the contact through-hole 107 can be avoided. The surface is again oxidized. In order to remove the cerium oxide on the bottom surface of the contact through-hole 107, a second reaction gas containing ammonia gas and nitrogen trifluoride is removed from the reaction machine of the present invention, and can be removed by etching with ammonia gas and nitrogen trifluoride. FIG. 2 is a diagram showing the relationship between the thickness of the first material layer and the second material layer and the etching time in an embodiment of the present invention. FIG. 2 shows that, at first, when the first The cleaning step temperature is lower than 50 degrees, and the ammonia gas to nitrogen trifluoride flow rate ratio is 5 cubic centimes per minute (sccm): 100 cubic centimeters per minute (sccm), ammonia gas and nitrogen trifluoride to the inner layer dielectric The etching thickness of the layer 104 (yttria layer) is greater than the etching thickness of the contact etching stop layer 103 (tantalum nitride layer), but after 17 seconds, the etching thickness of the second reactive gas gradually approaches the same. The first cleaning step is stopped at this time. The first cleaning step has the following reaction formula: NF 3 +NH 3 → NH 4 F+NH 4 F . HF
NHNH 44 F+NHF+NH 44 FF ．. HF+SiOHF+SiO 22 → (NH → (NH 44 )) 22 SiFSiF 6(S)6(S) +H+H 22 OO
當第一清潔步驟於接觸透孔107中產生副產物(NH4) 2 SiF 6 後，可繼續進行熱製程清除副產物。提供溫度為180℃之熱源，將金氧半電晶體100接近熱源，使接觸透孔107中之副產物到達其昇華溫度(約為1200)而被昇華以完成清除。清除副產物其反應式如下：(NH4) 2 SiF 6(S) → SiF 4(g) +NH 3(g) After the first cleaning step produces by-product (NH4) 2 SiF 6 in the contact through-hole 107, the hot-process removal by-product can be continued. A heat source having a temperature of 180 ° C is provided, and the gold-oxygen semi-crystal 100 is brought close to the heat source, so that the by-product in the contact through-hole 107 reaches its sublimation temperature (about 120 0 ) and is sublimated to complete the removal. The by-products are removed and the reaction formula is as follows: (NH4) 2 SiF 6(S) → SiF 4(g) +NH 3(g)
若尚未達到預定清潔效果(未完全清除接觸透孔107底部之氧化矽)，可繼續對具有複數材料層之接觸透孔107底部進行第二清潔步驟，第二清潔步驟可重覆上述第一清潔步驟，以清除接觸透孔107中之氧化矽，並直到複數種材料層損失程度相等時停止，其中，上述第一清潔步驟、清除副產物、第二清潔步驟皆可於同一機台中完成。 If the predetermined cleaning effect has not been achieved (the cerium oxide at the bottom of the contact through-hole 107 is not completely removed), the second cleaning step may be continued on the bottom of the contact through-hole 107 having a plurality of material layers, and the second cleaning step may repeat the first cleaning The step of removing the cerium oxide in the contact through-hole 107 and stopping until the degree of loss of the plurality of material layers is equal, wherein the first cleaning step, the cleaning by-product, and the second cleaning step can all be completed in the same machine.
值得一提的是，本發明若無法於第一清潔步驟徹底清除接觸透孔107中氧化矽，則可將氧化物的清除分成多個步驟，藉由控制第二反應氣體的流量，以複數種材料層消失程度相等之時間當作各個清潔步驟的停止點，以避免側壁108呈現凹凸不平整狀，並藉此以多步驟達到預定清潔效果。此外，要注意的是，本發明並不限定第一清潔步驟和第二清潔步驟要完全相同，第二清潔步驟也可選用其他反應條件，例如不同的溫度或是不同的第二反應氣體流量比。 It is worth mentioning that if the present invention is unable to completely remove the cerium oxide in the contact through-hole 107 in the first cleaning step, the oxide removal can be divided into a plurality of steps, and the flow rate of the second reaction gas is controlled to be plural. The time at which the disappearance of the material layers is equal is taken as the stopping point of each cleaning step, so that the side wall 108 is prevented from being uneven, and thereby the predetermined cleaning effect is achieved in multiple steps. In addition, it should be noted that the present invention does not limit the first cleaning step and the second cleaning step to be completely the same, and the second cleaning step may also use other reaction conditions, such as different temperatures or different second reactant gas flow ratios. .
另外，圖1中之金屬矽化物層106，除了可於接觸透孔107蝕刻形成前就已完成之外，也可於接觸透孔107完成後再完成。請參閱圖3，接觸透孔307形成於接觸蝕刻中止層103以及內層介電層104中，因此接觸透孔307完成 時之底部便是露出源/汲極301，而源/汲極301表面容易形成氧化物(氧化矽)而影響導電性，導致於其上所形成金屬矽化物，會有表面不平導致漏電和電阻值升高的問題。因此，同樣可於接觸透孔307完成後，馬上再運用上述方法來進行接觸透孔之清洗，然後再完成金屬矽化物，如此便可避免上述表面不平導致漏電和電阻值升高的問題。 In addition, the metal telluride layer 106 in FIG. 1 can be completed before the contact via 107 is formed, or after the contact via 107 is completed. Referring to FIG. 3, a contact via 307 is formed in the contact etch stop layer 103 and the inner dielectric layer 104, so that the contact via 307 is completed. At the bottom of the time, the source/drain 301 is exposed, and the surface of the source/drain 301 is prone to form an oxide (yttria) which affects the conductivity, resulting in a metal halide formed thereon, which may cause surface leakage and leakage and resistance. The problem of rising values. Therefore, after the completion of the contact through-hole 307, the above method can be used to clean the contact through-hole, and then the metal halide can be completed, so that the above-mentioned surface unevenness can be avoided to cause leakage and increase in resistance.
至於金屬閘極電晶體製程中之金屬矽化物也是同樣會有於接觸透孔完成前已完成，或是於接觸透孔完成完成後才完成的不同實施例，但本案方法都可適用，同樣可以解決習用手段之缺失。請參閱圖4，具有閘極結構(例如金屬閘極)402之電晶體400，其接觸透孔407形成於接觸蝕刻中止層403以及內層介電層404中。當接觸透孔407完成後才完成金屬矽化物時，因接觸透孔307完成時之底部便是露出源/汲極401，而源/汲極401表面容易形成氧化物(氧化矽)而影響導電性，導致於其上所形成金屬矽化物，會有表面不平導致漏電和電阻值升高的問題。同樣地，本發明之清潔方法可用於來清洗接觸透孔407以及由接觸透孔407露出的源/汲極401表面。 As for the metal telluride in the metal gate transistor process, the same can be done before the contact through hole is completed, or after the completion of the contact through hole is completed, but the method of the present invention is applicable, and the same can be applied. Solve the lack of customary means. Referring to FIG. 4, a transistor 400 having a gate structure (eg, a metal gate) 402 having a contact via 407 formed in the contact etch stop layer 403 and the inner dielectric layer 404. When the metal germanide is completed after the contact through hole 407 is completed, the bottom of the contact through hole 307 is exposed to expose the source/drain 401, and the surface of the source/drain 401 is likely to form an oxide (yttria) which affects the conduction. Sexuality, resulting in the formation of metal bismuth on it, there will be problems of surface leakage leading to leakage and increased resistance. Likewise, the cleaning method of the present invention can be used to clean the contact via 407 and the surface of the source/drain 401 exposed by the contact via 407.
綜上所述，本發明以物理式清潔方法(氬離子進行轟擊)清除部分氧化物，再搭配化學式清潔方法(以氟為基礎的化學清洗)清除剩餘氧化物，可同時改善只使用氬離子進行轟擊清洗透孔造成之電阻值升高，和只使用以氟為基礎的化學清洗時之擴孔現象。而以氟為基礎的化學清洗方法包含至少一個清潔步驟，在每個清除氧化物的清潔步驟，都以側壁各材料層損失程度相等時間當做終止點。如 此可避免至少包含第一材料層與第二材料層的側壁，因蝕刻選擇率不同造成對第一材料層與第二材料層蝕刻厚度的不同而呈現之凹凸不平整，亦可以分段、多步驟達成清除氧化物之目的。 In summary, the present invention removes some oxides by a physical cleaning method (argon ion bombardment), and then uses a chemical cleaning method (fluorine-based chemical cleaning) to remove residual oxides, and simultaneously improves the use of only argon ions. The increase in resistance caused by bombardment of the through-holes and the reaming of the fluorine-based chemical cleaning. The fluorine-based chemical cleaning method includes at least one cleaning step, and in each cleaning step of removing the oxide, the end point of each material layer loss is equal as the termination point. Such as This can avoid at least the sidewalls of the first material layer and the second material layer, and the unevenness of the etching thickness of the first material layer and the second material layer caused by the different etching selectivity is uneven, and can also be segmented and multi-layered. The steps achieve the purpose of removing oxides.
雖然本發明已以較佳實施例揭露如上，然其並非用以限定本發明，任何熟習此技藝者，在不脫離本發明之精神和範圍內，當可作些許之更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。 While the present invention has been described in its preferred embodiments, the present invention is not intended to limit the invention, and the present invention may be modified and modified without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application.
100、400‧‧‧金氧半電晶體 100, 400‧‧‧ gold oxide semi-transistor
110‧‧‧通道區域 110‧‧‧Channel area
101、301、401‧‧‧源/汲極結構 101, 301, 401‧‧‧ source/drain structure
102、402‧‧‧閘極結構 102, 402‧‧‧ gate structure
103、303、403‧‧‧接觸蝕刻中止層 103, 303, 403‧‧‧ contact etching stop layer
104、304、404‧‧‧內層介電層 104, 304, 404‧‧‧ inner dielectric layer
105‧‧‧間隙壁結構 105‧‧‧Gap structure
107、307、407‧‧‧接觸透孔 107, 307, 407‧‧‧ contact through hole
108‧‧‧側壁 108‧‧‧ side wall
圖1為本發明之一實施例之金氧半電晶體之剖面示意圖。 1 is a schematic cross-sectional view of a gold oxide semi-electrode according to an embodiment of the present invention.
圖2為本發明之一實施例中蝕刻第一材料層與第二材料層之厚度和蝕刻時間之對應關係圖。 2 is a diagram showing the relationship between the thickness of the first material layer and the second material layer and the etching time in an embodiment of the present invention.
圖3為本發明之另一實施例之金氧半電晶體之剖面示意圖。 3 is a cross-sectional view showing a gold oxide semi-electrode according to another embodiment of the present invention.
圖4為本發明之另一實施例之金氧半電晶體之剖面示意圖。 4 is a cross-sectional view showing a gold oxide semi-electrode according to another embodiment of the present invention.
100‧‧‧金氧半電晶體 100‧‧‧Gold oxygen semi-transistor
110‧‧‧通道區域 110‧‧‧Channel area
101‧‧‧源/汲極結構 101‧‧‧ source/drain structure
102‧‧‧閘極結構 102‧‧‧ gate structure
103‧‧‧接觸蝕刻中止層 103‧‧‧Contact etching stop layer
104‧‧‧內層介電層 104‧‧‧ Inner dielectric layer
105‧‧‧間隙壁結構 105‧‧‧Gap structure
106‧‧‧金屬矽化物層 106‧‧‧metal telluride layer
107‧‧‧接觸透孔 107‧‧‧Contact through hole
108‧‧‧側壁 108‧‧‧ side wall
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| US20080311711A1 (en) * | 2007-06-13 | 2008-12-18 | Roland Hampp | Gapfill for metal contacts |
| US20090191714A1 (en) * | 2008-01-24 | 2009-07-30 | Kuo-Chih Lai | Method of removing oxides |
| US20090298294A1 (en) * | 2008-05-30 | 2009-12-03 | United Microelectronics Corp. | Method for clearing native oxide |
| US20090320749A1 (en) * | 2007-04-17 | 2009-12-31 | Hyungsuk Alexander Yoon | Apparatus for integrated surface treatment and deposition for copper interconnect |
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| US20090320749A1 (en) * | 2007-04-17 | 2009-12-31 | Hyungsuk Alexander Yoon | Apparatus for integrated surface treatment and deposition for copper interconnect |
| US20080311711A1 (en) * | 2007-06-13 | 2008-12-18 | Roland Hampp | Gapfill for metal contacts |
| US20090191714A1 (en) * | 2008-01-24 | 2009-07-30 | Kuo-Chih Lai | Method of removing oxides |
| US20090298294A1 (en) * | 2008-05-30 | 2009-12-03 | United Microelectronics Corp. | Method for clearing native oxide |
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