TWI556359B - Quad flat non-leaded package structure and leadframe thereof - Google Patents
Quad flat non-leaded package structure and leadframe thereof Download PDFInfo
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- TWI556359B TWI556359B TW104110498A TW104110498A TWI556359B TW I556359 B TWI556359 B TW I556359B TW 104110498 A TW104110498 A TW 104110498A TW 104110498 A TW104110498 A TW 104110498A TW I556359 B TWI556359 B TW I556359B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Description
本發明是有關於一種半導體封裝結構，且特別是有關於一種四方扁平無引腳(QFN)封裝結構。 This invention relates to a semiconductor package structure, and more particularly to a quad flat no-lead (QFN) package structure.
半導體封裝技術包含有許多封裝形態，其中四方扁平封裝系列的四方扁平無引腳封裝具有較短的訊號傳遞路徑及相對較快的訊號傳遞速度，因此為封裝型態的主流之一。一般而言，當晶片與導線架進行接合時，例如為焊線接合(wire bonding)或覆晶接合(flip chip bonding)，須於導線架之底部設置一背膠膜(backside tape)，以使導線架可藉由真空吸附的方式固定其位置，以確保焊線接合或覆晶接合過程能夠順利進行，進而提高晶片與導線架接合製程之良率(yield rate)。 Semiconductor packaging technology includes many package types, and the quad flat no-lead package of the quad flat package series has a short signal transmission path and a relatively fast signal transmission speed, and thus is one of the mainstream of the package type. In general, when the wafer is bonded to the lead frame, such as wire bonding or flip chip bonding, a backside tape is disposed at the bottom of the lead frame to enable The lead frame can be fixed in position by vacuum adsorption to ensure smooth bonding of the wire bonding or flip chip bonding process, thereby improving the yield rate of the wafer and lead frame bonding process.
然而，在晶片與導線架接合製程完成之後，通常需將前述的背膠膜移除以利後續製程進行，而背膠膜的移除需要額外的製程，通常會使製造成本與工時增加。此外，在晶片與導線架電 性連接之後移除膠膜可能會造成導線架、焊線、凸塊被拉扯，進而導致晶片與導線架電性連接出現異常之情況，此舉有降低封裝良率的可能。 However, after the wafer and leadframe bonding process is completed, the aforementioned adhesive film is usually removed for subsequent processing, and the removal of the adhesive film requires an additional process, which generally increases manufacturing costs and man-hours. In addition, the wafer and lead frame are electrically Removing the film after the sexual connection may cause the lead frame, the bonding wire and the bump to be pulled, which may cause an abnormal connection between the wafer and the lead frame, which may reduce the package yield.
本發明提供一種四方扁平無引腳封裝結構，其可藉由介電膜的配置達到簡化製程以及提高良率之目的。 The invention provides a quad flat no-lead package structure, which can simplify the process and improve the yield by the configuration of the dielectric film.
本發明提供一種可簡化製程以及提高良率之四方扁平無引腳之導線架結構。 The present invention provides a quad flat no-lead leadframe structure that simplifies the process and improves yield.
本發明提出一種四方扁平無引腳封裝結構，其包括一導線架、一介電膜、一晶片、多條焊線以及一封裝膠體。導線架包括多個引腳。介電膜配置於導線架上。介電膜具有多個開孔，且各開孔分別位於各對應的引腳上方。晶片配置於介電膜上。各焊線分別連接於晶片與對應開孔所暴露出的引腳之間。封裝膠體包覆導線架、介電膜、晶片以及焊線。 The invention provides a quad flat no-lead package structure comprising a lead frame, a dielectric film, a wafer, a plurality of bonding wires and an encapsulant. The leadframe includes multiple pins. The dielectric film is disposed on the lead frame. The dielectric film has a plurality of openings, and each of the openings is located above each corresponding pin. The wafer is disposed on a dielectric film. Each of the bonding wires is connected between the wafer and a pin exposed by the corresponding opening. The package is coated with a lead frame, a dielectric film, a wafer, and a bonding wire.
在本發明的一實施例中，上述的引腳從晶片下方延伸至封裝膠體的邊緣。 In an embodiment of the invention, the pins extend from below the wafer to the edge of the encapsulant.
在本發明的一實施例中，上述的導線架更包括一晶片座，其中晶片座位於晶片下方，且引腳環繞晶片座。 In an embodiment of the invention, the lead frame further includes a wafer holder, wherein the wafer holder is located under the wafer, and the lead surrounds the wafer holder.
在本發明的一實施例中，上述的介電膜的分佈範圍涵蓋引腳之間。 In an embodiment of the invention, the distribution range of the dielectric film described above covers between pins.
在本發明的一實施例中，上述的介電膜的邊緣與封裝膠 體的邊緣切齊。 In an embodiment of the invention, the edge of the dielectric film and the encapsulant are The edges of the body are aligned.
在本發明的一實施例中，上述的各開孔的最大孔徑不超出對應各引腳的外輪廓。 In an embodiment of the invention, the maximum aperture of each of the openings is not beyond the outer contour of the corresponding pin.
在本發明的一實施例中，上述的介電膜位於晶片與導線架之間。 In an embodiment of the invention, the dielectric film is located between the wafer and the lead frame.
本發明提出另一種四方扁平無引腳覆晶封裝結構，其包括一導線架、一介電膜、一晶片以及一封裝膠體。導線架包括多個引腳。介電膜配置於導線架上。介電膜具有多個開孔，且各開孔分別位於對應的引腳上方。晶片配置於介電膜上。晶片具有一主動面，並於主動面上設置有多個導電凸塊。各導電凸塊分別連接於晶片與對應開孔所暴露出的引腳之間。封裝膠體包覆導線架、介電膜、晶片以及導電凸塊。 The present invention provides another quad flat no-lead flip chip package structure comprising a lead frame, a dielectric film, a wafer and an encapsulant. The leadframe includes multiple pins. The dielectric film is disposed on the lead frame. The dielectric film has a plurality of openings, and each of the openings is located above the corresponding pin. The wafer is disposed on a dielectric film. The wafer has an active surface and a plurality of conductive bumps are disposed on the active surface. Each of the conductive bumps is connected between the wafer and a pin exposed by the corresponding opening. The encapsulant encapsulates the leadframe, the dielectric film, the wafer, and the conductive bumps.
在本發明的一實施例中，上述的各開孔之最大孔徑不超出對應各引腳的外輪廓。 In an embodiment of the invention, the maximum aperture of each of the openings is not beyond the outer contour of the corresponding pin.
本發明提出一種四方扁平無引腳之導線架結構，其包括一導線架以及一介電膜。導線架包括多個引腳，且相鄰引腳間具有至少一間距。介電膜設置於引腳上，並全面覆蓋引腳及相鄰引腳間之間距。介電膜具有多個對應引腳之開孔，各開孔的最大孔徑不超出對應各引腳的外輪廓。 The invention provides a quad flat no-lead leadframe structure comprising a lead frame and a dielectric film. The leadframe includes a plurality of pins with at least one spacing between adjacent pins. The dielectric film is placed on the pin and covers the entire distance between the pin and the adjacent pin. The dielectric film has a plurality of openings corresponding to the pins, and the maximum aperture of each of the openings does not exceed the outer contour of the corresponding pins.
基於上述，由於本發明於導線架上配置有介電膜，其以涵蓋導線架的引腳之間的範圍分佈，因此當晶片與導線架進行接合(即進行接合製程)，導線架可藉由真空吸附的方式而固定其位 置，以確保焊線接合或覆晶接合過程能夠順利進行。此外，由於介電膜是位於晶片與導線架之間，故此介電膜於接合製程完成後毋需進一步移除，即可繼續進行後續製程。本發明提供的四方扁平無引腳封裝結構可簡化製程複雜度以及提高良率。 Based on the above, since the present invention is provided with a dielectric film on the lead frame to cover the range distribution between the leads of the lead frame, when the wafer is bonded to the lead frame (ie, the bonding process is performed), the lead frame can be used Fix the position by vacuum adsorption Set to ensure that the wire bonding or flip chip bonding process can proceed smoothly. In addition, since the dielectric film is located between the wafer and the lead frame, the dielectric film can be further removed after the bonding process is completed, and the subsequent process can be continued. The quad flat no-lead package structure provided by the invention simplifies process complexity and improves yield.
為讓本發明的上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。 The above described features and advantages of the invention will be apparent from the following description.
10、20、30、40‧‧‧四方扁平無引腳封裝結構 10, 20, 30, 40‧‧‧ square flat leadless package structure
100、110‧‧‧導線架 100, 110‧‧‧ lead frame
102‧‧‧引腳 102‧‧‧ pin
114‧‧‧晶片座 114‧‧‧ Wafer holder
200‧‧‧介電膜 200‧‧‧ dielectric film
202‧‧‧開孔 202‧‧‧Opening
300、310‧‧‧晶片 300, 310‧‧‧ wafer
302‧‧‧焊墊 302‧‧‧ solder pads
312‧‧‧導電凸塊 312‧‧‧Electrical bumps
400‧‧‧多條焊線 400‧‧‧multiple bonding wires
500‧‧‧封裝膠體 500‧‧‧Package colloid
600‧‧‧黏著層 600‧‧‧Adhesive layer
A‧‧‧主動面 A‧‧‧ active face
G‧‧‧間距 G‧‧‧ spacing
I-I’、II-II’、III-III’，IV-IV’‧‧‧剖線 I-I', II-II', III-III', IV-IV'‧‧‧
L‧‧‧導線架結構 L‧‧‧ lead frame structure
S‧‧‧空間 S‧‧‧ Space
圖1A為本發明之一實施例之四方扁平無引腳封裝結構的上視圖。 1A is a top view of a quad flat no-lead package structure in accordance with an embodiment of the present invention.
圖1B為圖1A之四方扁平無引腳封裝結構沿剖線I-I’的剖面示意圖。 1B is a cross-sectional view of the quad flat no-lead package structure of FIG. 1A taken along line I-I'.
圖2A為本發明之另一實施例之四方扁平無引腳封裝結構的上視圖。 2A is a top view of a quad flat no-lead package structure in accordance with another embodiment of the present invention.
圖2B為圖2A之四方扁平無引腳封裝結構沿剖線II-II’的剖面示意圖。 2B is a cross-sectional view of the quad flat no-lead package structure of FIG. 2A taken along line II-II'.
圖3A為本發明之又一實施例之四方扁平無引腳封裝結構的上視圖。 3A is a top view of a quad flat no-lead package structure in accordance with yet another embodiment of the present invention.
圖3B為圖3A之四方扁平無引腳封裝結構沿剖線III-III’的剖面示意圖。 3B is a cross-sectional view of the quad flat no-lead package structure of FIG. 3A taken along line III-III'.
圖4A為本發明之再一實施例之四方扁平無引腳封裝結構的 上視圖。 4A is a diagram of a quad flat no-lead package structure according to still another embodiment of the present invention; Top view.
圖4B為圖4A之四方扁平無引腳封裝結構沿剖線IV-IV’的剖面示意圖。 4B is a cross-sectional view of the quad flat no-lead package structure of FIG. 4A taken along line IV-IV'.
圖1A為本發明之一實施例之四方扁平無引腳封裝結構的上視圖。圖1B為圖1A之四方扁平無引腳封裝結構沿剖線I-I’的剖面示意圖。請同時參考圖1A與圖1B，在本實施例中，四方扁平無引腳封裝結構10包括一導線架100、一介電膜200、一晶片300、多條焊線400以及一封裝膠體500。為清楚繪示出本發明，封裝膠體500的分佈範圍將以虛線表示，而介電膜200以斜線表示。以下為便於解釋說明，本發明圖式中所繪製之導線架100僅為整條導線架上之其中之一個單元，於實施上，介電膜200為對應整條導線架的大小而形成之薄膜，為全面式覆蓋於整條導線架的各個單元上，且介電膜200所選用之材質可例如為晶片接合膜(die attach film，DAF)或與其類似之材質。 1A is a top view of a quad flat no-lead package structure in accordance with an embodiment of the present invention. 1B is a cross-sectional view of the quad flat no-lead package structure of FIG. 1A taken along line I-I'. Referring to FIG. 1A and FIG. 1B simultaneously, in the embodiment, the quad flat no-lead package structure 10 includes a lead frame 100, a dielectric film 200, a wafer 300, a plurality of bonding wires 400, and an encapsulant 500. To clearly illustrate the invention, the distribution of encapsulation 500 will be indicated by dashed lines and dielectric film 200 will be indicated by diagonal lines. In the following, for convenience of explanation, the lead frame 100 drawn in the drawing of the present invention is only one of the units on the entire lead frame. In practice, the dielectric film 200 is a film formed corresponding to the size of the entire lead frame. The material for the dielectric film 200 may be, for example, a die attach film (DAF) or a material similar thereto.
具體而言，導線架100可具有多個引腳102，導線架100的多個引腳102從晶片300下方延伸至封裝膠體500的邊緣。詳細來說，如圖1A所示，多個引腳102是以環繞晶片300四周的方式分佈，相鄰的引腳102彼此之間至少相隔一間距G，一般來說，間距G之範圍大約在120um左右，且各引腳102是從晶片300的下方延伸至封裝膠體500的邊緣。 In particular, leadframe 100 can have a plurality of pins 102 from which a plurality of leads 102 of leadframe 100 extend from the bottom of wafer 300 to the edge of encapsulant 500. In detail, as shown in FIG. 1A, a plurality of pins 102 are distributed around the periphery of the wafer 300, and adjacent pins 102 are at least spaced apart from each other by a distance G. Generally, the range of the pitch G is approximately Around 120 um, and each pin 102 extends from below the wafer 300 to the edge of the encapsulant 500.
另一方面，介電膜200配置於導線架100上，介電膜200具有多個開孔202，且各開孔202分別位於各對應的引腳102上。在本實施例中，開孔202可藉由對介電膜200進行蝕刻或雷射移除而形成，且開孔202可在介電膜200配置於導線架100上之前或之後形成。介電膜200的分佈範圍涵蓋各引腳102間之區域，且介電膜200的邊緣例如是與封裝膠體500的邊緣切齊，且介電膜200的各開孔202的最大孔徑不超出各對應的引腳102的外輪廓，換言之，介電膜200上的開孔202可與導線架100的引腳102搭配以構成一氣密結構，以使表面貼附有介電膜200的導線架100能夠被真空吸附。詳細而言，該介電膜200開孔202孔徑之最小孔徑範圍為露出焊線400與引腳102接合區域，最大孔徑範圍則為整個引腳102之上表面而不超出引腳102的外輪廓(圖未示)。此處，導線架100與介電膜200可構成一導線架結構L。如圖1B所示，晶片300配置於介電膜200上，以使介電膜200位於晶片300與導線架100之間，而晶片300可具有多個焊墊302，且晶片300與對應開孔202所暴露出的引腳102之間可藉由焊線400電性連接。 On the other hand, the dielectric film 200 is disposed on the lead frame 100. The dielectric film 200 has a plurality of openings 202, and the openings 202 are respectively located on the corresponding pins 102. In the present embodiment, the opening 202 can be formed by etching or laser removing the dielectric film 200, and the opening 202 can be formed before or after the dielectric film 200 is disposed on the lead frame 100. The distribution of the dielectric film 200 covers the area between the pins 102, and the edge of the dielectric film 200 is, for example, aligned with the edge of the encapsulant 500, and the maximum aperture of each opening 202 of the dielectric film 200 does not exceed each other. The outer contour of the corresponding pin 102, in other words, the opening 202 in the dielectric film 200 can be matched with the pin 102 of the lead frame 100 to form a hermetic structure, so that the lead frame 100 with the surface of the dielectric film 200 attached thereto Can be vacuum absorbed. In detail, the minimum aperture range of the aperture of the dielectric film 200 opening 202 is to expose the bonding area of the bonding wire 400 and the pin 102, and the maximum aperture range is the upper surface of the entire pin 102 without exceeding the outer contour of the pin 102. (not shown). Here, the lead frame 100 and the dielectric film 200 may constitute a lead frame structure L. As shown in FIG. 1B, the wafer 300 is disposed on the dielectric film 200 such that the dielectric film 200 is located between the wafer 300 and the lead frame 100, and the wafer 300 may have a plurality of pads 302, and the wafer 300 and the corresponding opening The exposed pins 102 of the 202 can be electrically connected by the bonding wires 400.
在本實施例中，焊線400是於焊線接合製程形成，各焊墊302藉由焊線400而與對應的開孔202所暴露出的引腳102達到電性連接的目的。此處，焊線400的材質例如是金、銅、銀合金或其他合適之導電材料。 In the present embodiment, the bonding wires 400 are formed in a wire bonding process, and the pads 302 are electrically connected to the leads 102 exposed by the corresponding openings 202 by the bonding wires 400. Here, the material of the bonding wire 400 is, for example, gold, copper, silver alloy or other suitable electrically conductive material.
值得注意的是，由於介電膜200與導線架100二者的搭 配可構成一氣密結構，因此在進行晶片300、焊線400與導線架100的接合製程時，導線架100可藉由真空吸附的方式固定其位置，以確保焊線接合過程能夠順利進行。 It is worth noting that due to the dielectric film 200 and the lead frame 100 The arrangement can form an airtight structure. Therefore, when the bonding process of the wafer 300, the bonding wire 400 and the lead frame 100 is performed, the lead frame 100 can be fixed by vacuum suction to ensure that the bonding process can be smoothly performed.
為了保護晶片300與焊線400以及確保四方扁平無引腳封裝結構10的信賴性，封裝膠體500會包覆導線架100、介電膜200、晶片300以及焊線400。如圖1B所示，封裝膠體500可分佈於導線架100的兩側，除了可包覆介電膜200、晶片300以及焊線400之外，更可填充於導線架另一側的空間S內，換言之，封裝膠體500可填入任二相鄰引腳102之間，以包覆所有引腳102。當然，引腳102的末端會暴露於封裝膠體500外，以利於與外部裝置(例如電路板)電性連接。 In order to protect the wafer 300 and the bonding wires 400 and to ensure the reliability of the quad flat no-lead package structure 10, the encapsulant 500 covers the leadframe 100, the dielectric film 200, the wafer 300, and the bonding wires 400. As shown in FIG. 1B, the encapsulant 500 can be distributed on both sides of the lead frame 100. In addition to covering the dielectric film 200, the wafer 300, and the bonding wire 400, the encapsulant 500 can be filled in the space S on the other side of the lead frame. In other words, the encapsulant 500 can be filled between any two adjacent pins 102 to cover all of the pins 102. Of course, the end of the pin 102 is exposed outside the encapsulant 500 to facilitate electrical connection with an external device such as a circuit board.
除上述之外，本實施例更可包括一黏著層600，此黏著層600配置於晶片300與介電膜200之間，用以使晶片300貼合於介電膜200上。 In addition to the above, the embodiment further includes an adhesive layer 600 disposed between the wafer 300 and the dielectric film 200 for bonding the wafer 300 to the dielectric film 200.
當晶片300與導線架100進行接合製程時，由於介電膜200與導線架100共同構成一氣密結構，因此導線架100可藉由真空吸附的方式固定其位置，據此達到導線架100在接合製程過程中不易產生偏移之效果。詳細來說，當進行焊線接合製程時，需提升製程溫度以利各焊線400與對應的各引腳112接合，此時，導線架100的各引腳112由於受到高溫以及接合壓力的影響，因此容易發生變形移位之情況。在本實施例中，介電膜200與導線架100共同構成的氣密結構可使導線架100得以完全的被真空吸 附固定於機台上，介電膜200更可作為輔助導線架100之支撐用途，如此可確保晶片300、焊線400與導線架100的接合製程能夠順利的進行。再者，由於介電膜200是位於晶片300與導線架100之間，介電膜200不會妨礙晶片300與導線架100之間的電性連接，且介電膜200在晶片300與導線架100完成電性連接之後無需被移除，故介電膜200的使用可達到簡化製程以及提高良率之目的。 When the wafer 300 is bonded to the lead frame 100, since the dielectric film 200 and the lead frame 100 together form an airtight structure, the lead frame 100 can be fixed by vacuum suction, thereby achieving the engagement of the lead frame 100. The effect of offset is not easy to occur during the process. In detail, when the wire bonding process is performed, the process temperature needs to be increased to facilitate bonding of the bonding wires 400 to the corresponding pins 112. At this time, the pins 112 of the lead frame 100 are affected by high temperature and bonding pressure. Therefore, it is easy to cause deformation displacement. In the present embodiment, the airtight structure formed by the dielectric film 200 and the lead frame 100 allows the lead frame 100 to be completely vacuumed. Attached to the machine table, the dielectric film 200 can be used as a support for the auxiliary lead frame 100. This ensures that the bonding process of the wafer 300, the bonding wire 400 and the lead frame 100 can be smoothly performed. Moreover, since the dielectric film 200 is located between the wafer 300 and the lead frame 100, the dielectric film 200 does not interfere with the electrical connection between the wafer 300 and the lead frame 100, and the dielectric film 200 is on the wafer 300 and the lead frame. After the 100 electrical connection is completed, it is not necessary to be removed, so the use of the dielectric film 200 can achieve the purpose of simplifying the process and improving the yield.
圖2A為本發明之另一實施例之四方扁平無引腳封裝結構的上視圖。圖2B為圖2A之四方扁平無引腳封裝結構沿剖線II-II’的剖面示意圖。請同時參考圖2A以及圖2B，本實施例的四方扁平無引腳封裝結構20與前一實施例中的四方扁平無引腳封裝結構10相似，二者主要差別之處在於：本實施例的四方扁平無引腳封裝結構20中，除了具有多個引腳112之外，導線架110更包括一晶片座114。 2A is a top view of a quad flat no-lead package structure in accordance with another embodiment of the present invention. 2B is a cross-sectional view of the quad flat no-lead package structure of FIG. 2A taken along line II-II'. Referring to FIG. 2A and FIG. 2B simultaneously, the quad flat no-lead package structure 20 of the present embodiment is similar to the quad flat no-lead package structure 10 of the previous embodiment, and the main difference between the two is: the embodiment In the quad flat no-lead package structure 20, in addition to having a plurality of pins 112, the leadframe 110 further includes a wafer holder 114.
如圖2A與圖2B所示，晶片300對應於導線架110的晶片座114而配置。此處，晶片座114例如具有散熱及/或接地的功能。 As shown in FIGS. 2A and 2B, the wafer 300 is disposed corresponding to the wafer holder 114 of the lead frame 110. Here, the wafer holder 114 has a function of, for example, heat dissipation and/or grounding.
圖3A為本發明之一實施例之四方扁平無引腳封裝結構的上視圖。圖3B為圖3A之四方扁平無引腳封裝結構沿剖線III-III’的剖面示意圖。請同時參考圖3A與圖3B，本實施例的四方扁平無引腳封裝結構30與前一實施例中的四方扁平無引腳封裝結構10相似，兩者主要差別在於：本實施例的四方扁平無引腳封 裝結構30為四方扁平無引腳覆晶封裝結構。 3A is a top plan view of a quad flat no-lead package structure in accordance with an embodiment of the present invention. 3B is a cross-sectional view of the quad flat no-lead package structure of FIG. 3A taken along line III-III'. Referring to FIG. 3A and FIG. 3B simultaneously, the quad flat no-lead package structure 30 of the present embodiment is similar to the quad flat no-lead package structure 10 of the previous embodiment. The main difference between the two is: the quad flat of the embodiment. Leadless seal The mounting structure 30 is a quad flat no-lead flip chip package structure.
如圖3A與圖3B所示，本實施例的四方扁平無引腳覆晶封裝結構30包括一導線架100、一介電膜200、一晶片310以及一封裝膠體500。具體而言，導線架100可具有多個引腳102，導線架100的多個引腳102從晶片310下方延伸至封裝膠體500的邊緣。詳細來說，如圖3A所示，多個引腳102是以環繞晶片310四周的方式分佈，相鄰的引腳102彼此之間至少相隔一間距G，且各引腳102是從晶片310的下方延伸至封裝膠體500的邊緣。 As shown in FIG. 3A and FIG. 3B , the quad flat no-lead flip chip package structure 30 of the present embodiment includes a lead frame 100 , a dielectric film 200 , a wafer 310 , and an encapsulant 500 . In particular, leadframe 100 can have a plurality of pins 102 from which a plurality of leads 102 extend from below wafer 310 to the edge of encapsulant 500. In detail, as shown in FIG. 3A, the plurality of pins 102 are distributed around the periphery of the wafer 310, the adjacent pins 102 are at least spaced apart from each other by a distance G, and each of the pins 102 is from the wafer 310. The lower portion extends to the edge of the encapsulant 500.
另一方面，介電膜200配置於導線架100上，介電膜200具有多個開孔202，且各開孔202分別位於對應的引腳102上方。在本實施例中，開孔202可藉由對介電膜200進行蝕刻或雷射移除而形成。介電膜200的分佈範圍涵蓋各引腳102間之區域，且介電膜200的邊緣例如是與封裝膠體500的邊緣切齊，且介電膜200的各開孔202的最大孔徑不超出各對應的引腳102的外輪廓，換言之，介電膜200上的開孔202可與導線架100的引腳102搭配以構成一氣密結構，以使表面貼附有介電膜200的導線架100能夠被真空吸附。此處，導線架100與介電膜200可構成一導線架結構L。如圖3B所示，晶片310配置於介電膜200上，以使介電膜200位於晶片310與導線架100之間，而晶片310具有一主動面A，在主動面A側可具有多個焊墊302，且導電凸塊312可設置於主動面A的焊墊302上，晶片310與對應開孔202所暴露出的引腳102之間可藉由導電凸塊312電性連接。 On the other hand, the dielectric film 200 is disposed on the lead frame 100. The dielectric film 200 has a plurality of openings 202, and the openings 202 are respectively located above the corresponding pins 102. In the present embodiment, the opening 202 can be formed by etching or laser removing the dielectric film 200. The distribution of the dielectric film 200 covers the area between the pins 102, and the edge of the dielectric film 200 is, for example, aligned with the edge of the encapsulant 500, and the maximum aperture of each opening 202 of the dielectric film 200 does not exceed each other. The outer contour of the corresponding pin 102, in other words, the opening 202 in the dielectric film 200 can be matched with the pin 102 of the lead frame 100 to form a hermetic structure, so that the lead frame 100 with the surface of the dielectric film 200 attached thereto Can be vacuum absorbed. Here, the lead frame 100 and the dielectric film 200 may constitute a lead frame structure L. As shown in FIG. 3B, the wafer 310 is disposed on the dielectric film 200 such that the dielectric film 200 is located between the wafer 310 and the lead frame 100, and the wafer 310 has an active surface A, and may have a plurality of sides on the active surface A side. The pad 302 is disposed, and the conductive bumps 312 are disposed on the pads 302 of the active surface A. The pads 310 and the leads 102 corresponding to the corresponding openings 202 are electrically connected by the conductive bumps 312.
在本實施例中，晶片310是以其主動面A面對介電膜200的方式設置介電膜200上，且介電膜200之開孔202被晶片310所覆蓋，以進行覆晶接合製程。晶片310上的各焊墊302藉由各導電凸塊312而與對應的開孔202所暴露出的引腳102達到電性連接的目的。此處，導電凸塊312的材質例如是金、銅、銀合金或其他合適之導電材料。 In this embodiment, the wafer 310 is disposed on the dielectric film 200 with the active surface A facing the dielectric film 200, and the opening 202 of the dielectric film 200 is covered by the wafer 310 for the flip chip bonding process. . Each of the pads 302 on the wafer 310 is electrically connected to the leads 102 exposed by the corresponding openings 202 by the respective conductive bumps 312. Here, the material of the conductive bump 312 is, for example, gold, copper, silver alloy or other suitable conductive material.
值得注意的是，由於介電膜200與導線架100二者的搭配可構成一氣密結構，且介電膜200作為輔助導線架100之支撐用途，因此在進行晶片310、焊墊302與導線架100接合製程時，導線架100可藉由真空吸附的方式固定其位置，且避免導線架100在進行接合製程時發生移位之情形，進而提高晶片310與導線架100接合之精準度。進一步而言，介電膜200的開孔202之最小孔徑範圍為露出導電凸塊312與引腳102接合區域，最大孔徑範圍則為整個引腳102之上表面而不超出引腳102的外輪廓(圖未示)。 It should be noted that since the combination of the dielectric film 200 and the lead frame 100 can constitute an airtight structure, and the dielectric film 200 serves as a support for the auxiliary lead frame 100, the wafer 310, the pad 302 and the lead frame are performed. During the 100 bonding process, the lead frame 100 can be fixed in position by vacuum adsorption, and the displacement of the lead frame 100 during the bonding process can be avoided, thereby improving the precision of bonding the wafer 310 to the lead frame 100. Further, the minimum aperture range of the opening 202 of the dielectric film 200 is to expose the bonding region of the conductive bump 312 and the pin 102, and the maximum aperture range is the upper surface of the entire pin 102 without exceeding the outer contour of the pin 102. (not shown).
為了保護晶片310與導電凸塊312以及確保四方扁平無引腳封裝結構30的信賴性，封裝膠體500會包覆導線架100、介電膜200、晶片310以及焊線400。圖3B所示，封裝膠體500可分佈於導線架100的兩側，除了可包覆介電膜200、晶片310以及焊線400之外，更可填充於導線架另一側的空間S內，換言之，封裝膠體500可填入任二相鄰引腳102之間，以包覆所有引腳102。當然，引腳102的末端會暴露於封裝膠體500，以利於與外部裝置(例如電路板)電性連接。 In order to protect the wafer 310 and the conductive bumps 312 and to ensure the reliability of the quad flat no-lead package structure 30, the encapsulant 500 covers the leadframe 100, the dielectric film 200, the wafer 310, and the bonding wires 400. As shown in FIG. 3B, the encapsulant 500 can be distributed on both sides of the lead frame 100. In addition to covering the dielectric film 200, the wafer 310, and the bonding wire 400, the encapsulant 500 can be filled in the space S on the other side of the lead frame. In other words, the encapsulant 500 can be filled between any two adjacent pins 102 to wrap all of the pins 102. Of course, the end of the pin 102 will be exposed to the encapsulant 500 to facilitate electrical connection with an external device such as a circuit board.
圖4A為本發明之另一實施例之四方扁平無引腳封裝結構的上視圖。圖4B為圖4A之四方扁平無引腳封裝結構沿剖線IV-IV’的剖面示意圖。請同時參考圖4A以及圖4B，本實施例的四方扁平無引腳封裝結構40與前一實施例中的四方扁平無引腳封裝結構30相似，二者主要差別之處在於：本實施例的四方扁平無引腳封裝結構40中，導線架110除了具有多個引腳112之外，導線架110更包括一晶片座114。 4A is a top view of a quad flat no-lead package structure in accordance with another embodiment of the present invention. 4B is a cross-sectional view of the quad flat no-lead package structure of FIG. 4A taken along line IV-IV'. Referring to FIG. 4A and FIG. 4B simultaneously, the quad flat no-lead package structure 40 of the present embodiment is similar to the quad flat no-lead package structure 30 of the previous embodiment, and the main difference between the two is: the embodiment In the quad flat no-lead package structure 40, the lead frame 110 includes a wafer holder 114 in addition to the plurality of pins 112.
如圖4A與圖4B所示，晶片310對應於導線架100的晶片座114而配置。此處，晶片座114例如具有散熱及/或接地的功能。 As shown in FIGS. 4A and 4B, the wafer 310 is disposed corresponding to the wafer holder 114 of the lead frame 100. Here, the wafer holder 114 has a function of, for example, heat dissipation and/or grounding.
綜上所述，本發明的四方扁平無引腳之導線架結構以及四方扁平無引腳封裝結構將介電膜設置於導線架之引腳上，並全面覆蓋引腳及相鄰引腳間之間距，則當晶片、焊線與導線架進行焊接接合製程或晶片、焊墊與導線架進行覆晶接合製程(即進行接合製程)，導線架可藉由真空吸附的方式而固定其位置，且介電膜可輔助導線架之支撐用途，由此確保焊線接合或覆晶接合過程能夠順利進行。再者，由於介電膜是位於晶片與導線架之間，故介電膜的使用可達到簡化製程以及提高良率之目的。 In summary, the quad flat no-lead lead frame structure and the quad flat no-lead package structure of the present invention have a dielectric film disposed on the lead of the lead frame and completely cover the pin and the adjacent pin. The spacing, when the wafer, the bonding wire and the lead frame are soldered to a bonding process or the wafer, the bonding pad and the lead frame are subjected to a flip chip bonding process (ie, a bonding process), the lead frame can be fixed by vacuum adsorption, and The dielectric film can assist the support of the leadframe, thereby ensuring that the wire bond or flip chip bonding process can proceed smoothly. Moreover, since the dielectric film is located between the wafer and the lead frame, the use of the dielectric film can achieve the purpose of simplifying the process and improving the yield.
雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明的精神和範圍內，當可作些許的更動與潤飾，故本發明的保護範圍當視後附的申請專利範圍所界定者為準。 Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.
10‧‧‧四方扁平無引腳封裝結構 10‧‧‧Quad Flat No-Lead Package Structure
100‧‧‧導線架 100‧‧‧ lead frame
102‧‧‧引腳 102‧‧‧ pin
200‧‧‧介電膜 200‧‧‧ dielectric film
202‧‧‧開孔 202‧‧‧Opening
300‧‧‧晶片 300‧‧‧ wafer
302‧‧‧焊墊 302‧‧‧ solder pads
400‧‧‧焊線 400‧‧‧welding line
500‧‧‧封裝膠體 500‧‧‧Package colloid
600‧‧‧黏著層 600‧‧‧Adhesive layer
I-I’‧‧‧剖線 I-I’‧‧‧ cut line
L‧‧‧導線架結構 L‧‧‧ lead frame structure
S‧‧‧空間 S‧‧‧ Space
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| TW200627608A (en) * | 2005-01-26 | 2006-08-01 | Advanced Semiconductor Eng | Quad flat no-lead chip package structure |
| TW201010035A (en) * | 2008-08-29 | 2010-03-01 | Chipmos Technologies Inc | Quad flat non-leaded package |
| TW201027643A (en) * | 2009-01-15 | 2010-07-16 | Chipmos Technologies Inc | Manufacturing process for quad flat non-leaded package |
| TW201027637A (en) * | 2009-01-15 | 2010-07-16 | Chipmos Technologies Inc | Manufacturing process for quad flat non-leaded package |
| TW201027642A (en) * | 2009-01-15 | 2010-07-16 | Chipmos Technologies Inc | Manufacturing process for quad flat non-leaded package |
Also Published As
| Publication number | Publication date |
|---|---|
| TW201635447A (en) | 2016-10-01 |
| CN106206479A (en) | 2016-12-07 |
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