TW200627608A - Quad flat no-lead chip package structure - Google Patents

Quad flat no-lead chip package structure

Info

Publication number
TW200627608A
TW200627608A TW094102285A TW94102285A TW200627608A TW 200627608 A TW200627608 A TW 200627608A TW 094102285 A TW094102285 A TW 094102285A TW 94102285 A TW94102285 A TW 94102285A TW 200627608 A TW200627608 A TW 200627608A
Authority
TW
Taiwan
Prior art keywords
mold lock
package structure
metal plate
chip package
quad flat
Prior art date
Application number
TW094102285A
Other languages
Chinese (zh)
Other versions
TWI261901B (en
Inventor
Chien Liu
Meng-Jen Wang
Original Assignee
Advanced Semiconductor Eng
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Semiconductor Eng filed Critical Advanced Semiconductor Eng
Priority to TW094102285A priority Critical patent/TWI261901B/en
Publication of TW200627608A publication Critical patent/TW200627608A/en
Application granted granted Critical
Publication of TWI261901B publication Critical patent/TWI261901B/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Wire Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

A QFN type chip package structure is provided. The structure includes a chip, a lead frame and a molding compound. The lead frame has a plurality of bump bonding leads and a metal plate surrounded by the bump bonding leads for electrically connection with bumps on the chip. In addition, the metal plate has a first surface, a second surface and a plurality of mold lock holes concaved from the first surface, especially, the inner size of each mold lock hole is increased gradually from the first surface to the second surface. The cross-section shape of the mold lock holes is trapezoid or arc, for example. Therefore, the delamination between compound and metal plate is reduced to get better mold lock.
TW094102285A 2005-01-26 2005-01-26 Quad flat no-lead chip package structure TWI261901B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW094102285A TWI261901B (en) 2005-01-26 2005-01-26 Quad flat no-lead chip package structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW094102285A TWI261901B (en) 2005-01-26 2005-01-26 Quad flat no-lead chip package structure

Publications (2)

Publication Number Publication Date
TW200627608A true TW200627608A (en) 2006-08-01
TWI261901B TWI261901B (en) 2006-09-11

Family

ID=37987037

Family Applications (1)

Application Number Title Priority Date Filing Date
TW094102285A TWI261901B (en) 2005-01-26 2005-01-26 Quad flat no-lead chip package structure

Country Status (1)

Country Link
TW (1) TWI261901B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI556359B (en) * 2015-03-31 2016-11-01 南茂科技股份有限公司 Quad flat non-leaded package structure and leadframe thereof

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI409924B (en) * 2007-09-12 2013-09-21 Advanced Semiconductor Eng Semiconductor package and manufacturing method thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI556359B (en) * 2015-03-31 2016-11-01 南茂科技股份有限公司 Quad flat non-leaded package structure and leadframe thereof

Also Published As

Publication number Publication date
TWI261901B (en) 2006-09-11

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