TWI555202B - Igbt and manufacturing method thereof - Google Patents
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Description
本案是有關於一種半導體裝置及其製造方法。詳細而言，本案中所述實施例是有關於一種絕緣閘雙極電晶體及其製造方法。 The present invention relates to a semiconductor device and a method of fabricating the same. In detail, the embodiment described in the present invention relates to an insulated gate bipolar transistor and a method of fabricating the same.
隨著科技的快速進展，半導體裝置(如電晶體)已被廣泛地應用在各式電子裝置中，如行動電話、平板電腦等。 With the rapid development of technology, semiconductor devices (such as transistors) have been widely used in various electronic devices, such as mobile phones, tablets, and the like.
一般而言，絕緣閘雙極電晶體(Insulated Gate Bipolar Transistor,IGBT)具有低導通電阻以及高驅動電流的特性，故經常被應用在高功率的開關電路中。 In general, Insulated Gate Bipolar Transistors (IGBTs) have low on-resistance and high drive current characteristics, and are often used in high-power switching circuits.
本發明的一態樣提供一種絕緣閘雙極電晶體。根據本發明一實施例，絕緣閘雙極電晶體包括射極電極、集極電極、第一導電型態的集極層、第二導電型態的摻雜層、第二導電型態的集極層以及第一導電型態的基底層。射極電極與集極電極分別位於絕緣閘雙極電晶體的相對兩側。第一導電型態的集極層接觸集極電極的第一表面。第二導 電型態的摻雜層覆蓋第一導電型態的集極層。第二導電型態的集極層接觸集極電極的第二表面。第一導電型態的集極層與第二導電型態的集極層交替設置。第一導電型態的基底層，用以阻隔第二導電型態的集極層與第一導電型態的集極層。 One aspect of the invention provides an insulated gate bipolar transistor. According to an embodiment of the invention, an insulating gate bipolar transistor includes an emitter electrode, a collector electrode, a collector layer of a first conductivity type, a doped layer of a second conductivity type, and a collector of a second conductivity type a layer and a base layer of a first conductivity type. The emitter electrode and the collector electrode are respectively located on opposite sides of the insulating gate bipolar transistor. The collector layer of the first conductivity type contacts the first surface of the collector electrode. Second guide The electrically doped layer covers the collector layer of the first conductivity type. The collector layer of the second conductivity type contacts the second surface of the collector electrode. The collector layer of the first conductivity type is alternately disposed with the collector layer of the second conductivity type. a base layer of a first conductivity type for blocking a collector layer of the second conductivity type and a collector layer of the first conductivity type.
本發明的另一態樣提供一種絕緣閘雙極電晶體的 製造方法。根據本發明一實施例，製造方法包括：提供一主體，其中主體包括第二導電型態的摻雜層；形成第一導電型態的基底層；形成第二導電型態的集極層，其中第一導電型態的基底層介於第二導電型態的集極層與第二導電型態的摻雜層之間；形成第一導電型態的集極層，其中第二導電型態的摻雜層覆蓋第一導電型態的集極層，且第一導電型態的集極層與第二導電型態的集極層交替設置；以及形成集極電極，其中集極電極的第一表面接觸第一導電型態的集極層，集極電極的第二表面接觸第二導電型態的集極層。 Another aspect of the present invention provides an insulated gate bipolar transistor Production method. According to an embodiment of the invention, a method of manufacturing includes: providing a body, wherein the body comprises a doped layer of a second conductivity type; forming a base layer of a first conductivity type; forming a collector layer of a second conductivity type, wherein The base layer of the first conductivity type is interposed between the collector layer of the second conductivity type and the doped layer of the second conductivity type; forming a collector layer of the first conductivity type, wherein the second conductivity type The doped layer covers the collector layer of the first conductivity type, and the collector layer of the first conductivity type and the collector layer of the second conductivity type are alternately disposed; and the collector electrode is formed, wherein the collector electrode is first The surface contacts the collector layer of the first conductivity type, and the second surface of the collector electrode contacts the collector layer of the second conductivity type.
綜上所述，透過應用上述一實施例，可實現一種絕緣閘雙極電晶體，可同時改進絕緣閘雙極電晶體的能量耗損及操作上的穩定度。 In summary, by applying the above embodiment, an insulated gate bipolar transistor can be realized, which can simultaneously improve the energy consumption and operational stability of the insulated gate bipolar transistor.
100‧‧‧絕緣閘雙極電晶體 100‧‧‧Insulated gate bipolar transistor
110‧‧‧集極電極 110‧‧‧ Collector electrode
120‧‧‧射極電極 120‧‧ ‧ emitter electrode
124‧‧‧層間中介層 124‧‧‧Interlayer
130‧‧‧閘極 130‧‧‧ gate
132‧‧‧閘極絕緣層 132‧‧‧ gate insulation
140‧‧‧P型基底層 140‧‧‧P type basal layer
SF1‧‧‧集極電極的第一表面 First surface of the SF1‧‧‧ collector electrode
SF2‧‧‧集極電極的第二表面 Second surface of the SF2‧‧ ‧ collector electrode
SF3‧‧‧集極電極的第三表面 The third surface of the SF3‧‧‧ collector electrode
I1‧‧‧間距 I1‧‧‧ spacing
I2‧‧‧間距 I2‧‧‧ spacing
TR‧‧‧溝槽 TR‧‧‧ trench
SD1‧‧‧第一側 SD1‧‧‧ first side
140a‧‧‧待移除部份 140a‧‧‧Parts to be removed
150‧‧‧N型集極層 150‧‧‧N type collector layer
150a‧‧‧待移除部份 150a‧‧‧Parts to be removed
160‧‧‧P型集極層 160‧‧‧P type collector layer
170‧‧‧N型緩衝層 170‧‧‧N type buffer layer
170a‧‧‧暴露部份 170a‧‧‧Exposed parts
180‧‧‧N型漂移層 180‧‧‧N type drift layer
190‧‧‧P型井層 190‧‧‧P type well
200‧‧‧P型射極層 200‧‧‧P-type emitter layer
210‧‧‧N型射極層 210‧‧‧N type emitter layer
SD2‧‧‧第二側 SD2‧‧‧ second side
C1-C6‧‧‧曲線 C1-C6‧‧‧ Curve
C22、C44、C66‧‧‧曲線 C22, C44, C66‧‧‧ curves
第1圖為根據本發明一實施例繪示的一種絕緣閘雙極電晶體的示意圖； 第2A-2D圖為根據本發明一實施例繪示的一種絕緣閘雙極電晶體的製造方法的示意圖；第3圖為根據本發明一實施例的絕緣閘雙極電晶體、一比較例I的絕緣閘雙極電晶體以及一比較例II的逆導絕緣閘雙極電晶體之崩潰電壓(breakdown voltage)所繪示的比較圖；第4圖為根據本發明一實施例的絕緣閘雙極電晶體、一比較例I的絕緣閘雙極電晶體以及一比較例II的逆導絕緣閘雙極電晶體之電壓-電流關係所繪示的比較圖；以及第5圖為根據本發明一實施例的絕緣閘雙極電晶體、一比較例I的絕緣閘雙極電晶體以及一比較例II的逆導絕緣閘雙極電晶體之順向導通電壓(forward turn-on voltage)與截止延遲時間(turn-off delay time)的相應關係所繪示的比較圖。 1 is a schematic view of an insulated gate bipolar transistor according to an embodiment of the invention; 2A-2D is a schematic diagram of a method for fabricating an insulated gate bipolar transistor according to an embodiment of the invention; FIG. 3 is an insulating gate bipolar transistor according to an embodiment of the invention, and a comparative example I A comparison diagram of the breakdown voltage of the insulated gate bipolar transistor and a reverse conducting insulated gate bipolar transistor of Comparative Example II; and FIG. 4 is an insulated gate bipolar according to an embodiment of the present invention. A comparison diagram of voltage-current relationships between a transistor, an insulated gate bipolar transistor of Comparative Example I, and a reverse conducting insulated gate bipolar transistor of Comparative Example II; and FIG. 5 is an embodiment in accordance with the present invention Example of an insulated gate bipolar transistor, an insulated gate bipolar transistor of Comparative Example I, and a forward turn-on voltage and an off-delay time of a reverse conducting insulated gate bipolar transistor of Comparative Example II A comparison diagram drawn by the corresponding relationship of (turn-off delay time).
以下將以圖式及詳細敘述清楚說明本揭示內容之精神，任何所屬技術領域中具有通常知識者在瞭解本揭示內容之實施例後，當可由本揭示內容所教示之技術，加以改變及修飾，其並不脫離本揭示內容之精神與範圍。 The spirit and scope of the present disclosure will be apparent from the following description of the embodiments of the present disclosure, which may be modified and modified by the teachings of the present disclosure. It does not depart from the spirit and scope of the disclosure.
關於本文中所使用之『第一』、『第二』、...等，並非特別指稱次序或順位的意思，亦非用以限定本發明，其僅為了區別以相同技術用語描述的元件或操作。 The terms "first", "second", etc., as used herein, are not intended to refer to the order or the order, and are not intended to limit the invention, only to distinguish between elements described in the same technical terms or operating.
關於本文中所使用之方向用語，例如：上、下、 左、右、前或後等，僅是參考附加圖式的方向。因此，使用的方向用語是用來說明並非用來限制本創作。 For the directional terms used in this article, for example: up, down, Left, right, front or back, etc., only refer to the direction of the additional schema. Therefore, the directional terminology used is used to illustrate that it is not intended to limit the creation.
關於本文中所使用之『包含』、『包括』、『具有』、『含有』等等，均為開放性的用語，即意指包含但不限於。 The terms "including", "including", "having", "containing", etc., as used in this document are all open terms, meaning, but not limited to.
關於本文中所使用之『及/或』，係包括所述事物的任一或全部組合。 With respect to "and/or" as used herein, it is meant to include any or all combinations of the recited.
關於本文中所使用之用語『大致』、『約』等，係用以修飾任何可些微變化的數量或誤差，但這種些微變化或誤差並不會改變其本質。一般而言，此類用語所修飾的些微變化或誤差之範圍在部份實施例中可為20%，在部份實施例中可為10%，在部份實施例中可為5%或是其他數值。本領域技術人員應當瞭解，前述提及的數值可依實際需求而調整，並不以此為限。 The terms "substantially", "about", and the like, as used herein, are used to modify the quantity or error of any slight variation, but such slight variations or errors do not alter the nature. In general, the range of slight variations or errors modified by such terms may be 20% in some embodiments, 10% in some embodiments, or 5% in some embodiments. Other values. It should be understood by those skilled in the art that the aforementioned numerical values may be adjusted according to actual needs, and are not limited thereto.
關於本文中所使用之用詞(terms)，除有特別註明外，通常具有每個用詞使用在此領域中、在此揭露之內容中與特殊內容中的平常意義。某些用以描述本揭露之用詞將於下或在此說明書的別處討論，以提供本領域技術人員在有關本揭露之描述上額外的引導。 The terms used in this document, unless otherwise specified, generally have the usual meaning of each term used in the art, in the context of the disclosure, and in the particular content. Certain terms used to describe the disclosure are discussed below or elsewhere in this specification to provide additional guidance to those skilled in the art in the description of the disclosure.
絕緣閘雙極電晶體在關閉(turn-off)時，有一截止延遲時間(turn-off delay time)，此截止延遲時間可造成額外的能量損耗。此外，絕緣閘雙極電晶體容易因其內部的P-N接面而造成負微分電阻(negative differential resistance，NDR)現象，導致操作上的不易及不穩定。針對前述之部份/全部缺陷，於下列實施例中，提出了一種絕緣閘雙極電晶 體。 Insulated gate bipolar transistors have a turn-off delay time when turned off, which can cause additional energy losses. In addition, the insulated gate bipolar transistor is susceptible to a negative differential resistance (NDR) phenomenon due to its internal P-N junction, resulting in difficulty in operation and instability. In view of some/all of the above defects, in the following embodiments, an insulating gate bipolar electro-crystal is proposed. body.
第1圖為根據本發明一實施例繪示的一種絕緣閘 雙極電晶體100的示意圖。在本實施例中，絕緣閘雙極電晶體100例如為一種溝槽式絕緣閘雙極電晶體(trench gate IGBT)，然而本發明不以此為限。 FIG. 1 is an insulating gate according to an embodiment of the invention. A schematic of a bipolar transistor 100. In the present embodiment, the insulating gate bipolar transistor 100 is, for example, a trench gate IGBT, but the invention is not limited thereto.
在本實施例中，絕緣閘雙極電晶體100包括集極電極(collector electrode)110、射極電極(emitter electrode)120、層間中介層(interlayer dielectric)124、閘極(gate electrode)130、閘極絕緣層(gate insulator)132、P型基底層(P-type base layer)140、N型集極層(N-type collector layer)150、P型集極層(P-type collector layer)160、N型摻雜層(N-type doped layer)(其中可包括N型緩衝層(N-type buffer layer)170及N型漂移層(N-type drift layer)180)、P型井層(P-type well layer)190、P型射極層(P-type emitter layer)200以及N型射極層(N-type emitter layer)210。在一些實施例中，N型摻雜層可為N型漂移層180，亦即，N型緩衝層170可被省略。此外，本領域人士當可明白，在一些實施例中，上述摻雜P型摻質的各層可改變為摻雜N型摻質，且上述摻雜N型摻質的各層可改變為摻雜P型摻質。是以，本發明不以此處所述實施例為限。 In the present embodiment, the insulating gate bipolar transistor 100 includes a collector electrode 110, an emitter electrode 120, an interlayer dielectric 124, a gate electrode 130, and a gate. a gate insulator 132, a P-type base layer 140, an N-type collector layer 150, a P-type collector layer 160, N-type doped layer (which may include N-type buffer layer 170 and N-type drift layer 180), P-type well layer (P- A type well layer 190, a P-type emitter layer 200, and an N-type emitter layer 210. In some embodiments, the N-type doped layer may be an N-type drift layer 180, that is, the N-type buffer layer 170 may be omitted. In addition, it will be understood by those skilled in the art that in some embodiments, the layers of the doped P-type dopant may be changed to doped N-type dopants, and the layers of the doped N-type dopant may be changed to doped P. Type dopant. Therefore, the invention is not limited to the embodiments described herein.
在本實施例中，集極電極110與射極電極120分別位於絕緣閘雙極電晶體100的相對兩側，例如射極電極120位於絕緣閘雙極電晶體100的第一側SD1，且集極電極110位於絕緣閘雙極電晶體100的第二側SD2。N型漂移層 180位於N型緩衝層170之上。P型井層190位於N型漂移層180之上。P型射極層200以及N型射極層210皆位於P型井層190之上。在本實施例中，P型射極層200以及N型射極層210的高度大致相同(例如在第1圖中的y軸上具有大致相同的y軸座標)，更進一步來說，P型射極層200的頂面與絕緣閘雙極電晶體100的底面之間的距離和N型射極層210的頂面與絕緣閘雙極電晶體100的底面之間的距離大致相同。但在其他實施例中，P型射極層200的頂面與絕緣閘雙極電晶體100的底面之間的距離可小於N型射極層210的頂面與絕緣閘雙極電晶體100的底面之間的距離。 In this embodiment, the collector electrode 110 and the emitter electrode 120 are respectively located on opposite sides of the insulating gate bipolar transistor 100. For example, the emitter electrode 120 is located on the first side SD1 of the insulating gate bipolar transistor 100, and is set. The pole electrode 110 is located on the second side SD2 of the insulated gate bipolar transistor 100. N-type drift layer 180 is located above the N-type buffer layer 170. The P-type well layer 190 is located above the N-type drift layer 180. Both the P-type emitter layer 200 and the N-type emitter layer 210 are located above the P-type well layer 190. In the present embodiment, the heights of the P-type emitter layer 200 and the N-type emitter layer 210 are substantially the same (for example, having substantially the same y-axis coordinates on the y-axis in FIG. 1), and further, the P-type The distance between the top surface of the emitter layer 200 and the bottom surface of the insulating gate bipolar transistor 100 and the distance between the top surface of the N-type emitter layer 210 and the bottom surface of the insulating gate bipolar transistor 100 are substantially the same. However, in other embodiments, the distance between the top surface of the P-type emitter layer 200 and the bottom surface of the insulating gate bipolar transistor 100 may be less than the top surface of the N-type emitter layer 210 and the insulating gate bipolar transistor 100. The distance between the bottom surfaces.
在本實施例中，絕緣閘雙極電晶體100具有一溝 槽(trench)TR，溝槽TR蝕刻於絕緣閘雙極電晶體100上，可穿過P型井層190並抵達N型漂移層180。閘極130以及閘極絕緣層132可形成於溝槽TR之內。 In this embodiment, the insulating gate bipolar transistor 100 has a trench A trench TR, which is etched onto the insulating gate bipolar transistor 100, passes through the P-type well layer 190 and reaches the N-type drift layer 180. The gate 130 and the gate insulating layer 132 may be formed within the trench TR.
在本實施例中，射極電極120可位於N型射極層 210及P型射極層200之上，可電性接觸N型射極層210及P型射極層200。射極電極120可用以驅動負載子(如電子)往第二側SD2移動。另外，層間中介層124可設置於射極電極120與閘極130之間，用以電性絕緣。 In this embodiment, the emitter electrode 120 can be located in the N-type emitter layer. Above the 210 and P-type emitter layers 200, the N-type emitter layer 210 and the P-type emitter layer 200 are electrically contacted. The emitter electrode 120 can be used to drive a load (such as an electron) to move to the second side SD2. In addition, the interlayer interposer 124 may be disposed between the emitter electrode 120 and the gate 130 for electrical insulation.
另一方面，在本實施例中，P型集極層160位於N 型緩衝層170之下，並電性及實體地接觸集極電極110的第一表面SF1。以另一角度而言，N型緩衝層170可覆蓋P型集極層160。P型基底層140位於N型緩衝層170之下， 並電性及實體地接觸集極電極110的第二表面SF2，其中集極電極110的第二表面SF2相鄰於集極電極110的第一表面SF1。N型集極層150位於P型基底層140之下，並電性及實體地接觸集極電極110的第二表面SF2。集極電極110設置於N型集極層150與P型集極層160之下，並分別與N型集極層150、P型基底層140以及P型集極層160進行電性及實體地接觸。集極電極110可用以驅動正載子(如電洞)往第一側SD1移動。 On the other hand, in the present embodiment, the P-type collector layer 160 is located at N. Below the buffer layer 170, the first surface SF1 of the collector electrode 110 is electrically and physically contacted. In another aspect, the N-type buffer layer 170 can cover the P-type collector layer 160. The P-type base layer 140 is located below the N-type buffer layer 170. The second surface SF2 of the collector electrode 110 is electrically and physically contacted, wherein the second surface SF2 of the collector electrode 110 is adjacent to the first surface SF1 of the collector electrode 110. The N-type collector layer 150 is located under the P-type base layer 140 and electrically and physically contacts the second surface SF2 of the collector electrode 110. The collector electrode 110 is disposed under the N-type collector layer 150 and the P-type collector layer 160, and electrically and physically respectively with the N-type collector layer 150, the P-type base layer 140, and the P-type collector layer 160. contact. The collector electrode 110 can be used to drive a positive carrier (such as a hole) to move toward the first side SD1.
在本實施例中，P型集極層160與集極電極110 的第三表面SF3的間距I1大於N型集極層150與集極電極110的第三表面SF3的間距I2。亦即，P型集極層160與N型集極層150的高度不同(例如在第1圖中的y軸上具有不同的座標)。P型集極層160與N型集極層150彼此在實體上並不進行接觸。此外，P型基底層140可介於N型緩衝層170與N型集極層150之間，或是可介於P型集極層160與N型集極層150之間，可用以防止(或阻隔)N型緩衝層170及P型集極層160實體上接觸N型集極層150。在一實施例中，P型基底層140在集極電極110的第三表面SF3(集極電極110的第三表面SF3與集極電極110的第一表面SF1彼此相對)的正投影可大於或等於N型集極層150在集極電極110的第三表面SF3的正投影。 In this embodiment, the P-type collector layer 160 and the collector electrode 110 The pitch I1 of the third surface SF3 is greater than the pitch I2 of the N-type collector layer 150 and the third surface SF3 of the collector electrode 110. That is, the P-type collector layer 160 is different in height from the N-type collector layer 150 (for example, has different coordinates on the y-axis in FIG. 1). The P-type collector layer 160 and the N-type collector layer 150 are not physically in contact with each other. In addition, the P-type base layer 140 may be interposed between the N-type buffer layer 170 and the N-type collector layer 150, or may be interposed between the P-type collector layer 160 and the N-type collector layer 150, and may be used to prevent ( Or blocking the N-type buffer layer 170 and the P-type collector layer 160 physically contacting the N-type collector layer 150. In an embodiment, the positive projection of the P-type base layer 140 at the third surface SF3 of the collector electrode 110 (the third surface SF3 of the collector electrode 110 and the first surface SF1 of the collector electrode 110 are opposite to each other) may be greater than or Equal to the orthographic projection of the N-type collector layer 150 at the third surface SF3 of the collector electrode 110.
在一實施例中，P型基底層140的P型摻質之摻雜 濃度係低於P型集極層160的P型摻質之摻雜濃度。因此，藉由P型基底層140的設置，可避免高摻雜濃度的N型集 極層150直接實體上接觸高摻雜濃度的P型集極層160並形成P-N接面。如此一來，即可降低絕緣閘雙極電晶體100的負微分電阻(negative differential resistance，NDR)效應。 In an embodiment, the doping of the P-type dopant of the P-type base layer 140 The concentration is lower than the doping concentration of the P-type dopant of the P-type collector layer 160. Therefore, by the arrangement of the P-type base layer 140, the N-type set with high doping concentration can be avoided. The pole layer 150 directly physically contacts the highly doped P-type collector layer 160 and forms a P-N junction. In this way, the negative differential resistance (NDR) effect of the insulated gate bipolar transistor 100 can be reduced.
再者，在本實施例中，N型集極層150與P型集 極層160可沿著水平方向(如第1圖中的x軸方向)交替設置(相對地，N型緩衝層170、N型漂移層180、P型井層190可依序沿著垂直方向(如第1圖中的y軸方向)設置)。前述之交替設置可為以下幾種實施態樣，例如在一實施例中，N型集極層150在集極電極110的第三表面SF3上的正投影與P型集極層160在集極電極110的第三表面SF3上的正投影大致上彼此交錯。在另一實施例中，N型集極層150在集極電極110的第三表面SF3上的正投影與P型集極層160在集極電極110的第三表面SF3上的正投影可部分重疊且彼此交錯。在更一實施例中，N型集極層150在集極電極110的第三表面SF3上的正投影與P型集極層160在集極電極110的第三表面SF3上的正投影彼此大致不重疊。在一實施例中，N型集極層150在集極電極110的第三表面SF3上的正投影與P型集極層160在集極電極110的第三表面SF3上的正投影之間的比例大致為1：4。 Furthermore, in the present embodiment, the N-type collector layer 150 and the P-type set The pole layers 160 may be alternately arranged along the horizontal direction (such as the x-axis direction in FIG. 1) (relatively, the N-type buffer layer 170, the N-type drift layer 180, and the P-type well layer 190 may be sequentially along the vertical direction ( Set as in the y-axis direction in Figure 1). The foregoing alternate arrangement may be in the following embodiments. For example, in an embodiment, the orthographic projection of the N-type collector layer 150 on the third surface SF3 of the collector electrode 110 and the P-type collector layer 160 are in the collector. The orthographic projections on the third surface SF3 of the electrode 110 are substantially staggered with each other. In another embodiment, the orthographic projection of the N-type collector layer 150 on the third surface SF3 of the collector electrode 110 and the orthographic projection of the P-type collector layer 160 on the third surface SF3 of the collector electrode 110 may be partially Overlapping and staggered with each other. In a further embodiment, the orthographic projection of the N-type collector layer 150 on the third surface SF3 of the collector electrode 110 and the orthographic projection of the P-type collector layer 160 on the third surface SF3 of the collector electrode 110 are substantially equal to each other. Do not overlap. In an embodiment, the orthographic projection of the N-type collector layer 150 on the third surface SF3 of the collector electrode 110 and the orthographic projection of the P-type collector layer 160 on the third surface SF3 of the collector electrode 110 The ratio is roughly 1:4.
藉由N型集極層150與P型集極層160沿著水平 方向交替設置，可減少在導通狀態(on-state)下，經由P型集極層160進入絕緣閘雙極電晶體100的電洞。如此一來，即可減低絕緣閘雙極電晶體100的截止延遲時間(turn-off delay time)。 Horizontal along the N-type collector layer 150 and the P-type collector layer 160 The directions are alternately arranged to reduce the entry into the insulating gate bipolar transistor 100 via the P-type collector layer 160 in an on-state. In this way, the turn-off delay time of the insulating gate bipolar transistor 100 can be reduced.
在一實施例中，P型集極層160的P型摻質之摻雜 濃度例如是介於5e19與5e20(載子/立方公分)之間。P型基底層140的P型摻質之摻雜濃度例如是介於1e17與5e18(載子/立方公分)之間。N型集極層150的N型摻質之摻雜濃度例如是介於1e20與5e20(載子/立方公分)之間。 In an embodiment, the doping of the P-type dopant of the P-type collector layer 160 The concentration is, for example, between 5e19 and 5e20 (carrier/cubic centimeter). The doping concentration of the P-type dopant of the P-type base layer 140 is, for example, between 1e17 and 5e18 (carrier/cm 3 ). The doping concentration of the N-type dopant of the N-type collector layer 150 is, for example, between 1e20 and 5e20 (carrier/cm 3 ).
在一實施例中，P型集極層160的厚度例如約為 0.2與0.5微米之間。N型集極層150的厚度例如約為0.2至0.5微米之間。P型基底層140的厚度例如約為0.2至0.5微米之間。 In an embodiment, the thickness of the P-type collector layer 160 is, for example, approximately Between 0.2 and 0.5 microns. The thickness of the N-type collector layer 150 is, for example, between about 0.2 and 0.5 microns. The thickness of the P-type base layer 140 is, for example, between about 0.2 and 0.5 microns.
在一實施例中，在P型基底層140的摻雜劑量(其 單位為1/cm2，不同於本文中摻雜濃度之單位(即1/cm3))固定的情形下，P型基底層140的摻雜濃度與P型基底層140的厚度之間存在負相關關係。亦即，為維持大致固定的摻雜濃度，在P型基底層140的厚度(如y軸方向上的長度)增加時，P型基底層140的摻雜劑量提高，以維持大致固定的摻雜濃度於P型基底層140中。 In one embodiment, in the case where the doping amount of the P-type base layer 140 (whose unit is 1/cm 2 , which is different from the unit of the doping concentration herein (ie, 1/cm 3 )), the P-type substrate is fixed. There is a negative correlation between the doping concentration of layer 140 and the thickness of P-type base layer 140. That is, in order to maintain a substantially fixed doping concentration, when the thickness of the P-type base layer 140 (such as the length in the y-axis direction) is increased, the doping amount of the P-type base layer 140 is increased to maintain a substantially fixed doping. The concentration is in the P-type base layer 140.
透過上述的設置，可在提升絕緣閘雙極電晶體100 的關斷速度的同時，降低絕緣閘雙極電晶體100的負微分電阻效應。如此一來，即可同時改進絕緣閘雙極電晶體100的能量耗損及操作上的穩定度。 Through the above settings, the insulating gate bipolar transistor 100 can be lifted At the same time as the turn-off speed, the negative differential resistance effect of the insulated gate bipolar transistor 100 is reduced. In this way, the energy consumption and operational stability of the insulated gate bipolar transistor 100 can be improved at the same time.
本發明的另一實施態樣為一種絕緣閘雙極電晶體 的製造方法。此一製造方法可用以製造相同或相似於第1圖中所示結構之絕緣閘雙極電晶體。而為使敘述簡單，以下將根據本發明一實施例，以第1圖中的絕緣閘雙極電晶 體100為例進行對製造方法的敘述，然本發明不以此應用為限。 Another embodiment of the invention is an insulated gate bipolar transistor Manufacturing method. This manufacturing method can be used to fabricate an insulating gate bipolar transistor that is the same or similar to the structure shown in FIG. In order to simplify the description, in accordance with an embodiment of the present invention, the insulating gate bipolar electro-crystal in FIG. 1 will be described below. The body 100 is described as an example of the manufacturing method, but the invention is not limited to this application.
另外，應瞭解到，在本實施方式中所提及的操作方法的步驟，除特別敘明其順序者外，均可依實際需要調整其前後順序，甚至可同時或部分同時執行。 In addition, it should be understood that the steps of the operation method mentioned in the embodiment may be adjusted according to actual needs, and may be performed simultaneously or partially simultaneously, unless the order is specifically described.
再者，在不同實施例中，此些步驟亦可適應性地增加、置換、及/或省略。 Furthermore, in various embodiments, such steps may also be adaptively added, replaced, and/or omitted.
第2A-2D圖為根據本發明一實施例所繪示的絕緣閘雙極電晶體的製造方法的示意圖。 2A-2D are schematic views of a method of fabricating an insulated gate bipolar transistor according to an embodiment of the invention.
參照第2A圖。首先，可提供一N型基板(未繪示)，在N型基板的頂側，可分別形成P型井層190、P型射極層200、N型射極層210、層間中介層124、射極電極120、閘極130、閘極絕緣層132以及溝槽TR，以形成一主體，其中主體可具有第一側SD1以及第二側SD2。經由上述的製造方法，在主動區(active region)內的N型基板中未形成P型井層190、P型射極層200、N型射極層210、閘極130、閘極絕緣層132以及溝槽TR的區域則可被定義為N型漂移層180，其中，P型井層190可位於N型漂移層180之上。P型射極層200及N型射極層210可形成於P型井層190之中。溝槽TR可蝕刻於絕緣閘雙極電晶體100上，穿過P型井層190並抵達N型漂移層180。閘極130與閘極絕緣層132可形成在溝槽TR之中。層間中介層124可設置於閘極130之上。射極電極120可形成於層間中介層124、N型射極層210及P型射極層200之上。在其他實施例中，前述 的主體可更包含一N型緩衝層170。N型漂移層180位於N型緩衝層170之上，以形成例如第2A圖的結構。N型緩衝層170的形成方式有很多種，在一個實施例中，可透過離子植入製法，於N型漂移層180中植入N型摻質(dopant)以形成N型緩衝層170，其中N型緩衝層170位於相對於P型井層190的一側，即N型緩衝層170與P型井層190分別位於N型漂移層180的相對兩側。在另一個實施例中，可透過離子植入製法，於前述的N型基板(未繪示)中植入N型摻質以形成N型緩衝層170(即在N型漂移層180尚未被定義前形成N型緩衝層170)，其中N型緩衝層170與P型井層190分別位於N型漂移層180的相對兩側。 Refer to Figure 2A. First, an N-type substrate (not shown) may be provided. On the top side of the N-type substrate, a P-type well layer 190, a P-type emitter layer 200, an N-type emitter layer 210, and an interlayer interposer 124 may be respectively formed. The emitter electrode 120, the gate 130, the gate insulating layer 132, and the trench TR form a body, wherein the body may have a first side SD1 and a second side SD2. Through the above manufacturing method, the P-type well layer 190, the P-type emitter layer 200, the N-type emitter layer 210, the gate electrode 130, and the gate insulating layer 132 are not formed in the N-type substrate in the active region. The region of the trench TR can then be defined as an N-type drift layer 180, wherein the P-type well layer 190 can be over the N-type drift layer 180. P-type emitter layer 200 and N-type emitter layer 210 may be formed in P-type well layer 190. The trench TR can be etched onto the insulating gate bipolar transistor 100, through the P-type well layer 190 and onto the N-type drift layer 180. A gate 130 and a gate insulating layer 132 may be formed in the trench TR. The interlayer interposer 124 may be disposed over the gate 130. The emitter electrode 120 may be formed on the interlayer interposer 124, the N-type emitter layer 210, and the P-type emitter layer 200. In other embodiments, the foregoing The body may further include an N-type buffer layer 170. The N-type drift layer 180 is positioned over the N-type buffer layer 170 to form, for example, the structure of FIG. 2A. There are many ways to form the N-type buffer layer 170. In one embodiment, an N-type dopant can be implanted into the N-type drift layer 180 to form an N-type buffer layer 170 through an ion implantation process. The N-type buffer layer 170 is located on one side with respect to the P-type well layer 190, that is, the N-type buffer layer 170 and the P-type well layer 190 are respectively located on opposite sides of the N-type drift layer 180. In another embodiment, an N-type dopant is implanted in the aforementioned N-type substrate (not shown) to form an N-type buffer layer 170 by ion implantation (ie, the N-type drift layer 180 has not been defined yet). An N-type buffer layer 170) is formed before, wherein the N-type buffer layer 170 and the P-type well layer 190 are respectively located on opposite sides of the N-type drift layer 180.
參照第2B圖。在形成上述位於主體的第一側SD1 的結構後，可依序於主體的第二側(例如是底側)SD2形成P型基底層140與N型集極層150。P型基底層140與N型集極層150分別具有待移除部份140a、150a。P型基底層140可介於N型集極層150與N型緩衝層170之間，可用以阻隔N型集極層150與N型緩衝層170。 Refer to Figure 2B. In forming the above-mentioned first side SD1 located on the main body After the structure, the P-type base layer 140 and the N-type collector layer 150 may be formed sequentially on the second side (for example, the bottom side) SD2 of the body. The P-type base layer 140 and the N-type collector layer 150 have portions to be removed 140a, 150a, respectively. The P-type base layer 140 may be interposed between the N-type collector layer 150 and the N-type buffer layer 170 to block the N-type collector layer 150 and the N-type buffer layer 170.
參照第2C圖，在形成P型基底層140與N型集極 層150後，可移除P型基底層140與N型集極層150中的待移除部份140a、150a，以暴露出N型緩衝層170中相應的暴露部份170a。在一實施例中，P型基底層140與N型集極層150中的待移除部份140a與150a例如是可藉由蝕刻(etch)製程移除。 Referring to FIG. 2C, a P-type base layer 140 and an N-type collector are formed. After the layer 150, the portions to be removed 140a, 150a in the P-type base layer 140 and the N-type collector layer 150 may be removed to expose the corresponding exposed portions 170a of the N-type buffer layer 170. In an embodiment, the portions to be removed 140a and 150a in the P-type base layer 140 and the N-type collector layer 150 can be removed, for example, by an etch process.
參照第2D圖，接著，可提供P型摻質至N型緩 衝層170中的暴露部份170a，其中暴露部分170a可相應於圖2B中的待移除部份140a以及150a，以使此一暴露部份170a成為P型集極層160。在一實施例中，P型集極層160例如是藉由植入(implantation)製程及擴散(diffusion)製程形成。在一實施例中，植入製程與前述蝕刻製程所使用的遮罩可為同一遮罩，以節省重新製作遮罩成本與時間。 Referring to Figure 2D, then, P-type dopants can be provided to the N-type The exposed portion 170a of the layer 170, wherein the exposed portion 170a may correspond to the portions to be removed 140a and 150a in FIG. 2B, such that the exposed portion 170a becomes the P-type collector layer 160. In one embodiment, the P-type collector layer 160 is formed, for example, by an implantation process and a diffusion process. In one embodiment, the implant process and the mask used in the etching process described above may be the same mask to save cost and time for re-shaping the mask.
接著，可形成集極電極110於P型集極層160與N 型集極層150之下(參照第1圖)，並使集極電極110分別實體及電性上接觸P型基底層140、P型集極層160與N型集極層150。 Next, the collector electrode 110 can be formed on the P-type collector layer 160 and N. Below the collector layer 150 (see FIG. 1), the collector electrode 110 is physically and electrically contacted with the P-type base layer 140, the P-type collector layer 160, and the N-type collector layer 150, respectively.
藉由上述的製造方法，即可簡便地製成前述具有 較低能量損耗及關斷(截止)延遲時間的絕緣閘雙極電晶體100。 By the above manufacturing method, it is possible to easily produce the aforementioned Insulated gate bipolar transistor 100 with lower energy loss and turn-off (cutoff) delay time.
此外，當注意到，在上述製造方法中，具體的細節可參照前一實施態樣，在此不贅述。 In addition, it is noted that, in the above manufacturing method, specific details can be referred to the previous embodiment, and details are not described herein.
以下將透過第3-5圖對絕緣閘雙極電晶體100的特性進行進一步說明。其中，第3-5圖中的量測結果皆是針對單一元件(unit cell，例如可為第1圖的結構)進行量測。 The characteristics of the insulating gate bipolar transistor 100 will be further described below through Figures 3-5. The measurement results in FIGS. 3-5 are all measured for a single cell (for example, the structure of FIG. 1).
參照第3圖，第3圖為根據本發明一實施例的絕緣閘雙極電晶體100、比較例I的絕緣閘雙極電晶體、以及比較例II的逆導絕緣閘雙極電晶體(RC-IGBT)之崩潰電壓(breakdown voltage)所繪示的比較圖。曲線C1代表本發明此一實施例的絕緣閘雙極電晶體100在截止狀態(off state)下的電壓-電流關係。曲線C2代表比較例I的絕緣閘雙極電 晶體在截止狀態下的電壓與電流關係。曲線C22代表比較例II逆導絕緣閘雙極電晶體在截止狀態下的電壓與電流關係。如圖所示，本發明此一實施例的絕緣閘雙極電晶體100的崩潰電壓(約1.34kV)與比較例I的絕緣閘雙極電晶體的崩潰電壓(約1.29kV)及比較例II的逆導絕緣閘雙極電晶體的崩潰電壓(約1.355kV)相比相差不大。其中，在進行此一量測時，施加於本發明此一實施例的絕緣閘雙極電晶體100、比較例I的絕緣閘雙極電晶體以及比較例II的逆導絕緣閘雙極電晶體的閘極的電壓皆為0V。 Referring to FIG. 3, FIG. 3 is an insulating gate bipolar transistor 100, an insulated gate bipolar transistor of Comparative Example 1, and a reverse conducting insulating gate bipolar transistor of Comparative Example II according to an embodiment of the present invention. - IGBT) comparison diagram of the breakdown voltage. Curve C1 represents the voltage-current relationship of the insulated gate bipolar transistor 100 of this embodiment of the present invention in an off state. Curve C2 represents the insulated gate bipolar of Comparative Example I The relationship between voltage and current of the crystal in the off state. Curve C22 represents the voltage versus current relationship of the comparative example II reverse conducting insulated gate bipolar transistor in the off state. As shown, the breakdown voltage (about 1.34 kV) of the insulated gate bipolar transistor 100 of this embodiment of the present invention and the breakdown voltage (about 1.29 kV) of the insulated gate bipolar transistor of Comparative Example I and Comparative Example II are shown. The breakdown voltage of the reverse conducting insulated gate bipolar transistor (about 1.355 kV) is comparable. Wherein, in performing such a measurement, the insulating gate bipolar transistor 100 of the embodiment of the invention, the insulating gate bipolar transistor of Comparative Example I, and the reverse conducting insulating gate bipolar transistor of Comparative Example II are used. The voltage of the gate is 0V.
參照第4圖，第4圖為根據前述實施例的絕緣閘 雙極電晶體100、比較例I的絕緣閘雙極電晶體、以及比較例II的逆導絕緣閘雙極電晶體之電壓-電流關係所繪示的比較圖。曲線C3代表本發明此一實施例的絕緣閘雙極電晶體100在導通狀態下的電壓-電流關係。曲線C4代表比較例I的絕緣閘雙極電晶體在導通狀態下的電壓與電流關係。曲線C44代表比較例II逆導絕緣閘雙極電晶體在導通狀態下的電壓與電流關係。如圖所示，比較例II的逆導絕緣閘雙極電晶體出現負微分電阻現象。相對地，本發明此一實施例的絕緣閘雙極電晶體100與比較例I的絕緣閘雙極電晶體並未出現負微分電阻現象。其中，在進行此一量測時，施加於本發明此一實施例的絕緣閘雙極電晶體100、比較例I的絕緣閘雙極電晶體以及比較例II的逆導絕緣閘雙極電晶體的閘極的電壓皆為15V。 Referring to FIG. 4, FIG. 4 is an insulating gate according to the foregoing embodiment. A comparison diagram of the voltage-current relationship of the bipolar transistor 100, the insulated gate bipolar transistor of Comparative Example 1, and the reverse conducting insulated gate bipolar transistor of Comparative Example II. Curve C3 represents the voltage-current relationship of the insulated gate bipolar transistor 100 of this embodiment of the present invention in an on state. Curve C4 represents the voltage versus current relationship of the insulated gate bipolar transistor of Comparative Example I in the on state. Curve C44 represents the voltage versus current relationship of the comparative example II reverse conducting insulated gate bipolar transistor in the on state. As shown in the figure, the reverse conducting insulating gate bipolar transistor of Comparative Example II exhibits a negative differential resistance phenomenon. In contrast, the insulated gate bipolar transistor 100 of this embodiment of the present invention does not exhibit a negative differential resistance phenomenon with the insulated gate bipolar transistor of Comparative Example 1. Wherein, in performing such a measurement, the insulating gate bipolar transistor 100 of the embodiment of the invention, the insulating gate bipolar transistor of Comparative Example I, and the reverse conducting insulating gate bipolar transistor of Comparative Example II are used. The gate voltage is 15V.
參照第5圖，第5圖為根據前述實施例的絕緣閘 雙極電晶體100、比較例I的絕緣閘雙極電晶體、以及比較例II的逆導絕緣閘雙極電晶體之順向導通電壓(forward turn-on voltage)與截止延遲時間的相應關係所繪示的比較圖。曲線C5代表本發明此一實施例的絕緣閘雙極電晶體100在具有不同順向導通偏壓下的截止延遲時間。 曲線C6代表比較例I的絕緣閘雙極電晶體在具有不同順向導通偏壓下的截止延遲時間。曲線C66代表比較例II逆導絕緣閘雙極電晶體在具有不同順向導通偏壓下的截止延遲時間。如圖所示，在相同的順向導通偏壓下，本發明此一實施例的絕緣閘雙極電晶體100具有最短的截止延遲時間。 Referring to Figure 5, Figure 5 is an insulating gate according to the foregoing embodiment. Corresponding relationship between the forward turn-on voltage of the bipolar transistor 100, the insulated gate bipolar transistor of Comparative Example I, and the reverse conducting insulated gate bipolar transistor of Comparative Example II and the cutoff delay time A comparison chart drawn. Curve C5 represents the turn-off delay time of the insulated gate bipolar transistor 100 of this embodiment of the present invention with different forward bias voltages. Curve C6 represents the cut-off delay time of the insulated gate bipolar transistor of Comparative Example I with different forward bias voltages. Curve C66 represents the off-delay time of the Comparative Example II reverse conducting insulated gate bipolar transistor with different forward bias voltages. As shown, the insulated gate bipolar transistor 100 of this embodiment of the present invention has the shortest off-delay time under the same forward bias.
雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何熟習此技藝者，在不脫離本發明之精神和範圍內，當可作各種之更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。 Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and the present invention can be modified and retouched without departing from the spirit and scope of the present invention. The scope is subject to the definition of the scope of the patent application attached.
100‧‧‧絕緣閘雙極電晶體 100‧‧‧Insulated gate bipolar transistor
110‧‧‧集極電極 110‧‧‧ Collector electrode
120‧‧‧射極電極 120‧‧ ‧ emitter electrode
124‧‧‧層間中介層 124‧‧‧Interlayer
130‧‧‧閘極 130‧‧‧ gate
132‧‧‧閘極絕緣層 132‧‧‧ gate insulation
140‧‧‧P型基底層 140‧‧‧P type basal layer
150‧‧‧N型集極層 150‧‧‧N type collector layer
160‧‧‧P型集極層 160‧‧‧P type collector layer
190‧‧‧P型井層 190‧‧‧P type well
200‧‧‧P型射極層 200‧‧‧P-type emitter layer
210‧‧‧N型射極層 210‧‧‧N type emitter layer
SF1‧‧‧集極電極的第一表面 First surface of the SF1‧‧‧ collector electrode
SF2‧‧‧集極電極的第二表面 Second surface of the SF2‧‧ ‧ collector electrode
SF3‧‧‧集極電極的第三表面 The third surface of the SF3‧‧‧ collector electrode
I1‧‧‧間距 I1‧‧‧ spacing
I2‧‧‧間距 I2‧‧‧ spacing
TR‧‧‧溝槽 TR‧‧‧ trench
170‧‧‧N型緩衝層 170‧‧‧N type buffer layer
180‧‧‧N型漂移層 180‧‧‧N type drift layer
SD1‧‧‧第一側 SD1‧‧‧ first side
SD2‧‧‧第二側 SD2‧‧‧ second side
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| TW200600620A (en) * | 2004-05-07 | 2006-01-01 | Toyota Motor Co Ltd | Semiconductor substrate and semiconductor device, and manufacturing methods thereof |
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| CN102544084B (en) * | 2012-03-15 | 2014-02-12 | 电子科技大学 | Insulated gate bipolar translator (IGBT) device with two short-circuit positive electrodes |
| CN103383958B (en) * | 2013-07-17 | 2016-06-08 | 电子科技大学 | A kind of RC-IGBT device and making method thereof |
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