TWI553841B - 晶片封裝及其製造方法 - Google Patents
晶片封裝及其製造方法 Download PDFInfo
- Publication number
- TWI553841B TWI553841B TW102103806A TW102103806A TWI553841B TW I553841 B TWI553841 B TW I553841B TW 102103806 A TW102103806 A TW 102103806A TW 102103806 A TW102103806 A TW 102103806A TW I553841 B TWI553841 B TW I553841B
- Authority
- TW
- Taiwan
- Prior art keywords
- semiconductor wafer
- metal
- pad
- wafer
- conductive layer
- Prior art date
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 9
- 235000012431 wafers Nutrition 0.000 claims description 85
- 239000004065 semiconductor Substances 0.000 claims description 61
- 239000002184 metal Substances 0.000 claims description 44
- 229910000679 solder Inorganic materials 0.000 claims description 44
- 239000005304 optical glass Substances 0.000 claims description 14
- 230000003287 optical effect Effects 0.000 claims description 10
- 239000010410 layer Substances 0.000 description 51
- 230000017525 heat dissipation Effects 0.000 description 6
- 230000000694 effects Effects 0.000 description 4
- 238000000034 method Methods 0.000 description 4
- 238000003466 welding Methods 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 239000011241 protective layer Substances 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 230000007812 deficiency Effects 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000012858 packaging process Methods 0.000 description 1
- 239000000565 sealant Substances 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
- H01L23/3192—Multilayer coating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
- H01L23/3677—Wire-like or pin-like cooling fins or heat sinks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14618—Containers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0237—Disposition of the redistribution layers
- H01L2224/02371—Disposition of the redistribution layers connecting the bonding area on a surface of the semiconductor or solid-state body with another surface of the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/0502—Disposition
- H01L2224/05022—Disposition the internal layer being at least partially embedded in the surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05541—Structure
- H01L2224/05548—Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/05567—Disposition the external layer being at least partially embedded in the surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1302—Disposition
- H01L2224/13022—Disposition the bump connector being at least partially embedded in the surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
- H01L2224/1751—Function
- H01L2224/17515—Bump connectors having different functions
- H01L2224/17519—Bump connectors having different functions including bump connectors providing primarily thermal dissipation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Electromagnetism (AREA)
- Solid State Image Pick-Up Elements (AREA)
Description
本發明係有關一種晶片封裝及其製造方法,特別是指一種具有散熱功能之晶片封裝及其製造方法。
第1圖舉例顯示一種先前技術晶片封裝1之剖視示意圖。如第1圖所示,晶片封裝1例如為一種影像感測的晶片封裝。包含:半導體晶片11、銲墊12、空腔牆13、光學玻璃14、導電墊15、電導線16、內部焊接布局層17、焊球18、以及外部焊接布局層19。光學影像訊號穿過光學玻璃14,由空腔牆13所形成的空腔,進入半導體晶片11。藉由半導體晶片11中的電路操作,將光學影像訊號轉換為電子訊號後,由銲墊12經由導電墊15、電導線16與焊球18,傳送至印刷電路板(未示出)。
當導體基板11中的電路操作時,會產生熱量,而晶片封裝1例如為晶片級封裝(chip scale package,CSP),會產生散熱的問題,以致晶片的效能受到影響,影像訊號受雜訊干擾,甚至導致晶片封裝1損壞。
有鑑於此,本發明即針對上述先前技術之不足,提出一種晶片封裝及其製造方法,以改善晶片封裝散熱問題,進而降低晶片工作溫度,提高晶片工作效率。
本發明提供了一種晶片封裝,包含:一半導體晶片,具有相對之上表面及下表面;一金屬導熱層,形成於該下表面上,用以吸收該半導體晶片所產生之熱量;以及一銲墊,形成於該上表面上,用以電連接至該半導體晶片中之電路。
就另一觀點,本發明也提供了一種晶片封裝製造方法,包含:提供一半導體晶片,具有相對之上表面及下表面;形成一金屬導熱層於該下表面上,用以吸收該半導體晶片所產生之熱量;以及形成一銲墊於
該上表面上,用以電連接至該半導體晶片中之電路。
在一種較佳的實施例中,該晶片封裝,更包含:一金屬導熱帶,與該金屬導熱層連接;以及一焊球或一引腳,與該金屬導熱帶耦接;其中,該半導體晶片中之電路所產生的熱量,藉由該金屬導熱層與該金屬導熱帶,傳導至該焊球或該引腳。
上述的實施例中,該焊球或該引腳較佳地電連接至一接地電位。
在另一種較佳的實施例中,該金屬層完全覆蓋該下表面。
在其中一種實施例中,該半導體晶片中之電路包括一影像感測電路。
底下藉由具體實施例詳加說明,當更容易瞭解本發明之目的、技術內容、特點及其所達成之功效。
1,2,3,4,5,6‧‧‧晶片封裝
11,21,31,41,51,61‧‧‧半導體晶片
12,22,32,42,52,62‧‧‧銲墊
13,23,33,43‧‧‧空腔牆
14,24,34,44‧‧‧光學玻璃
15,25,35,45‧‧‧導電墊
16,26,36,46,56,63‧‧‧電導線
17,27,37,47‧‧‧內部焊接布局層
18,28,38,38a,48,48a,58‧‧‧焊球
19,29,39,49‧‧‧外部焊接布局層
21a,31a,41a,51a,61a‧‧‧金屬導熱層
31b,41b‧‧‧金屬導熱帶
53‧‧‧保護層
54‧‧‧第一絕緣層
57‧‧‧第二絕緣層
60‧‧‧導線架
64‧‧‧封膠層
65‧‧‧模板
68‧‧‧引腳
211,311,411,511‧‧‧上表面
212,312,412,512‧‧‧下表面
第1圖舉例顯示一種先前技術晶片封裝1之剖視示意圖。
第2圖顯示本發明的第一個實施例。
第3圖顯示本發明第二個實施例。
第4圖顯示本發明的第三個實施例。
第5A-5E圖顯示本發明的第四個實施例。
第6圖顯示本發明的第五個實施例。
本發明中的圖式均屬示意,主要意在表示製程步驟以及各層之間之上下次序關係,至於形狀、厚度與寬度則並未依照比例繪製。
請參閱第2圖,顯示本發明的第一個實施例。第2圖顯示晶片封裝2之剖視示意圖。如第2圖所示,晶片封裝2例如但不限於為一種影像感測電路的晶片級封裝。晶片封裝2包含:半導體晶片21、金屬導熱層21a、銲墊22、空腔牆23、光學玻璃24、導電墊25、電導線26、內部焊接布局層27、焊球28、以及外部焊接布局層29。其中,半導體晶片21具
有相對之上表面211與下表面212;且銲墊22形成於上表面211上,用以電連接至半導體晶片21中之電路。(在本實施例圖中半導體晶片21具有電路的一面朝下、基板的一面朝上,因一般慣稱具有電路的一面為上方,故將圖中的下方表面稱為上表面211。)光學影像訊號穿過光學玻璃24,由空腔牆23所形成的空腔,進入半導體晶片21。藉由半導體晶片21中的電路操作,將光學影像訊號轉換為電子訊號後,由銲墊22經由導電墊25、電導線26與焊球28,傳送至印刷電路板(未示出)。須說明的是,在不同方式的晶片封裝中,焊球28亦可以為引腳的形式,而不限於如圖中所示之焊球28。
本實施例與先前技術的不同,主要在於金屬導熱層21a形成於下表面212上,用以吸收半導體晶片21所產生之熱量,以降低半導體晶片21中的電路溫度,提升電路的效能。
另須說明的是,金屬導熱層21a較佳但不限於如圖所示,完全覆蓋下表面212,如此一來,可以將散熱的效果最佳化,此外,對影像感測電路的晶片級封裝來說,可加強影像感測訊號,並提供均勻的背景訊號,此亦為本發明優於先前技術之處。
請參閱第3圖,顯示本發明的第二個實施例。第3圖顯示晶片封裝3之剖視示意圖。如第3圖所示,晶片封裝3例如但不限於為一種影像感測電路的晶片級封裝。晶片封裝3包含:半導體晶片31、金屬導熱層31a、金屬導熱帶31b、銲墊32、空腔牆33、光學玻璃34、導電墊35、電導線36、內部焊接布局層37、焊球38與38a、以及外部焊接布局層39。其中,半導體晶片31具有相對之上表面311與下表面312;且銲墊32形成於上表面311上,用以電連接至半導體晶片31中之電路。光學影像訊號穿過光學玻璃34,由空腔牆23所形成的空腔,進入半導體晶片31。藉由半導體晶片31中的電路操作,將光學影像訊號轉換為電子訊號後,由銲墊32經由導電墊35、電導線36與焊球38與38a,傳送至印刷電路板(未示出)。
本實施例與第一個實施例不同之處在於,晶片封裝3更包含金屬導熱帶31b,其與金屬導熱層31a連接,且透過導電墊35與電導線36,連接至其中一個或多個焊球38(圖示數目與位置僅是舉例,可為不同的數目與位置)。半導體晶片3中之電路所產生的熱量,藉由金屬導熱層31a、
金屬導熱帶31b、導電墊35、電導線36,傳導至焊球38,由於金屬導熱層31a、金屬導熱帶31b、導電墊35、電導線36、與焊球38皆為金屬,也是熱的良導體,故電路所產生的熱量可傳導至外部散逸。須說明的是,在不同方式的晶片封裝中,焊球38與38a亦可以為引腳的形式,而不限於如圖中所示之焊球38與38a。另外,金屬導熱層31a、金屬導熱帶31b、導電墊35、電導線36、與焊球38可具有相同電位,一種較佳的方式為,將其電連接至接地電位,不但可以改善散熱效果,亦可以改善電路中,接地電位的穩定性。
請參閱第4圖,顯示本發明的第三個實施例。第4圖顯示晶片封裝4之剖視示意圖。如第4圖所示,晶片封裝4例如但不限於為一種影像感測電路的晶片級封裝。晶片封裝4包含:半導體晶片41、金屬導熱層41a、金屬導熱帶41b、銲墊42、空腔牆43、光學玻璃44、導電墊45、電導線46、內部焊接布局層47、焊球48與48a、以及外部焊接布局層49。其中,半導體晶片41具有相對之上表面411與下表面412;且銲墊42形成於上表面411上,用以電連接至半導體晶片41中之電路。光學影像訊號穿過光學玻璃44,由空腔牆43所形成的空腔,進入半導體晶片41。藉由半導體晶片41中的電路操作,將光學影像訊號轉換為電子訊號後,由銲墊42經由導電墊45、電導線46與焊球48與48a,傳送至印刷電路板(未示出)。
本實施例與第二個實施例不同之處在於,晶片封裝4中之金屬導熱帶41b,其與金屬導熱層41a連接,但不經由導電墊45而直接由電導線46連接至一個或多個焊球48(圖示數目與位置僅是舉例,可為不同的數目與位置)。本實施例旨在說明金屬導熱帶與焊球或引腳有多種的連接形式,而不限於如第3圖所示之方式。且在此實施例中,由於焊球48不必須與導電墊45連接,因此焊球48不必須具有電性上的功能。
第5A-5E圖顯示本發明的第四個實施例。本實施例顯示另一種晶片封裝5的製造方法之剖視示意圖。如第5A圖所示,首先提供半導體晶片51,半導體晶片51具有相對之上表面511與下表面512。接著請參閱第5B圖,於下表面512上,形成金屬導熱層51a,與半導體晶片51連接,用以吸收半導體晶片51所產生之熱量。接著,如第5C圖所示,形成
銲墊52於上表面511上,用以電連接至半導體晶片51中之電路。接著於上表面511上,形成保護層53與第一絕緣層54。接下來如第5D圖所示,於第一絕緣層54上,形成電導線56。接著如第5E圖所示,於電導線56上,形成第二絕緣層57,然後形成焊球58與電導線56電連接。本實施例旨在說明根據本發明之晶片封裝5的製作方法,並舉例示出金屬導熱層亦可以如本實施例所示,相對焊球位於半導體晶片51之不同側,也就是說,本實施例與前述之實施例不同,焊球58可位於上表面511上,而非位於下表面512上,以此說明本實施例可應用於各種晶片封裝架構。
請參閱第6圖,顯示本發明的第五個實施例。本實施例顯示晶片封裝6之剖視示意圖。如第6圖所示,導線架60包含複數引腳68(lead),利用打線(wire bond)技術,將引腳68分別經由複數電導線63電性連接至半導體晶片61上之銲墊62,進而電連接至半導體晶片61中之電路。如圖所示,金屬導熱層61a形成於半導體晶片61之下表面上,並黏著於導線架60中之晶片模板65(die paddle)上,經過打線後,半導體晶片61經由電導線63電性連接至導線架60中之引腳68;接著以封膠層64封膠(molding)半導體晶片61、導線架60、與電導線63,就完成晶片封裝6。接著,將引腳68固定於電路板66上,就可使此晶片封裝6成為電路板66上電路的一部分。
本實施例旨在說明,本發明亦可以應用於具有引腳之另一種晶片封裝的形式,並將半導體晶片61所產生的熱量,經由金屬導熱層61a,傳導至晶片模板65,或亦可透過其他連接方式(例如但不限於直通矽穿孔,TSV),傳導至銲墊62與引腳68。
以上已針對較佳實施例來說明本發明,唯以上所述者,僅係為使熟悉本技術者易於了解本發明的內容而已,並非用來限定本發明之權利範圍。在本發明之相同精神下,熟悉本技術者可以思及各種等效變化。例如,雖然在一些實施例中半導體晶片以影像感測電路晶片為例,但本發明不限於此,亦可應用在其他種類的半導體晶片中;再如,在不影響元件主要的特性下,可加入其他製程步驟或結構,如緩衝層等;又如,金屬導熱層的形成,可於封裝製程中完成,亦可於晶圓製程中完成。本發明的範
圍應涵蓋上述及其他所有等效變化。
2‧‧‧晶片封裝
21‧‧‧半導體晶片
211‧‧‧上表面
212‧‧‧下表面
21a‧‧‧金屬導熱層
22‧‧‧銲墊
23‧‧‧空腔牆
24‧‧‧光學玻璃
25‧‧‧導電墊
26‧‧‧電導線
27‧‧‧內部焊接布局層
28‧‧‧焊球
29‧‧‧外部焊接布局層
Claims (4)
- 一種晶片封裝製造方法,包含:提供一半導體晶片,具有相對之上表面及下表面,該半導體晶片包括一影像感測電路;形成一金屬導熱層於該下表面上,用以吸收該半導體晶片所產生之熱量;形成一銲墊於該上表面上,用以電連接至該半導體晶片中之該影像感測電路形成一空腔牆,與該上表面連接;以及形成一光學玻璃,與該空腔牆連接;其中,一光學影像訊號穿過該光學玻璃,經由該空腔牆所形成的空腔,進入該半導體晶片。
- 如申請專利範圍第1項所述之晶片封裝製造方法,更包含:形成一銲墊,其中該半導體晶片與該銲墊電連接,且該半導體晶片所產生的熱量,經由金屬導熱層,傳導至該銲墊。
- 一種晶片封裝,包含:一半導體晶片,具有相對之上表面及下表面,該半導體晶片包括一影像感測電路;一金屬導熱層,形成於該下表面上,用以吸收該半導體晶片所產生之熱量;一銲墊,形成於該上表面上,用以電連接至該半導體晶片中之該影像感測電路一空腔牆,與該上表面連接;以及一光學玻璃,與該空腔牆連接;其中,一光學影像訊號穿過該光學玻璃,經由該空腔牆所形成的空腔,進入該半導體晶片。
- 一種晶片封裝,包含:一半導體晶片,具有相對之上表面及下表面;一金屬導熱層,形成於該下表面上,用以傳導或吸收該半導體晶片所產生之熱量; 一銲墊,形成於該上表面上,用以電連接至該半導體晶片中之一電路;一金屬導熱帶,與該金屬導熱層連接;以及一焊球或一引腳,與該金屬導熱帶連接,但不與一導電墊連接,該焊球提供散熱的功能而不具有電性上的功能,其中該半導體晶片所產生的熱量,經由該金屬導熱層與該金屬導熱帶,傳導至該焊球或該引腳。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW102103806A TWI553841B (zh) | 2013-01-31 | 2013-01-31 | 晶片封裝及其製造方法 |
US14/163,569 US9142529B2 (en) | 2013-01-31 | 2014-01-24 | Chip package with improved heat dissipation and manufacturing method thereof |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW102103806A TWI553841B (zh) | 2013-01-31 | 2013-01-31 | 晶片封裝及其製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
TW201431053A TW201431053A (zh) | 2014-08-01 |
TWI553841B true TWI553841B (zh) | 2016-10-11 |
Family
ID=51222033
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW102103806A TWI553841B (zh) | 2013-01-31 | 2013-01-31 | 晶片封裝及其製造方法 |
Country Status (2)
Country | Link |
---|---|
US (1) | US9142529B2 (zh) |
TW (1) | TWI553841B (zh) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TW201607014A (zh) * | 2014-08-08 | 2016-02-16 | 精材科技股份有限公司 | 半導體結構及其製造方法 |
CN107068611A (zh) * | 2016-12-23 | 2017-08-18 | 苏州能讯高能半导体有限公司 | 半导体芯片、半导体晶圆及半导体晶圆的制造方法 |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20060171698A1 (en) * | 2005-02-01 | 2006-08-03 | Samsung Electro-Mechanics Co., Ltd. | Chip scale image sensor module and fabrication method of same |
TWI285945B (en) * | 2002-10-02 | 2007-08-21 | Advanced Semiconductor Eng | Thermal-enhance semiconductor package and manufacturing method thereof |
US7372122B2 (en) * | 2004-11-01 | 2008-05-13 | Dongbu Electronics Co., Ltd. | Image sensor chip package and method of fabricating the same |
Family Cites Families (21)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2003078347A2 (en) | 2002-03-13 | 2003-09-25 | W.R. Grace & Co.-Conn | Beneficiated water reducing compositions |
US7576425B2 (en) * | 2007-01-25 | 2009-08-18 | Xintec, Inc. | Conducting layer in chip package module |
JP2010245121A (ja) * | 2009-04-01 | 2010-10-28 | Toshiba Corp | 半導体装置 |
CN102244047B (zh) * | 2010-05-11 | 2015-09-23 | 精材科技股份有限公司 | 晶片封装体及其形成方法 |
US9437478B2 (en) * | 2010-05-11 | 2016-09-06 | Xintec Inc. | Chip package and method for forming the same |
TWI437700B (zh) * | 2010-05-31 | 2014-05-11 | Kingpak Tech Inc | 晶圓級影像感測器構裝結構之製造方法 |
US8692358B2 (en) * | 2010-08-26 | 2014-04-08 | Yu-Lung Huang | Image sensor chip package and method for forming the same |
JP5573645B2 (ja) * | 2010-12-15 | 2014-08-20 | 富士通セミコンダクター株式会社 | 半導体装置及び半導体装置の製造方法 |
US8742564B2 (en) * | 2011-01-17 | 2014-06-03 | Bai-Yao Lou | Chip package and method for forming the same |
US8900913B2 (en) * | 2011-08-19 | 2014-12-02 | Chuan-Jin Shiu | Chip package and method for forming the same |
US8810012B2 (en) * | 2011-11-15 | 2014-08-19 | Xintec Inc. | Chip package, method for forming the same, and package wafer |
CN103107153B (zh) * | 2011-11-15 | 2016-04-06 | 精材科技股份有限公司 | 晶片封装体及其形成方法 |
US8872196B2 (en) * | 2011-12-19 | 2014-10-28 | Xintec Inc. | Chip package |
US9768223B2 (en) * | 2011-12-21 | 2017-09-19 | Xintec Inc. | Electronics device package and fabrication method thereof |
US8780561B2 (en) * | 2012-03-30 | 2014-07-15 | Raytheon Company | Conduction cooling of multi-channel flip chip based panel array circuits |
US20140048950A1 (en) * | 2012-08-14 | 2014-02-20 | Bridge Semiconductor Corporation | Thermally enhanced semiconductor assembly with embedded semiconductor device and built-in stopper and method of making the same |
US20140063742A1 (en) * | 2012-08-28 | 2014-03-06 | Freescale Semiconductor, Inc. | Thermally Enhanced Electronic Component Packages with Through Mold Vias |
TWI512930B (zh) * | 2012-09-25 | 2015-12-11 | Xintex Inc | 晶片封裝體及其形成方法 |
US9484313B2 (en) * | 2013-02-27 | 2016-11-01 | Advanced Semiconductor Engineering, Inc. | Semiconductor packages with thermal-enhanced conformal shielding and related methods |
US9691809B2 (en) * | 2013-03-14 | 2017-06-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Backside illuminated image sensor device having an oxide film and method of forming an oxide film of a backside illuminated image sensor device |
KR20140115668A (ko) * | 2013-03-21 | 2014-10-01 | 삼성전자주식회사 | 방열판과 수동 소자를 갖는 반도체 패키지 |
-
2013
- 2013-01-31 TW TW102103806A patent/TWI553841B/zh active
-
2014
- 2014-01-24 US US14/163,569 patent/US9142529B2/en active Active
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI285945B (en) * | 2002-10-02 | 2007-08-21 | Advanced Semiconductor Eng | Thermal-enhance semiconductor package and manufacturing method thereof |
US7372122B2 (en) * | 2004-11-01 | 2008-05-13 | Dongbu Electronics Co., Ltd. | Image sensor chip package and method of fabricating the same |
US20060171698A1 (en) * | 2005-02-01 | 2006-08-03 | Samsung Electro-Mechanics Co., Ltd. | Chip scale image sensor module and fabrication method of same |
Also Published As
Publication number | Publication date |
---|---|
TW201431053A (zh) | 2014-08-01 |
US9142529B2 (en) | 2015-09-22 |
US20140210069A1 (en) | 2014-07-31 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP5081578B2 (ja) | 樹脂封止型半導体装置 | |
TWI543314B (zh) | 半導體封裝物 | |
TWI551198B (zh) | 具散熱功能之印刷電路板結構 | |
JP2009278103A5 (zh) | ||
TW201434121A (zh) | 封裝基板及其製法暨半導體封裝件及其製法 | |
KR20110020548A (ko) | 반도체 패키지 및 그의 제조방법 | |
TWI503935B (zh) | 半導體封裝件及其製法 | |
TWI553841B (zh) | 晶片封裝及其製造方法 | |
CN103354228A (zh) | 半导体封装件及其制造方法 | |
KR101391081B1 (ko) | 플립칩 반도체 패키지 및 그 제조방법 | |
TWI613771B (zh) | 半導體封裝 | |
CN103972187B (zh) | 芯片封装及其制造方法 | |
TWI595616B (zh) | 晶片封裝體及其形成方法 | |
US20100265683A1 (en) | Semiconductor device | |
TWI423405B (zh) | 具載板之封裝結構 | |
TWI428997B (zh) | 半導體封裝結構及其製作方法 | |
JP2010153491A5 (ja) | 電子装置及びその製造方法、並びに半導体装置 | |
TWI553799B (zh) | 半導體封裝結構 | |
TWI466262B (zh) | 電磁干擾遮蔽層連接至接地訊號之導線架型半導體封裝構造 | |
TW201304099A (zh) | 晶片封裝體 | |
TWI413232B (zh) | 多晶片封裝結構 | |
TWI643297B (zh) | 具有內置散熱片之半導體封裝構造 | |
TWI485824B (zh) | 封裝結構 | |
JP2012256935A (ja) | 樹脂封止型半導体装置 | |
TWI553805B (zh) | 半導體封裝件之製法 |