TWI553816B - 半導體元件以及在半導體晶粒上配置預先製造的遮蔽框架的方法 - Google Patents

半導體元件以及在半導體晶粒上配置預先製造的遮蔽框架的方法 Download PDF

Info

Publication number
TWI553816B
TWI553816B TW099106840A TW99106840A TWI553816B TW I553816 B TWI553816 B TW I553816B TW 099106840 A TW099106840 A TW 099106840A TW 99106840 A TW99106840 A TW 99106840A TW I553816 B TWI553816 B TW I553816B
Authority
TW
Taiwan
Prior art keywords
semiconductor die
semiconductor
frame
encapsulant
die
Prior art date
Application number
TW099106840A
Other languages
English (en)
Other versions
TW201044540A (en
Inventor
瑞莎Ａ 派蓋菈
杜雍台
迪歐斯可洛Ａ 馬力羅
Original Assignee
史達晶片有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 史達晶片有限公司 filed Critical 史達晶片有限公司
Publication of TW201044540A publication Critical patent/TW201044540A/zh
Application granted granted Critical
Publication of TWI553816B publication Critical patent/TWI553816B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/20—Structure, shape, material or disposition of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45139—Silver (Ag) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45147—Copper (Cu) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45155—Nickel (Ni) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1035—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1041—Special adaptations for top connections of the lowermost container, e.g. redistribution layer, integral interposer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047—Details of electrical connections between containers
    • H01L2225/1058—Bump or bump-like electrical connections, e.g. balls, pillars, posts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1094—Thermal management, e.g. cooling
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0103—Zinc [Zn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01073—Tantalum [Ta]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01074—Tungsten [W]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097—Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701—Low temperature co-fired ceramic [LTCC]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12041—LED
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1433—Application-specific integrated circuit [ASIC]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15172—Fan-out arrangement of the internal vias
    • H01L2924/15174—Fan-out arrangement of the internal vias in different layers of the multilayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
    • H01L2924/15331—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19042—Component type being an inductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19043—Component type being a resistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30105—Capacitance
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Health & Medical Sciences (AREA)
  • Electromagnetism (AREA)
  • Toxicology (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)

Description

半導體元件以及在半導體晶粒上配置預先製造的遮蔽框架的方法
本發明概括關於半導體元件，且尤指一種半導體元件以及在半導體晶粒上配置預先製造的遮蔽框架以隔離電磁干擾(EMI，electromagnetic interference)與射頻干擾(RFI，radio frequency interference)或其他元件間干擾的方法。
半導體元件常見於現代電子產品。半導體元件為於電氣構件的數目與密度而變化。離散的半導體元件通常含有一個型式的電氣構件，例如：發光二極體(LED，light emitting diode)、電晶體、電阻器、電容器、電感器與功率(power)金屬氧化物半導體場效電晶體(MOSFET，metal oxide semiconductor field effect transistor)。積體的半導體元件典型為含有數百個到數百萬個電氣構件。積體的半導體元件之實例包括：微控制器、微處理器、電荷耦合元件(CCD，charge-coupled device)、太陽能電池與數位微鏡元件(DMD，digital micro-mirror device)。
半導體元件實行廣泛範圍的作用，諸如：高速計算、傳送及接收電磁訊號、控制電子元件、轉變陽光為電力及產生視覺投影以供電視顯像。半導體元件可見於娛樂、通訊、發電、網路、電腦與消費產品之領域。半導體元件亦可見於其包括軍事、航空、汽車、工業控制器與辦公室設備之電子產品。
半導體元件利用半導體材料的電氣性質。半導體材料的原子結構允許其導電性為藉由電場施加或透過摻雜過程而操縱。摻雜為引入雜質至半導體材料以操縱及控制半導體元件的導電性。
一種半導體元件含有主動與被動的電氣結構。主動結構(包括：電晶體)控制電流之流通。藉由改變摻雜位準及電場施加，電晶體促進或限制電流之流通。被動結構(包括：電阻器、二極體與電感器)建立於電壓與電流之間的一種關係，其為必要以實行種種電氣作用。被動與主動結構電氣連接以形成電路，致使半導體元件為能夠實行高速計算與其他有用的作用。
半導體元件通常運用二個複雜的製程所製造，即：前段(front-end)製造與後段(back-end)製造，各者涉及潛在為數百個步驟。前段製造涉及於半導體晶圓表面的複數個晶粒之形成。各個晶粒典型為相同且含有其藉由電氣連接主動與被動構件所形成的電路。後段製造涉及自所完成的晶圓以單一化個別的晶粒且封裝該晶粒以提供結構支撐與環境隔離。
半導體製造之一個目標為產生較小的半導體元件。較小的元件典型為消耗較少的功率，具有較高的性能，且可為較有效率製造。此外，較小的半導體元件具有較小的使用空間，其針對於較小的最終產品為合意。較小晶粒尺寸可由於前段製程之改良而達成，造成其具有較小、較高密度的主動與被動構件之晶粒。後段製程可由於電氣互連與封裝材料之改良而造成其具有較小的使用空間之半導體元件封裝。
於高頻的應用，諸如：射頻(RF，radio frequency)無線通訊，積體被動元件(IPD，integrated passive device)經常包含於半導體元件之內。IPD之實例包括：電阻器、電容器與電感器。一種典型的射頻系統需要於一或多個半導體封裝之多個IPD以實行必要的電氣作用。然而，高頻的電氣元件產生不期望的電磁干擾(EMI)、射頻干擾(RFI)與其他的元件間干擾，諸如：電容、電感或電導耦合，亦習稱為串音(cross-talk)，此將干擾於相鄰電路元件之操作。
於堆疊半導體封裝與外部元件之間的垂直電氣互連可藉著傳導的矽通孔(TSV，through silicon via)或通孔(THV，through hole via)而達成。THV藉由鑽孔穿過囊封物且將諸孔填充導體而形成於環繞元件的周圍區域中。垂直傳導柱亦可在囊封之前而形成於周圍區域中。二種垂直互連技術耗費製造時間與費用。
對於提供垂直電氣互連且進而隔離半導體晶粒為免於電磁干擾(EMI)、射頻干擾(RFI)與其他元件間干擾的需要為存在。是以，於一個實施例，本發明為一種製造半導體元件的方法，包含步驟：提供一預先製造的遮蔽框架；提供一犧牲性(sacrificial)基板；安裝一半導體晶粒至犧牲性基板；安裝遮蔽框架在半導體晶粒與犧牲性基板之上；透過遮蔽框架而沉積一囊封物為環繞半導體晶粒；及，移除遮蔽框架的一第一部分以暴露囊封物。移除遮蔽框架的第一部分以保留遮蔽框架的一第二部分在半導體晶粒之上而作為免於干擾之遮蔽。該種方法更包括步驟：形成一第一互連結構在半導體晶粒、遮蔽框架的第二部分與囊封物的一第一側之上；移除犧牲性基板；及，形成一第二互連結構在半導體晶粒與其相對於囊封物的第一側之囊封物的一第二側之上。
於另一個實施例，本發明為一種製造半導體元件的方法，包含步驟：提供一預先製造的遮蔽框架；提供一犧牲性基板；安裝一半導體晶粒至犧牲性基板；安裝遮蔽框架在半導體晶粒與犧牲性基板之上；透過遮蔽框架而沉積一囊封物為環繞半導體晶粒；及，移除遮蔽框架的一第一部分以暴露囊封物。移除遮蔽框架的第一部分以保留遮蔽框架的一第二部分在半導體晶粒之上而作為免於干擾之遮蔽。該種方法更包括步驟：形成一第一互連結構在半導體晶粒、遮蔽框架的第二部分與囊封物的一第一側之上。
於另一個實施例，本發明為一種製造半導體元件的方法，包含步驟：提供一預先製造的遮蔽框架；安裝遮蔽框架在一半導體晶粒之上；透過遮蔽框架而沉積一囊封物為環繞半導體晶粒；及，移除遮蔽框架的一第一部分以暴露囊封物而保留遮蔽框架的一第二部分在半導體晶粒之上。
於另一個實施例，本發明為一種半導體元件，其包含一半導體晶粒及安裝在半導體晶粒之上的預先製造的遮蔽框架。一囊封物沉積為環繞半導體晶粒。一第一互連結構形成在囊封物的一第一側、遮蔽框架與半導體晶粒之上。
本發明參考圖式而描述於以下說明的一或多個實施例，其中，同樣的參考符號代表相同或類似元件。儘管本發明依據用於達成本發明的目標之最佳模式而描述，將為熟悉此技術人士所理解的是：意圖以涵蓋如可為納入於由隨附的申請專利範圍與以下揭露內容與圖式所支持的其等效者所界定之本發明的精神與範疇內的替代、修改與等效者。
半導體元件通常運用二個複雜的製程所製造：前段製造與後段製造。前段製造涉及於半導體晶圓表面的複數個晶粒之形成。於晶圓上的各個晶粒含有主動與被動的電氣構件，其為電氣連接以形成作用的電路。主動電氣構件(諸如：電晶體)具有能力以控制電流之流通。被動電氣構件(諸如：電容器、電感器、電阻器與變壓器)建立於電壓與電流之間的一種關係，其為必要以實行電路作用。
被動與主動構件藉由其包括摻雜、沉積、光刻、蝕刻與平面化之一連串的處理步驟而形成於半導體晶圓的表面上。摻雜為藉由諸如離子植入或熱擴散之技術而引入雜質至半導體材料。摻雜過程修改於主動元件之半導體材料的導電性，轉變半導體材料成為一種永久的絕緣體、永久的導體，或響應於電場而改變半導體材料的導電性。電晶體含有變化型式與摻雜程度的區域，其隨著必要而配置以致使電晶體為能夠於電場施加時而促進或限制電流的流通。
主動與被動構件為由具有不同的電氣性質之數層材料所形成。諸層可藉由其部分為所沉積的材料型式所決定之種種沉積技術所形成。舉例而言，薄膜沉積可能涉及化學汽相沉積(CVD，chemical vapor deposition)、物理汽相沉積(PVD，physical vapor deposition)、電解電鍍及無電電鍍過程。各層通常為圖案化以形成部分的主動構件、被動構件或於構件之間的電氣連接。
諸層可運用光刻法所圖案化，光刻法涉及例如光阻的光敏材料之沉積於將作圖案化之層上。一圖案(pattern)運用光線而轉移自一光罩至光阻。受到光線之光阻圖案部分運用一種溶劑所移除，暴露將作圖案化之下面層的部分者。移除光阻的其餘部分，留下一圖案化層。或者是，一些型式的材料藉由直接沉積材料至其運用諸如無電及電解電鍍法的技術之一種先前沉積/蝕刻過程所形成的區域或空隙而圖案化。
沉積一薄膜的材料於現存的圖案上可能擴大在下面的圖案且產生一不均勻平坦表面。一均勻平坦表面需要以產生較小且較密集封裝的主動與被動構件。平面化可運用以移除自晶圓表面的材料且產生一均勻平坦表面。平面化涉及磨光晶圓表面為具有一磨光墊。一種研磨材料與腐蝕化學製品為於磨光期間而添加至晶圓表面。研磨料的機械作用與化學製品的腐蝕作用之組合者移除任何不規則的拓撲結構，造成一均勻平坦表面。
後段製造是指將所完成的晶圓切割或單一化成為個別的晶粒且接著封裝該晶粒以供結構支撐與環境隔離。欲將晶粒單一化，晶圓沿著稱為鋸道或劃線之晶圓的非作用區域而刻劃及切斷。晶圓運用一種雷射切割裝置或鋸條而單一化。在單一化之後，個別晶粒安裝至一封裝基板，其包括接腳或接觸墊以供互連於其他的系統構件。形成在半導體晶粒之上的接觸墊接著連接至於封裝內的接觸墊。電氣連接可藉著焊塊、柱塊、導電糊膏或線接合而作成。一種囊封物或其他的模製材料沉積於封裝之上以提供實際支撐與電氣隔離。完成的封裝接著***至一種電氣系統且該半導體元件的功能性成為可用於其他的系統構件。
圖1為說明電子元件10，其具有一晶片載體基板或印刷電路板(PCB，printed circuit board) 12，印刷電路板12具有安裝於其表面之複數個半導體封裝。電子元件10可具有一個型式的半導體封裝、或多個型式的半導體封裝，視應用而定。不同型式的半導體封裝為了說明而顯示於圖1。
電子元件10可為一種獨立系統，其運用該等半導體封裝以實行一種電氣作用。或者是，電子元件10可為一較大系統的一個子構件。舉例而言，電子元件10可為一圖形卡、網路介面卡或其可為***至電腦之其他的訊號處理卡。半導體封裝可包括：微處理器、記憶體、特定應用積體電路(ASIC，application specific integrated circuit)、邏輯電路、類比電路、射頻電路、離散元件或其他的半導體晶粒或電氣構件。
於圖1，PCB 12提供一種通用的基板以供其安裝於PCB的半導體封裝之結構支撐及電氣互連。傳導訊號線跡14運用蒸鍍、電解電鍍、無電電鍍、網印、PVD或其他適合金屬沉積過程而形成在PCB 12的一表面上或於PCB 12的諸層內。訊號線跡14提供於各個半導體封裝、安裝構件與其他外部系統構件之間的電氣連通。線跡14亦提供對於各個半導體封裝之電力與接地連接。
於一些實施例，一種半導體元件具有二個封裝階層。第一階層封裝為用於機械及電氣式附接半導體晶粒至一載體的一種技術。第二階層封裝涉及：機械及電氣式附接該載體至PCB。於其他實施例，一種半導體元件可僅具有第一階層封裝，其中，該晶粒為機械及電氣式直接安裝至PCB。
為了說明，數個型式的第一階層封裝顯示於PCB 12，包括：線接合封裝16與倒裝晶片18。此外，數個型式的第二階層封裝顯示為安裝於PCB 12，包括：球柵陣列(BGA，ball grid array) 20、塊形晶片載體(BCC，bump chip carrier) 22、雙列直插封裝(DIP，dual in-line package) 24、岸柵陣列(LGA，land grid array) 26、多晶片模組(MCM，multi-chip module) 28、四面扁平無引線封裝(QFN，quad flat non-leaded package) 30與四面扁平封裝32。視系統需求而定，任何組合的第一與第二階層封裝型式所構成之任何組合的半導體封裝以及其他的電子構件可連接至PCB 12。於一些實施例，電子元件10包括單一個附接的半導體封裝，而其他實施例為需要多個互連的封裝。藉由組合一或多個半導體封裝在單一個基板之上，製造業者可將事先作成的構件納入至電子元件及系統。因為半導體封裝包括複雜的功能性，電子元件可運用較便宜的構件及一種有效率的製程所製造。造成的元件為較不可能失效且較不昂貴以製造，造成對於消費者之較低的成本。
圖2a說明其安裝於PCB 12之DIP 24的進一步細節。DIP 24包括其具有接觸墊36之半導體晶粒34。半導體晶粒34包括：一主動區域，其含有類比或數位電路而實施為主動元件、被動元件、傳導層與介電層，形成於半導體晶粒34之內且為根據晶粒的電氣設計而電氣互連。舉例而言，該電路可包括：一或多個電晶體、二極體、電感器、電容器、電阻器與其形成於晶粒34之主動區域內的其他電路元件。接觸墊36為以一種傳導材料所作成，諸如：鋁(Al)、銅(Cu)、錫(Sn)、鎳(Ni)、金(Au)或銀(Ag)，且為電氣連接至其形成於晶粒34之內的電路元件。接觸墊36藉由PVD、CVD、電解電鍍或無電電鍍過程所形成。於DIP 24之組裝期間，半導體晶粒34運用一種金-矽的共熔層或諸如熱環氧化物的黏著材料而安裝至一載體38。封裝本體包括一種絕緣封裝材料，諸如：聚合物或陶瓷。導體引線40連接至載體38且線接合42形成於引線40與晶粒34的接觸墊36之間而作為一第一階層封裝。囊封物44沉積在封裝上以供環境保護，藉由阻止濕氣與微粒而免於進入封裝及污染晶粒34、接觸墊36、或線接合42。DIP 24藉由***引線40至其形成穿過PCB 12的孔而連接至PCB 12。焊料46流通環繞引線40且進入孔以實際及電氣式連接DIP 24至PCB 12。焊料46可為任何的金屬或導電材料，例如：Sn、鉛(Pb)、Au、Ag、Cu、鋅(Zn)、鉍(Bi)與其合金，具有一種選用的助熔材料。舉例而言，焊料可為共熔Sn/Pb、高鉛或無鉛。
圖2b說明其安裝於PCB 12之BCC 22的進一步細節。半導體晶粒47藉由線接合型式的第一階層封裝而連接至一載體。BCC 22以一種BCC型式的第二階層封裝而安裝至PCB 12。具有接觸墊48之半導體晶粒47運用一種底部填充(underfill)或環氧樹脂的黏著材料50而安裝在一載體上。半導體晶粒47為包括：一主動區域，其含有類比或數位電路而實施為主動元件、被動元件、傳導層與介電層，形成於半導體晶粒47之內且為根據晶粒的電氣設計而電氣互連。舉例而言，該電路可包括：一或多個電晶體、二極體、電感器、電容器、電阻器與其形成於晶粒47之主動區域內的其他電路元件。接觸墊48以一種傳導材料所作成，諸如：Al、Cu、Sn、Ni、Au或Ag，且為電氣連接至其形成於晶粒47之內的電路元件。接觸墊48藉由PVD、CVD、電解電鍍或無電電鍍過程所形成。線接合54及接合墊56與58電氣連接半導體晶粒47的接觸墊48至BCC 22的接觸墊52而形成第一階層封裝。模製化合物或囊封物60沉積在半導體晶粒47、線接合54、接觸墊48與接觸墊52之上，以提供針對於該元件的實際支撐及電氣隔離。接觸墊64運用蒸鍍、電解電鍍、無電電鍍、網印、PVD或其他適合金屬沉積過程而形成在PCB 12之一表面上且典型為電鍍以防止氧化。接觸墊64電氣連接至一或多個傳導訊號線跡14。焊料沉積於BCC 22的接觸墊52與PCB 12的接觸墊64之間。焊料回流以形成凸塊66，其形成於BCC 22與PCB 12之間的機械及電氣連接。
於圖2c，半導體晶粒18以一種倒裝晶片型式的第一階層封裝而安裝為面對朝下至載體76。BGA 20以一種BGA型式的第二階層封裝而附接至PCB 12。主動區域70含有類比或數位電路而實施為主動元件、被動元件、傳導層與介電層，形成於半導體晶粒18之內且為根據晶粒的電氣設計而電氣互連。舉例而言，該電路可包括：一或多個電晶體、二極體、電感器、電容器、電阻器與其形成於半導體晶粒18的主動區域70之內的其他電路元件。半導體晶粒18透過大量個別傳導焊塊或球78而電氣及機械式附接至載體76。焊塊78形成在其配置於主動區域70的凸塊墊或互連位置80之上。凸塊墊80以一種傳導材料所作成，諸如：Al、Cu、Sn、Ni、Au或Ag，且為電氣連接至其形成於主動區域70的電路元件。凸塊墊80藉由PVD、CVD、電解電鍍或無電電鍍過程所形成。焊塊78藉由一種焊料回流過程而電氣及機械式連接至於載體76的接觸墊或互連位置82。
BGA 20藉由大量個別傳導焊塊或球86而電氣及機械式附接至PCB 12。焊塊形成在凸塊墊或互連位置84之上。凸塊墊84透過其路由通過載體76之導線90而電氣連接至互連位置82。接觸墊88運用蒸鍍、電解電鍍、無電電鍍、網印、PVD或其他適合金屬沉積過程而形成在PCB 12之一表面上且典型為電鍍以防止氧化。接觸墊88電氣連接至一或多個傳導訊號線跡14。焊塊86藉由一種焊料回流過程而電氣及機械式連接至於PCB 12的接觸墊或接合墊88。模製化合物或囊封物92沉積在半導體晶粒18與載體76之上，以提供針對於該元件的實際支撐及電氣隔離。倒裝晶片式半導體元件提供自於半導體晶粒18的主動元件至於PCB 12的傳導軌跡之一短的導電路徑，藉以縮小訊號傳播距離、降低電容及改良整體電路性能。於另一個實施例，半導體晶粒18可運用倒裝晶片型式的第一階層封裝且無載體76而機械及電氣式直接附接至PCB 12。
圖3a至3g說明一種形成於一扇出晶圓階層晶片尺度封裝(FO-WLCSP，fan-out wafer level chip scale package)之其具有置放在半導體晶粒上的預先製造的遮蔽層之半導體封裝的過程。於圖3a，一犧牲性的基板或載體100含有暫置或犧牲性的底座材料，諸如：矽、聚合物、聚合複合物、金屬、陶瓷、玻璃、玻璃環氧化物、氧化鈹、或用於結構支撐之其他適合的低成本、剛性的材料或塊狀半導體材料。
一介面層102為以熱或光能釋放的暫時接合膜而施加至載體100。介面層102可為具有濕式蝕刻選擇性之一或多層的二氧化矽(SiO2)、氮化矽(Si3N4)、氮氧化矽(SiON)、有機膜或金屬膜。介面層102運用疊合、PVD、CVD、印製、旋轉塗覆、噴灑塗覆、燒結或熱氧化而沉積。介面層102可為一暫時的接合膜或蝕刻阻止層。
半導體晶粒104安裝至介面層102。各個半導體晶粒104包括類比或數位電路，其實施為形成於頂側主動表面106且根據晶粒的電氣設計而電氣互連之主動與被動元件、傳導層與介電層。舉例而言，該電路可包括：一或多個電晶體、二極體與形成於主動表面106之內的其他電路元件，以實施基頻數位電路，諸如：數位訊號處理器(DSP，digital signal processor)、記憶體或其他訊號處理電路。半導體晶粒104亦可含有用於射頻(RF)訊號處理之積體被動元件(IPD)，諸如：電感器、電容器與電阻器。接觸墊108電氣連接至於半導體晶粒104的主動表面106之內的主動與被動元件與訊號線跡。
於半導體晶粒104的IPD提供針對於高頻應用所需的電氣特性，諸如：共振器、高通濾波器、低通濾波器、帶通濾波器、對稱高品質(Hi-Q)共振變壓器、匹配網路與調諧電容器。IPD可運用作為前端的無線射頻構件，其可定位於天線與收發器之間。IPD電感器可為其操作於高達100千兆赫茲(GHz)之一種高品質的平衡-不平衡轉換器(balun)、變壓器或線圈。於一些應用，多個平衡-不平衡轉換器形成於同一個基板，允許多頻帶的操作。舉例而言，二或多個平衡-不平衡轉換器運用於針對於行動電話或其他的全球行動通訊系統(GSM，global system for mobile communication)之一四頻帶(quad-band)，各個平衡-不平衡轉換器專用於四頻帶元件之一個頻帶的操作。
一種典型射頻(RF)系統需要於一或多個半導體封裝之多個IPD與其他高頻電路以實行必要的電氣作用。高頻電氣元件產生或易感受到不期望的電磁干擾(EMI)、射頻干擾(RFI)或其他的元件間干擾，諸如：電容、電感或傳導耦合，亦習稱為串音(cross-talk)，其可能干擾相鄰或附近的電路元件之操作。
欲降低元件間的干擾，一預先製造的遮蔽框架110安裝在半導體晶粒104與介面層102之上，如於圖3a與3b所示。遮蔽框架110包括一平板111及複數個本體114a-114f，其整合於板111且由腔部116所分開。本體114a、114c、114d與114f為充分厚以朝下延伸至介面層102。本體114a、114c、114d與114f將成為傳導柱，如下所述。本體114b與114e相較於本體114a、114c、114d與114f為較薄以容納半導體晶粒104。複數個開口112形成通過板111至腔部116。遮蔽框架110可為Cu、Al、鐵氧體或羰基鐵、不銹鋼、鎳銀、低碳鋼、矽鐵鋼、箔片、環氧化物、傳導樹脂及其能夠阻斷或吸收EMI、RFI與其他干擾的其他金屬與複合物。遮蔽框架110亦可為一非金屬材料，諸如：碳黑或鋁薄片，以降低EMI與RFI的效應。遮蔽框架110的本體114b與114e接觸相對於主動表面106之半導體晶粒104的一背表面。在安裝遮蔽框架110之前，一選用式的黏著或熱介面材料可施加至半導體晶粒104的背表面。
圖3c顯示一種囊封物或模製化合物118為運用一種糊膏印製、壓縮模製、轉移模製、液體囊封物模製、真空疊合或其他適合施加器而沉積在半導體晶粒104與介面層102之上。囊封過程透過開口112而將囊封物118為散佈至遮蔽框架110之下方的腔部116。囊封物118可為聚合物複合材料，諸如：具有填料的環氧樹脂、具有填料的環氧丙烯酸酯或具有適當填料的聚合物。囊封物118為非傳導性且環境保護半導體元件為免於外部元件與污染物的損害。
於圖3d，研磨機120移除其包括板111之遮蔽框架110的一部分而朝下至開口112，以暴露於腔部116之囊封物118。遮蔽框架110的本體114b與114e維持在半導體晶粒104的背表面之上，以提供針對於晶粒之期望的EMI與RFI隔離。半導體晶粒104之間的遮蔽框架110的其餘部分成為用於垂直z方向的互連之傳導柱或樁114a、114c、114d與114f。
於圖3e，一頂側建立的互連結構124形成在囊封物118、遮蔽框架110的本體114b與114e及傳導柱114a、114c、114d與114f之上。建立的互連結構124包括一導電層126，其運用一種圖案化與沉積過程以片段或部分而形成在遮蔽框架110及傳導柱114a、114c、114d與114f之上。導電層126運用PVD、CVD、電解電鍍、無電電鍍過程或其他適合金屬沉積過程而形成。導電層126可為一或多層的Al、Cu、Sn、Ni、Au、Ag或其他適合導電材料。導電層126的一個部分電氣連接至傳導柱114a、114c、114d與114f。導電層126的其他部分可為電氣共同或電氣隔離，視半導體晶粒的設計與作用而定。
一絕緣或鈍化層128形成在囊封物118、遮蔽框架110的本體114b與114e及導電層126之上。絕緣層128可為一或多層的SiO2、Si3N4、SiON、五氧化二鉭(Ta2O5)、氧化鋁(Al2O3)或其具有類似絕緣與結構性質的其他材料。絕緣層128運用PVD、CVD、印製、旋轉塗覆、噴灑塗覆、燒結或熱氧化而沉積。絕緣層128的一部分藉由一種蝕刻過程而移除以暴露導電層126。
一導電層130運用一種圖案化與沉積過程以片段或部分而形成在絕緣層128與導電層126之上。導電層130可為一或多層的Al、Cu、Sn、Ni、Au、Ag或其他適合導電材料。導電層130的一個部分電氣連接至導電層126。導電層130的其他部分可為電氣共同或電氣隔離，視半導體元件的設計與作用而定。
一絕緣或鈍化層132形成在絕緣層128與導電層130之上。絕緣層132可為一或多層的SiO2、Si3N4、SiON、Ta2O5、Al2O3或其具有類似絕緣與結構性質的其他材料。絕緣層132運用PVD、CVD、印製、旋轉塗覆、噴灑塗覆、燒結或熱氧化而沉積。絕緣層132的一部分藉由一種蝕刻過程而移除以暴露導電層130。
於圖3f，基板100與介面層102藉由化學蝕刻、機械脫落、CMP、機械研磨、熱烘烤、雷射掃描或濕式剝除而移除。一底側建立的互連結構134形成在囊封物118、半導體晶粒104及傳導柱114a、114c、114d與114f之上。建立的互連結構134包括一導電層136，其運用一種圖案化與沉積過程以片段或部分而形成在囊封物118及傳導柱114a、114c、114d與114f之上。導電層136運用PVD、CVD、電解電鍍、無電電鍍過程或其他適合金屬沉積過程而形成。導電層136可為一或多層的Al、Cu、Sn、Ni、Au、Ag或其他適合導電材料。導電層136的一個部分電氣連接至傳導柱114a、114c、114d與114f。導電層136的其他部分可為電氣共同或電氣隔離，視半導體晶粒的設計與作用而定。
一絕緣或鈍化層138形成在囊封物118、半導體晶粒104與導電層136之上。絕緣層138可為一或多層的SiO2、Si3N4、SiON、Ta2O5、Al2O3或其具有類似絕緣與結構性質的其他材料。絕緣層138運用PVD、CVD、印製、旋轉塗覆、噴灑塗覆、燒結或熱氧化而沉積。絕緣層138的一部分藉由一種蝕刻過程而移除以暴露導電層136。
一導電層140運用一種圖案化與沉積過程以片段或部分而形成在絕緣層138與導電層136之上。導電層140可為一或多層的Al、Cu、Sn、Ni、Au、Ag或其他適合導電材料。導電層140的一個部分電氣連接至導電層136。導電層140的其他部分可為電氣共同或電氣隔離，視半導體元件的設計與作用而定。
一絕緣或鈍化層142形成在絕緣層138與導電層140之上。絕緣層142可為一或多層的SiO2、Si3N4、SiON、Ta2O5、Al2O3或其具有類似絕緣與結構性質的其他材料。絕緣層142運用PVD、CVD、印製、旋轉塗覆、噴灑塗覆、燒結或熱氧化而沉積。絕緣層142的一部分藉由一種蝕刻過程而移除以暴露導電層140。
一導電焊料運用一種蒸鍍、電解電鍍、無電電鍍、球滴或網印過程而沉積在導電層140之上。焊料可為任何的金屬或導電材料，例如：Sn、Ni、Au、Ag、Pb、Bi與其合金，具有一種選用的助熔材料。舉例而言，焊料可為共熔Sn/Pb、高鉛或無鉛。焊料藉由將材料加熱為高於其熔點而回流以形成圓球或凸塊144。於一些應用，焊塊144回流第二次以改良對於導電層140之電氣接觸。
半導體晶粒104以鋸條或雷射切割裝置146而單一化為個別的半導體元件150，如於圖3g所示。在單一化之後，可堆疊個別的半導體元件150，如於圖4所示。傳導柱114a、114c、114d與114f提供於頂側互連建立層124與底側互連建立層134之間的z互連。導電層126與130透過傳導柱114a與114c而電氣連接至導電層136與140及半導體晶粒104的接觸墊108。遮蔽框架110的本體114b與114e提供針對於半導體晶粒104的隔離而免於EMI、RFI與其他元件間干擾。遮蔽框架110的本體114b與114e可透過互連結構124與134或傳導柱114a、114c、114d與114f而連接至一低阻抗的接地點。遮蔽框架110的本體114b與114e免除需要單獨的EMI遮蔽(如於先前技術所見)，其增加對於製程的時間與成本。遮蔽框架110的本體114b與114e亦提供由半導體晶粒104所產生的熱量之消散。遮蔽框架110的本體114a、114c、114d與114f連接於互連結構124與134之間的傳導柱。
圖5顯示半導體元件的另一個實施例。於此例，半導體元件152包括其形成於半導體晶粒104之矽通孔(TSV)154。矽通孔154藉由蝕刻或鑽孔一通孔為通過半導體晶粒104的矽材料且以Al、Cu、Sn、Ni、Au、Ag、鈦(Ti)、鎢(W)或其他適合導電材料而填充該通孔所形成。遮蔽框架110的本體114b與114e透過矽通孔154而電氣連接至接觸墊108與互連結構134。是以，矽通孔154提供自遮蔽框架110的本體114b與114e為透過接觸墊108與互連結構134至一外部的低阻抗接地點之一傳導路徑。
圖6顯示半導體元件160，其具有方位為面朝上之半導體晶粒104的主動表面106與接觸墊108。接觸墊108透過接合線162而電氣連接至互連結構134。接合線166可為一或多層的Al、Cu、Sn、Ni、Au、Ag或其他適合導電材料。
圖7顯示半導體元件164，其具有形成於互連結構124與134之間的附加遮蔽層166。遮蔽層166可為Cu、Al、不銹鋼、鎳銀、低碳鋼、矽鐵鋼、箔片、環氧化物、傳導樹脂及其能夠阻斷EMI、RFI與其他元件間干擾的其他金屬與複合物。
儘管本發明之一或多個實施例為已經詳細說明，熟悉此技術人士將理解的是：對於彼等實施例的修改與調適可作成而未脫離如以下申請專利範圍所陳述之本發明的範疇。
10．．．電子元件
12．．．印刷電路板
14．．．訊號線跡
16．．．線接合封裝
18．．．倒裝晶片
20．．．球柵陣列
22．．．塊形晶片載體
24．．．雙列直插封裝
26．．．岸柵陣列
28．．．多晶片模組
30．．．四面扁平無引線封裝
32．．．四面扁平封裝
34、47．．．半導體晶粒
36、48、52、64、88．．．接觸墊
38、76．．．載體
40．．．導體引線
42、54．．．線接合
44．．．囊封物
46．．．焊料
50．．．底部填充或環氧樹脂黏著材料
56、58．．．接合墊
60、92．．．模製化合物或囊封物
66．．．凸塊
70．．．主動區域
78、86．．．焊塊或球
80．．．凸塊墊
82．．．接觸墊或互連位置
84．．．凸塊墊或互連位置
90．．．導線
100．．．基板或載體
102．．．介面層
104‧‧‧半導體晶粒
106‧‧‧主動表面
108‧‧‧接觸墊
110‧‧‧遮蔽框架
111‧‧‧平板
112‧‧‧開口
114a-114f‧‧‧本體
116‧‧‧腔部
118‧‧‧囊封物或模製化合物
120‧‧‧研磨機
124、134‧‧‧互連結構
126、130、136、140‧‧‧導電層
128、132、138、142‧‧‧絕緣或鈍化層
144‧‧‧焊塊
146‧‧‧鋸條或雷射切割裝置
150、152、160、164‧‧‧半導體元件
154‧‧‧矽通孔(TSV)
162‧‧‧接合線
166‧‧‧遮蔽層
圖1為說明一種具有安裝於其表面的不同型式的封裝之印刷電路板(PCB)；
圖2a至2c為說明其安裝於PCB的代表的半導體封裝之進一步細節；
圖3a至3g為說明一種在半導體晶粒上形成預先製造的遮蔽框架的方法；
圖4為說明其具有預先製造的遮蔽框架之堆疊式扇出晶圓階層晶片尺度封裝(FO-WLCSP)，遮蔽框架為安裝在半導體晶粒之上且互連於傳導柱；
圖5為說明其具有半導體晶粒之FO-WLCSP，半導體晶粒具有矽通孔(TSV)以將遮蔽框架接地；
圖6為說明其具有接合線之FO-WLCSP，接合線連接於半導體晶粒接觸墊與底側互連結構之間；及
圖7為說明其具有附加遮蔽層之FO-WLCSP，遮蔽層環繞半導體晶粒而形成於頂側與底側的互連結構之間。
104．．．半導體晶粒
106．．．主動表面
108．．．接觸墊
114a-114f．．．本體
118．．．囊封物或模製化合物
124、134．．．互連結構
126、130、136、140．．．導電層
128、132、138、142．．．絕緣或鈍化層
144．．．焊塊
150．．．半導體元件

Claims (15)

  1. 一種製造半導體元件的方法，包含：提供一預先製造的遮蔽框架；提供一犧牲性基板；安裝一半導體晶粒至該犧牲性基板；安裝該遮蔽框架在該半導體晶粒與該犧牲性基板之上；透過該遮蔽框架而沉積一囊封物為環繞該半導體晶粒；移除該遮蔽框架的一第一部分以暴露該囊封物，其中，移除該遮蔽框架的第一部分以保留該遮蔽框架的一第二部分在該半導體晶粒之上而作為免於干擾之遮蔽；及形成一第一互連結構在該半導體晶粒、該遮蔽框架的第二部分與該囊封物的一第一側之上。
  2. 如申請專利範圍第1項之方法，更包括：形成一第二互連結構在該半導體晶粒與相對於該囊封物的第一側之該囊封物的一第二側之上。
  3. 如申請專利範圍第2項之方法，更包括：形成於該第一互連結構與該第二互連結構之間而環繞該半導體晶粒的一遮蔽層。
  4. 如申請專利範圍第1項之方法，更包括：提供通過該遮蔽框架的一開口以將該囊封物散佈至該遮蔽框架之下方的腔部。
  5. 如申請專利範圍第1項之方法，更包括：形成於該半 導體晶粒的一矽通孔以將該遮蔽框架接地。
  6. 一種製造半導體元件的方法，包含：提供一預先製造的遮蔽框架；安裝該遮蔽框架在一半導體晶粒之上；透過該遮蔽框架而沉積一囊封物為環繞該半導體晶粒；及移除該遮蔽框架的一第一部分以暴露該囊封物而保留該遮蔽框架的一第二部分在該半導體晶粒之上。
  7. 如申請專利範圍第6項之方法，更包括：形成一第一互連結構在該半導體晶粒、該遮蔽框架的第二部分與該囊封物的一第一側之上；及形成一第二互連結構在該半導體晶粒與相對於該囊封物的第一側之該囊封物的一第二側之上。
  8. 如申請專利範圍第6項之方法，其中，移除該遮蔽框架的第一部分以保留環繞該半導體晶粒之該遮蔽框架的一第三部分以提供一傳導柱。
  9. 如申請專利範圍第8項之方法，更包括：堆疊複數個半導體元件；及透過該傳導柱而電氣連接該等堆疊的半導體元件。
  10. 如申請專利範圍第6項之方法，更包括：提供通過該遮蔽框架的一開口以將該囊封物散佈至該遮蔽框架之下方的腔部。
  11. 一種半導體元件，包含：一框架，包括： (a)一平板；(b)一本體，整合在該平板的一表面上；以及(c)一傳導柱，整合在該平板的該表面上並且鄰近該本體；一半導體晶粒，設置在該本體之上且包含朝該本體定向的該半導體晶粒的一背表面；以及一囊封物，形成在該半導體晶粒、該本體和該傳導柱周圍且包括與該半導體晶粒的一主動表面共平面的該囊封物的一表面，該主動表面與該背表面相對。
  12. 如申請專利範圍第11項之半導體元件，其中，該框架更包括通過該平板的一開口。
  13. 如申請專利範圍第11項之半導體元件，其中，該本體接觸該半導體晶粒的該背表面。
  14. 如申請專利範圍第11項之半導體元件，更包括：一傳導孔，形成於該半導體晶粒中且電氣連接至該本體。
  15. 如申請專利範圍第11項之半導體元件，更包括：一遮蔽層，整合於該平板的表面，並且透過該囊封物配置在該半導體晶粒的一部份的周圍。
TW099106840A 2009-03-23 2010-03-10 半導體元件以及在半導體晶粒上配置預先製造的遮蔽框架的方法 TWI553816B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US12/409,142 US8097489B2 (en) 2009-03-23 2009-03-23 Semiconductor device and method of mounting pre-fabricated shielding frame over semiconductor die

Publications (2)

Publication Number Publication Date
TW201044540A TW201044540A (en) 2010-12-16
TWI553816B true TWI553816B (zh) 2016-10-11

Family

ID=42736797

Family Applications (1)

Application Number Title Priority Date Filing Date
TW099106840A TWI553816B (zh) 2009-03-23 2010-03-10 半導體元件以及在半導體晶粒上配置預先製造的遮蔽框架的方法

Country Status (3)

Country Link
US (2) US8097489B2 (zh)
SG (2) SG10201509258TA (zh)
TW (1) TWI553816B (zh)

Families Citing this family (75)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8343809B2 (en) 2010-03-15 2013-01-01 Stats Chippac, Ltd. Semiconductor device and method of forming repassivation layer with reduced opening to contact pad of semiconductor die
US7767496B2 (en) 2007-12-14 2010-08-03 Stats Chippac, Ltd. Semiconductor device and method of forming interconnect structure for encapsulated die having pre-applied protective layer
US8456002B2 (en) 2007-12-14 2013-06-04 Stats Chippac Ltd. Semiconductor device and method of forming insulating layer disposed over the semiconductor die for stress relief
US9318441B2 (en) 2007-12-14 2016-04-19 Stats Chippac, Ltd. Semiconductor device and method of forming sacrificial adhesive over contact pads of semiconductor die
US8183095B2 (en) 2010-03-12 2012-05-22 Stats Chippac, Ltd. Semiconductor device and method of forming sacrificial protective layer to protect semiconductor die edge during singulation
US7888184B2 (en) * 2008-06-20 2011-02-15 Stats Chippac Ltd. Integrated circuit packaging system with embedded circuitry and post, and method of manufacture thereof
US8378383B2 (en) 2009-03-25 2013-02-19 Stats Chippac, Ltd. Semiconductor device and method of forming a shielding layer between stacked semiconductor die
KR101583354B1 (ko) * 2009-06-01 2016-01-07 삼성전자주식회사 반도체 소자 패키지의 형성방법
US8237252B2 (en) 2009-07-22 2012-08-07 Stats Chippac, Ltd. Semiconductor device and method of embedding thermally conductive layer in interconnect structure for heat dissipation
TWI497679B (zh) * 2009-11-27 2015-08-21 Advanced Semiconductor Eng 半導體封裝件及其製造方法
US8569894B2 (en) 2010-01-13 2013-10-29 Advanced Semiconductor Engineering, Inc. Semiconductor package with single sided substrate design and manufacturing methods thereof
TWI406379B (zh) * 2010-02-25 2013-08-21 Inpaq Technology Co Ltd 晶粒尺寸半導體元件封裝及其製造方法
US9548240B2 (en) 2010-03-15 2017-01-17 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming repassivation layer for robust low cost fan-out semiconductor package
TWI411075B (zh) 2010-03-22 2013-10-01 Advanced Semiconductor Eng 半導體封裝件及其製造方法
US8319318B2 (en) 2010-04-06 2012-11-27 Intel Corporation Forming metal filled die back-side film for electromagnetic interference shielding with coreless packages
US8349658B2 (en) 2010-05-26 2013-01-08 Stats Chippac, Ltd. Semiconductor device and method of forming conductive posts and heat sink over semiconductor die using leadframe
US9269691B2 (en) 2010-05-26 2016-02-23 Stats Chippac, Ltd. Semiconductor device and method of making an embedded wafer level ball grid array (EWLB) package on package (POP) device with a slotted metal carrier interposer
US9048233B2 (en) 2010-05-26 2015-06-02 Taiwan Semiconductor Manufacturing Company, Ltd. Package systems having interposers
US9484279B2 (en) 2010-06-02 2016-11-01 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming EMI shielding layer with conductive material around semiconductor die
US20110316140A1 (en) * 2010-06-29 2011-12-29 Nalla Ravi K Microelectronic package and method of manufacturing same
TWI460834B (zh) * 2010-08-26 2014-11-11 Unimicron Technology Corp 嵌埋穿孔晶片之封裝結構及其製法
US8941222B2 (en) 2010-11-11 2015-01-27 Advanced Semiconductor Engineering Inc. Wafer level semiconductor package and manufacturing methods thereof
TW201225246A (en) * 2010-12-06 2012-06-16 Ind Tech Res Inst Multi-chip stack structure
US9406658B2 (en) 2010-12-17 2016-08-02 Advanced Semiconductor Engineering, Inc. Embedded component device and manufacturing methods thereof
US8642385B2 (en) * 2011-08-09 2014-02-04 Alpha & Omega Semiconductor, Inc. Wafer level package structure and the fabrication method thereof
US9224669B2 (en) 2011-08-09 2015-12-29 Alpha And Omega Semiconductor Incorporated Method and structure for wafer level packaging with large contact area
US9190297B2 (en) * 2011-08-11 2015-11-17 Stats Chippac, Ltd. Semiconductor device and method of forming a stackable semiconductor package with vertically-oriented discrete electrical devices as interconnect structures
CN103828043B (zh) 2011-09-07 2017-11-24 株式会社村田制作所 模块的制造方法及模块
JP5768888B2 (ja) * 2011-09-07 2015-08-26 株式会社村田製作所 モジュールの製造方法および端子集合体
US8552556B1 (en) 2011-11-22 2013-10-08 Amkor Technology, Inc. Wafer level fan out package
KR101323925B1 (ko) * 2012-03-30 2013-10-31 주식회사 네패스 반도체 패키지 및 그 제조 방법
KR101469799B1 (ko) * 2012-03-30 2014-12-05 주식회사 네패스 반도체 패키지의 제조 방법
FI20125725L (fi) * 2012-06-26 2013-12-27 Tellabs Oy Mekaanisella suojauksella varustettu piirikorttijärjestely
US8669655B2 (en) * 2012-08-02 2014-03-11 Infineon Technologies Ag Chip package and a method for manufacturing a chip package
EP2704536B1 (en) * 2012-08-31 2015-12-16 Harman Becker Automotive Systems GmbH Method for producing a circuit board system
US10622310B2 (en) 2012-09-26 2020-04-14 Ping-Jung Yang Method for fabricating glass substrate package
US9685350B2 (en) 2013-03-08 2017-06-20 STATS ChipPAC, Pte. Ltd. Semiconductor device and method of forming embedded conductive layer for power/ground planes in Fo-eWLB
US9252135B2 (en) 2014-02-13 2016-02-02 Taiwan Semiconductor Manufacturing Company, Ltd. Packaged semiconductor devices and methods of packaging semiconductor devices
US9034694B1 (en) 2014-02-27 2015-05-19 Freescale Semiconductor, Inc. Embedded die ball grid array package
US9831214B2 (en) * 2014-06-18 2017-11-28 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device packages, packaging methods, and packaged semiconductor devices
US10177032B2 (en) 2014-06-18 2019-01-08 Taiwan Semiconductor Manufacturing Company, Ltd. Devices, packaging devices, and methods of packaging semiconductor devices
US10068862B2 (en) * 2015-04-09 2018-09-04 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming a package in-fan out package
US9781819B2 (en) * 2015-07-31 2017-10-03 Laird Technologies, Inc. Multifunctional components for electronic devices and related methods of providing thermal management and board level shielding
TWI618156B (zh) * 2016-08-05 2018-03-11 矽品精密工業股份有限公司 電子封裝件及其製法
TWI765944B (zh) 2016-12-14 2022-06-01 成真股份有限公司 標準大宗商品化現場可編程邏輯閘陣列（ｆｐｇａ）積體電路晶片組成之邏輯驅動器
US11625523B2 (en) 2016-12-14 2023-04-11 iCometrue Company Ltd. Logic drive based on standard commodity FPGA IC chips
US10134683B2 (en) * 2017-02-10 2018-11-20 Advanced Semiconductor Engineering, Inc. Semiconductor device package and method of manufacturing the same
US10217719B2 (en) * 2017-04-06 2019-02-26 Micron Technology, Inc. Semiconductor device assemblies with molded support substrates
US10447274B2 (en) 2017-07-11 2019-10-15 iCometrue Company Ltd. Logic drive based on standard commodity FPGA IC chips using non-volatile memory cells
US10804115B2 (en) 2017-08-03 2020-10-13 General Electric Company Electronics package with integrated interconnect structure and method of manufacturing thereof
US10541209B2 (en) * 2017-08-03 2020-01-21 General Electric Company Electronics package including integrated electromagnetic interference shield and method of manufacturing thereof
US10541153B2 (en) 2017-08-03 2020-01-21 General Electric Company Electronics package with integrated interconnect structure and method of manufacturing thereof
US10957679B2 (en) 2017-08-08 2021-03-23 iCometrue Company Ltd. Logic drive based on standardized commodity programmable logic semiconductor IC chips
KR102344320B1 (ko) * 2017-08-11 2021-12-28 삼성전자주식회사 더미 콘택을 갖는 반도체 소자
US10630296B2 (en) 2017-09-12 2020-04-21 iCometrue Company Ltd. Logic drive with brain-like elasticity and integrality based on standard commodity FPGA IC chips using non-volatile memory cells
CN209000911U (zh) * 2017-10-30 2019-06-18 莱尔德电子材料(深圳)有限公司 热管理和电磁干扰减轻组件、包括该组件的装置
US10608642B2 (en) 2018-02-01 2020-03-31 iCometrue Company Ltd. Logic drive using standard commodity programmable logic IC chips comprising non-volatile radom access memory cells
US10623000B2 (en) 2018-02-14 2020-04-14 iCometrue Company Ltd. Logic drive using standard commodity programmable logic IC chips
US10608638B2 (en) 2018-05-24 2020-03-31 iCometrue Company Ltd. Logic drive using standard commodity programmable logic IC chips
US10978408B2 (en) * 2018-06-07 2021-04-13 Powertech Technology Inc. Semiconductor package and manufacturing method thereof
US11309334B2 (en) 2018-09-11 2022-04-19 iCometrue Company Ltd. Logic drive using standard commodity programmable logic IC chips comprising non-volatile random access memory cells
US10937762B2 (en) 2018-10-04 2021-03-02 iCometrue Company Ltd. Logic drive based on multichip package using interconnection bridge
US11211334B2 (en) 2018-11-18 2021-12-28 iCometrue Company Ltd. Logic drive based on chip scale package comprising standardized commodity programmable logic IC chip and memory IC chip
US10910322B2 (en) * 2018-12-14 2021-02-02 STATS ChipPAC Pte. Ltd. Shielded semiconductor package with open terminal and methods of making
CN110323176B (zh) * 2019-05-29 2021-10-22 宁波芯健半导体有限公司 一种芯片的三维封装方法及封装结构
US10985154B2 (en) 2019-07-02 2021-04-20 iCometrue Company Ltd. Logic drive based on multichip package comprising standard commodity FPGA IC chip with cryptography circuits
US11227838B2 (en) 2019-07-02 2022-01-18 iCometrue Company Ltd. Logic drive based on multichip package comprising standard commodity FPGA IC chip with cooperating or supporting circuits
US11887930B2 (en) 2019-08-05 2024-01-30 iCometrue Company Ltd. Vertical interconnect elevator based on through silicon vias
US11637056B2 (en) 2019-09-20 2023-04-25 iCometrue Company Ltd. 3D chip package based on through-silicon-via interconnection elevator
CN110767614A (zh) * 2019-10-10 2020-02-07 华为技术有限公司 封装结构和电子装置
US11227837B2 (en) * 2019-12-23 2022-01-18 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit package and method
US11600526B2 (en) 2020-01-22 2023-03-07 iCometrue Company Ltd. Chip package based on through-silicon-via connector and silicon interconnection bridge
US20220077113A1 (en) * 2020-09-04 2022-03-10 Intel Corporation 3d stacked die package with molded integrated heat spreader
US12002729B2 (en) * 2021-07-30 2024-06-04 Advanced Semiconductor Engineering, Inc. Electronic package and method of manufacturing the same
US12040284B2 (en) * 2021-11-12 2024-07-16 Invensas Llc 3D-interconnect with electromagnetic interference (“EMI”) shield and/or antenna

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060249802A1 (en) * 2001-09-28 2006-11-09 Epcos Ag Method for encapsulating an electrical component, and surface acoustic wave device encapsulated using said method
US7196415B2 (en) * 2002-03-22 2007-03-27 Broadcom Corporation Low voltage drop and high thermal performance ball grid array package
US7247517B2 (en) * 2003-09-30 2007-07-24 Intel Corporation Method and apparatus for a dual substrate package

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5250843A (en) * 1991-03-27 1993-10-05 Integrated System Assemblies Corp. Multichip integrated circuit modules
US5353498A (en) * 1993-02-08 1994-10-11 General Electric Company Method for fabricating an integrated circuit module
US5841193A (en) * 1996-05-20 1998-11-24 Epic Technologies, Inc. Single chip modules, repairable multichip modules, and methods of fabrication thereof
US6136128A (en) * 1998-06-23 2000-10-24 Amerasia International Technology, Inc. Method of making an adhesive preform lid for electronic devices
US5977626A (en) * 1998-08-12 1999-11-02 Industrial Technology Research Institute Thermally and electrically enhanced PBGA package
US6856007B2 (en) * 2001-08-28 2005-02-15 Tessera, Inc. High-frequency chip packages
DE10348620A1 (de) * 2003-10-15 2005-06-02 Infineon Technologies Ag Halbleitermodul mit Gehäusedurchkontakten
US7633170B2 (en) * 2005-01-05 2009-12-15 Advanced Semiconductor Engineering, Inc. Semiconductor device package and manufacturing method thereof
JP4593616B2 (ja) * 2005-01-25 2010-12-08 富士通株式会社 半導体装置
DE102005026098B3 (de) * 2005-06-01 2007-01-04 Infineon Technologies Ag Nutzen und Halbleiterbauteil aus einer Verbundplatte mit Halbleiterchips und Kunststoffgehäusemasse sowie Verfahren zur Herstellung derselben
DE102006023123B4 (de) * 2005-06-01 2011-01-13 Infineon Technologies Ag Abstandserfassungsradar für Fahrzeuge mit einem Halbleitermodul mit Komponenten für Höchstfrequenztechnik in Kunststoffgehäuse und Verfahren zur Herstellung eines Halbleitermoduls mit Komponenten für ein Abstandserfassungsradar für Fahrzeuge in einem Kunststoffgehäuse
US8022512B2 (en) * 2006-02-28 2011-09-20 Unisem (Mauritus) Holdings Limited No lead package with heat spreader
US7993972B2 (en) 2008-03-04 2011-08-09 Stats Chippac, Ltd. Wafer level die integration and method therefor
US7830000B2 (en) * 2007-06-25 2010-11-09 Epic Technologies, Inc. Integrated thermal structures and fabrication methods thereof facilitating implementing a cell phone or other electronic system
US7888184B2 (en) 2008-06-20 2011-02-15 Stats Chippac Ltd. Integrated circuit packaging system with embedded circuitry and post, and method of manufacture thereof
US7842542B2 (en) 2008-07-14 2010-11-30 Stats Chippac, Ltd. Embedded semiconductor die package and method of making the same using metal frame carrier
US7951643B2 (en) * 2008-11-29 2011-05-31 Stats Chippac Ltd. Integrated circuit packaging system with lead frame and method of manufacture thereof

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060249802A1 (en) * 2001-09-28 2006-11-09 Epcos Ag Method for encapsulating an electrical component, and surface acoustic wave device encapsulated using said method
US7196415B2 (en) * 2002-03-22 2007-03-27 Broadcom Corporation Low voltage drop and high thermal performance ball grid array package
US7247517B2 (en) * 2003-09-30 2007-07-24 Intel Corporation Method and apparatus for a dual substrate package

Also Published As

Publication number Publication date
US20100237477A1 (en) 2010-09-23
US8097489B2 (en) 2012-01-17
SG10201509258TA (en) 2015-12-30
SG165239A1 (en) 2010-10-28
US9406619B2 (en) 2016-08-02
TW201044540A (en) 2010-12-16
US20120112328A1 (en) 2012-05-10

Similar Documents

Publication Publication Date Title
TWI553816B (zh) 半導體元件以及在半導體晶粒上配置預先製造的遮蔽框架的方法
TWI517270B (zh) 半導體元件以及在半導體晶粒的周圍區域中的導電孔之間形成雜訊吸收區域的方法
TWI520231B (zh) 半導體元件以及在膠封之後形成通過互連結構而接地的遮蔽層之方法
US10211183B2 (en) Semiconductor device and method of forming shielding layer over integrated passive device using conductive channels
US9583446B2 (en) Semiconductor device and method of forming a shielding layer between stacked semiconductor die
TWI508199B (zh) 半導體元件以及提供具有內部聚合物核心的ｚ互連傳導柱的方法
TWI538150B (zh) 半導體裝置及形成具有圍繞半導體晶粒之導體材料的電磁干擾防護層之方法
TWI550763B (zh) 半導體元件以及形成自預先構建的柱狀框架的３ｄ電感之方法
US9401347B2 (en) Semiconductor device and method of forming a shielding layer over a semiconductor die disposed in a cavity of an interconnect structure and grounded through the die TSV
TWI515810B (zh) 半導體元件以及在垂直互連結構附近形成非流動的底部填充材料的方法
TWI579977B (zh) 使用引線架體以形成用於半導體晶粒的垂直互連的通過密封物的開口之半導體裝置和方法
TWI479577B (zh) 形成屏障材料於晶粒之周圍以減少翹曲之半導體裝置和方法
US7935570B2 (en) Semiconductor device and method of embedding integrated passive devices into the package electrically interconnected using conductive pillars
TWI508202B (zh) 雙重模造晶粒形成於增進互連結構之對邊上之半導體裝置和方法
TWI499030B (zh) 在矽穿孔***物中形成開放孔穴以包含在晶圓級晶片尺寸模組封裝的半導體晶粒之半導體裝置和方法
US9257356B2 (en) Semiconductor device and method of forming an IPD beneath a semiconductor die with direct connection to external devices
US20140319661A1 (en) Semiconductor Device and Method of Forming Shielding Layer Over Semiconductor Die Mounted to TSV Interposer