TWI517270B - 半導體元件以及在半導體晶粒的周圍區域中的導電孔之間形成雜訊吸收區域的方法 - Google Patents

半導體元件以及在半導體晶粒的周圍區域中的導電孔之間形成雜訊吸收區域的方法 Download PDF

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TWI517270B
TWI517270B TW099106839A TW99106839A TWI517270B TW I517270 B TWI517270 B TW I517270B TW 099106839 A TW099106839 A TW 099106839A TW 99106839 A TW99106839 A TW 99106839A TW I517270 B TWI517270 B TW I517270B
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semiconductor die
semiconductor
conductive
region
forming
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TW099106839A
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TW201113960A (en
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瑞莎Ａ 派蓋菈
杜雍台
納薩彭 蘇司王上尚爾
黃双武
迪歐斯可洛 馬力羅
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史達晶片有限公司
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Description

半導體元件以及在半導體晶粒的周圍區域中的導電孔之間形成雜訊吸收區域的方法
本發明概括關於半導體元件，且尤指一種半導體晶粒(die)以及在晶粒的周圍區域中的傳導通孔之間形成雜訊吸收區域的方法。
半導體元件為常見於現代電子產品。半導體元件為於電氣構件的數目與密度而變化。離散的半導體元件通常含有一個型式的電氣構件，例如：發光二極體(LED，light emitting diode)、電晶體、電阻器、電容器、電感器、與功率(power)金屬氧化物半導體場效電晶體(MOSFET，metal oxide semiconductor field effect transistor)。積體的半導體元件典型為含有數百個到數百萬個電氣構件。積體的半導體元件之實例包括：微控制器、微處理器、電荷耦合元件(CCD，charge-coupled device)、太陽能電池與數位微鏡元件(DMD，digital micro-mirror device)。
半導體元件實行廣泛範圍的作用，諸如：高速計算、傳送及接收電磁訊號、控制電子元件、轉變陽光為電力及產生視覺投影以供電視顯像。半導體元件可見於娛樂、通訊、發電、網路、電腦與消費產品之領域。半導體元件亦可見於包括軍事、航空、汽車、工業控制器與辦公室設備之電子產品。
半導體元件利用半導體材料的電氣性質。半導體材料的原子結構允許其導電性藉由電場施加或透過摻雜過程而操縱。摻雜為引入雜質至半導體材料以操縱及控制半導體元件的導電性。
一種半導體元件含有主動與被動的電氣結構。主動結構(包括：電晶體)為控制電流之流通。藉由改變摻雜位準及電場施加，電晶體促進或限制電流之流通。被動結構(包括：電阻器、二極體、與電感器)為建立於電壓與電流之間的一種關係，其為必要以實行種種電氣作用。電氣連接被動與主動結構以形成電路，致使半導體元件為能夠實行高速計算與其他有用的作用。
半導體元件通常運用二個複雜的製程所製造，即：前段(front-end)製造與後段(back-end)製造，各者涉及潛在為數百個步驟。前段製造涉及於半導體晶圓表面的複數個晶粒之形成。各個晶粒典型為相同且含有藉由電氣連接主動與被動構件所形成的電路。後段製造涉及自所完成的晶圓而單一化個別的晶粒且封裝該晶粒以提供結構支撐與環境隔離。
半導體製造之一個目標為產生較小的半導體元件。較小的元件典型為消耗較少的功率，具有較高的性能，且可為較有效率製造。此外，較小的半導體元件具有較小的使用空間，其針對於較小的最終產品為合意。較小晶粒尺寸可由於前段製程之改良而達成，造成其具有較小、較高密度的主動與被動構件之晶粒。後段製程可由於電氣互連與封裝材料之改良而造成其具有較小的使用空間之半導體元件封裝。
半導體製造之另一個目標為產生較高性能的半導體元件。於元件性能的提高可藉由形成其為能夠操作於較高速度之主動構件而達成。於高頻應用，諸如：射頻(RF，radio frequency)無線通訊，積體被動元件(IPD，integrated passive device)經常包含於半導體元件之內。IPD之實例包括：電阻器、電容器與電感器。一種典型的射頻系統需要於一或多個半導體封裝之多個IPD以實行必要的電氣作用。然而，高頻的電氣元件產生或易於受到不期望的電磁干擾(EMI，electromagnetic interference)與射頻干擾(RFI，radio frequency interference)或其他的元件間干擾，諸如：電容、電感或電導耦合，亦習稱為串音(cross-talk)，此將干擾其操作。
於堆疊半導體封裝與外部元件之間的垂直電氣互連可藉著傳導的矽通孔(TSV，through silicon via)或通孔(THV，through hole via)而達成。THV以有機材料而形成於環繞元件的周圍區域中。於運用THV之射頻應用，由各個THV所載有的數位與射頻訊號可能引起於相鄰THV之間的干擾。有機材料其本身並未提供適當的EMI或RFI隔離。結果，訊號的完整度為降低，可能會引起訊號傳輸誤差且阻礙晶粒之操作。
對於隔離半導體晶粒為免於EMI、RFI與其他元件內干擾的需要為存在。是以，於一個實施例，本發明為一種製造半導體元件的方法，包含步驟：提供具有複數個半導體晶粒的一半導體晶圓；形成環繞半導體晶粒的一周圍區域；沉積一絕緣材料於周圍區域；移除絕緣材料的一部分以形成一通孔(THV)；沉積一傳導材料於通孔以形成一傳導通孔；形成一傳導層於傳導通孔與半導體晶粒的接觸墊之間；沉積雜訊吸收材料於傳導通孔之間的周圍區域以隔離半導體晶粒為免於元件內的干擾；及，透過周圍區域而使該半導體晶圓為單一化以分隔半導體晶粒。
於另一個實施例，本發明為一種製造半導體元件的方法，包含步驟：提供具有複數個半導體晶粒的一半導體晶圓；形成環繞半導體晶粒的一周圍區域；沉積一絕緣材料於周圍區域；移除絕緣材料的一部分以形成一通孔(THV)；沉積一傳導材料於通孔以形成一傳導通孔；形成一傳導層於傳導通孔與半導體晶粒的接觸墊之間；及，形成一遮蔽區域於傳導通孔之間的周圍區域以隔離半導體晶粒為免於干擾。
於另一個實施例，本發明為一種製造半導體元件的方法，包含步驟：形成一通孔(THV)於一半導體晶粒的一周圍區域；沉積一傳導材料於通孔以形成一傳導通孔；形成一傳導層於傳導通孔與半導體晶粒的接觸墊之間；及，沉積一遮蔽材料於傳導通孔之間的周圍區域以隔離半導體晶粒為免於干擾。
於另一個實施例，本發明為一種半導體元件，其包含具有一周圍區域的一半導體晶粒。一傳導通孔(THV)形成於半導體晶粒的周圍區域。一傳導層形成於傳導通孔與半導體晶粒的接觸墊之間。一遮蔽材料沉積於傳導通孔之間的周圍區域，以隔離半導體晶粒為免於干擾。
本發明參考圖式而描述於以下說明的一或多個實施例，其中，同樣的參考符號代表相同或類似元件。儘管本發明依據用於達成本發明的目標之最佳模式而描述，將為熟悉此技術人士所理解的是：意圖以涵蓋如可為納入於由隨附的申請專利範圍與以下揭露內容與圖式所支持的其等效者所界定之本發明的精神與範疇內的替代、修改、與等效者。
半導體元件通常運用二個複雜的製程所製造：前段製造與後段製造。前段製造涉及於半導體晶圓表面的複數個晶粒之形成。於晶圓上的各個晶粒含有主動與被動的電氣構件，其為電氣連接以形成作用的電路。主動電氣構件(諸如：電晶體)具有能力以控制電流之流通。被動電氣構件(諸如：電容器、電感器、電阻器與變壓器)建立於電壓與電流之間的一種關係，其為必要以實行電路作用。
被動與主動構件藉由包括摻雜、沉積、光刻、蝕刻與平面化之一連串的處理步驟而形成於半導體晶圓的表面上。摻雜為藉由諸如離子植入或熱擴散之技術而引入雜質至半導體材料。摻雜過程修改於主動元件之半導體材料的導電性，轉變半導體材料成為一種永久的絕緣體、永久的導體，或響應於電場而改變半導體材料的導電性。電晶體含有變化型式與摻雜程度的區域，其隨著必要而配置以致使電晶體為能夠於電場施加時而促進或限制電流的流通。
主動與被動構件為由具有不同的電氣性質之數層材料所形成。諸層可藉由其部分為所沉積的材料型式所決定之種種沉積技術所形成。舉例而言，薄膜沉積可能涉及化學汽相沉積(CVD，chemical vapor deposition)、物理汽相沉積(PVD，physical vapor deposition)、電解電鍍及無電電鍍過程。各層通常為圖案化以形成部分的主動構件、被動構件或於構件之間的電氣連接。
諸層可運用光刻法所圖案化，光刻法涉及例如光阻的光敏材料之沉積於將作圖案化之層上。一圖案(pattern)運用光線而轉移自一光罩至光阻。受到光線之光阻圖案部分運用一種溶劑所移除，暴露將作圖案化之下面層的部分者。移除光阻的其餘部分，留下一圖案化層。或者是，一些型式的材料藉由直接沉積材料至其運用諸如無電及電解電鍍法的技術之一種先前沉積/蝕刻過程所形成的區域或空隙而圖案化。
沉積一薄膜的材料於現存的圖案上可能擴大在下面的圖案且產生一不均勻平坦表面。需要一均勻平坦表面以產生較小且較密集封裝的主動與被動構件。平面化為可運用以移除自晶圓表面的材料且產生一均勻平坦表面。平面化涉及磨光晶圓表面為具有一磨光墊。一種研磨材料與腐蝕化學製品於磨光期間而添加至晶圓表面。研磨料的機械作用與化學製品的腐蝕作用之組合者移除任何不規則的拓撲結構，造成一均勻平坦表面。
後段製造指將所完成的晶圓切割或單一化成為個別的晶粒且接著封裝該晶粒以供結構支撐與環境隔離。欲將晶粒單一化，晶圓沿著稱為鋸道或劃線之晶圓的非作用區域而刻劃及切斷。晶圓運用一種雷射切割裝置或鋸條而單一化。在單一化之後，個別晶粒安裝至一封裝基板，其包括接腳或接觸墊以供互連於其他的系統構件。形成在半導體晶粒之上的接觸墊接著連接至於封裝內的接觸墊。電氣連接可藉著焊塊、柱塊、導電糊膏或線接合而作成。一種囊封物或其他的模製材料沉積於封裝之上以提供實際支撐與電氣隔離。完成的封裝接著***至一種電氣系統且該半導體元件的功能性成為可用於其他的系統構件。
圖1為說明電子元件10，其具有一晶片載體基板或印刷電路板(PCB，printed circuit board) 12，印刷電路板12具有安裝於其表面之複數個半導體封裝。電子元件10可具有一個型式的半導體封裝、或多個型式的半導體封裝，視應用而定。不同型式的半導體封裝為了說明而顯示於圖1。
電子元件10可為一種獨立系統，其運用該等半導體封裝以實行一種電氣作用。或者是，電子元件10可為一較大系統的一個子構件。舉例而言，電子元件10可為一圖形卡、網路介面卡或可為***至電腦之其他的訊號處理卡。半導體封裝可包括：微處理器、記憶體、特定應用積體電路(ASIC，application specific integrated circuit)、邏輯電路、類比電路、射頻電路、離散元件或其他的半導體晶粒或電氣構件。
於圖1，PCB 12提供一種通用的基板以供其安裝於PCB的半導體封裝之結構支撐及電氣互連。傳導訊號線跡14運用蒸鍍、電解電鍍、無電電鍍、網印、PVD或其他適合金屬沉積過程而形成在PCB 12的一表面上或於PCB 12的諸層內。訊號線跡14提供於各個半導體封裝、安裝構件與其他外部系統構件之間的電氣連通。線跡14亦提供對於各個半導體封裝之電力與接地連接。
於一些實施例，一種半導體元件具有二個封裝階層。第一階層封裝用於機械及電氣式附接半導體晶粒至一載體的一種技術。第二階層封裝涉及：機械及電氣式附接該載體至PCB。於其他實施例，一種半導體元件可僅具有第一階層封裝，其中，該晶粒機械及電氣式直接安裝至PCB。
為了說明，數個型式的第一階層封裝顯示於PCB 12，包括：線接合封裝16與倒裝晶片18。此外，數個型式的第二階層封裝顯示為安裝於PCB 12，包括：球柵陣列(BGA，ball grid array) 20、塊形晶片載體(BCC，bump chip carrier) 22、雙列直插封裝(DIP，dual in-line package) 24、岸柵陣列(LGA，land grid array) 26、多晶片模組(MCM，multi-chip module) 28、四面扁平無引線封裝(QFN，quad flat non-leaded package) 30與四面扁平封裝32。視系統需求而定，任何組合的第一與第二階層封裝型式所構成之任何組合的半導體封裝以及其他的電子構件可連接至PCB 12。於一些實施例，電子元件10包括單一個附接的半導體封裝，而其他實施例需要多個互連的封裝。藉由組合一或多個半導體封裝在單一個基板之上，製造業者可將事先作成的構件納入至電子元件及系統。因為半導體封裝包括複雜的功能性，電子元件可運用較便宜的構件及一種有效率的製程所製造。造成的元件較不可能失效且較不昂貴以製造，造成對於消費者之較低的成本。
圖2a為說明其安裝於PCB 12之DIP 24的進一步細節。DIP 24包括具有接觸墊36之半導體晶粒34。半導體晶粒34包括：一主動區域，其含有類比或數位電路而實施為主動元件、被動元件、傳導層與介電層，形成於半導體晶粒34之內且為根據晶粒的電氣設計而電氣互連。舉例而言，該電路可包括：一或多個電晶體、二極體、電感器、電容器、電阻器與形成於晶粒34之主動區域內的其他電路元件。接觸墊36為以一種傳導材料所作成，諸如：鋁(Al)、銅(Cu)、錫(Sn)、鎳(Ni)、金(Au)或銀(Ag)，且為電氣連接至其形成於晶粒34之內的電路元件。接觸墊36為藉由PVD、CVD、電解電鍍或無電電鍍過程所形成。於DIP 24之組裝期間，半導體晶粒34運用一種金-矽的共熔層或諸如熱環氧化物的黏著材料而安裝至一載體38。封裝本體包括一種絕緣封裝材料，諸如：聚合物或陶瓷。導體引線40連接至載體38且線接合42形成於引線40與晶粒34的接觸墊36之間而作為一第一階層封裝。囊封物44沉積在封裝上以供環境保護，藉由阻止濕氣與微粒而免於進入封裝及污染晶粒34、接觸墊36或線接合42。DIP 24藉由***引線40至其形成穿過PCB 12的孔而連接至PCB 12。焊料46流通環繞引線40且進入孔以實際及電氣式連接DIP 24至PCB 12。焊料46可為任何的金屬或導電材料，例如：Sn、鉛(Pb)、Au、Ag、Cu、鋅(Zn)、鉍(Bi)與其合金，具有一種選用的助熔材料。舉例而言，焊料可為共熔Sn/Pb、高鉛或無鉛。
圖2b為說明其安裝於PCB 12之BCC 22的進一步細節。半導體晶粒47藉由線接合型式的第一階層封裝而連接至一載體。BCC 22為以一種BCC型式的第二階層封裝而安裝至PCB 12。具有接觸墊48之半導體晶粒47運用一種底部填充(underfill)或環氧樹脂的黏著材料50而安裝在一載體上。半導體晶粒47包括：一主動區域，其含有類比或數位電路而實施為主動元件、被動元件、傳導層與介電層，形成於半導體晶粒47之內且為根據晶粒的電氣設計而電氣互連。舉例而言，該電路可包括：一或多個電晶體、二極體、電感器、電容器、電阻器與其形成於晶粒47之主動區域內的其他電路元件。接觸墊48為以一種傳導材料所作成，諸如：Al、Cu、Sn、Ni、Au或Ag，且為電氣連接至其形成於晶粒47之內的電路元件。接觸墊48藉由PVD、CVD、電解電鍍或無電電鍍過程所形成。線接合54及接合墊56與58為電氣連接半導體晶粒47的接觸墊48至BCC 22的接觸墊52而形成第一階層封裝。模製化合物或囊封物60沉積在半導體晶粒47、線接合54、接觸墊48與接觸墊52之上，以提供針對於該元件的實際支撐及電氣隔離。接觸墊64運用蒸鍍、電解電鍍、無電電鍍、網印、PVD或其他適合金屬沉積過程而形成在PCB 12之一表面上且典型為電鍍以防止氧化。接觸墊64電氣連接至一或多個傳導訊號線跡14。焊料沉積於BCC 22的接觸墊52與PCB 12的接觸墊64之間。焊料回流以形成凸塊66，其形成於BCC 22與PCB 12之間的機械及電氣連接。
於圖2c，半導體晶粒18為以一種倒裝晶片型式的第一階層封裝而安裝為面對朝下至載體76。BGA 20為以一種BGA型式的第二階層封裝而附接至PCB 12。主動區域70含有類比或數位電路而實施為主動元件、被動元件、傳導層與介電層，形成於半導體晶粒18之內且為根據晶粒的電氣設計而電氣互連。舉例而言，該電路可包括：一或多個電晶體、二極體、電感器、電容器、電阻器與其形成於半導體晶粒18的主動區域70之內的其他電路元件。半導體晶粒18透過大量個別傳導焊塊或球78而電氣及機械式附接至載體76。焊塊78形成在其配置於主動區域70的凸塊墊或互連位置80之上。凸塊墊80為以一種傳導材料所作成，諸如：Al、Cu、Sn、Ni、Au或Ag，且為電氣連接至其形成於主動區域70的電路元件。凸塊墊80為藉由PVD、CVD、電解電鍍或無電電鍍過程所形成。焊塊78為藉由一種焊料回流過程而電氣及機械式連接至於載體76的接觸墊或互連位置82。
BGA 20為藉由大量個別傳導焊塊或球86而電氣及機械式附接至PCB 12。焊塊為形成在凸塊墊或互連位置84之上。凸塊墊84為透過其路由通過載體76之導線90而電氣連接至互連位置82。接觸墊88運用蒸鍍、電解電鍍、無電電鍍、網印、PVD或其他適合金屬沉積過程而形成在PCB 12之一表面上且典型為電鍍以防止氧化。接觸墊88電氣連接至一或多個傳導訊號線跡14。焊塊86為藉由一種焊料回流過程而電氣及機械式連接至於PCB 12的接觸墊或接合墊88。模製化合物或囊封物92沉積在半導體晶粒18與載體76之上，以提供針對於該元件的實際支撐及電氣隔離。倒裝晶片式半導體元件提供自於半導體晶粒18的主動元件至於PCB 12的傳導軌跡之一短的導電路徑，藉以縮小訊號傳播距離、降低電容及改良整體電路性能。於另一個實施例，半導體晶粒18可運用倒裝晶片型式的第一階層封裝且無載體76而機械及電氣式直接附接至PCB 12。
圖3a至3l為說明一種形成傳導通孔於環繞半導體晶粒的周圍區域之方法。開始該種方法，圖3a顯示複數個半導體晶粒102，其運用習用的積體電路製程而形成於一半導體晶圓100，如上所述。各個半導體晶粒102包括：類比或數位電路，實施為主動與被動元件、積體被動元件(IPD)、傳導層與介電層，形成在頂側主動表面106且根據晶粒的電氣設計而電氣互連。舉例而言，該電路可包括一或多個電晶體、二極體與形成於主動表面106之內的其他電路元件，以實施基頻數位電路，諸如：數位訊號處理器(DSP，digital signal processor)、記憶體或其他的訊號處理電路。半導體晶粒102亦可含有用於射頻(RF)訊號處理之IPD，諸如：電感器、電容器與電阻器。接觸墊104電氣連接至於半導體晶粒102的主動區域106之內的主動與被動元件及訊號線跡。半導體晶粒102由鋸道108所分開。於圖3b，半導體晶圓100為以紫外線(UV，ultraviolet)帶而安裝至擴展台103，使得接觸墊104與主動表面106方位為面對朝上。
於圖3c，於一種切塊操作，一種鋸條或雷射工具110切割為通過鋸道108而朝下至擴展台103。鋸條切割一間隙，其具有寬度為小於鋸道108的寬度。於圖3d，擴展台102移動於二維的側向方向，如由箭頭114所示，以擴展鋸道108的寬度，即：形成一周圍區域116且產生於晶粒之間的一較大實際分隔。擴展台103為於該台控制的容許度內而實質移動於x軸與y軸的相同距離以提供環繞各個晶粒的一周圍之分隔。周圍區域116的擴展後寬度範圍為自5至200微米(μm)。擴展的尺度視設計實施例而定，即：半THV、全THV、單列通孔或雙/多列通孔。
於一個替代實施例，切塊半導體晶圓以分離半導體晶粒。於一拾取及置放操作，個別的半導體晶粒接著轉移且運用一黏著層(例如：熱環氧化物)而固定至一暫時的晶片載體。半導體晶粒置放於晶片載體，藉以具有預定的分隔或周圍區域。概括而言，分隔具有充分的寬度以形成於周圍區域之內的傳導通孔，如下所述。
於圖3e，一種有機絕緣材料120運用旋轉塗覆、針形分配或其他適合施加過程而沉積於周圍區域116。圖3f沉積於周圍區域116之有機絕緣材料120的俯視圖。有機材料120可為苯環丁烯(BCB，benzocyclobutene)、聚醯亞胺(PI，polyimide)或丙烯酸酯樹脂。或者是，諸如聚合物模製化合物、液體環氧化物模製、壓縮模製、軟疊合膜或具有介電或電氣絕緣性質的其他材料之其他非傳導材料可沉積於周圍區域116。非傳導材料亦可運用一種轉移模製或注射模製過程而沉積。
於圖3g，有機材料118的一部分藉由雷射鑽孔或深度反應性離子蝕刻(DRIE，deep reactive ion etching)所移除以產生開口或孔122，其朝下延伸至擴展台103。開口122延伸完全通過周圍區域而自半導體晶粒的一側至其相對側。圖3h為顯示開口122的俯視圖。開口122的側壁可為垂直或漸縮。
於圖3i，一種導電材料126運用PVD、CVD、蒸鍍、電解電鍍、無電電鍍、網印或其他適合金屬沉積過程而沉積於開口122。一種導電材料128運用PVD、CVD、蒸鍍、電解電鍍、無電電鍍、網印或其他適合金屬沉積過程而圖案化及沉積在有機材料120之上。一種選用的鈍化層可沉積在半導體晶圓100之上以隔離導電層128與主動表面106。鈍化層可為一或多層的二氧化矽(SiO2)、氮化矽(Si3N4)、氮氧化矽(SiON)、五氧化二鉭(Ta2O5)、氧化鋁(Al2O3)、或具有類似絕緣與結構性質的其他材料。絕緣層運用PVD、CVD、印製、旋轉塗覆、噴灑塗覆、燒結或熱氧化而沉積。鈍化層的一部分藉由一種蝕刻過程所移除以暴露接觸墊104。導電層128形成訊號線跡或重新分佈層(RDL，redistribution layer)以電氣連接接觸墊104至導電材料126，如於圖3j所示。導電材料126與導電層128可為一或多層的Al、Cu、Sn、Ni、Au、Ag或其他適合導電材料。
於圖3k，半導體晶粒102透過周圍區域116的中央部分而單一化，即：將導電材料128平分且產生傳導通孔(THV)130。周圍區域116為由諸如一鋸條或雷射之一種切割工具132所切割。藉由切割通過導電材料128的中央，THV 130為傳導半通孔，其提供自半導體晶粒102的一側至晶粒的相對側之電氣連接。切割工具完全切斷周圍區域以分離該晶粒。圖31顯示THV 130的俯視圖。半導體晶粒自擴展台103而移除。
圖3a至3l之處理流程亦可運用一種重新組態的晶圓技術，其涉及複數個半導體晶粒之附接於一暫時的載體。一囊封劑沉積在半導體晶粒之上。傳導通孔透過通孔而形成於囊封物。載體為解除接合且RDL為形成於半導體晶粒的接觸墊與傳導通孔之間。諸如焊塊之一互連結構形成且晶圓單一化成為個別的半導體晶粒。
圖4顯示針對於具有傳導THV 130的半導體晶粒102之一種最終組態，傳導THV 130形成於晶粒的周圍區域以提供自各個晶粒的一側至晶粒的相對側之電氣連接。傳導THV 130透過RDL 128而電氣連接至接觸墊104以及於半導體晶粒102的主動區域106之主動與被動元件與訊號線跡。
圖5顯示具有傳導全THV 142的半導體晶粒140，全THV 142形成於晶粒的周圍區域以提供自各個晶粒的一側至晶粒的相對側之電氣連接。欲形成全THV 142，周圍區域成為充分寬以形成二個並排的導電區域，類似於圖3i之126。周圍區域填充其類似於120的有機材料且該二個導電區域由有機材料所形成分離於周圍區域。切割工具切斷於二個傳導通孔之間的有機材料以提供全THV 142。RDL 144類似於圖3j之RDL 128而形成。傳導THV 142透過RDL 144而電氣連接至半導體晶粒140的接觸墊146。
圖6顯示二個堆疊的半導體晶粒140，其透過傳導THV 142而電氣互連於垂直(z)方向。於各個半導體晶粒140的主動區域148之主動與被動元件與訊號線跡透過接觸墊146、RDL 144與傳導THV 142而電氣連接。
圖7顯示具有傳導全THV 152與傳導半THV 154的半導體晶粒150，全THV 152與半THV 154形成於其環繞晶粒的周圍區域之多個偏離列，以提供自各個晶粒的一側至晶粒的另一側之電氣連接。欲形成THV 152與半THV 154，周圍區域成為充分寬以形成於多個偏離列的三個導電區域，類似於圖3i之126。周圍區域填充其類似於120的有機材料且該等導電區域為由有機材料所形成分離於周圍區域。切割工具切斷中間的傳導通孔以提供一個全THV 152與一個半THV 154於各個半導體晶粒150的周圍區域。RDL 156類似於圖3j之RDL 128而形成。傳導THV 152、154透過RDL 156而電氣連接至接觸墊158以及於半導體晶粒150的主動區域之主動與被動元件與訊號線跡。
半導體晶粒102、140與150可各自含有基頻電路，其為易感受到EMI、RFI或其他干擾，諸如：電容、電感或傳導耦合。於其他實施例，半導體晶粒102、140與150含有積體被動元件(IPD)，其產生EMI、RFI或其他干擾。舉例而言，容納於半導體晶粒102、140與150之內的IPD提供針對於高頻應用所需的電氣特性，諸如：共振器、高通濾波器、低通濾波器、帶通濾波器、對稱高品質(Hi-Q)共振變壓器與調諧電容器。IPD可運用作為前端的無線射頻構件，其可定位於天線與收發器之間。IPD電感器可為其操作於高達100千兆赫茲(GHz)之一種高品質的平衡-不平衡轉換器(balun)、變壓器、或線圈。於一些應用，多個平衡-不平衡轉換器形成於同一個基板，允許多頻帶的操作。舉例而言，二或多個平衡-不平衡轉換器用於針對於行動電話或其他的全球行動通訊系統(GSM，global system for mobile communication)之一四頻帶(quad-band)，各個平衡-不平衡轉換器專用於四頻帶元件之一個頻帶的操作。一種典型射頻(RF)系統需要於一或多個半導體封裝之多個IPD與其他高頻電路以實行必要的電氣作用。
圖8顯示自圖5之環繞半導體晶粒140的周圍區域、THV 142與RDL 144之進一步細節。於一個實施例，一個THV 142a可載有其切換於高速率之一數位訊號。一相鄰THV 142b載有其為易受到EMI與RFI之一射頻訊號。於THV 142a之數位訊號的高頻切換可能引起EMI與RFI雜訊且不利影響於相鄰THV 142b之射頻訊號。
欲降低於半導體晶粒140之內的元件內EMI與RFI的效應，一雜訊吸收或遮蔽區域160植入或形成於半導體晶粒140的傳導THV 142a與142b之間的周圍區域的有機材料120。遮蔽區域160典型為在單一化之前而形成。於一個實施例，遮蔽區域160隨著有機材料120為沉積而形成。或者是，遮蔽區域160在有機材料120為沉積後而植入，例如：在傳導THV為形成後。EMI/RFI遮蔽區域160具有一稜角、半圓形、矩形或其他幾何形狀。圖9為遮蔽區域160的橫截面圖，遮蔽區域160延伸通過半導體晶粒140的周圍區域以遮蔽相鄰的傳導THV 142a與142b為免於元件內的EMI與RFI。遮蔽區域160連接至於一基板或印刷電路板(PCB)之一低阻抗的接地點以提供針對於EMI/RFI能量的排放路徑。
遮蔽區域160可為一種介電材料，諸如：碳黑或鋁薄片，以降低EMI與RFI的效應。或者是，遮蔽區域160可為軟磁性材料，諸如：鐵氧體或羰基鐵、Cu、Al、不銹鋼、鎳銀、低碳鋼、矽鐵鋼、箔片、環氧化物、傳導樹脂及其能夠阻斷或吸收EMI、RFI與其他干擾的其他金屬與複合物。
於一個替代實施例，EMI/RFI雜訊吸收或遮蔽材料162以散佈組態而植入或沉積於傳導THV 142之間且環繞傳導THV 142，如於圖10所示。散佈組態可為其填充雜訊吸收或遮蔽材料的通孔或是其植入於有機材料120之粒狀微粒結構。遮蔽材料162可為一種介電材料，諸如：碳黑或鋁薄片，以降低EMI與RFI的效應。或者是，遮蔽材料162可為軟磁性材料，諸如：鐵氧體或羰基鐵、Cu、Al、不銹鋼、鎳銀、低碳鋼、矽鐵鋼、箔片、環氧化物、傳導樹脂及其能夠阻斷或吸收EMI、RFI與其他元件內干擾的其他金屬與複合物。
圖11為顯示雜訊吸收或遮蔽區域164，其植入或沉積於半導體晶粒140之周圍區域的有機材料120。於此實施例，EMI/RFI遮蔽區域164為圓形且植入或沉積為環繞傳導THV 142。遮蔽區域164延伸通過半導體晶粒140的周圍區域以遮蔽相鄰的傳導THV 142為免於元件內的EMI與RFI。遮蔽區域164連接至於一基板或PCB之一低阻抗的接地點以提供針對於EMI/RFI能量的排放路徑。
遮蔽區域164可為一種介電材料，諸如：碳黑或鋁薄片，以降低EMI與RFI的效應。或者是，遮蔽區域164可為軟磁性材料，諸如：鐵氧體或羰基鐵、Cu、Al、不銹鋼、鎳銀、低碳鋼、矽鐵鋼、箔片、環氧化物、傳導樹脂及其能夠阻斷或吸收EMI、RFI與其他元件內干擾的其他金屬與複合物。
圖12顯示雜訊吸收或遮蔽區域166，其植入或沉積於半導體晶粒102之周圍區域的有機材料120。於此實施例，EMI/RFI遮蔽區域166為半圓形且植入或沉積為環繞傳導THV 130。遮蔽區域166延伸通過半導體晶粒102的周圍區域以遮蔽相鄰的傳導THV 130為免於元件內的EMI與RFI。遮蔽區域166連接至於一基板或PCB之一低阻抗的接地點以提供針對於EMI/RFI能量的排放路徑。
圖13顯示障壁層168，其環繞傳導THV 142而形成。一雜訊吸收或遮蔽區域170環繞障壁層168而形成。在開口122為形成後，參閱：圖3g，遮蔽區域170形成於腔部的內表面。障壁層168形成在遮蔽區域170之上。於一個實施例，障壁層168可為一或多層的絕緣材料，諸如：SiO2、Si3N4、SiON、Ta2O5、鋯英石(ZrO2)、Al2O3、聚醯亞胺、BCB、聚苯并噁唑(PBO，polybenzoxazoles)或其具有類似的絕緣與結構性質的其他材料。障壁層168運用PVD、CVD、印製、旋轉塗覆、噴灑塗覆、燒結或熱氧化而沉積。開口122的其餘部分填充傳導材料以形成傳導THV 142。遮蔽區域170延伸通過半導體晶粒140的周圍區域以遮蔽相鄰的傳導THV 142為免於元件內的EMI與RFI。遮蔽區域170連接至於一基板或PCB之一低阻抗的接地點以提供針對於EMI/RFI能量的排放路徑。
遮蔽區域170可為一種介電材料，諸如：碳黑或鋁薄片，以降低EMI與RFI的效應。或者是，遮蔽區域170可為軟磁性材料，諸如：鐵氧體或羰基鐵、Cu、Al、不銹鋼、鎳銀、低碳鋼、矽鐵鋼、箔片、環氧化物、傳導樹脂及其能夠阻斷或吸收EMI、RFI與其他元件內干擾的其他金屬與複合物。
圖14顯示雜訊吸收或遮蔽區域172，其植入或沉積於半導體晶粒140之周圍區域的有機材料120。於此實施例，各個EMI/RFI遮蔽區域172為橢圓形或矩形且植入或沉積為環繞二或多個傳導THV 142。遮蔽區域172延伸通過半導體晶粒140的周圍區域以遮蔽相鄰的傳導THV 142為免於元件內的EMI與RFI。遮蔽區域172連接至於一基板或PCB之一低阻抗的接地點以提供針對於EMI/RFI能量的排放路徑。
遮蔽區域172可為一種介電材料，諸如：碳黑或鋁薄片，以降低EMI與RFI的效應。或者是，遮蔽區域172可為軟磁性材料，諸如：鐵氧體或羰基鐵、Cu、Al、不銹鋼、鎳銀、低碳鋼、矽鐵鋼、箔片、環氧化物、傳導樹脂及其能夠阻斷或吸收EMI、RFI與其他元件內干擾的其他金屬與複合物。
圖15顯示雜訊吸收或遮蔽區域174，其植入或沉積於半導體晶粒140之周圍區域的有機材料120。於此實施例，EMI/RFI遮蔽區域174為圓形且植入或沉積為環繞偏置或多列的傳導THV 142以用於較高密度I/O。遮蔽區域174延伸通過半導體晶粒140的周圍區域以遮蔽相鄰的傳導THV 142為免於元件內的EMI與RFI。遮蔽區域174連接至於一基板或PCB之一低阻抗的接地點以提供針對於EMI/RFI能量的排放路徑。
遮蔽區域174可為一種介電材料，諸如：碳黑或鋁薄片，以降低EMI與RFI的效應。或者是，遮蔽區域174可為軟磁性材料，諸如：鐵氧體或羰基鐵、Cu、Al、不銹鋼、鎳銀、低碳鋼、矽鐵鋼、箔片、環氧化物、傳導樹脂及其能夠阻斷或吸收EMI、RFI與其他元件內干擾的其他金屬與複合物。
儘管本發明之一或多個實施例已經詳細說明，熟悉此技術人士將理解的是：對於彼等實施例的修改與調適可作成而未脫離如以下申請專利範圍所陳述之本發明的範疇。
10．．．電子元件
12．．．印刷電路板
14．．．訊號線跡
16．．．線接合封裝
18．．．倒裝晶片
20．．．球柵陣列
22．．．塊形晶片載體
24．．．雙列直插封裝
26．．．岸柵陣列
28．．．多晶片模組
30．．．四面扁平無引線封裝
32．．．四面扁平封裝
34、47．．．半導體晶粒
36、48、52、64、88．．．接觸墊
38、76．．．載體
40．．．導體引線
42、54．．．線接合
44．．．囊封物
46．．．焊料
50．．．底部填充或環氧樹脂黏著材料
56、58．．．接合墊
60、92．．．模製化合物或囊封物
66．．．凸塊
70．．．主動區域
78、86．．．焊塊或球
80．．．凸塊墊
82．．．接觸墊或互連位置
84．．．凸塊墊或互連位置
90．．．導線
100．．．半導體晶圓
102、140、150．．．半導體晶粒
103．．．擴展台
104、146、158．．．接觸墊
106、148．．．主動表面(區域)
108．．．鋸道
110．．．鋸條或雷射工具
114．．．箭頭(移動方向)
116．．．周圍區域
120．．．有機絕緣材料
122．．．開口
126．．．導電材料
128、144、156．．．導電材料或重新分佈層(RDL)
130、142、142a、142b、152、154．．．通孔(THV)
132．．．切割工具
160、164、166．．．雜訊吸收或遮蔽區域
162．．．EMI/RFI雜訊吸收或遮蔽材料
168．．．障壁層
170、172、174．．．雜訊吸收或遮蔽區域
圖1為說明一種具有安裝於其表面的不同型式的封裝之印刷電路板(PCB)；
圖2a至2c為說明其安裝於PCB的代表的半導體封裝之進一步細節；
圖3a至3l為說明一種在半導體晶粒的周圍區域中形成通孔(THV)的方法；
圖4為說明其形成於半導體晶粒的周圍區域之傳導半THV的俯視圖；
圖5為說明其形成於半導體晶粒的周圍區域之傳導全THV的俯視圖；
圖6為說明其具有傳導THV之堆疊的半導體晶粒；
圖7為說明其形成為於半導體晶粒的周圍區域的多個偏離列之傳導全THV與傳導半THV的俯視圖；
圖8為說明其形成於半導體晶粒的周圍區域的傳導THV之間的雜訊吸收區域的俯視圖；
圖9為說明其形成於半導體晶粒的周圍區域的傳導THV之間的雜訊吸收區域的橫截面圖；
圖10為說明其散佈於半導體晶粒的周圍區域的傳導THV之間的一雜訊吸收材料；
圖11為說明其形成為環繞於半導體晶粒的周圍區域的各個傳導全THV之一雜訊吸收區域；
圖12為說明其形成為環繞於半導體晶粒的周圍區域的各個傳導半THV之一雜訊吸收區域；
圖13為說明於半導體晶粒的周圍區域的雜訊吸收區域與傳導THV之間的一障壁層；
圖14為說明其形成為環繞於半導體晶粒的周圍區域的多個傳導THV之一雜訊吸收區域；及
圖15為說明其形成為環繞於半導體晶粒的周圍區域之多個偏離列的各個傳導全THV之一雜訊吸收區域。
102．．．半導體晶粒
104．．．接觸墊
120．．．有機絕緣材料
128．．．導電材料或重新分佈層(RDL)
130．．．通孔(THV)

Claims (24)

  1. 一種製造半導體元件的方法，包含：提供包括一第一半導體晶粒和一第二半導體晶粒的一半導體晶圓；在該第一半導體晶粒和該第二半導體晶粒之間提供一周圍區域；沉積一絕緣材料於該第一半導體晶粒的一第一表面和相對該第一表面的一第二表面之間的該周圍區域中；形成一傳導孔在該絕緣材料中；形成一傳導層於該傳導孔與該第一半導體晶粒的一接觸墊之間；沉積一雜訊吸收材料於該第一半導體晶粒和該第二半導體晶粒之間的該周圍區域中，以使該第一半導體晶粒隔離有關元件內的干擾；及透過該周圍區域而使該半導體晶圓為單一化，以分隔該第一半導體晶粒與該第二半導體晶粒。
  2. 如申請專利範圍第1項之方法，其中，沉積該雜訊吸收材料更包含沉積該雜訊吸收材料自該第一半導體晶粒的該第一表面延伸通過該周圍區域而至該第一半導體晶粒的該第二表面。
  3. 如申請專利範圍第1項之方法，其中，該雜訊吸收材料具有一稜角、半圓形或矩形的形狀。
  4. 如申請專利範圍第1項之方法，更包括：散射該雜訊吸收材料於該傳導孔和該第一半導體晶粒之間的該周圍區 域中。
  5. 如申請專利範圍第1項之方法，更包括：形成該雜訊吸收材料以完全環繞於該周圍區域的傳導孔。
  6. 如申請專利範圍第1項之方法，更包括：形成複數個傳導孔於該周圍區域中；及沉積該雜訊吸收材料於該複數個傳導孔之間。
  7. 如申請專利範圍第1項之方法，更包括：形成一障壁層於該周圍區域的雜訊吸收材料與傳導孔之間。
  8. 一種製造半導體元件的方法，包含：提供具有一第一半導體晶粒和一第二半導體晶粒的一半導體晶圓；提供在該第一半導體晶粒和該第二半導體晶粒之間的一周圍區域；沉積一絕緣材料於該周圍區域中；形成一傳導孔於該絕緣材料中；形成一傳導層於該傳導孔與該第一半導體晶粒的一接觸墊之間；及形成一遮蔽區域於該第一半導體晶粒和該第二半導體晶粒之間的該周圍區域中。
  9. 如申請專利範圍第8項之方法，其中，形成該遮蔽區域更包括形成該遮蔽區域自該第一半導體晶粒的一第一側延伸通過該周圍區域而至該第一半導體晶粒中相對該第一側的一第二側。
  10. 如申請專利範圍第8項之方法，其中，該遮蔽區域 具有一稜角、半圓形或矩形的形狀。
  11. 如申請專利範圍第8項之方法，更包括：散射遮蔽材料於該傳導孔和該第一半導體晶粒之間的該遮蔽區域。
  12. 如申請專利範圍第8項之方法，更包括：形成該遮蔽區域以環繞於該周圍區域的傳導孔。
  13. 如申請專利範圍第8項之方法，更包括：形成一障壁層於該周圍區域的遮蔽區域與傳導孔之間。
  14. 一種製造半導體元件的方法，包含：形成一傳導孔於一半導體晶粒的一周圍區域；形成一傳導層於該傳導孔與該半導體晶粒的一接觸墊之間；及沉積一遮蔽材料於該周圍區域中且在該半導體晶粒的側表面上，以使該半導體晶粒隔離有關干擾。
  15. 如申請專利範圍第14項之方法，其中，沉積該遮蔽材料更包括沉積該遮蔽材料自該半導體晶粒的一第二側延伸通過該周圍區域而至該半導體晶粒中相對該第二側的一第三側。
  16. 如申請專利範圍第14項之方法，其中，該遮蔽材料具有一稜角、半圓形或矩形的形狀。
  17. 如申請專利範圍第14項之方法，更包括：沉積該遮蔽材料以環繞於該周圍區域的傳導孔。
  18. 如申請專利範圍第14項之方法，更包括：形成一障壁層於該周圍區域的遮蔽材料與傳導孔之間。
  19. 一種半導體元件，包含： 一半導體晶粒，包括一周圍區域；一傳導孔，形成於該半導體晶粒的周圍區域；一傳導層，形成於該傳導孔與該半導體晶粒的接觸墊之間；及一遮蔽材料，沉積於該周圍區域中且在該半導體晶粒的側表面上，以使該半導體晶粒隔離有關干擾。
  20. 如申請專利範圍第19項之半導體元件，其中，該遮蔽材料自該半導體晶粒的一第二表面延伸通過該周圍區域至該半導體晶粒的一第三表面。
  21. 如申請專利範圍第19項之半導體元件，其中，該遮蔽材料具有一稜角、半圓形或矩形的形狀。
  22. 如申請專利範圍第19項之半導體元件，其中，該遮蔽材料散射於該傳導孔之間的周圍區域。
  23. 如申請專利範圍第19項之半導體元件，其中，該遮蔽材料形成環繞於該周圍區域的傳導孔。
  24. 如申請專利範圍第19項之半導體元件，更包括：一障壁層，其形成於該周圍區域的遮蔽材料與傳導孔之間。
TW099106839A 2009-03-13 2010-03-10 半導體元件以及在半導體晶粒的周圍區域中的導電孔之間形成雜訊吸收區域的方法 TWI517270B (zh)

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