TWI553713B - 半導體裝置之製造方法 - Google Patents

半導體裝置之製造方法 Download PDF

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TWI553713B
TWI553713B TW103101925A TW103101925A TWI553713B TW I553713 B TWI553713 B TW I553713B TW 103101925 A TW103101925 A TW 103101925A TW 103101925 A TW103101925 A TW 103101925A TW I553713 B TWI553713 B TW I553713B
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metal
dielectric material
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TW201436006A (zh
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黃琮閔
李忠儒
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台灣積體電路製造股份有限公司
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Description

半導體裝置之製造方法
本發明係有關於半導體裝置及其製造方法，特別係有關於一種具有自組裝單層膜的半導體裝置及其製造方法。
在現代積體電路中，最小元件尺寸，例如場效電晶體的通道長度，已達到深次微米範圍，並藉此穩定地增加電路在速度及功率消耗方面的性能。當個別電路元件的尺寸縮小時，積體電路中可供用來作為導電內連線的區域亦跟著縮小。因此，此內連線必須縮小以補償可用區域的縮小量以及每個晶片上電路元件數量的增加。
在最小尺寸約為0.35μm以下的積體電路中，其中一個裝置性能的限制因素為電晶體元件切換速度所造成的訊號傳遞延遲。當這些電晶體元件的通道長度已達到0.18μm或更小時，鄰近的導電結構間的電容會增加並造成問題。寄生電阻電容時間常數(Parasitic RC time constants)使半導體製成技術亟需一個形成金屬化層的新材料與方法。
傳統上，金屬化層的形成係將介電層堆疊，例如包括二氧化矽及/或氮化矽，並以鋁作為典型的金屬材料。由於鋁在高電流密度下會有顯著的電遷移，因此以銅取代鋁。銅具有明顯較低的電阻且減少了電遷移的問題。
然而，將銅引入製程亦產生許多需要解決的問題。例如，銅無法藉由已發展完備的異向性蝕刻製程有效的圖案化，因此鑲嵌技術被用來形成包括銅線的金屬化層。另一個問題是銅很容易在二氧化矽中擴散，銅的擴散會對元件的性能有負面的影響，甚至導致元件完全故障。因此，必須要有一個擴散阻障層介於銅表面及相鄰的材料之間，以防止銅擴散進入元件的敏感區。氮化矽、TiN及TaN係已知的有效的銅擴散阻障層，因此常被當作介電阻障材料以隔離銅表面及層間介電層，例二氧化矽。此阻障層通常以現有的沉積技術沉積，例如物理氣相沉積及原子層沉積。然而，由於圖案的頂部相對於底部有較快的阻障層材料沉積速率，此用於圖案化材料的沉積技術無法提供均勻的圖案化形狀。此外，物理氣相沉積及原子層沉積需要高溫且其成本較高。
本揭露提供多個實施例。根據一實施例，一種半導體裝置之製造方法包括：形成第一介電材料層於半導體基底上；圖案化第一介電材料層並於其中形成多個介層窗；形成金屬層於第一介電材料層上，其中金屬層填入多個介層窗；蝕刻金屬層使設於第一介電材料層上的部分金屬層被圖案化並形成多個金屬元件，其中多個金屬元件個別與多個介層窗對準；及形成自組裝單層膜於多個金屬元件的表面上。
一種半導體裝置之製造方法包括：提供半導體基底；形成第一介電材料層於半導體基底上；圖案化第一介電材料層並於其中形成多個介層窗；形成金屬層於第一介電材料層 上，其中金屬層填入多個介層窗；蝕刻金屬層使設於第一介電材料層上的部分金屬層被圖案化並形成多個金屬元件，其中多個金屬元件個別與多個介層窗對準；沉積自組裝單層膜於多個金屬元件及第一介電材料層的表面上並覆蓋半導體基底，自組裝單層膜與多個金屬元件的金屬反應；沖洗除去形成於第一介電材料層表面上自組裝單層膜未反應的部份，留下金屬元件表面上的自組裝單層膜；及形成第二介電材料層於自組裝單層膜及第一介電材料層上。
一種半導體裝置，包括第一低介電常數介電材料層，設於半導體基底上；第一銅合金元件，嵌入於第一低介電常數介電材料層中；阻障層，圍繞第一銅合金元件且***於第一低介電常數介電材料層與第一銅合金元件之間；第二低介電常數介電材料層，設於第一低介電常數介電材料層上；第二銅合金元件，嵌入於第二低介電常數介電材料層中；及自組裝單層膜，圍繞第二銅合金元件且***於第二低介電常數介電材料層與第二銅合金元件之間。
100‧‧‧半導體結構
110‧‧‧半導體基底
115‧‧‧導電元件
120‧‧‧阻障層
125‧‧‧第一介電材料層
130‧‧‧圖案化光阻層
135‧‧‧開口
140‧‧‧介層窗
145‧‧‧第一阻障層
150‧‧‧金屬層
155‧‧‧金屬元件
160‧‧‧金屬元件
165‧‧‧自組裝單層膜
170‧‧‧第二介電材料層
第1圖係根據本發明某些實施例之半導體裝置之製造方法的流程圖；第2-6及8-10圖係根據本發明某些實施例之部分晶圓於各製造階段的概略剖面圖；及第7圖係根據本發明一實施例之單層結構。
應了解的是，以下之敘述提供許多不同的實施例或例子，用以實施本發明之不同樣態。以下所述特定的元件及排列方式儘為簡單描述本發明。當然，這些僅用以舉例而非本發明之限定。此外，在不同實施例中可能使用重複的標號或標示。這些重複僅為了簡單清楚地敘述本發明，不代表所討論之不同實施例及/或結構之間具有任何關連性。再者，當述及一第一材料層位於一第二材料層上或之上時，包括第一材料層與第二材料層直接接觸之情形。或者，亦可能間隔有一或更多其它材料層之情形，在此情形中，第一材料層與第二材料層之間可能不直接接觸。
第1圖係根據本發明某些實施例之半導體裝置之製造方法2的流程圖。參見第1圖，方法2包括步驟4，其中形成第一介電材料層於半導體基底上。方法2包括步驟6，其中圖案化第一介電材料層並於其中形成多個介層窗。方法2包括步驟8，其中形成金屬層於第一介電材料層上，其中金屬層填入多個介層窗。方法2包括步驟10，其中蝕刻金屬層使設於第一介電材料層上的部分金屬層被圖案化並形成多個金屬元件，其中多個金屬元件個別與多個介層窗對準。方法2包括步驟12，其中形成自組裝單層膜於多個金屬元件的表面上。
第2-6及8-10圖係根據本發明第1圖方法2之某些實施例之部分晶圓於各製造階段的概略剖面圖。應了解的是，為了更佳的了解本揭露之發明精神，第2-6及8-10圖係為簡化之圖式。應了解的是，此處描述之材料、形狀、尺寸、結構及製程參數僅為說明之用，其並非用以限定本發明，任何所屬技術領 域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作任意之更動與潤飾。
參見第2圖，其提供半導體結構100。半導體結構100包括半導體基底110，其包括矽。此外，半導體基底110可包括其它元素半導體例如鍺。半導體基底110亦可包括化合物半導體例如碳化矽、砷化鎵、砷化銦及磷化銦。在一實施例中，半導體基底110包括磊晶層。例如，此基底可包括覆蓋於主體半導體上的磊晶層。此外，半導體基底110可包括絕緣層上覆矽(SOI)結構。例如，基底可包括埋藏氧化物(BOX)層，此埋藏氧化物(BOX)層可藉由例如植氧分離(SIMOX)或其它適合的技術的步驟形成，其它適合的步驟例如為晶圓結合及研磨。半導體基底110亦包括P型摻雜區及/或N型摻雜區，由例如離子佈植及/或擴散的步驟佈植。此摻雜區包括N井、P井、輕摻雜區(LDD)、重摻雜源極及汲極(S/D)及各種通道摻雜輪廓，將上述摻雜區作配置可形成各種積體電路裝置，例如互補金氧半場效電晶體(CMOSFET)、影像感測器及/或發光二極體。半導體基底110更包括功能元件，例如形成於基底上或基底中的電阻或電容。半導體基底110更包括橫向隔離元件，其可隔離形成於半導體基底110中的個裝置。在一實施例中，淺溝槽隔離(STI)元件係作為橫向隔離元件。各個積體電路裝置更包括其它元件，例如設於源極及汲極上的金屬矽化物及覆蓋於通道上的閘極堆疊。
半導體結構100亦可包括多個介電層及導電元件，其可整合形成內連線結構並連結各P型或N型摻雜區及其它 功能元件(例如閘極)，得到功能性的積體電路。在一實施例中，半導體結構100可包括部分內連線結構。此內連線結構將於後更進一步描述。
如上所述，半導體結構100包括內連線結構。此內連線結構包括多層內連線結構及與多層內連線結構整合之層間介電層，並提供電路以將基底110中的各裝置連結至輸入/輸出電源及訊號。此內連線結構包括各種金屬線、接點及導孔元件(或導孔栓塞)。金屬線提供水平電路。接點提供矽基底與金屬線之間的垂直連結，而導孔元件提供不同金屬層的金屬線間的垂直連結。
第2圖顯示作為範例之導電元件115。在一實施例中，導電元件115包括部分內連線結構。例如，導電元件115包括接點、金屬導孔或金屬線。在此實施例中，導電元件115可更進一步被阻障層120圍繞以防止擴散及/或提供材料附著力。導電元件115可包括Al、Cu、W或上述之組合。阻障層120可包括TiN、TaN、WN、TiSiN、TaSiN或其它相似材料。導電元件115及阻障層120可藉由包括微影製程、蝕刻及沉積的步驟形成。在另一實施例中，導電元件115包括電容、電阻或部分電阻的電極。或者，導電元件115包括摻雜區(例如源極或汲極)或閘極。在另一實施例中，導電元件115為設於源極、汲極或閘極上的金屬矽化物元件。此金屬矽化物元件可由自對準金屬矽化物(salicide)技術形成。
第2圖亦顯示第一介電材料層125，設於基底110及導電元件115上。第一介電材料層125包括例如氧化矽、氮化矽 的介電材料層、具有介電常數(K)低於熱氧化矽之介電材料層(因此稱為低介電常數介電材料層)或其它適合的介電材料層。在某些實施例中，低介電常數介電材料可包括氟摻雜矽玻璃、碳摻雜二氧化矽、黑鑽石®(Applied Materials of Santa Clara,California)、乾凝膠(Xerogel)、氣凝膠(Aerogel)、非晶氟化碳、聚對二甲苯(Parylene)、二苯並環丁烯(BCB，bis-benzocyclobutenes)、SiLK(Dow Chemical,Midland,Michigan)、聚醯亞胺及/或其它材料。在另一實施例中，低介電常數介電材料可包括超低介電常數介電材料(XLK)。在另一實施例中，低介電常數介電材料包括已知的多孔型態的Dow Corning介電材料，其以氫化矽倍半氧烷(hydrogen silsesquioxane)為主且稱為可流動氧化物(FOX；flowable oxide)。形成第一介電材料層125可為旋轉塗佈或化學氣相沉積。在一實施例中，化學機械研磨步驟、回蝕刻步驟及其它相似步驟可更進一步將第一介電材料層125的頂面磨平。
第2圖亦顯示形成於第一介電材料層125上的圖案化光阻層(或圖案化罩幕層)130。圖案化光阻層130包括各種開口135，其定義第一介電材料層125中形成介層窗的部份，並露出這些部分使其可於後續蝕刻步驟中被蝕刻。特別地，各開口135與各導電元件115對準。在一實施例中，圖案化光阻層130可由包括塗佈、曝光、曝光後烘烤及顯影的步驟形成。特別地，光阻塗佈可使用旋轉塗佈。在一曝光之實施例中，塗佈的光阻層由通過具有預先決定圖案的罩幕的輻射光束選擇性地曝光。在一實施例中，此輻射光束包括UV光。曝光步驟更包括 其它技術例如無罩幕曝光或寫入步驟。在曝光步驟後，圖案化光阻層130藉由熱烘烤步驟更進一步處理，此步驟稱為曝光後烘烤(PEB)。曝光後烘烤(PEB)包括在光阻層曝光部分的化學性質轉變的梯瀑反應(cascade)，光阻層的曝光部分轉變並使其在顯影劑中的溶解度增加。接著，基底上的光阻層被顯影。在顯影步驟中，光阻層的曝光部分被溶解並沖洗移除。因此，如第2圖所示，光阻層被圖案化並具有一或多個開口135。上述微影步驟僅為圖案化微影技術的製程步驟的子集合。此微影步驟更包括其它步驟，例如於適當的製程程序中清洗或烘烤。例如，已顯影的光阻層可更進一步烘烤，亦即硬烘烤。在某些實施例中，未曝光的部份溶解於顯影劑中(亦即，正光阻及負光阻皆包含於本發明)。
如第3圖所示，藉由將圖案化光阻層130作為蝕刻罩幕，第一介電材料層125可經由圖案化光阻層130的開口135蝕刻，並得到一或多個介層窗140於第一介電材料層125中，其中各導電元件115至少部分露出於介層窗140中。在圖案化光阻層130的開口135中露出的第一介電材料層125可藉由蝕刻步驟移除，此蝕刻步驟例如為乾蝕刻、濕蝕刻或上述之組合。在一實施例中，蝕刻步驟使用中密度電漿蝕刻系統，其使用電容耦合電漿；或高密度電漿蝕刻系統，其使用感應式電漿、螺旋電漿或電子迴旋共振電漿，其中露出的介電材料係藉由氟碳電漿異向性地移除，並形成介層窗140，如第3圖所示。此蝕刻步驟亦可使用其它乾蝕刻步驟。各乾蝕刻步驟的蝕刻機制可具有物理機制(亦即輝光放電濺射或離子研磨)或化學機制(亦即純 電漿蝕刻)或上述兩者之組合(亦即反應性離子蝕刻)。接著，光阻層130可藉由如濕式剝除或氧電漿灰化的步驟移除。在另一實施例中，蝕刻停止層設於基底110與第一介電材料層125之間，蝕刻步驟包括乾蝕刻以蝕刻第一介電材料層125並停止於蝕刻停止層。蝕刻步驟更包括濕蝕刻以移除介層窗140中的蝕刻停止層。在另一實施例中，硬罩幕可在蝕刻步驟中作為蝕刻罩幕以圖案化第一介電材料層125。
參見第4圖，第一阻障層145形成於介層窗140中，亦同時形成於第一介電材料層125之頂部。在一實施例中，第一阻障層145包括金屬且具有導電性，但不容許第一介電材料層125與填入介層窗140的金屬層之間的擴散與反應。第一阻障層145可包括耐火金屬及其氮化物。在某些實施例中，第一阻障層145包括TiN、TaN、Co、WN、TiSiN、TaSiN或上述之組合。第一阻障層145包括多層結構。例如，Ti及TiN層可作為第一阻障層。第一阻障層145可藉由物理氣相沉積、化學氣相沉積、有機金屬化學氣相沉積、原子層沉積或其它適合的技術沉積。在某些實施例中，如第5圖所示，第一阻障層145可藉由化學機械研磨步驟磨平，例如留下介層窗140中的第一阻障層。其它磨平第一阻障層145的方法亦可使用。
參見第5圖，金屬層150形成於第一阻障層145上。金屬層150填入介層窗140並更進一步覆蓋第一介電材料層125。金屬層150可包括Cu、Al、W或其它適合的導電材料。在本實施例中，金屬層150包括銅或銅合金，例如CuMn、CuAl或CuSi。更進一步在本實施例中，CuMn中Mn的重量濃度為約 0.5%至約2%。在一實施例中，金屬層150包括由物理氣相沉積步驟沉積的銅層。在另一實施例中，金屬層150包括由物理氣相沉積步驟沉積的銅種晶層及由化學電鍍形成的主體銅層。在另一實施例中，銅可藉由其它適合技術沉積，例如物理氣相沉積、化學氣相沉積、有機金屬化學氣相沉積或電鍍。可加入銅回焊(reflow)步驟以增進銅填充輪廓。
參見第6圖，金屬層150被圖案化並形成一或多個金屬元件於第一介電材料層125上。圖案化金屬層150的方法包括微影步驟及蝕刻。在微影步驟中，圖案化光阻層(未顯示)形成於金屬層150上，其係作為具有各個開口的蝕刻罩幕並露出要被移除的金屬層的區域。此形成圖案化光阻層的微影技術與形成圖案化光阻層130的技術相似。
進行金屬蝕刻步驟並經由蝕刻罩幕的開口蝕刻金屬層150，得到各金屬元件155於介層窗140中及各金屬元件160於第一介電材料層125上，如第6圖所示。在一實施例中，當位於下方的導電元件115為不同金屬層的金屬線時，介層窗140中的金屬元件155亦稱為金屬導孔、導孔元件或導孔，其提供金屬線之間的垂直電路。在另一實施例中，當位於下方的導電元件115為源極/汲極元件及/或閘極時，介層窗140中的金屬元件155亦稱為金屬接點、接點元件或接點，其提供金屬線與半導體基底之間的電路。在另一實施例中，第一介電材料層125上的金屬元件160稱為金屬線，其提供水平電路。
金屬蝕刻步驟使用電漿蝕刻。由於銅會形成具有氯的蝕刻產物-CuCl，且其在低於特定溫度時為非揮發性，因 此通常認為銅難以使用電漿蝕刻步驟蝕刻。因此實務上銅不可使用具有任何含有氯的蝕刻氣體蝕刻。因此，傳統用於形成鋁金屬線的消去蝕刻方法無法用於銅的蝕刻。克服非揮發性的銅化合物並使用適合的氣體組合是目前銅電漿蝕刻發展上面臨的挑戰。在一實施例中，蝕刻氣體包括碳、氫、氧及氮。在另一實施例中，使用於銅電漿蝕刻的銅蝕刻氣體包括含有氫的氣體，例如CxHy、CxFy、CxHyFz或上述之組合，其中下標X、Y或Z為大於0且小於6的值。為了簡潔的目的，下標X、Y或Z將於之後的敘述中省略。在本實施例中，使用於銅電漿蝕刻的銅蝕刻氣體更包括至少CO或O2其中之一，且至少N2或Ar其中之一。在一實施例中，含氫氣體的氣體流量為約1sccm至約100sccm，CO(或O2)的氣體流量為約1sccm至約500sccm，N2(或Ar)的氣體流量為約1sccm至約1000sccm。更進一步在本實施例中，電漿蝕刻溫度(基板溫度)為約20℃至約250℃。在另一實施例中，電漿蝕刻溫度為約20℃至約80℃。本發明之實驗指出，CuMn合金具有較高之蝕刻速率。某些實驗更顯示CuMn合金之蝕刻速率為不含有Mn的銅金屬蝕刻速率的1.5至3倍。
除了上述之圖案化金屬層150的方法外，亦可使用其它實施例之方法。在一實施例中，可額外使用濕蝕刻或使用濕蝕刻替代乾蝕刻以圖案化金屬層150。在另一實施例中，當金屬層150包括其它適合之金屬(例如Al、W)時，可以使用其它蝕刻氣體。在另一實施例中，可藉由包括微影及蝕刻的步驟形成並作為蝕刻罩幕的硬罩幕，此硬罩幕例如為氧化矽、碳 化矽、氮化矽、氮化鈦或氮化鉭。
於本發明中的半導體裝置製程裡，自組裝單層膜(SAM)形成於半導體結構100及金屬元件160上並作為銅阻障層。第7圖係為自組裝單層膜之代表圖，此自組裝單層膜沉積於覆蓋在半導體基底上的犧牲金屬層上。自組裝單層膜包括兩性分子的組織層(organized layer)，其中此兩性(amphiphilic)分子的其中一端，亦即頭基，對基板具有專一且可逆的親和力。一般來說，頭基連結至烷基鏈(alkyl chain)，其中尾基或末端可以被官能化並改變濕潤及介面性質。在一實施例中，此末端被官能化以增加蝕刻選擇性。此外，在一實施例中，烷基鏈的碳鏈長度(C-C)n可以被調整以定義關鍵尺寸，其可增加或減少圖案的寬度。頭基的選擇係依據使用之自組裝單層膜而決定，而此自組裝單層膜係依據使用的基底而決定。在一實施例中，頭基可包括有機硫化合物，例如二正烷硫基(di-n-alkyl sulfide)、二正烷二硫基(di-n-alkyl disulfide)、苯硫酚(thiophenol)、吡啶硫醇(mercaptopyridine)、氨基苯硫酚(mercaptoaniline)、噻吩(thiophene)、半胱胺酸(cysteine)、黃酸鹽(xanthate)、thiocarbaminate、硫代氨基甲酸酯(thiocarbamate)、硫代尿素(thiourea)、咪唑硫醇(mercaptoimidazole)、烷基硫醇(alkanethiol)及烷基硒醇(alkaneselenol)。在一實施例中，頭基包括硫醇、氯或氟。基底可具有平坦表面，例如矽及金屬，此金屬可包括銅、鐵、銀、金、鎳、鉑、鈀、不鏽鋼。基底亦可具有彎曲表面，例如奈米粒子。在一實施例中，基底包括金屬犧牲層。
如第8圖所示，自組裝單層膜(SAM)165沉積於多個金屬元件160及第一介電材料層125的表面上並覆蓋半導體基底100。此自組裝單層膜係由親水性頭基化學吸附於金屬元件160上及後續之緩慢的親油性尾基的二維組織化(organization)形成。自組裝單層膜之吸附可於溶液中完成。在一實施例中，基底110浸入烷基硫醇的稀釋乙醇溶液。自組裝單層膜之吸附可於氣相中完成。吸附之分子一開始形成不規則的分子聚集，並立即開始於金屬元件160上的單層中形成結晶結構或半結晶結構。由於自組裝單層膜的頭基對金屬元件160的金屬具有親和力，此自組裝單層膜會選擇性地沉積於金屬元件160上並形成金屬錯合物。此自組裝單層膜不會與第一介電材料層125反應。自組裝單層膜可藉由溶液的旋轉塗佈沉積。例如，此溶液可為烷基硫醇的乙醇溶液。在第一介電材料層125的表面上自組裝單層膜未反應的部份可藉由適當的溶劑沖洗除去，並留下金屬元件160的表面上的自組裝單層膜。然而，應瞭解的是，留在金屬元件160表面上的自組裝單層膜的厚度可藉由調整自組裝單層膜的烷基鏈的碳鏈長度來調整，如第9圖所示。因此，自組裝單層膜165可達到良好的均勻性。在一實施例中，自組裝單層膜165具有小於10埃的厚度。
參見第10圖，第二介電材料層170形成並圍繞金屬元件160。在一實施例中，第二介電材料層170的組成與第一介電材料層125相似。例如，第二介電材料層170包括低介電常數介電材料、氧化矽或其它適合的介電材料層。第二介電材料層170沉積於自組裝單層膜165與第一介電材料層125上。在一實 施例中，第二介電材料層170實質上填入金屬元件160之間的區域。或者，沉積於金屬元件160之間的第二介電材料層170包括空隙(或空氣間隙)以進一步降低平均介電常數並增加隔離效率。空氣間隙可藉由選擇並調整用以形成第二介電材料層170的沉積製程來形成。
在一實施例中，第二介電材料層170係藉由化學氣相沉積形成，並可藉由調整此化學氣相沉積來形成空氣間隙。例如，當化學氣相沉積速率被調高使第二介電材料層170於填滿金屬元件160之間的區域之前即封閉，可形成空氣間隙。在另一實施例中，第二介電材料層170藉由旋轉塗佈介電質(SOD)製程沉積並填入金屬元件160之間的區域。如果需要平坦的輪廓，第二介電材料層170可藉由化學機械研磨來磨平。
雖然本發明的實施例及其優點已揭露如上，但應該瞭解的是，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作更動、替代與潤飾。此外，本發明之保護範圍並未侷限於說明書內所述特定實施例中的製程、機器、製造、物質組成、裝置、方法及步驟，任何所屬技術領域中具有通常知識者可從本發明揭示內容中理解現行或未來所發展出的製程、機器、製造、物質組成、裝置、方法及步驟，只要可以在此處所述實施例中實施大抵相同功能或獲得大抵相同結果皆可根據本發明使用。因此，本發明之保護範圍包括上述製程、機器、製造、物質組成、裝置、方法及步驟。另外，每一申請專利範圍構成個別的實施例，且本發明之保護範圍也包括各個申請專利範圍及實施例的組合。
100‧‧‧半導體結構
110‧‧‧半導體基底
115‧‧‧導電元件
120‧‧‧阻障層
125‧‧‧第一介電材料層
145‧‧‧第一阻障層
150‧‧‧金屬層
155‧‧‧金屬元件
160‧‧‧金屬元件
165‧‧‧自組裝單層膜
170‧‧‧第二介電材料層

Claims (9)

  1. 一種半導體裝置之製造方法，包括：形成一第一介電材料層於一半導體基底上；圖案化該第一介電材料層並於其中形成多個介層窗；形成一金屬層於該第一介電材料層上，其中該金屬層填入該多個介層窗；蝕刻該金屬層使設於該第一介電材料層上的部分該金屬層被圖案化並形成多個金屬元件，其中該多個金屬元件個別與該多個介層窗對準；及形成一自組裝單層膜於該多個金屬元件的表面上。
  2. 如申請專利範圍第1項所述之半導體裝置之製造方法，其中形成該自組裝單層膜包括旋轉塗佈。
  3. 如申請專利範圍第1項所述之半導體裝置之製造方法，其中該自組裝單層膜包括一頭基及一尾基，其中該自組裝單層膜包括硫醇基、氯或氟的頭基，該尾基係可調整的以增加或減少該自組裝單層膜之厚度。
  4. 如申請專利範圍第3項所述之半導體裝置之製造方法，其中該尾基被官能化以增加蝕刻選擇性。
  5. 如申請專利範圍第1項所述之半導體裝置之製造方法，其中該自組裝單層膜選擇性地形成於該多個金屬元件上，且不形成於該第一介電材料層的表面上。
  6. 如申請專利範圍第1項所述之半導體裝置之製造方法，其中形成該金屬層包括形成一擇自由Cu、CuMn、CuAl、CuSi及前述之組合所組成之族群的含銅材料。
  7. 一種半導體裝置之製造方法，包括：提供一半導體基底；形成一第一介電材料層於該半導體基底上；圖案化該第一介電材料層並於其中形成多個介層窗；形成一金屬層於該第一介電材料層上，其中該金屬層填入該多個介層窗；蝕刻該金屬層使設於該第一介電材料層上的部分該金屬層被圖案化並形成多個金屬元件，其中該多個金屬元件個別與該多個介層窗對準；沉積一自組裝單層膜於該多個金屬元件及該第一介電材料層的表面上並覆蓋該半導體基底，該自組裝單層膜與該多個金屬元件的金屬反應；沖洗除去形成於該第一介電材料層表面上該自組裝單層膜未反應的部份，留下該金屬元件表面上的該自組裝單層膜；及形成一第二介電材料層於該自組裝單層膜及該第一介電材料層上。
  8. 如申請專利範圍第7項所述之半導體裝置之製造方法，其中該自組裝單層膜包括一頭基及一尾基，其中該頭基包括硫醇基、氯或氟，該尾基係可調整的以增加或減少該自組裝單層膜之厚度。
  9. 如申請專利範圍第8項所述之半導體裝置之製造方法，其中該尾基被官能化以增加蝕刻選擇性。
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