TWI550145B - An oxide sintered body, a sputtering target, and an oxide semiconductor thin film obtained therefrom - Google Patents

An oxide sintered body, a sputtering target, and an oxide semiconductor thin film obtained therefrom Download PDF

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Publication number
TWI550145B
TWI550145B TW104120446A TW104120446A TWI550145B TW I550145 B TWI550145 B TW I550145B TW 104120446 A TW104120446 A TW 104120446A TW 104120446 A TW104120446 A TW 104120446A TW I550145 B TWI550145 B TW I550145B
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Taiwan
Prior art keywords
phase
oxide
sintered body
less
gallium
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TW104120446A
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English (en)
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TW201608066A (zh
Inventor
Tokuyuki Nakayama
Eiichiro Nishimura
Fumihiko Matsumura
Masashi Iwara
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Sumitomo Metal Mining Co
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    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/22—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the process of coating
    • C23C14/34—Sputtering
    • C23C14/3407—Cathode assembly for sputtering apparatus, e.g. Target
    • C23C14/3414—Metallurgical or chemical aspects of target preparation, e.g. casting, powder metallurgy
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    • C01G15/00—Compounds of gallium, indium or thallium
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Description

氧化物燒結體、濺鍍用靶及使用其而得之氧化物半導體薄膜
本發明係關於一種氧化物燒結體、靶及使用其而得之氧化物半導體薄膜，更詳細而言，係關於一種顯示出較低之載體濃度與較高之載體遷移率之非晶質之含有銦、鎵及正二價元素(選自由鎳、鈷、鈣、鍶及鉛組成之群中之一種以上之正二價元素)之氧化物半導體薄膜、適於其之形成之含有銦、鎵及正二價元素(選自由鎳、鈷、鈣、鍶及鉛組成之群中之一種以上之正二價元素)之濺鍍用靶、適於獲得其之含有銦、鎵及正二價元素(選自由鎳、鈷、鈣、鍶及鉛組成之群中之一種以上之正二價元素)之氧化物燒結體。
薄膜電晶體(Thin Film Transistor，TFT)為場效電晶體(Field Effect Transistor，以下稱為FET)之一種。TFT係具備閘極端子、源極端子、及汲極端子作為基本構成之3端子元件，且係使用於基板上成膜之半導體薄膜作為供電子或電洞進行遷移之通道層，具有對閘極端子施加電壓，控制通道層中所流動之電流，而對源極端子與汲極端子間之電流進行切換之功能的主動元件。TFT係目前最多地被實用化之電子裝置，作為其代表性用途有液晶驅動用元件。
作為TFT，目前被最廣泛地使用者係以多晶矽膜或非晶質矽膜作為通道層材料之Metal-Insulator-Semiconductor-FET(MIS-FET)。使用矽之MIS-FET由於對可見光為不透明，故而無法構成透明電路。因此，於應用MIS-FET作為液晶顯示器之液晶驅動用開關元件之情形時，該器件之顯示器像素之開口比變小。
又，最近，隨著要求液晶之高精細化，對液晶驅動用開關元件亦要求高速驅動。為了實現高速驅動，需要將電子或電洞之遷移率至少高於非晶質矽的半導體薄膜用於通道層。
針對此種狀況，專利文獻1中提出有一種透明半絕緣性非晶質氧化物薄膜，其係藉由氣相成膜法而成膜且由In、Ga、Zn及O之元素構成之透明非晶質氧化物薄膜，其特徵在於：關於該氧化物之組成，經結晶化時之組成為InGaO3(ZnO)m(m為未達6之自然數)，於未添加雜質離子之情況下為半絕緣性，即，載體遷移率(亦稱為載體電子遷移率)超過1cm2V-1sec-1且載體濃度(亦稱為載體電子濃度)為1016cm-3以下；以及提出有一種薄膜電晶體，其特徵在於：將該透明半絕緣性非晶質氧化物薄膜作為通道層。
但是，對於專利文獻1中所提出之藉由濺鍍法、脈衝雷射蒸鍍法之任一氣相成膜法而成膜且由In、Ga、Zn及O之元素構成之透明非晶質氧化物薄膜(a-IGZO膜)，業界指出其止於大致1~10cm2V-1sec-1之範圍之電子載體遷移率，故而於作為TFT之通道層而形成之情形時遷移率不足。
又，專利文獻2中提出有如下之半導體器件：其使用含有In 與In以外之兩種以上之金屬，且電子載體濃度未達1×1018cm-3之多晶氧化物半導體薄膜。專利文獻2之請求項6中記載有上述In以外之兩種以上之金屬為正二價金屬與正三價金屬，進而專利文獻2之請求項7中記載有上述正二價金屬係選自Zn、Mg、Cu、Ni、Co、Ca及Sr中之至少一種元素，且上述正三價金屬係選自Ga、Al、B、La、Ce、Pr、Nd、Sm、Eu、Gd、Tb、Dy、Ho、Er、Tm、Yb及Lu中之至少一種元素。
然而，專利文獻2中未記載Ga與選自Ni、Co、Ca及Si中之至少一種元素之組合之實施例。又，關於該等組合以外之實施例，其電洞遷移率較低而未達10cm2V-1sec-1。進而，並無為了避免產生電弧或結核(nodule)，氧化物半導體薄膜之濺鍍成膜中所使用之氧化物燒結體較佳為何種燒結體組織之啟示。又，濺鍍成膜係以高頻(RF)濺鍍進行，亦不確定濺鍍靶是否可進行直流(DC)濺鍍。
[先前技術文獻]
[專利文獻]
[專利文獻1]日本特開2010-219538號公報
[專利文獻2]WO2008/117739號公報
[專利文獻3]WO2003/014409號公報
[專利文獻4]日本特開2012-253372號公報
[非專利文獻1]A. Takagi, K. Nomura, H. Ohta, H. Yanagi, T. Kamiya, M. Hirano, and H. Hosono, Thin Solid Films 486, 38 (2005)
本發明之目的在於提供一種可降低非晶質之氧化物半導體薄膜之載體濃度之濺鍍用靶、對於獲得其而言最適合之氧化物燒結體、以及使用其而得之顯示出較低之載體濃度與較高之載體遷移率的氧化物半導體薄膜。
本發明人等新發現，尤其是藉由使銦與鎵之Ga/(In+Ga)比為0.20以上且0.45以下，且以氧化物之形式含有鎵之氧化物燒結體含有少量選自由鎳、鈷、鈣、鍶及鉛組成之群中之一種以上之正二價元素M、具體而言為M/(In+Ga+M)之比為0.0001以上且0.05以下之正二價元素M，從而經燒結之氧化物燒結體實質上由方鐵錳礦(bixbyite)型結構之In2O3相與In2O3相以外之生成相之β-Ga2O3型結構之GaInO3相、或β-Ga2O3型結構之GaInO3相與(Ga,In)2O3相構成，且使用該氧化物燒結體所製作之氧化物半導體薄膜之載體遷移率為10cm2V-1sec-1以上。
即，第一發明係一種氧化物燒結體，其以氧化物之形式含有銦、鎵及正二價元素，上述鎵之含量以Ga/(In+Ga)原子數比計為0.20以上且0.45以下，上述正二價元素之總含量以M/(In+Ga+M)原子數比計為0.0001以上且0.05以下，上述正二價元素係選自由鎳、鈷、鈣、鍶及鉛組成之群中之一種以上，由方鐵錳礦型結構之In2O3相與In2O3相以外之生成相之β-Ga2O3型結構之GaInO3相、或β-Ga2O3型結構之GaInO3相及(Ga,In)2O3相構成，實質上不含由上述正二價元素與鎵構成之複合氧化物之 NiGa2O4相、CoGa2O4相、CaGa4O7相、Ca5Ga6O14相、SrGa12O19相、SrGa2O4相、Sr3Ga2O6相、Ga2PbO4相、或該等之複合氧化物相。
第二發明係如第一發明之氧化物燒結體，其中，上述正二價元素之總含量以M/(In+Ga+M)原子數比計為0.0001以上且0.03以下。
第三發明係如第一或第二發明之氧化物燒結體，其中，上述鎵之含量以Ga/(In+Ga)原子數比計為0.20以上且0.30以下。
第四發明係如第一或第二發明之氧化物燒結體，其實質上不含上述正二價元素以外之正二價元素、及銦與鎵以外之正三價至正六價元素。
第五發明係如第一或第二發明之氧化物燒結體，其中，下述式1所定義之β-Ga2O3型結構之GaInO3相的X射線繞射波峰強度比為29%以上且75%以下之範圍。
100×I[GaInO3相(111)]/{I[In2O3相(400)]+I[GaInO3相(111)]}[%]式1
第六發明係一種濺鍍用靶，其係對第一或第二發明之氧化物燒結體進行加工而獲得。
第七發明係一種氧化物半導體薄膜，其係使用第六發明之濺鍍用靶藉由濺鍍法形成於基板上之後，進行熱處理而成之非晶質之氧化物半導體薄膜。
第八發明係如第七發明之氧化物半導體薄膜，其載體遷移率為10cm2V-1sec-1以上。
第九發明係如第七或第八發明之氧化物半導體薄膜，其載體 濃度未達3.0×1018cm-3。
本發明之以氧化物之形式含有銦及鎵且含有以M/(In+Ga+M)之原子數比計為0.0001以上且0.05以下之上述正二價元素M之氧化物燒結體例如於用作濺鍍用靶之情形時，可獲得藉由濺鍍成膜而形成，其後藉由熱處理而獲得之本發明之非晶質之氧化物半導體薄膜。上述非晶質之氧化物半導體薄膜藉由含有特定量之鎵與鎂之效果，不會生成微晶等，而具有充分之非晶質性，故而可藉由濕式蝕刻圖案化加工成所需之形狀。又，藉由相同效果，本發明之非晶質之氧化物半導體薄膜顯示出較低之載體濃度與較高之載體遷移率。因此，本發明之非晶質之氧化物半導體薄膜可用作TFT之通道層。因此，本發明之氧化物燒結體、靶及使用其而得之氧化物半導體薄膜於工業上極有用。
以下，對本發明之氧化物燒結體、濺鍍用靶及使用其而得之氧化物半導體薄膜進行詳細說明。
本發明之氧化物燒結體之特徵在於：其以氧化物之形式含有銦、鎵及正二價元素M，並且鎵以Ga/(In+Ga)原子數比計為0.20以上且0.45以下，上述正二價元素M以M/(In+Ga+M)原子數比計為0.0001 以上且0.05以下，且上述二價元素M係選自由鎳、鈷、鈣、鍶及鉛組成之群中之一種以上之元素。
鎵之含量以Ga/(In+Ga)原子數比計為0.20以上且0.45以下，更佳為0.20以上且0.30以下。鎵於與氧之鍵結力方面較強，有降低本發明之非晶質之氧化物半導體薄膜之氧空位量的效果。於鎵之含量以Ga/(In+Ga)原子數比計未達0.20之情形時，無法充分地獲得該效果。另一方面，於超過0.45之情形時，無法獲得作為氧化物半導體薄膜而言充分高之載體遷移率。
本發明之氧化物燒結體除含有如上述般規定之組成範圍之銦與鎵以外，亦含有上述正二價元素M。上述正二價元素M之濃度以M/(In+Ga+M)之原子數比計為0.0001以上且0.05以下，較佳為0.0001以上且0.03以下。
本發明之氧化物燒結體藉由添加上述範圍內之上述正二價元素M，可藉由將主要因氧空位所生成之電子加以中和之作用而抑制載體濃度，於將本發明之非晶質之氧化物半導體薄膜應用於TFT之情形時，可提高TFT之on/off。
再者，較佳為於本發明之氧化物燒結體中，實質上不含上述正二價元素M以外之正二價元素、及銦與鎵以外之正三價至正六價元素即元素M'。此處，所謂實質上不含，係各自單獨之元素M'以M'/(In+Ga+M')之原子數比計為500ppm以下，較佳為200ppm以下，更佳為100ppm以下。作為具體之元素M'之例示，作為正二價元素，可例示：Cu、Mg、Zn，作為正三價元素，可例示：Al、Y、Sc、B、鑭系元素，作為正四價元素， 可例示：Sn、Ge、Ti、Si、Zr、Hf、C、Ce，作為正五價元素，可例示Nb、Ta，作為正六價元素，可例示W、Mo。
1.氧化物燒結體組織
本發明之氧化物燒結體較佳為由方鐵錳礦型結構之In2O3相與In2O3相以外之生成相之β-Ga2O3型結構之GaInO3相、或β-Ga2O3型結構之GaInO3相與(Ga,In)2O3相構成。若氧化物燒結體僅由In2O3相構成，則無論是否含有上述正二價元素M，例如與專利文獻3(WO2003/014409號公報)之比較例11同樣地產生結核。另一方面，上述NiGa2O4相、CoGa2O4相、CaGa4O7相、Ca5Ga6O14相、SrGa12O19相、SrGa2O4相、Sr3Ga2O6相、Ga2PbO4相、或該等之複合氧化物相由於電阻值高於In2O3相或GaInO3，故而於濺鍍成膜中容易凹陷而容易產生結核。又，使用生成該等相之氧化物燒結體而濺鍍成膜之氧化物半導體薄膜有載體遷移率降低之傾向。
鎵及上述正二價元素M固溶於In2O3相。又，鎵構成GaInO3相或(Ga,In)2O3相。於固溶於In2O3相之情形時，鎵與上述正二價元素M置換至作為正三價離子之銦之晶格位置。因燒結未進行等原因，鎵在未固溶於In2O3相之情況下形成β-Ga2O3型結構之Ga2O3相，故而欠佳。Ga2O3相由於缺乏導電性，故而會導致異常放電。
本發明之氧化物燒結體除含有方鐵錳礦型結構之In2O3相以外，亦可在下述式1所定義之X射線繞射波峰強度比為29%以上且75%以下之範圍內僅含有β-Ga2O3型結構之GaInO3相，或含有β-Ga2O3型結構之GaInO3相與(Ga,In)2O3相。
100×I[GaInO3相(111)]/{I[In2O3相(400)]+I[GaInO3相 (111)]}[%] 式1
(式中，I[In2O3相(400)]為方鐵錳礦型結構之In2O3相之(400)波峰強度，I[GaInO3相(111)]表示β-Ga2O3型結構之複合氧化物β-GaInO3相(111)波峰強度)
2.氧化物燒結體之製造方法
本發明之氧化物燒結體係以由氧化銦粉末與氧化鎵粉末構成之氧化物粉末、以及上述正二價元素M之氧化物粉末作為原料粉末。
於本發明之氧化物燒結體之製造步驟中，於將該等原料粉末混合後進行成形，並藉由常壓燒結法對成形物進行燒結。本發明之氧化物燒結體組織之生成相較強地取決於氧化物燒結體之各步驟之製造條件，例如原料粉末之粒徑、混合條件及燒結條件。
較佳為本發明之氧化物燒結體之組織係由方鐵錳礦型結構之In2O3相與In2O3相以外之生成相之β-Ga2O3型結構之GaInO3相、或β-Ga2O3型結構之GaInO3相與(Ga,In)2O3相以所需比率構成，為此，較佳為將上述各原料粉末之平均粒徑設為3μm以下，更佳為設為1.5μm以下。如上所述，由於除含有In2O3相以外亦含有β-Ga2O3型結構之GaInO3相、或β-Ga2O3型結構之GaInO3相與(Ga,In)2O3相，故而為了抑制該等相之過量生成，較佳為將各原料粉末之平均粒徑設為1.5μm以下。
氧化銦粉末為ITO(銦-錫氧化物)之原料，燒結性優異之微細之氧化銦粉末之開發係與ITO之改良一併推進。氧化銦粉末由於被持續大量用作ITO用原料，故而最近可獲取平均粒徑0.8μm以下之原料粉末。
且說，於氧化鎵粉末或上述正二價元素M之氧化物粉末之 情形時，由於與氧化銦粉末相比使用量依然較少，故而難以獲取平均粒徑1.5μm以下之原料粉末。因此，於僅可獲取粗大之氧化鎵粉末之情形時，需要粉碎至平均粒徑1.5μm以下。
於本發明之氧化物燒結體之燒結步驟中，較佳為應用常壓燒結法。常壓燒結法為簡便且於工業上有利之方法，就低成本之觀點而言亦為較佳手段。
於使用常壓燒結法之情形時，如上所述，首先製作成形體。將原料粉末添加至樹脂製罐中，與黏合劑(例如PVA)等一併利用濕式球磨機等進行混合。於本發明之氧化物燒結體之製作中，為了抑制除In2O3相以外之β-Ga2O3型結構之GaInO3相、或β-Ga2O3型結構之GaInO3相與(Ga,In)2O3相之過量生成，或者不生成β-Ga2O3型結構之Ga2O3相，較佳為進行上述球磨機混合18小時以上。此時，作為混合用球，使用硬質ZrO2球即可。混合後，將漿料取出，並進行過濾、乾燥、造粒。其後，藉由冷均壓加壓而施加9.8MPa(0.1ton/cm2)~294MPa(3ton/cm2)左右之壓力將所獲得之造粒物成形，而製成成形體。
於常壓燒結法之燒結步驟中，較佳為設為存在氧之環境，更佳為環境中之氧體積分率超過20%。尤其是藉由使氧體積分率超過20%，氧化物燒結體進一步高密度化。藉由環境中之過量之氧，而於燒結初期先進行成形體表面之燒結。繼而，進行成形體內部之還原狀態下之燒結，最終獲得高密度之氧化物燒結體。
於不存在氧之環境中，由於未先進行成形體表面之燒結，因此結果燒結體之高密度化不會進行。若不存在氧，則尤其於900~1000℃左 右氧化銦會分解而產生金屬銦，因此難以獲得目標之氧化物燒結體。
常壓燒結之溫度範圍較佳為設為1200℃以上且1550℃以下，更佳為於在燒結爐內之大氣中導入氧氣之環境中於1350℃以上且1450℃以下進行燒結。燒結時間較佳為10~30小時，更佳為15~25小時。
藉由將燒結溫度設為上述範圍，且使用由上述平均粒徑已調整為1.5μm以下之氧化銦粉末與氧化鎵粉末構成之氧化物粉末、以及上述正二價元素M之氧化物粉末作為原料粉末，可獲得由方鐵錳礦型結構之In2O3相與In2O3相以外之生成相之β-Ga2O3型結構之GaInO3相、或β-Ga2O3型結構之GaInO3相與(Ga,In)2O3相構成之氧化物燒結體。
於燒結溫度未達1200℃之情形時，燒結反應未充分進行，而發生氧化物燒結體之密度未達6.4g/cm3之不良情況。另一方面，若燒結溫度超過1550℃，則(Ga,In)2O3相之形成變得明顯。(Ga,In)2O3相之電阻高於GaInO3相，因此成為成膜速度降低之原因。若燒結溫度為1550℃以下、即有少量之(Ga,In)2O3相，則不會成為問題。就此種觀點而言，較佳為將燒結溫度設為1200℃以上且1550℃以下，更佳為設為1350℃以上且1450℃以下。
關於至燒結溫度為止之升溫速度，為了防止燒結體之破裂，進行脫黏合劑，較佳為將升溫速度設為0.2~5℃/min之範圍。若為該範圍，則視需要亦可將不同升溫速度組合而升溫至燒結溫度。於升溫過程中，為了進行脫黏合劑或燒結，亦可於特定溫度下保持一定時間。尤其於使用氧化鉛粉末作為原料粉末之情形時，為了促進鉛元素固溶於In2O3相，有效的是於1100℃以下之溫度下保持一定時間。保持時間並無特別限制，較佳為1 小時以上且10小時以下。燒結後進行冷卻時較佳為停止導入氧氣，並以0.2~5℃/min、尤其是0.2℃/min以上且未達1℃/min之範圍之降溫速度降溫至1000℃。
3.靶
可將上述氧化物燒結體切斷為特定大小，對表面進行研磨加工，並接著於背襯板而獲得。靶形狀較佳為平板形，但亦可為圓筒形。於使用圓筒形靶之情形時，較佳為抑制因靶旋轉所引起之微粒產生。
為了用作濺鍍用靶，本發明之氧化物燒結體之密度較佳為6.3g/cm3以上。於密度未達6.3g/cm3之情形時，會成為量產使用時產生結核之原因，故而欠佳。
4.氧化物半導體薄膜與其成膜方法
本發明之非晶質之氧化物半導體薄膜可藉由使用上述濺鍍用靶，藉由濺鍍法於基板上暫時形成非晶質之薄膜，繼而實施熱處理而獲得。
上述濺鍍用靶係利用氧化物燒結體所獲得，重要的是其氧化物燒結體組織、即由方鐵錳礦型結構之In2O3相及β-Ga2O3型結構之GaInO3相基本構成之組織。為了獲得本發明之非晶質之氧化物半導體薄膜，重要的是非晶質之氧化物薄膜之結晶化溫度較高，而其與氧化物燒結體組織相關。即，於如本發明中所使用之氧化物燒結體般不僅含有方鐵錳礦型結構之In2O3相，亦含有β-Ga2O3型結構之GaInO3相之情形時，由此獲得之成膜後之氧化物薄膜顯示出較高之結晶化溫度、即較佳為250℃以上、更佳為300℃以上、進而較佳為350℃以上之結晶化溫度，成為穩定之非晶質。相對於此，於氧化物燒結體僅由方鐵錳礦型結構之In2O3相構成之情形時，關 於成膜後之氧化物薄膜，其結晶化溫度較低，為190~230℃左右，而非穩定之非晶質。因此，存在若於250℃左右進行熱處理則進行結晶化之情形。再者，於該情形時，於成膜後已生成微晶，未維持非晶質，而變得難以進行利用濕式蝕刻之圖案化加工。關於該情況，於通常之ITO(摻錫氧化銦)透明導電膜中眾所周知。
於非晶質之薄膜形成步驟中，可使用通常之濺鍍法，尤其是若為直流(DC)濺鍍法，則成膜時之熱影響較少，可進行高速成膜，故而於工業上有利。於藉由直流濺鍍法形成本發明之氧化物半導體薄膜時，較佳為使用由非活性氣體與氧氣、尤其是氬氣與氧氣構成之混合氣體作為濺鍍氣體。又，較佳為將濺鍍裝置之腔室內設為0.1~1Pa、尤其是0.2~0.8Pa之壓力而進行濺鍍。
關於基板，玻璃基板具有代表性，較佳為無鹼玻璃，樹脂板或樹脂膜中只要為可耐受上述製程之溫度者即可使用。
上述非晶質之薄膜形成步驟例如可於真空排氣至1×10-4Pa以下後，導入由氬氣與氧氣構成之混合氣體，將氣壓設為0.2~0.5Pa，以使相對於靶之面積之直流功率、即直流功率密度成為1~7W/cm2左右之範圍之方式施加直流功率而產生直流電漿，並實施預濺鍍。較佳為於進行該預濺鍍5~30分鐘後，視需要對基板位置進行修正，然後進行濺鍍成膜。於濺鍍成膜中，為了提高成膜速度，於所容許之範圍內提高所輸入之直流功率。
本發明之非晶質之氧化物半導體薄膜可藉由在上述非晶質之薄膜形成後，對其進行熱處理使之結晶化而獲得。熱處理條件於氧化性 環境中為結晶化溫度以上之溫度。作為氧化性環境，較佳為包含氧、臭氧、水蒸氣、或氮氧化物等之環境。熱處理溫度較佳為250~600℃，更佳為300~550℃，進而較佳為350~500℃。關於熱處理時間，保持在熱處理溫度之時間較佳為1~120分鐘，更佳為5~60分鐘。作為熱處理前之方法之一，例如於室溫附近等低溫下形成非晶質膜，其後，於未達結晶化溫度之上述溫度範圍內進行熱處理，於維持非晶質之狀態下獲得氧化物半導體薄膜。作為另一方法，將基板加熱至未達氧化物薄膜之結晶化溫度之溫度、較佳為100~300℃，而成膜非晶質之氧化物半導體薄膜。繼而，亦可進一步進行熱處理。
上述熱處理前之薄膜及熱處理後之非晶質之氧化物半導體薄膜之銦、鎵、及上述正二價元素M之組成係與本發明之氧化物燒結體之組成大致相同。即，為以氧化物之形式含有銦及鎵且含有上述正二價元素M之非晶質之氧化物半導體薄膜。鎵之含量以Ga/(In+Ga)原子數比計為0.20以上且0.45以下，上述正二價元素M之含量以M/(In+Ga+M)原子數比計為0.0001以上且0.05以下。鎵之含量以Ga/(In+Ga)原子數比計更佳為0.20以上且0.30以下，進而較佳為0.25以上且0.30以下。又，上述正二價元素M之含量以M/(In+Ga+M)原子數比計更佳為0.01以上且0.03以下。
本發明之非晶質之氧化物半導體薄膜藉由將如上所述之組成及組織經控制之氧化物燒結體用於濺鍍靶等而進行成膜，並於上述適當之條件下進行熱處理，從而使載體濃度降低至3.0×1018cm-3以下，更佳為獲得1.0×1018cm-3以下之載體濃度，尤佳為獲得8.0×1017cm-3以下之載體濃度。 如以非專利文獻1中所記載之由銦、鎵、及鋅構成之非晶質之氧化物半導體薄膜為代表，大量含有銦之非晶質之氧化物半導體薄膜於載體濃度為4×1018cm-3以上呈退化狀態，故而將其應用於通道層之TFT變得不顯示為常斷開(normally-off)。因此，本發明之非晶質之氧化物半導體薄膜可將載體濃度控制在上述TFT顯示為常斷開之範圍內，故而較佳。又，載體遷移率顯示10cm2V-1sec-1以上，更佳為載體遷移率顯示15cm2V-1sec-1以上。
本發明之非晶質之氧化物半導體薄膜藉由濕式蝕刻或乾式蝕刻，根據TFT等用途而實施所需之微細加工。通常，可自未達結晶化溫度之溫度、例如室溫至300℃之範圍內選擇適當之基板溫度而暫時形成非晶質之氧化物薄膜，然後利用濕式蝕刻實施微細加工。作為蝕刻劑，只要為弱酸，則基本上可使用，較佳為以草酸作為主成分之弱酸。例如可使用關東化學製造之ITO-06 N等。根據TFT之構成，亦可選擇乾式蝕刻。
本發明之非晶質之氧化物半導體薄膜之膜厚並無限定，為10~500nm，較佳為20~300nm，進而較佳為30~100nm。若未達10nm，則無法實現較高之載體遷移率。另一方面，若超過500nm，則產生生產性之問題，故而欠佳。
又，關於本發明之非晶質之氧化物半導體薄膜，其於可見光範圍(400~800nm)之平均透過率較佳為80%以上，更佳為85%以上，進而較佳為90%以上。於應用於透明TFT之情形時，若平均透過率未達80%，則作為透明顯示器件而言液晶元件或有機EL元件等之光之提取效率降低。
[實施例]
以下，使用本發明之實施例更詳細地進行說明，但本發明並 不受該等實施例之限定。
<氧化物燒結體之評價>
藉由ICP發光分光法調查所獲得之氧化物燒結體之金屬元素之組成。使用所獲得之氧化物燒結體之邊角材料，使用X射線繞射裝置(PHILIPS製造)藉由粉末法進行生成相之鑑定。
<氧化物薄膜之基本特性評價>
藉由ICP發光分光法調查所獲得之氧化物薄膜之組成。氧化物薄膜之膜厚係利用表面粗糙度計(Tencor公司製造)進行測定。成膜速度係根據膜厚與成膜時間而算出。氧化物薄膜之載體濃度及遷移率係藉由霍耳效應(Hall effect)測定裝置(東陽技術製造)而求出。膜之生成相係藉由X射線繞射測定而進行鑑定。
1.正二價元素M為Ni之情形
(燒結體之製作及評價)
以使平均粒徑成為1.5μm以下之方式調整氧化銦粉末、氧化鎵粉末、以及作為正二價元素M之氧化鎳粉末而製成原料粉末。以成為如表1之實施例及比較例之Ga/(In+Ga)原子數比、M/(In+Ga+M)原子數比之方式調製該等原料粉末，與水一併添加至樹脂製罐中，並利用濕式球磨機進行混合。此時，使用硬質ZrO2球，將混合時間設為18小時。混合後，將漿料取出，並進行過濾、乾燥、造粒。藉由冷均壓加壓而施加3ton/cm2之壓力將造粒物成形。
其次，以如下之方式對成形體進行燒結。於爐內容積每0.1m3以5升/分鐘之比率向燒結爐內之大氣中導入氧氣之環境下，於1000~1550 ℃之燒結溫度下進行20小時燒結。此時，以1℃/min進行升溫，於燒結後之冷卻時停止導入氧氣，並以10℃/min降溫至1000℃。
藉由ICP發光分光法進行所獲得之氧化物燒結體之組成分析，結果關於金屬元素，於任一實施例中均確認到與原料粉末之調配時之添加組成大致相同。
其次，利用X射線繞射測定進行氧化物燒結體之相鑑定，結果如表1所示，僅確認到由方鐵錳礦型結構之In2O3相所產生之繞射波峰，或僅確認到方鐵錳礦型結構之In2O3相、β-Ga2O3型結構之GaInO3相、及(Ga,In)2O3相之繞射波峰。
再者，於包含β-Ga2O3型結構之GaInO3相之情形時，將下述式1所定義之β-Ga2O3型結構之GaInO3相之X射線繞射波峰強度比示於表1。
100×I[GaInO3相(111)]/{I[In2O3相(400)]+I[GaInO3相(111)]}[%] 式1
(正二價元素為Ni)
將氧化物燒結體加工為直徑152mm、厚度5mm之大小，利用杯形磨石以使最大高度Rz成為3.0μm以下之方式對濺鍍面進行研磨。使用金屬銦將所加工之氧化物燒結體接合於無氧銅製之背襯板，而製成濺鍍用靶。
2.正二價元素M為Co、Ca、Sr、Pb之情形
使用作為上述正二價元素M之氧化鈷(II)、氧化鈣(II)、氧化鍶(II)、氧化鉛(II)，除此以外，與正二價元素M為Ni之情形同樣地進行氧化物燒結體之製作，並進行組成分析、相鑑定，而算出β-Ga2O3型結構之GaInO3相之X射線繞射波峰強度比。將使用氧化鈷(II)之情形時之結果示於表2，將使用氧化鈣(II)之情形時之結果示於表3，將使用氧化鍶(II)之情形時之結果示於表4，將使用氧化鉛(II)之情形時之結果示於表5。再者，於組成分析中，關於金屬元素，於任一實施例中均確認到與原料粉末之調 配時之添加組成大致相同。
(正二價元素為Co)
(正二價元素為Ca)
(正二價元素為Sr)
(正二價元素為Pb)
(濺鍍成膜評價)
於各實施例及比較例中，於基板溫度200℃藉由直流濺鍍進行成膜。於裝備有無電弧抑制功能之直流電源之直流磁控濺鍍裝置(Tokki製造)之陰極，安裝上述濺鍍靶。此時，將靶-基板(保持器)間距離固定為60mm。於真空排氣至1×10-4Pa以下後，根據各靶之鎵量以成為適當之氧之比率之方式導入氬氣與氧氣之混合氣體，將氣壓調整為0.6Pa。施加直流功率300W(1.64W/cm2)而產生直流電漿。於10分鐘之預濺鍍後，於濺鍍靶之正上方、即靜止對向位置配置基板，而形成膜厚50nm之氧化物薄膜。確認到所獲得之氧化物薄膜之組成與靶大致相同。又，進行測定X射線繞射，結果確認為非晶質。對所獲得之非晶質之氧化物薄膜，使用RTA(Rapid Thermal Annealing，快速熱退火)裝置，於大氣中在250~600℃實施30分鐘以內之熱處理。對熱處理後之氧化物薄膜進行X射線繞射測定，結果確認為非晶質。進行所獲得之非晶質之氧化物半導體薄膜之霍耳效應測定，求出載體濃度及遷移率。將所獲得之評價結果彙總記載於表6~表10。
(正二價元素為Ni)
(正二價元素為Co)
(正二價元素為Ca)
(正二價元素為Sr)
(正二價元素為Pb)
(結核產生評價)
對實施例2、10、14及比較例3、6之濺鍍用靶，實施模擬量產之因濺鍍成膜所引起之結核產生之評價。濺鍍裝置使用裝備有無電弧抑制功能之 直流電源之裝載鎖固(load lock)式通過型磁控濺鍍裝置(ULVAC製造)。靶使用縱5英吋、橫15英吋之方型之靶。將濺鍍成膜評價濺鍍室真空排氣至7×10-5Pa以下後，根據各靶之鎵量以成為適當之氧之比率之方式導入氬氣與氧氣之混合氣體，將氣壓調整為0.6Pa。選擇此種條件之濺鍍氣體之原因在於，於濺鍍室之真空度超過1×10-4Pa且腔室內之水分壓較高或添加氫氣之情形時，無法進行合理之評價。如ITO等眾所周知般，若源自水分或氫氣之H+被取入至膜中，則膜之結晶化溫度增高，附著於靶非剝蝕部之膜變得容易非晶質化。其結果為，膜應力降低，因此不易自非剝蝕部剝離，而不易產生結核。關於直流功率，考慮到通常量產中所採用之直流功率密度為3~6W/cm2左右，而設為2500W(直流功率密度5.17W/cm2)。
結核產生評價係於上述條件下，於50kWh之連續濺鍍放電後，對靶表面進行觀察，而評價有無結核產生。
「評價」
如表1~表5所示，於實施例1~29之鎵含量以Ga/(In+Ga)原子數比計為0.20以上且0.45以下，且上述正二價元素M之含量以M/(In+Ga+M)原子數比計為0.0001以上且0.05以下之情形時，由方鐵錳礦型結構之In2O3相與In2O3相以外之生成相之β-Ga2O3型結構之GaInO3相、或β-Ga2O3型結構之GaInO3相與(Ga,In)2O3相構成。
相對於此，比較例1、5、8、11、14之氧化物燒結體中，由於鎵含量以Ga/(In+Ga)原子數比計低於0.20，故而如下所述，由上述比較例之氧化物燒結體獲得之氧化物半導體薄膜尤其是載體濃度超過本發明之上限。又，比較例2、3、6、9、12、15之氧化物燒結體由於上述正二 價元素M之含量以M/(In+Ga+M)原子數比計超過0.05，故而包含由上述正二價元素M與Ga構成之複合氧化物之NiGa2O4相、CoGa2O4相、CaGa4O7相、SrGa2O4相、Ga2PbO4相作為方鐵錳礦型結構In2O3相以外之生成相，未獲得本發明之目標之氧化物燒結體。
又，於實施例2、10、14及比較例3、6之結核產生評價中，於本發明之氧化物燒結體之實施例2、10、14之靶中，未確認到結核之產生。另一方面，於比較例3、6之靶中，確認到大量結核產生。對於比較例3、6，認為原因在於燒結體密度較低、以及包含電阻較高且於濺鍍中容易凹陷之由上述正二價元素M與Ga構成之複合氧化物之NiGa2O4相、或由上述正二價元素M與Ga構成之複合氧化物之CoGa2O4相。因此，於濺鍍放電中經常產生電弧。
又，於表6~表10中，顯示如下之氧化物半導體薄膜之特性，該氧化物半導體薄膜係以氧化物之形式含有銦、鎵及上述正二價元素M的非晶質之氧化物半導體薄膜，並且鎵含量以Ga/(In+Ga)原子數比計被控制為0.20以上且0.45以下，且上述正二價元素M含量以M/(In+Ga+M)原子數比計被控制為0.0001以上且0.05以下。
可知實施例之氧化物半導體薄膜之載體濃度未達3.0×1018cm-3，且載體遷移率為10cm2V-1sec-1以上。
其中，鎵含量以Ga/(In+Ga)原子數比計為0.20以上且0.30以下，且上述正二價元素M含量以M/(In+Ga+M)原子數比計為0.0001以上且0.03以下之實施例1~4、6、7、13~15、18、19、22、23、26、27之氧化物半導體薄膜顯示出載體遷移率為15cm2V-1sec-1以上之優異特 性。
相對於此，於比較例4、7、10、13、16之氧化物半導體薄膜中，鎵含量以Ga/(In+Ga)原子數比計超過0.45，於燒結體中大量產生Ga2O3相，而未能成膜。

Claims (9)

  1. 一種氧化物燒結體，其以氧化物之形式含有銦、鎵及正二價元素M，上述鎵之含量以Ga/(In+Ga)原子數比計為0.20以上且0.45以下，上述正二價元素M之總含量以M/(In+Ga+M)原子數比計為0.0001以上且0.05以下，上述正二價元素M係選自由鎳、鈷、鈣、鍶及鉛組成之群中之一種以上，由方鐵錳礦型(bixbyitc)結構之In2O3相與In2O3相以外之生成相之β-Ga2O3型結構之GaInO3相、或β-Ga2O3型結構之GaInO3相與(Ga,In)2O3相構成，實質上不含由上述正二價元素M與鎵構成之複合氧化物之NiGa2O4相、CoGa2O4相、CaGa4O7相、Ca5Ga6O14相、SrGa12O19相、SrGa2O4相、Sr3Ga2O6相、Ga2PbO4相、或該等之複合氧化物相。
  2. 如申請專利範圍第1項之氧化物燒結體，其中，上述正二價元素M之總含量以M/(In+Ga+M)原子數比計為0.0001以上且0.03以下。
  3. 如申請專利範圍第1或2項之氧化物燒結體，其中，上述鎵之含量以Ga/(In+Ga)原子數比計為0.20以上且0.30以下。
  4. 如申請專利範圍第1或2項之氧化物燒結體，其實質上不含上述正二價元素M以外之正二價元素、及銦與鎵以外之正三價至正六價元素。
  5. 如申請專利範圍第1或2項之氧化物燒結體，其中，下述式1所定義之β-Ga2O3型結構之GaInO3相的X射線繞射波峰強度比為29%以上 且75%以下之範圍，100×I[GaInO3相(111)]/{I[In2O3相(400)]+I[GaInO3相(111)]}[%]式1。
  6. 一種濺鍍用靶，其係對申請專利範圍第1或2項之氧化物燒結體進行加工而獲得。
  7. 一種氧化物半導體薄膜，其係使用申請專利範圍第6項之濺鍍用靶藉由濺鍍法形成於基板上之後，進行熱處理而成之非晶質之氧化物半導體薄膜。
  8. 如申請專利範圍第7項之氧化物半導體薄膜，其載體遷移率為10cm2V-1sec-1以上。
  9. 如申請專利範圍第7或8項之氧化物半導體薄膜，其載體濃度未達3.0×1018cm-3。
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