TWI607676B - Package substrate and its electronic package and the manufacture thereof - Google Patents

Package substrate and its electronic package and the manufacture thereof Download PDF

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Publication number
TWI607676B
TWI607676B TW105118131A TW105118131A TWI607676B TW I607676 B TWI607676 B TW I607676B TW 105118131 A TW105118131 A TW 105118131A TW 105118131 A TW105118131 A TW 105118131A TW I607676 B TWI607676 B TW I607676B
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Taiwan
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layer
insulating protective
protective layer
package
package substrate
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TW105118131A
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Chinese (zh)
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TW201743665A (en
Inventor
邱士超
陳嘉成
林俊賢
范植文
米軒皞
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矽品精密工業股份有限公司
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Priority to TW105118131A priority Critical patent/TWI607676B/en
Priority to CN201610504135.0A priority patent/CN107481991B/en
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Publication of TWI607676B publication Critical patent/TWI607676B/en
Publication of TW201743665A publication Critical patent/TW201743665A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Geometry (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Wire Bonding (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Description

封裝基板及其電子封裝件與製法 Package substrate and electronic package thereof and manufacturing method

本發明係有關一種封裝基板，尤指一種無核心層之封裝基板及其電子封裝件與製法。 The invention relates to a package substrate, in particular to a package substrate without a core layer and an electronic package thereof and a manufacturing method thereof.

隨著電子產業的蓬勃發展，許多高階電子產品都逐漸往輕、薄、短、小等高集積度方向發展，且隨著封裝技術之演進，晶片的封裝技術也越來越多樣化，半導體封裝件之尺寸或體積亦隨之不斷縮小，藉以使該半導體封裝件達到輕薄短小之目的 With the rapid development of the electronics industry, many high-end electronic products are gradually developing in the direction of light, thin, short, and small high integration. With the evolution of packaging technology, the packaging technology of wafers is becoming more and more diversified. The size or volume of the piece is also shrinking, so that the semiconductor package can be light, thin and short.

第1圖係為習知覆晶式半導體封裝件1之剖視示意圖。如第1圖所示，該半導體封裝件1係包括一封裝基板1a以及一半導體元件9。 1 is a schematic cross-sectional view of a conventional flip-chip semiconductor package 1. As shown in FIG. 1, the semiconductor package 1 includes a package substrate 1a and a semiconductor element 9.

所述之封裝基板1a係包含：核心層10；形成於核心層10表面的第一線路層12a與第二線路層12b；導電孔13，係貫穿該核心層10，以電性連接該第一線路層12a與第二線路層12b；第一絕緣層11a與第二絕緣層11b，係分別形成於該第一線路層12a與第二線路層12b上，並外露出部分該第一線路層12a與第二線路層12b。 The package substrate 1a includes a core layer 10, a first circuit layer 12a and a second circuit layer 12b formed on the surface of the core layer 10, and a conductive hole 13 extending through the core layer 10 to electrically connect the first layer. The circuit layer 12a and the second circuit layer 12b; the first insulating layer 11a and the second insulating layer 11b are formed on the first circuit layer 12a and the second circuit layer 12b, respectively, and partially expose the first circuit layer 12a. And the second circuit layer 12b.

所述之半導體元件9係具有複數電極墊90，以結合複數導電凸塊91，俾供覆晶結合至該第一線路層12a。 The semiconductor component 9 has a plurality of electrode pads 90 for bonding the plurality of conductive bumps 91 to be bonded to the first wiring layer 12a.

習知封裝基板1a中，係具有至少二層的線路層(第一線路層12a與第二線路層12b)，並藉該導電孔13電性連接該第一線路層12a與第二線路層12b。 In the conventional package substrate 1a, there are at least two circuit layers (a first circuit layer 12a and a second circuit layer 12b), and the first circuit layer 12a and the second circuit layer 12b are electrically connected by the conductive holes 13. .

然而，該導電孔13需透過機械鑽孔或雷射鑽孔於該核心層10中形成貫穿該核心層10的通孔100後，再於該貫穿之通孔100中電鍍銅，因而增加製程的複雜度。 However, the conductive hole 13 needs to be mechanically drilled or laser drilled to form a through hole 100 penetrating the core layer 10 in the core layer 10, and then copper is plated in the through hole 100, thereby increasing the process. the complexity.

再者，習知封裝基板1a因具有核心層10及至少二層的線路層，而難以降低該封裝基板1a之厚度，故在該封裝基板1a之厚度難以降低的情況下，整體半導體封裝件1之厚度亦難以有效的降低。 Furthermore, the conventional package substrate 1a has a core layer 10 and at least two wiring layers, and it is difficult to reduce the thickness of the package substrate 1a. Therefore, in the case where the thickness of the package substrate 1a is difficult to be reduced, the entire semiconductor package 1 is The thickness is also difficult to effectively reduce.

因此，如何克服上述習知技術的種種問題，實已成目前亟欲解決的課題。 Therefore, how to overcome the various problems of the above-mentioned prior art has become a problem that is currently being solved.

鑑於上述習知技術之種種缺失，本發明係提供一種封裝基板，係包括：一絕緣保護層，係具有相對之第一表面與第二表面；一線路層，係嵌埋於該絕緣保護層之第一表面中且外露於該第一表面而未外露於該第二表面；以及導電柱，係貫穿地形成於該絕緣保護層中且外露於該第一表面與第二表面並電性連接該線路層。 The present invention provides a package substrate comprising: an insulating protective layer having opposite first and second surfaces; And the first surface is exposed on the first surface without being exposed to the second surface; and the conductive pillar is formed in the insulating protective layer and exposed to the first surface and the second surface and electrically connected to the first surface Line layer.

本發明復提供一種封裝基板之製法，係包括：提供一具有相對之第一表面與第二表面的絕緣保護層，其中，該絕緣保護層形成有複數開孔與至少一通孔，該開孔係形成 於該第一表面上而未連通該第二表面，且該通孔係連通該第一表面與第二表面；以及形成線路層於該開孔中，且形成導電柱於該通孔中，並使該導電柱電性連接該線路層。 The invention provides a method for manufacturing a package substrate, comprising: providing an insulating protective layer having a first surface and a second surface opposite to each other, wherein the insulating protective layer is formed with a plurality of openings and at least one through hole, the opening system form And the second surface is not connected to the first surface, and the through hole is connected to the first surface and the second surface; and a wiring layer is formed in the opening, and a conductive pillar is formed in the through hole, and The conductive post is electrically connected to the circuit layer.

前述之製法中，復包括先將該絕緣保護層以其第二表面結合至一承載件上，再形成該開孔與該通孔。又包括於形成該線路層與該導電柱後，移除該承載件。 In the above method, the insulating layer is first bonded to a carrier by the second surface thereof, and the opening and the through hole are formed. The method further includes removing the carrier after forming the circuit layer and the conductive pillar.

前述之封裝基板及其製法中，該絕緣保護層係為防銲層。 In the above package substrate and method of manufacturing the same, the insulating protective layer is a solder resist layer.

前述之封裝基板及其製法中，該線路層之表面係齊平該絕緣保護層之第一表面。 In the above package substrate and method of manufacturing the same, the surface of the wiring layer is flush with the first surface of the insulating protective layer.

前述之封裝基板及其製法中，該導電柱係具有相對之第一端面及第二端面，使該第一端面外露於該第一表面，且該第二端面外露於該第二表面。例如，該第一端面係齊平該第一表面及/或該第二端面係齊平該第二表面。 In the above package substrate and method of manufacturing the same, the conductive pillar has opposite first and second end faces, such that the first end surface is exposed on the first surface, and the second end surface is exposed on the second surface. For example, the first end surface is flush with the first surface and/or the second end surface is flush with the second surface.

本發明亦提供一種電子封裝件，係包括：前述之封裝基板；以及電子元件，係設於該絕緣保護層之第一表面上並電性連接該導電柱。 The present invention also provides an electronic package comprising: the package substrate; and an electronic component disposed on the first surface of the insulating protective layer and electrically connected to the conductive pillar.

本發明另提供一種電子封裝件之製法，係包括：提供一前述之封裝基板；以及設置電子元件於該絕緣保護層之第一表面上，並使該電子元件電性連接該導電柱。 The invention further provides a method for manufacturing an electronic package, comprising: providing a package substrate as described above; and disposing an electronic component on the first surface of the insulating protection layer and electrically connecting the electronic component to the conductive pillar.

前述之電子封裝件及其製法中，該導電柱之第一端面係電性連接該電子元件。 In the above electronic package and method of manufacturing the same, the first end surface of the conductive post is electrically connected to the electronic component.

前述之電子封裝件及其製法中，復包括形成封裝層於該絕緣保護層之第一表面上以包覆該電子元件。 In the foregoing electronic package and method of manufacturing the same, the method further comprises forming an encapsulation layer on the first surface of the insulating protection layer to encapsulate the electronic component.

另外，前述之電子封裝件及其製法中，復包括設置複數導電元件於該絕緣保護層之第二表面上，並使該導電元件電性連接該導電柱。 In addition, in the foregoing electronic package and the manufacturing method thereof, the plurality of conductive elements are disposed on the second surface of the insulating protective layer, and the conductive element is electrically connected to the conductive pillar.

由上可知，本發明之封裝基板及其電子封裝件與製法，係免除使用核心層，故無需製作習知貫穿核心層之導電孔，因而相較於習知技術，達到簡易製程步驟及降低成本之目的。 It can be seen from the above that the package substrate and the electronic package and the manufacturing method thereof of the present invention eliminate the use of the core layer, so that it is not necessary to fabricate the conductive holes through the core layer, thereby achieving a simple process step and reducing the cost compared with the prior art. The purpose.

再者，本發明因未具有習知核心層，而能大幅降低該封裝基板之厚度，故在該封裝基板之厚度得以降低的情況下，該電子封裝件之整體厚度亦能有效的降低。 Furthermore, the present invention can greatly reduce the thickness of the package substrate because the conventional core layer is not provided. Therefore, when the thickness of the package substrate is reduced, the overall thickness of the electronic package can be effectively reduced.

1‧‧‧半導體封裝件 1‧‧‧Semiconductor package

1a,2‧‧‧封裝基板 1a, 2‧‧‧ package substrate

10‧‧‧核心層 10‧‧‧ core layer

100,211‧‧‧通孔 100,211‧‧‧through hole

11a‧‧‧第一絕緣層 11a‧‧‧First insulation

11b‧‧‧第二絕緣層 11b‧‧‧Second insulation

12a‧‧‧第一線路層 12a‧‧‧First circuit layer

12b‧‧‧第二線路層 12b‧‧‧Second circuit layer

13‧‧‧導電孔 13‧‧‧Electrical hole

20‧‧‧承載件 20‧‧‧Carrier

200‧‧‧結合層 200‧‧‧ bonding layer

21‧‧‧絕緣保護層 21‧‧‧Insulation protective layer

21a‧‧‧第一表面 21a‧‧‧ first surface

21b‧‧‧第二表面 21b‧‧‧ second surface

210‧‧‧開孔 210‧‧‧Opening

211’‧‧‧凹孔 211'‧‧‧ recessed hole

22‧‧‧線路層 22‧‧‧Line layer

22a‧‧‧表面 22a‧‧‧ surface

23‧‧‧導電柱 23‧‧‧conductive column

23a‧‧‧第一端面 23a‧‧‧ first end face

23b‧‧‧第二端面 23b‧‧‧second end face

3,3’‧‧‧電子封裝件 3,3’‧‧‧Electronic package

30‧‧‧電子元件 30‧‧‧Electronic components

30a‧‧‧作用面 30a‧‧‧Action surface

30b‧‧‧非作用面 30b‧‧‧Non-active surface

300,90‧‧‧電極墊 300,90‧‧‧electrode pads

31,91‧‧‧導電凸塊 31,91‧‧‧Electrical bumps

31’‧‧‧銲線 31’‧‧‧welding line

32‧‧‧導電元件 32‧‧‧Conductive components

33‧‧‧封裝層 33‧‧‧Encapsulation layer

9‧‧‧半導體元件 9‧‧‧Semiconductor components

第1圖係為習知覆晶式半導體封裝件的剖視示意圖；第2A至2E圖係為本發明之封裝基板之製法之剖視示意圖；以及第3A及3B圖係為本發明之電子封裝件之製法的剖視示意圖；其中，第3A’及3B’圖係為第3A及3B圖之另一實施例。 1 is a schematic cross-sectional view of a conventional flip-chip semiconductor package; FIGS. 2A to 2E are cross-sectional views showing a method of fabricating the package substrate of the present invention; and FIGS. 3A and 3B are electronic packages of the present invention. A schematic cross-sectional view of a method of manufacturing a part; wherein, Figures 3A' and 3B' are another embodiment of Figures 3A and 3B.

以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。 The other embodiments of the present invention will be readily understood by those skilled in the art from this disclosure.

須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定 條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如“上”、“下”、“第一”、“第二”、及“一”等之用語，亦僅為便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。 It is to be understood that the structure, the proportions, the size, and the like of the present invention are intended to be used in conjunction with the disclosure of the specification, and are not intended to limit the invention. Limited The conditions are not technically meaningful, and any modification of the structure, change of the proportional relationship or adjustment of the size should remain in the present invention without affecting the effects and the achievable objectives of the present invention. The technical content revealed can be covered. In the meantime, the terms "upper", "lower", "first", "second", "one", and the like, are used for convenience of description, and are not intended to limit the present invention. The scope of the invention, the change or adjustment of the relative relationship, is also considered to be within the scope of the invention.

第2A至2E圖係為本發明之封裝基板2之製法之剖視示意圖。 2A to 2E are schematic cross-sectional views showing a method of manufacturing the package substrate 2 of the present invention.

如第2A至2B圖所示，提供一承載件20，且該承載件20之上、下兩側均設有一絕緣保護層21，且該絕緣保護層21具有相對之第一表面21a與第二表面21b，並以其第二表面21b結合至該承載件20上。接著，於該絕緣保護層21之第一表面21a上形成複數開孔210與複數通孔211。 As shown in FIG. 2A to FIG. 2B, a carrier 20 is provided, and an insulating protective layer 21 is disposed on the upper and lower sides of the carrier 20, and the insulating protective layer 21 has a first surface 21a and a second opposite surface. The surface 21b is bonded to the carrier 20 with its second surface 21b. Next, a plurality of openings 210 and a plurality of through holes 211 are formed on the first surface 21a of the insulating protective layer 21.

於本實施例中，該承載件20以結合層200(如離型膜、金屬層或黏著層)結合該絕緣保護層21。 In the present embodiment, the carrier 20 is bonded to the insulating protective layer 21 by a bonding layer 200 such as a release film, a metal layer or an adhesive layer.

再者，該絕緣保護層21係為防銲層，且該些開孔210未連通該第二表面21b，而該些通孔211係連通該第一表面21a與第二表面21b。 Moreover, the insulating protective layer 21 is a solder resist layer, and the openings 210 are not connected to the second surface 21b, and the through holes 211 are connected to the first surface 21a and the second surface 21b.

又，該通孔211之製程係如第2A圖所示，於形成該些開孔210時一併形成複數凹孔211'，再如第2B圖所示，針對該凹孔211'處形成該通孔211。 Moreover, the process of the through hole 211 is as shown in FIG. 2A, and a plurality of recessed holes 211' are formed together when the openings 210 are formed, and as shown in FIG. 2B, the recessed holes 211' are formed. Through hole 211.

如第2C圖所示，形成一線路層22於該些開孔210中， 且形成複數導電柱23於該些通孔211中，並使該些導電柱23電性連接該線路層22。 As shown in FIG. 2C, a circuit layer 22 is formed in the openings 210, A plurality of conductive pillars 23 are formed in the through holes 211, and the conductive pillars 23 are electrically connected to the circuit layer 22.

於本實施例中，該線路層22係嵌埋於該絕緣保護層21之第一表面21a中，且該線路層22之表面22a齊平該絕緣保護層21之第一表面21a。 In this embodiment, the circuit layer 22 is embedded in the first surface 21a of the insulating protective layer 21, and the surface 22a of the wiring layer 22 is flush with the first surface 21a of the insulating protective layer 21.

再者，該導電柱23係具有對應該第一表面21a之第一端面23a及對應該第二表面21b之第二端面23b，使該第一端面23a外露於該第一表面21a，且該第二端面23b外露於該第二表面21b。例如，該第一表面21a齊平該第一端面23a，且該第二表面21b齊平該第二端面23b。 Furthermore, the conductive post 23 has a first end surface 23a corresponding to the first surface 21a and a second end surface 23b corresponding to the second surface 21b, such that the first end surface 23a is exposed on the first surface 21a, and the first surface The two end faces 23b are exposed on the second surface 21b. For example, the first surface 21a is flush with the first end surface 23a, and the second surface 21b is flush with the second end surface 23b.

如第2D至2E圖所示，移除該承載件20，以獲取複數封裝基板2。 As shown in FIGS. 2D to 2E, the carrier 20 is removed to obtain a plurality of package substrates 2.

於本實施例中，藉由結合層200分離該承載件20與各該封裝基板2。 In the embodiment, the carrier 20 and each of the package substrates 2 are separated by the bonding layer 200.

本發明之封裝基板之製法主要藉由該絕緣保護層21作為主體，避免使用核心層，因此，無需製作習知貫穿核心層之導電孔，故能簡化製程步驟及成本。 The method for manufacturing the package substrate of the present invention mainly utilizes the insulating protective layer 21 as a main body, thereby avoiding the use of the core layer. Therefore, it is not necessary to fabricate the conductive holes penetrating through the core layer, so that the process steps and costs can be simplified.

再者，本發明僅具有一層線路層，且未使用習知核心層，因而能大幅降低該封裝基板2之厚度。 Furthermore, the present invention has only one wiring layer and does not use a conventional core layer, so that the thickness of the package substrate 2 can be greatly reduced.

如第3A及3B圖所示，於該封裝基板2之後續應用中，設置至少一電子元件30於該絕緣保護層21之第一表面21a上，且形成一如封裝膠體(molding compound)之封裝層33於該絕緣保護層21之第一表面21a上以包覆該電子元件30，並形成複數如銲錫球之導電元件32於該絕緣保護層 21之第二表面21b上，以形成本發明之電子封裝件3。 As shown in FIGS. 3A and 3B, in the subsequent application of the package substrate 2, at least one electronic component 30 is disposed on the first surface 21a of the insulating protective layer 21, and a package such as a molding compound is formed. The layer 33 is on the first surface 21a of the insulating protective layer 21 to cover the electronic component 30, and forms a plurality of conductive elements 32 such as solder balls on the insulating protective layer. The second surface 21b of 21 is formed to form the electronic package 3 of the present invention.

於本實施例中，該些導電元件32係對應結合至各該導電柱23之第二端面23b上，以令該導電元件32電性連接該導電柱23。 In this embodiment, the conductive elements 32 are correspondingly coupled to the second end faces 23b of the conductive pillars 23 to electrically connect the conductive components 32 to the conductive pillars 23.

再者，該電子元件30係為主動元件、被動元件或其二者組合，其中，該主動元件係例如半導體晶片，而該被動元件係例如電阻、電容及電感。例如，該電子元件30係具有相對之作用面30a與非作用面30b，且該作用面30a具有複數電極墊300，且該電子元件30以其電極墊300電性連接該些導電柱23。 Moreover, the electronic component 30 is an active component, a passive component, or a combination thereof, wherein the active component is, for example, a semiconductor wafer, and the passive component is, for example, a resistor, a capacitor, and an inductor. For example, the electronic component 30 has an opposite active surface 30a and a non-active surface 30b, and the active surface 30a has a plurality of electrode pads 300, and the electronic component 30 is electrically connected to the conductive pillars 23 by its electrode pads 300.

具體地，如第3A圖所示，該電子元件30之電極墊300藉由複數導電凸塊31覆晶結合至該導電柱23之第一端面23a上，以令該電子元件30電性連接該些導電柱23。或者，如第3A’及3B’圖所示之電子封裝件3’，該電子元件30以非作用面30b設於該絕緣保護層21之第一表面21a上，並以複數銲線31’電性連接該些電極墊300與該導電柱23之第一端面23a，以令該電子元件30電性連接該些導電柱23。 Specifically, as shown in FIG. 3A, the electrode pad 300 of the electronic component 30 is flip-chip bonded to the first end surface 23a of the conductive pillar 23 by a plurality of conductive bumps 31 to electrically connect the electronic component 30. Some conductive pillars 23. Alternatively, as shown in FIGS. 3A' and 3B', the electronic component 30 is disposed on the first surface 21a of the insulating protective layer 21 with an inactive surface 30b, and is electrically connected by a plurality of bonding wires 31'. The electrode pads 300 and the first end faces 23a of the conductive posts 23 are connected to electrically connect the electronic components 30 to the conductive pillars 23.

本發明之電子封裝件3,3’在該封裝基板2之厚度得以降低的情況下，其整體厚度亦能有效的降低。 In the case where the thickness of the package substrate 2 is reduced, the electronic package 3, 3' of the present invention can be effectively reduced in overall thickness.

本發明提供一種封裝基板2，係包括：一絕緣保護層21、一線路層22以及複數導電柱23。 The present invention provides a package substrate 2 comprising: an insulating protective layer 21, a wiring layer 22, and a plurality of conductive pillars 23.

所述之絕緣保護層21係具有相對之第一表面21a與第二表面21b，且該絕緣保護層21係為防銲層。 The insulating protective layer 21 has a first surface 21a and a second surface 21b opposite to each other, and the insulating protective layer 21 is a solder resist layer.

所述之線路層22係嵌埋於該絕緣保護層21之第一表面21a中而外露於該第一表面21a且未外露於該第二表面21b。 The circuit layer 22 is embedded in the first surface 21a of the insulating protective layer 21 and exposed on the first surface 21a and not exposed on the second surface 21b.

所述之導電柱23係貫穿地形成於該絕緣保護層21中且外露於該第一表面21a與第二表面21b並電性連接該線路層22。 The conductive pillars 23 are formed in the insulating protective layer 21 and exposed to the first surface 21a and the second surface 21b and electrically connected to the wiring layer 22.

於一實施例中，該線路層22之表面22a係齊平該絕緣保護層21之第一表面21a。 In one embodiment, the surface 22a of the wiring layer 22 is flush with the first surface 21a of the insulating protective layer 21.

於一實施例中，該導電柱23係具有相對之第一端面23a及第二端面23b，使該第一端面23a外露於該第一表面21a，且該第二端面23b外露於該第二表面21b。例如，該第一表面21a係齊平該第一端面23a，且該第二表面21b係齊平該第二端面23b。 In one embodiment, the conductive post 23 has an opposite first end surface 23a and a second end surface 23b, such that the first end surface 23a is exposed on the first surface 21a, and the second end surface 23b is exposed on the second surface. 21b. For example, the first surface 21a is flush with the first end surface 23a, and the second surface 21b is flush with the second end surface 23b.

本發明復提供一種電子封裝件3,3’，係包括：上述之封裝基板2以及電子元件30。 The present invention further provides an electronic package 3, 3' comprising the above-described package substrate 2 and electronic component 30.

所述之電子元件30係設於該絕緣保護層21之第一表面21a上並電性連接該導電柱23。 The electronic component 30 is disposed on the first surface 21a of the insulating protective layer 21 and electrically connected to the conductive pillar 23.

於一實施例中，該導電柱23之第一端面23a係電性連接該電子元件30。 In one embodiment, the first end face 23a of the conductive post 23 is electrically connected to the electronic component 30.

於一實施例中，該電子封裝件3,3’復包括複數導電元件32，係設於該絕緣保護層21之第二表面21b上並電性連接該導電柱23。 In one embodiment, the electronic package 3, 3' includes a plurality of conductive elements 32 disposed on the second surface 21b of the insulating protective layer 21 and electrically connected to the conductive pillars 23.

綜上所述，本發明之封裝基板及其電子封裝件與製法，係藉由該絕緣保護層作為主體，避免使用核心層，因 而無需製作習知貫穿核心層之導電孔，俾能簡易製程步驟及降低成本。 In summary, the package substrate and the electronic package and the manufacturing method thereof of the present invention are mainly used by the insulating protective layer to avoid the use of the core layer. There is no need to make conductive holes through the core layer, so that the process steps can be simplified and the cost can be reduced.

再者，本發明因未具有習知核心層，而能大幅降低該封裝基板之厚度，故在該封裝基板之厚度得以降低的情況下，整體電子封裝件之厚度亦能有效的降低。 Furthermore, the present invention can greatly reduce the thickness of the package substrate because it does not have a conventional core layer. Therefore, when the thickness of the package substrate is reduced, the thickness of the entire electronic package can be effectively reduced.

上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。 The above embodiments are intended to illustrate the principles of the invention and its effects, and are not intended to limit the invention. Any of the above-described embodiments may be modified by those skilled in the art without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be as set forth in the appended claims.

2‧‧‧封裝基板 2‧‧‧Package substrate

21‧‧‧絕緣保護層 21‧‧‧Insulation protective layer

21a‧‧‧第一表面 21a‧‧‧ first surface

21b‧‧‧第二表面 21b‧‧‧ second surface

22‧‧‧線路層 22‧‧‧Line layer

22a‧‧‧表面 22a‧‧‧ surface

23‧‧‧導電柱 23‧‧‧conductive column

23a‧‧‧第一端面 23a‧‧‧ first end face

23b‧‧‧第二端面 23b‧‧‧second end face

Claims (20)

一種封裝基板，係包括：絕緣保護層，係具有相對之第一表面與第二表面；線路層，係嵌埋於該絕緣保護層之第一表面中且外露於該第一表面而未外露於該第二表面；以及導電柱，具有相對之第一端面及第二端面，係貫穿地形成於該絕緣保護層中且該第一端面係齊平該第一表面及/或該第二端面係齊平該第二表面並電性連接該線路層。 A package substrate comprising: an insulating protective layer having opposite first and second surfaces; and a circuit layer embedded in the first surface of the insulating protective layer and exposed on the first surface without being exposed The second surface; and the conductive post having a first end surface and a second end surface are formed in the insulating protective layer and the first end surface is flush with the first surface and/or the second end surface The second surface is flushed and electrically connected to the wiring layer. 如申請專利範圍第1項所述之封裝基板，其中，該絕緣保護層係為防銲層。 The package substrate according to claim 1, wherein the insulating protective layer is a solder resist layer. 如申請專利範圍第1項所述之封裝基板，其中，該線路層之表面係齊平該絕緣保護層之第一表面。 The package substrate of claim 1, wherein the surface of the circuit layer is flush with the first surface of the insulating protective layer. 一種封裝基板之製法，係包括：提供一具有相對之第一表面與第二表面的絕緣保護層，其中，該絕緣保護層形成有複數開孔與至少一通孔，該開孔係形成於該第一表面上而未連通該第二表面，且該通孔係連通該第一表面與第二表面；以及形成線路層於該開孔中，且形成導電柱於該通孔中，該導電柱係具有相對之第一端面及第二端面，該第一端面係齊平該第一表面及/或該第二端面係齊平該第二表面，並使該導電柱電性連接該線路層。 A method for manufacturing a package substrate, comprising: providing an insulating protective layer having a first surface and a second surface opposite to each other, wherein the insulating protective layer is formed with a plurality of openings and at least one through hole, wherein the opening is formed in the first a surface that is not connected to the second surface, and the through hole communicates with the first surface and the second surface; and a wiring layer is formed in the opening, and a conductive pillar is formed in the through hole, the conductive pillar The first end surface and the second end surface are flush with the first surface and/or the second end surface is flush with the second surface, and the conductive post is electrically connected to the circuit layer. 如申請專利範圍第4項所述之封裝基板之製法，其中，該絕緣保護層係為防銲層。 The method of manufacturing a package substrate according to claim 4, wherein the insulating protective layer is a solder resist layer. 如申請專利範圍第4項所述之封裝基板之製法，其中，該線路層之表面係齊平該絕緣保護層之第一表面。 The method of manufacturing a package substrate according to claim 4, wherein the surface of the circuit layer is flush with the first surface of the insulating protective layer. 如申請專利範圍第4項所述之封裝基板之製法，復包括先將該絕緣保護層以其第二表面結合至一承載件上，再形成該開孔與該通孔。 The method for manufacturing a package substrate according to claim 4, wherein the insulating protective layer is first bonded to a carrier by a second surface thereof, and the opening and the through hole are formed. 如申請專利範圍第7項所述之封裝基板之製法，復包括於形成該線路層與該導電柱後，移除該承載件。 The method for manufacturing a package substrate according to claim 7 is further included after the circuit layer and the conductive post are formed, and the carrier is removed. 一種電子封裝件，係包括：如申請專利範圍第1項所述之封裝基板；以及電子元件，係設於該絕緣保護層之第一表面上並電性連接該導電柱。 An electronic package comprising: the package substrate according to claim 1; and an electronic component disposed on the first surface of the insulating protective layer and electrically connected to the conductive pillar. 如申請專利範圍第9項所述之電子封裝件，其中，該絕緣保護層係為防銲層。 The electronic package of claim 9, wherein the insulating protective layer is a solder resist layer. 如申請專利範圍第9項所述之電子封裝件，其中，該線路層之表面係齊平該絕緣保護層之第一表面。 The electronic package of claim 9, wherein the surface of the circuit layer is flush with the first surface of the insulating protective layer. 如申請專利範圍第9項所述之電子封裝件，其中，該導電柱之第一端面係電性連接該電子元件。 The electronic package of claim 9, wherein the first end surface of the conductive post is electrically connected to the electronic component. 如申請專利範圍第9項所述之電子封裝件，復包括複數導電元件，係設於該絕緣保護層之第二表面上並電性連接該導電柱。 The electronic package of claim 9, comprising a plurality of conductive elements disposed on the second surface of the insulating protective layer and electrically connected to the conductive pillar. 如申請專利範圍第9項所述之電子封裝件，復包括封裝層，係形成於該絕緣保護層之第一表面上以包覆該電子元件。 The electronic package of claim 9, further comprising an encapsulation layer formed on the first surface of the insulating protection layer to encapsulate the electronic component. 一種電子封裝件之製法，係包括： 提供一如申請專利範圍第1項所述之封裝基板；以及設置電子元件於該絕緣保護層之第一表面上，並使該電子元件電性連接該導電柱。 A method of manufacturing an electronic package includes: Providing the package substrate as described in claim 1; and disposing the electronic component on the first surface of the insulating protective layer and electrically connecting the electronic component to the conductive pillar. 如申請專利範圍第15項所述之電子封裝件之製法，其中，該絕緣保護層係為防銲層。 The method of manufacturing an electronic package according to claim 15, wherein the insulating protective layer is a solder resist layer. 如申請專利範圍第15項所述之電子封裝件之製法，其中，該線路層之表面係齊平該絕緣保護層之第一表面。 The method of manufacturing an electronic package according to claim 15, wherein the surface of the circuit layer is flush with the first surface of the insulating protective layer. 如申請專利範圍第15項所述之電子封裝件之製法，其中，該導電柱之第一端面係電性連接該電子元件。 The method of manufacturing the electronic package of claim 15, wherein the first end surface of the conductive post is electrically connected to the electronic component. 如申請專利範圍第15項所述之電子封裝件之製法，復包括接置複數導電元件於該絕緣保護層之第二表面上，並使該導電元件電性連接該導電柱。 The method of manufacturing an electronic package according to claim 15 further comprising: connecting a plurality of conductive elements on the second surface of the insulating protective layer, and electrically connecting the conductive elements to the conductive pillars. 如申請專利範圍第15項所述之電子封裝件之製法，復包括形成封裝層於該絕緣保護層之第一表面上以包覆該電子元件。 The method of manufacturing an electronic package according to claim 15 further comprising forming an encapsulation layer on the first surface of the insulating protective layer to encapsulate the electronic component.
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