TWI541916B - 形成覆晶互連結構的半導體裝置和方法 - Google Patents

形成覆晶互連結構的半導體裝置和方法 Download PDF

Info

Publication number
TWI541916B
TWI541916B TW100102096A TW100102096A TWI541916B TW I541916 B TWI541916 B TW I541916B TW 100102096 A TW100102096 A TW 100102096A TW 100102096 A TW100102096 A TW 100102096A TW I541916 B TWI541916 B TW I541916B
Authority
TW
Taiwan
Prior art keywords
bump
substrate
interconnect
conductive
semiconductor die
Prior art date
Application number
TW100102096A
Other languages
English (en)
Other versions
TW201225193A (en
Inventor
拉簡德拉Ｄ 潘斯
Original Assignee
史達晶片有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 史達晶片有限公司 filed Critical 史達晶片有限公司
Publication of TW201225193A publication Critical patent/TW201225193A/zh
Application granted granted Critical
Publication of TWI541916B publication Critical patent/TWI541916B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/64—Manufacture or treatment of solid state devices other than semiconductor devices, or of parts thereof, not peculiar to a single device provided for in groups H01L31/00 - H10K99/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565—Moulds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/90—Methods for connecting semiconductor or solid state bodies using means for bonding not being attached to, or not being formed on, the body surface to be connected, e.g. pressure contacts using springs or clips
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05601—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/05611—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05624—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05639—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05644—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05647—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05655—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1133—Manufacturing methods by local deposition of the material of the bump connector in solid form
    • H01L2224/1134—Stud bumping, i.e. using a wire-bonding apparatus
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1301—Shape
    • H01L2224/13016—Shape in side view
    • H01L2224/13017—Shape in side view being non uniform along the bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1301—Shape
    • H01L2224/13016—Shape in side view
    • H01L2224/13018—Shape in side view comprising protrusions or indentations
    • H01L2224/13019—Shape in side view comprising protrusions or indentations at the bonding interface of the bump connector, i.e. on the surface of the bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13109—Indium [In] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13111—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/1601—Structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16235—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a via metallisation of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16237—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area disposed in a recess of the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16238—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area protruding from the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27—Manufacturing methods
    • H01L2224/27011—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature
    • H01L2224/27013—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature for holding or confining the layer connector, e.g. solder flow barrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/29109—Indium [In] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/29111—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8112—Aligning
    • H01L2224/81136—Aligning involving guiding structures, e.g. spacers or supporting members
    • H01L2224/81138—Aligning involving guiding structures, e.g. spacers or supporting members the guiding structures being at least partially left in the finished device
    • H01L2224/81141—Guiding structures both on and outside the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81193—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8134—Bonding interfaces of the bump connector
    • H01L2224/81345—Shape, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81385—Shape, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01032—Germanium [Ge]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01049—Indium [In]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0105—Tin [Sn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01061—Promethium [Pm]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01074—Tungsten [W]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0133—Ternary Alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/0665—Epoxy resin
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12041—LED
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12042—LASER
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1433—Application-specific integrated circuit [ASIC]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/325—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by abutting or pinching, i.e. without alloying process; mechanical auxiliary parts therefor

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Description

形成覆晶互連結構的半導體裝置和方法 國內優先權之申請
本申請案係為2004年5月20日提出申請之美國申請案第10/849,947號的部份接續申請案，其係並且依據35U.S.C.§120來申請對先前申請案的優先權
本發明一般係關於半導體裝置，而且更特別係關於一種形成覆晶互連結構的半導體裝置與方法。
在現代電子產品中，一般可發現半導體裝置。半導體裝置在電子元件的數目與密度上會有所變化。分散的半導體裝置一般包含一種電性元件，例如發光二極體(LED)、小訊號電晶體、電阻器、電容器、電感器與功率金屬氧化物半導體場效電晶體(MOSFET)。積體半導體裝置基本上包含數百至數百萬電性元件。積體半導體裝置的實例包括微型控制器、微型處理器、電荷耦合裝置(CCD)、太陽能電池以及數位微鏡裝置(DMD)。
半導體裝置進行廣範圍的功能，譬如訊號處理、高速計算、傳送與接收電磁訊號、控制電子裝置、將太陽光轉換為電以及產生電視顯示器用的視覺投射。在娛樂、通訊、功率轉換、網路、電腦與消費者產品之領域中，可發現半導體裝置。半導體裝置同樣可在軍事應用、航行、汽車、工業控制器與公司設備中被發現。
半導體裝置利用半導體材料的電特性。藉由施加電場或基部電流或經由摻雜製程，半導體材料的原子結構使得其導電率***縱。摻雜會將雜質引入半導體材料，以操縱並且控制半導體裝置的導電率。
半導體裝置包含主動與被動電性結構。主動結構，包括雙極性與場效電晶體，可控制電流的流動。藉由改變電場或基部電流之摻雜與施加的程度，電晶體可促進或限制電流的流動。被動結構，包括電阻器、電容器與電感器，其係會產生進行許多電功能所必要之電壓與電流之間的關係。被動與主動結構會被電性連接，以形成電路，以致使半導體裝置進行高速計算與其他有用功能。
半導體裝置一般使用兩複雜的製造製程來製造，亦即前端製造與後端製造，每一個均潛在地包含數百個步驟。前端製造包含在半導體晶圓表面上之複數個晶粒的形成。每一個晶粒基本上相同且包含由電性連接主動與被動元件所形成的電路。後端製造包含從拋光晶圓將各別晶粒切單，並且將該晶粒封裝，以提供結構性支撐與環境隔離。
半導體製造的一個目標係為產生更小的半導體裝置。更小裝置基本上消耗更少功率、具有更高性能並且可更有效率地生產。此外，更小半導體裝置具有更小足跡，其係對更小端產品而言是令人希望的。更小晶粒尺寸可藉由前端製程的改善來得到，以造成具有更小、更高密度主動與被動元件的晶粒。藉由電性互連與封裝材料的改善，後端製程可造成具有更小足跡的半導體裝置封裝。
在半導體晶粒與基板之間的覆晶互連，其係一般可在電子封裝組件中被發現。在最常見的形式中，在半導體晶粒上的互連凸塊可被粉末冶金地接合到形成在基板上的襯墊，其係通常藉由使用回流製程來熔化凸塊材料。當凸塊材料的回流提供強韌連接時，將起因於橋接風險之互連節距減少則是困難的，亦即在回流與固化製程期間內，將相鄰連接之間縮短。在替代性方法中，該附著係使用特定薄膜或糊狀物來製造，藉此在糊狀物或薄膜中的傳導性顆粒會連同樹脂的收縮力來影響電性連接。顆粒薄膜方法會使其本身在互連節距減少，但卻受害於起因於顆粒互連敏感度的有限長期可靠度，而隨著時間退化。
在精細節距應用中的半導體晶粒與基板之間形成可靠與強韌的互連接點的需求存在。於是，在一種實施例中，本發明係為一種製造半導體裝置的方法，其係包含以下步驟：提供一半導體晶粒，其係具有形成在半導體晶粒之主動表面上的複數個凸塊；提供一基板；以及形成複數個傳導軌跡，其係在基板上具有互連位置。該等凸塊比互連位置更寬。該方法進一步包括以下步驟：形成遮罩層於遠離互連位置的基板區域上；將該等凸塊接合到互連位置，以致於該等凸塊能夠覆蓋互連位置的頂表面與側表面上；以及將一封裝物沈積在半導體晶粒與基板之間的凸塊周圍。
在另一個實施例中，本發明係為生產半導體裝置的方法，其係包含以下步驟：提供半導體晶粒，其係具有形成在半導體晶粒表面上的複數個互連結構；提供一基板；將具有互連位置的複數個傳導軌跡形成在基板上；將互連結構接合到缺乏遮罩開口的互連位置，以致於互連結構能夠覆蓋互連位置的頂表面與側表面；以及將一封裝物沈積在半導體晶粒與基板之間的互連結構周圍。該互連結構會比該互連位置更寬。
在另一個實施例中，本發明係為一種製造半導體裝置的方法，其係包含以下步驟：提供半導體晶粒，其係具有形成在半導體晶粒表面上的複數個互連結構；提供一基板；將具有互連位置的複數個傳導軌跡形成在基板上；以及將互連結構接合到缺乏遮罩開口的互連位置，以致於互連結構能夠覆蓋互連位置的頂表面與側表面。該互連位置會比該互連結構更窄。
在另一個實施例中，本發明係為半導體裝置，其係包含一半導體晶粒，其係具有形成在半導體晶粒表面上的複數個互連結構。具有互連位置的複數個傳導軌跡係形成在基板上。該互連位置會比互連結構更窄。該互連結構係接合到該互連位置，以致於該互連結構能夠覆蓋互連位置的頂表面與側表面上。一種封裝物則被沈積在半導體晶粒與基板之間的互連結構周圍。
本發明係在關於該圖式之以下說明的一或更多實施例中說明，其中相同的數字代表相同或類似的元件。雖然本發明係根據最佳模式來說明，以得到本發明之目的，但是那些熟諳該技藝者將理解，其係意圖覆蓋被包括在本發明精神與範圍內的替代物、變更與等同物，其係由以下揭露與圖式所支撐的附加申請專利範圍與它們的等同物所定義。
半導體裝置一般使用兩複雜製造製程來製造：前端製造與後端製造。前端製造包含複數個晶粒形成在半導體晶圓表面上。在晶圓上的每一晶粒包含主動與被動電性元件，其係被電性連接以形成功能性電路。譬如電晶體與二極體的主動電性元件，具有控制電流流動的能力。被動電性元件，譬如電容器、電感器、電阻器與變壓器，其係在進行電路功能所必須的電壓與電流之間產生關係。
被動與主動元件會被形成在半導體晶圓的表面上，其係藉由一系列製程步驟，包括摻雜、沈積、光蝕刻、蝕刻與平面化。藉由譬如離子植入或熱擴散的技術，摻雜會將雜質引入到半導體材料內。該摻雜製程修改在主動裝置中半導體材料的導電率、將半導體材料轉換成絕緣體、導體、或者應電場或基部電流來動態改變半導體材料傳導率。電晶體包含改變型態的區域以及摻雜程度，其係如必要地被排列，以致使電晶體在施加電場或基部電流時提升或限制電流的流動。
主動與被動元件係藉由具有不同電性的材料層所形成。該些層可藉由被沈積之材料種類所部份決定的種種沈積技術來形成。例如，薄膜沈積包含化學蒸汽沈積(CVD)、物理蒸汽沈積(PVD)、電解電鍍以及無電電鍍製程。每層一般會被圖案化，以形成主動元件、被動元件部份，或元件之間的電性連接。
該等層可使用光微影來圖案化，其係包含將例如光阻的光敏材料沈積在欲被圖案化的層上。一圖案可使用光線從光罩被傳送到光阻。受到光線的光阻圖案部份可使用溶劑來移除，以將欲被圖案化的底層部份曝光。剩下的光阻則會被移除，以留下一圖案化層。或者，某些種類的材料可藉由使用譬如無電或電解電鍍的技術、將材料直接沈積入先前沈積/蝕刻製程所形成的區域或空隙內而被圖案化。
將薄膜材料沈積在現存圖案，其係會誇大底層圖案並且產生非均勻的平坦表面。均勻平坦表面會被要求產生更小與更密集封裝的主動與被動元件。平面化可被使用來將材料自晶圓表面移除，並且產生均勻的平坦表面。平面化包含將具有拋光襯墊的晶圓表面拋光。在拋光期間內，研磨材料與腐蝕化學品會被添加到晶圓表面。該化學品之研磨與腐蝕動作的結合機械動作，會將任何不規則的地勢移除，以造成均勻的平坦表面。
後端製造意指將該拋光晶圓切割或切單成各別晶粒，隨後並且將該晶粒包裝，以用於結構性支撐與環境隔離。為了將晶粒切單，該晶圓會沿著晶圓的非功能性區域被刻痕與斷裂，其係稱為鋸齒街或劃線。該晶圓可使用雷射切割工具或鋸齒刀片被切單。在切單以後，個別晶粒會被安裝到一封裝物基板，該封裝物基板係包括接腳或接觸襯墊，以與其他系統元件互連。形成在半導體晶粒上的接觸襯墊隨後可被連接到在該封裝物內的接觸襯墊。電性連接可以銲料凸塊、柱形凸塊、傳導黏膏或佈線接合而被製成。一封裝物或其它鑄模材料係被沈積在封裝物上，以提供物理支撐與電性隔離。該拋光封裝物隨後會被***於電性系統內，且該半導體裝置的功能可供其他系統元件使用。
圖1顯示具有晶片載體基板的電子裝置50或具有複數個半導體封裝物安裝在其表面上的印刷電路板(PCB)52。電子裝置50具有一種半導體封裝物，或複數種半導體封裝物，其係取決於該應用。為了顯示，不同種類的半導體封裝物係顯示於圖1。
電子裝置50係為使用半導體封裝物來進行一或更多電性功能的單獨系統。或者，電子裝置50係為更大系統的子元件。例如，電子裝置50係為部份的行動電話、個人數位助理(PDA)、數位影像照相機(DVC)或其它電子溝通裝置。或者，電子裝置50係為可被***於電腦的圖形卡、網路介面卡或其它訊號處理卡。半導體封裝物包括微處理器、記憶體、特殊應用積體電路(ASIC)、邏輯電路、類比電路、射頻電路、分隔裝置或其它半導體晶粒或電性元件。微型化與輕量化對這些被市場接受的產品而言是重要的。在半導體裝置之間的距離必須被減少，以得到更高的密度。
在圖1中，PCB 52提供一般性基板，以用於被安裝在PCB上之半導體封裝物的結構性支撐與電性互連。傳導訊號軌跡54係使用蒸發、電解電鍍、無電電鍍、網版印刷或其它適合的金屬沈積製程而被形成在PCB 52的表面上或層內。訊號軌跡54提供半導體封裝物、安裝元件與其他外部系統元件之每一個之間的電性溝通。軌跡54同樣提供功率與接地連接到半導體封裝物的每一個。
在一些實施例中，半導體裝置具有兩個封裝等級。第一封裝等級係為用來將半導體晶粒機械與電性附著到中間載體的技術。第二等級的封裝包含將中間載體機械性與電性附著到PCB。在其他實施例中，半導體裝置僅僅具有第一等級的封裝，在此該晶粒會被機械性與電性地直接安裝到PCB。
為了顯示之目的，數種第一等級的封裝，包括佈線接合封裝56與覆晶58，其係被顯示在PCB 52上。此外，數種第二等級的封裝，包括球柵陣列(BGA)60、凸塊晶片載體(BCC)62、雙列直插式封裝(DIP)64、地柵陣列(LGA)66、多晶片模組(MCM)68、四方形扁平無引腳封裝(QFN)70與四方形扁平封裝72，其係被顯示安裝在PCB 52上。取決於系統必要條件，連同第一與第二等級封裝型態之任何組合以及其他電子元件一起配置之半導體封裝物的任何組合，其係可被連接到PCB 52。在一些實施例中，電子裝置50包括單獨附著的半導體封裝物，同時其他實施例則要求複數個互連封裝物。藉由將一或更多個半導體封裝物組合在單一基板，製造商可將事先製造的元件合併入電子裝置與系統。因為半導體封裝物包括複雜功能，所以電子裝置可使用更便宜的元件與流線型製造製程來製造。結果產生的裝置不太可能會失敗，而且製造起來比較便宜，其係會使消費者的成本更低。
圖2a-2c顯示示範性半導體封裝物。圖2a顯示安裝在PCB 52上之DIP64的進一步詳情。半導體晶粒74包括一主動區域，其係包含實施當作形成在晶粒內之主動裝置、被動裝置、傳導層與介質層的類比或數位電路，其係並且根據該晶粒的電性設計而被電性互連。例如，該電路包括形成在半導體晶粒74之主動區域內的一或更多電晶體、二極體、電感器、電容器、電阻器與其他電路元件。接觸襯墊76係為一或更多層傳導材料，譬如鋁(Al)、銅(Cu)、錫(Sn)、鎳(Ni)、金(Au)或銀(Ag)，其係並且被電性連接到形成於半導體晶粒74內的電路元件。在DIP 64組裝期間內，半導體晶粒74係使用譬如熱環氧或環氧樹脂的金-矽共晶層或黏著材料而被安裝到中間載體78。封裝體包括一絕緣封裝材料，譬如聚合物或陶瓷。導體引線80與接合佈線82則在半導體晶粒74與PCB 52之間提供電性互連。封裝物84係藉由避免濕氣與顆粒進入該封裝物與污染晶粒74或接合佈線82而被沈積在封裝物上，以用於環境保護。
圖2b顯示安裝在PCB 52上之BCC 62的進一步詳情。半導體晶粒88係使用下填或環氧樹脂黏著材料92而被安裝在載體90上。接合佈線94提供接觸襯墊96與98之間的第一等級封裝互連。鑄模化合物或封裝材料100係被沈積在半導體晶粒88與接合佈線94上，以提供物理支撐與電性絕緣給該裝置。接觸襯墊102係使用適合的金屬沈積製程(譬如電解電鍍或無電電鍍)而被形成在PCB 52表面上以避免氧化。接觸襯墊102會被電性連接到在PCB 52中的一或更多傳導訊號軌跡54。凸塊104則會被形成在BCC 62的接觸襯墊98以及PCB 52的接觸襯墊102之間。
在圖2c中，半導體晶粒58係以覆晶型態的第一等級封裝而面向下地安裝到中間載體106。半導體晶粒58的主動區域108包含類比或數位電路，其係實施做為根據該晶粒之電性設計而形成的主動裝置、被動裝置、傳導層與介質層。例如，該電路包括在主動區域108內的一或更多電晶體、二極體、電感器、電容器、電阻器與其他電路元件。半導體晶粒58係經由凸塊110而電性並且機械性地連接到載體106。
BGA 60係電性且機械性地連接到PCB 52，其係具有使用凸塊112的BGA型態第二等級封裝。半導體晶粒58係經由凸塊110、訊號線114與凸塊112而電性連接到在PCB 52中的傳導訊號軌跡54。鑄模化合物或封裝材料116會被沈積在半導體晶粒58與載體106上，以提供物理支撐與電性絕緣給該裝置。該覆晶半導體裝置提供從半導體晶粒58上主動裝置到PCB 52上傳導軌跡的短導電路徑，以便減少訊號傳播距離、降低電容量並且改善整個電路性能。在另一個實施例中，半導體晶粒58可被機械與電性直接連接到PCB 52，其係使用不具有中間載體106的覆晶型態第一等級封裝。
圖3a顯示具有基部基板材料122的半導體晶圓120，譬如矽、鍺、鎵、砷化物、磷化銦或碳化矽，以用於結構性支撐。複數個半導體晶粒或元件124係被形成在晶圓120上，其係由鋸尺街126所隔開，如以上所說明。
圖3b顯示一部份半導體晶圓120的截面圖。每一半導體晶粒124具有背表面128與主動表面130，包含類比或數位電路，其係實施當作根據晶粒的電性設計與功能而被形成在該晶粒內並且被電性互連的主動裝置、被動裝置、傳導層與介質層。例如，電路包括形成在主動表面130內的一或更多個電晶體、二極體與其他電路元件，以實施類比電路或數位電路，譬如數位訊號處理器(DSP)、ASIC、記憶體或其它訊號處理電路。半導體晶粒124亦包含積體被動裝置(IPD)，譬如電感器、電容器與電阻器，以用於射頻訊號處理。在一個實施例中，半導體晶粒124係為覆晶型半導體晶粒。
導電層132係使用PVD、CVD、電解電鍍、無電電鍍製程或其它適當的金屬沈積製程而被形成在主動表面130上。傳導層132係為鋁、銅、錫、鎳、金、銀或其它適當導電材料的其中一層或更多層。傳導層132操作當作接觸襯墊，其係被電性連接到主動表面130上的電路。
圖3c顯示具有互連結構被形成在接觸襯墊132上的一部份半導體晶圓120。導電凸塊材料134係使用蒸發、電解電鍍、無電電鍍、球下降或網版印刷製程而被沈積在接觸襯墊132上。凸塊材料134係為鋁、錫、鎳、金、銀、鉛、鉍、銅、銲料與其組合，其係具有選擇性的溶液流。例如，凸塊材料134係為共晶錫/鉛、高鉛銲料或無鉛銲料。凸塊材料134一般是適用的，其係並且在等於大約250公克垂直負載的力作用下，受到大於大約25微米(μm)的塑膠變形。凸塊材料134會被接合到接觸襯墊132，其係使用適當的附著或接合製程。例如，凸塊材料134會被壓縮接合到接觸襯墊132。凸塊材料134亦可藉由將材料加熱到超過其熔點以形成圓球或凸塊136而被回流，如圖3d所示。在一些應用中，凸塊136會被再次回流，以改善到接觸襯墊132的電性接觸。凸塊136代表可形成在接觸襯墊132上的一種互連結構。該互連結構亦可使用柱型凸塊、微型凸塊或其它電性互連。
圖3e顯示形成在做為合成物凸塊138之接觸襯墊132上互連結構的另一個實施例，其係包括非可熔或非可拆卸部份140以及可熔或可拆卸部份142。可熔或可拆卸以及非可熔或非可拆卸屬性，其係被定義用於關於回流情況的凸塊138。非可熔部份140係為金、銅、鎳、高鉛銲料、或鉛錫合金。可熔部份142係為錫、無鉛合金、錫-銀合金、錫-銀-銅合金、錫-銀-銦(In)合金、共晶銲料、具有銀、銅或鉛或其它相當低溫度熔化銲料的錫合金。在一個實施例中，已知接觸襯墊132寬度或直徑為100μm，所以非可熔部份140的高度則大約45μm，且可熔部份142的高度則大約35μm。
圖3f顯示形成在接觸襯墊132上之互連結構的另一個實施例，其係做為在傳導柱146上的凸塊144。凸塊144係為可熔或可拆卸，且傳導柱146係為非可熔或非可拆卸。可熔或可拆卸以及非可熔或非可拆卸屬性，其係關於回流情況而被定義。凸塊144係為錫、無鉛合金、錫-銀合金、錫-銀-銅合金、錫-銀-銦合金、共晶銲料、具有銀、銅或鉛或其它相當低溫度熔化銲料的錫合金。傳導柱146可以是金、銅、鎳、高鉛銲料、或鉛-錫合金。在一個實施例中，傳導柱146係為銅柱，且凸塊144係為銲料罩。已知接觸襯墊132寬度或直徑為100μm，傳導柱146高度則大約45μm，且凸塊144高度則大約35μm。
圖3g顯示形成在接觸襯墊132上之互連結構的另一個實施例，其係做為具有平坦表面之突點150的凸塊材料148。在具有低產量強度與對失敗之高度延伸的回流情況下，凸塊材料148既軟且可變形的，其係類似凸塊材料134。平坦表面之突點150係以面板表面拋光來形成，其係並且為了顯示而被誇張地顯示於圖式中。平坦表面之突點150的規格一般大概大約1-25μm。平坦表面之突點亦可形成在凸塊136、合成物凸塊138與凸塊144上。
在圖3h中，半導體晶圓120係經由使用鋸尺刀或雷射切割工具152的鋸尺街126而被切單成各別半導體晶粒124。
圖4a顯示具有傳導軌跡156的基板或PCB 154。基板154係為單側FR5疊層或2側BT樹脂疊層。半導體晶粒124的位置使得凸塊材料134對準傳導軌跡156上的互連位置，見圖12a-12g。或者，凸塊材料134可對準形成在基板154上的傳導襯墊或其它互連位置。凸塊材料314會比傳導軌跡156更寬。在一個實施例中，凸塊材料134的寬度為80μm，且就凸塊節距150μm而言，傳導軌跡或襯墊156的寬度為35μm。壓力或力F會被施加到半導體晶粒124的背表面128，以將凸塊材料134壓到傳導軌跡156上。力F可隨著提高溫度來施加。由於凸塊材料134的適用特性，凸塊材料會在傳導軌跡156的頂表面與側表面周圍變形或擠壓，其係稱為鉛上凸塊(BOL)。特別是，壓力的施加會造成凸塊材料134在等於大約250公克之垂直負載的力F下受到大於大約25μm的塑膠變形，並且覆蓋傳導軌跡的頂表面與側表面，如圖4b所示。藉由引領凸塊材料物理接觸傳導軌跡，隨後並且在回流溫度下使凸塊材料回流，凸塊材料134亦可粉末冶金地連接到傳導軌跡156。
藉由使傳導軌跡156比凸塊材料134更窄，傳導軌跡節距可被減少，以增加路由密度與輸入/輸出數目。較窄的傳導軌跡156減少使該傳導軌跡周圍之凸塊材料134變形所需要的力F。例如，必要力F係為凸塊材料對著比凸塊材料更寬之傳導軌跡或襯墊變形所必需力的30－50%。低壓縮力F可使用於精細的節距互連與小晶粒，以維持與規定容差的共面性，並且得到均勻的z-方向變形以及高可靠度互連單元。此外，將傳導軌跡156周圍的凸塊材料134變形，其係可將凸塊機械性地鎖到軌跡，以避免在回流期間內的晶粒移位或晶粒浮動。
圖4c顯示形成在半導體晶粒124之接觸襯墊132上的凸塊136。半導體晶粒124的位置使得凸塊136對準在傳導軌跡156上的互連位置。或者，凸塊136可對準被形成在基板154上的傳導襯墊或其它互連位置。凸塊136比傳導軌跡156更寬。壓力或力F會被施加到半導體晶粒124的背表面128，以將凸塊136壓到傳導軌跡156上。力F可隨著升高溫度被施加。由於凸塊136的適用特性，凸塊會於傳導軌跡156之頂表面與側表面周圍變形或擠壓。特別是，壓力的施加會造成凸塊材料136受到塑膠變形並且覆蓋傳導軌跡156的頂表面與側表面。藉由在回流溫度下引領凸塊物理接觸傳導軌跡，凸塊136亦可粉末冶金地連接到傳導軌跡156。
藉由使傳導軌跡156比凸塊136更窄，傳導軌跡節距會被減少，以增加路由密度與I/O數目。較窄的傳導軌跡156會減少使傳導軌跡周圍之凸塊136變形所需要的力F。例如，必要力F係為使凸塊對著比凸塊更寬之傳導軌跡或襯墊變形所需力的30─50%。低壓縮力F可使用於精細的節距互連與小晶粒，以得到在規定容差內的共面性，並且得到均勻的z-方向變形以及高可靠度互連單元。此外，將傳導軌跡156周圍的凸塊136變形，其係可將凸塊機械性地鎖到軌跡，以避免在回流期間內的晶粒移位或晶粒浮動。
圖4d顯示形成在半導體晶粒124之接觸襯墊132上的合成物凸塊138。半導體晶粒124的位置使得合成物凸塊138對準在傳導軌跡156上的互連位置。或者，合成物凸塊138可對準被形成在基板154上的傳導襯墊或其它互連位置。合成物凸塊138會比傳導軌跡156更寬。壓力或力F可被施加到半導體晶粒124的背表面128，以將可熔部份142壓到傳導軌跡156上。力F可隨著升高溫度被施加。由於可熔部份142的適用特性，可熔部份會於傳導軌跡156之頂表面與側表面周圍變形或擠壓。特別是，壓力的施加會造成可熔部份142受到塑膠變形並且覆蓋傳導軌跡156的頂表面與側表面。藉由在回流溫度下引領可熔部份142物理接觸傳導軌跡，合成物凸塊138亦可粉末冶金地連接到傳導軌跡156。在壓力或溫度的施加期間內，非可熔部份140沒有熔化或變形，其係並且保留其高度與形狀，以做為半導體晶粒124與基板154之間的垂直間隙。在半導體晶粒124與基板154之間的額外位移，其係提供更大的共面容差於匹配表面之間。
在回流製程期間內，在半導體晶粒124上許多(例如，數千)的合成物凸塊138會被附著到在基板154之傳導軌跡156上的互連位置。一些凸塊138會無法適當地連接到傳導軌跡156，特別在假如晶粒124被彎曲的情形下。回憶合成物凸塊138會比傳導軌跡156更寬。由於施加適當力，可熔部份142會變形或在傳導軌跡156之頂表面與側表面周圍延伸，並且將合成物凸塊138機械性地鎖到傳導軌跡。機械互鎖係藉由可熔部份142的特性所形成，其係比傳導軌跡156更軟且更適用，其係並且因此在傳導軌跡的頂表面上與側表面周圍變形，以用於更大的接觸表面面積。在合成物凸塊138與傳導軌跡156之間的機械互鎖可在回流期間內將凸塊固持到傳導軌跡，亦即，凸塊與傳導軌跡並沒有失去接觸。於是，配合傳導軌跡156的合成物凸塊138會減少凸塊互連的失敗。
圖4e顯示形成在半導體晶粒124之接觸襯墊132上的傳導柱146與凸塊144。半導體晶粒124的位置使得凸塊144對準傳導軌跡156上的互連位置。或者，凸塊144可對準形成在基板154上的傳導襯墊或其它互連位置。凸塊144會比傳導軌跡156更寬。壓力或力F可被施加到半導體晶粒124的背表面128，以將凸塊144壓到傳導軌跡156上。力F可隨著升高溫度被施加。由於凸塊144的適用特性，凸塊會於傳導軌跡156之頂表面與側表面周圍變形或擠壓。特別是，壓力的施加會造成凸塊144受到塑膠變形並且覆蓋傳導軌跡156的頂表面與側表面。藉由在回流溫度下引領凸塊物理接觸傳導軌跡，傳導柱146與凸塊144亦可粉末冶金地連接到傳導軌跡156。在壓力或溫度的施加期間內，傳導柱146沒有熔化或變形，其係並且保留其高度與形狀，以做為半導體晶粒124與基板154之間的垂直間隙。在半導體晶粒124與基板154之間的額外位移，其係提供更大的共面容差於匹配表面之間。較寬的凸塊144與較窄的傳導軌跡156具有在以上所描述的類似低必要壓縮力與機械鎖住特徵與優點，以用於凸塊材料134與凸塊136。
圖4f顯示具有平坦表面之突點150形成在半導體晶粒124之接觸襯墊132上的凸塊材料148。半導體晶粒124的位置使得凸塊材料148能夠對準傳導軌跡156上的互連位置。或者，凸塊材料148可對準形成在基板154上的傳導襯墊或其它互連位置。凸塊材料148會比傳導軌跡156更寬。壓力或力F可被施加到半導體晶粒124的背表面128，以將凸塊材料148壓到傳導軌跡156上。力F可隨著升高溫度被施加。由於凸塊材料148的適用特性，凸塊會於傳導軌跡156之頂表面與側表面周圍變形或擠壓。特別是，壓力的施加會造成凸塊材料148受到塑膠變形並且覆蓋傳導軌跡156的頂表面與側表面。此外，凸塊150亦可粉末冶金地連接到傳導軌跡156。平坦表面之突點150的尺寸大概約1─25μm。
圖4g顯示基板或印刷電路板158，其係具有擁有有角或斜側的梯型傳導軌跡160。凸塊材料161係形成在半導體晶粒124的接觸襯墊132上。半導體晶粒124的位置使得凸塊材料161能夠對準傳導軌跡160上的互連位置。或者，凸塊材料161可對準形成在基板158上的傳導襯墊或其它互連位置。凸塊材料161比傳導軌跡160更寬。壓力或力F可被施加到半導體晶粒124的背表面128，以將凸塊材料161壓到傳導軌跡160上。力F可隨著升高溫度被施加。由於凸塊材料161的適用特性，凸塊材料會於傳導軌跡160之頂表面與側表面周圍變形或擠壓。特別是，壓力的施加會造成凸塊材料161在力F之下受到塑膠變形，以覆蓋傳導軌跡160的頂表面與有角側表面。藉由引領凸塊材料物理接觸傳導軌跡並且隨後在回流溫度下使凸塊材料回流，凸塊材料161亦可粉末冶金地連接到傳導軌跡160。
圖5a-5d顯示具有非可熔或非可拆卸部份164以及可熔或可拆卸部份166之半導體晶粒124與延長合成物凸塊162的BOL實施例。非可熔部份164係為金、銅、鎳、高鉛銲料或鉛-錫合金。可熔部份166係為錫、無鉛合金、錫-銀合金、錫-銀-銅合金、錫-銀-銦合金、共晶銲料、具有銀、銅或鉛或其它相當低溫度熔化銲料的錫合金。比起可熔部份166，非可熔部份164會組成一更大部分的合成物凸塊162。非可熔部份164會被固定到半導體晶粒124的接觸襯墊132。
半導體晶粒124的位置使得合成物凸塊162能夠對準形成在基板170上之傳導軌跡168上的互連位置，如圖5a所示。合成物凸塊162係沿著傳導軌跡168被錐形化，亦即，合成物凸塊具有楔形，其係沿著傳導軌跡168的長度而更長，且經由傳導軌跡而更窄。合成物凸塊162的錐形態樣係沿著傳導軌跡168的長度來發生。圖5a的圖式顯示更短態樣或與傳導軌跡168共線的變窄錐形。圖5b的圖式，垂直圖5a，其係顯示楔形合成物凸塊162的更長態樣。合成物凸塊162的更短態樣會比傳導軌跡168更寬。當施加壓力與/或以熱回流時，可熔部份166會繞著傳導軌跡168崩潰，如圖5c與5d所示。非可熔部份164並沒有在回流期間內熔化或變形，其係並且保留其形式與形狀。非可熔部份164可被維度化，以提供在半導體晶粒124與基板170之間的間隙距離。譬如銅有機保焊處理的拋光則可被施加到基板170。
在回流製程期間內，在半導體晶粒124上許多的(例如，數千)合成物凸塊162則可被附著到在基板170之傳導軌跡168上的互連位置。某些凸塊162則無法適當地連接到傳導軌跡168，特別在假如半導體晶粒124被彎曲的情形下。回憶合成物凸塊162比傳導軌跡168更寬。由於適當力的施加，可熔部份166則會在傳導軌跡168的頂表面與側表面周圍變形或擠壓，其係並且將合成物凸塊162機械性地鎖到傳導軌跡。機械互鎖係藉由可熔部份166的特性所形成，其係比傳導軌跡168更軟且更適用，其係並且因此在傳導軌跡的頂表面與側表面周圍變形，以用於更大的接觸面積。在不將沿著圖5a與5c之更短態樣的節距犧牲之下，合成物凸塊162的楔形會增加凸塊與傳導軌跡之間的接觸面積，例如，沿著圖5b與5d的更長態樣。在合成物凸塊162與傳導軌跡168之間的機械互鎖，會在回流期間內將凸塊固持到傳導軌跡，亦即，該凸塊與傳導軌跡並沒有喪失接觸。於是，配合到傳導軌跡168的合成物凸塊162則會減少凸塊互連的失敗。
圖6a-6d顯示具有凸塊材料174形成在接觸襯墊132上之半導體晶粒124的BOL實施例，其係類似圖3c。凸塊材料174一般是適用的，其係並且在等於大約250公克垂直負載的力作用下，受到大於大約25μm的塑膠變形。凸塊材料174比在基板178上的傳導軌跡176更寬。複數個平坦表面之突點180則形成在傳導軌跡176，其高度大概約1-25μm。
在圖6a中，半導體晶粒124的位置使得凸塊材料174對準在傳導軌跡176上的互連位置。或者，凸塊材料174可對準被形成在基板178上的傳導襯墊或其它互連位置。壓力或力F會被施加到半導體晶粒124的背表面128，以將凸塊材料174壓到傳導軌跡176與平坦表面之突點180上，如圖6b所示。力F可隨著升高溫度被施加。由於凸塊材料174的適用特性，凸塊材料會於傳導軌跡176與平坦表面之突點180之頂表面與側表面的周圍變形或擠壓。特別是，壓力的施加會造成凸塊材料174受到塑膠變形並且覆蓋傳導軌跡176與平坦表面之突點180的頂表面與側表面。凸塊材料174的塑膠流會產生宏觀的機械互鎖點於凸塊材料以及傳導軌跡176與平坦表面之突點180的頂表面與側表面之間。凸塊材料174的塑膠流產生於傳導軌跡176與平坦表面之突點180的頂表面與側表面周圍，但卻沒有過度延伸到基板178上，其係會造成電性短路與其他缺陷。在凸塊材料以及傳導軌跡176與平坦表面之突點180的頂表面與側表面之間的機械互鎖，其係會提供與各別表面之間之更大接觸區域的強韌連接，而沒有明顯增加接合力。凸塊材料與傳導軌跡176與平坦表面之突點180的頂表面與側表面之間的機械互鎖，其係亦會在隨後的製造製程(譬如封裝)期間內減少橫向晶粒移位。
圖6c顯示另一BOL實施例，其係具有比傳導軌跡176更窄的凸塊材料174。壓力或力F會被施加到半導體晶粒124的背表面128，以將凸塊材料174壓到傳導軌跡176與平坦表面之突點180上。力F可隨著升高溫度被施加。由於凸塊材料174的適用特性，凸塊材料會於傳導軌跡176與平坦表面之突點180的頂表面上變形或擠壓。特別是，壓力的施加會造成凸塊材料174受到塑膠變形並且覆蓋傳導軌跡176與平坦表面之突點180的頂表面。凸塊材料174的塑膠流會產生宏觀的機械互鎖點於凸塊材料以及傳導軌跡176與平坦表面之突點180的頂表面之間。在凸塊材料以及傳導軌跡176與平坦表面之突點180的頂表面之間的機械互鎖，其係會提供與各別表面之間之更大接觸區域的強韌連接，而沒有明顯增加接合力。凸塊材料與傳導軌跡176與平坦表面之突點180的頂表面之間的機械互鎖，其係亦會在隨後的製造製程(譬如封裝)期間內減少橫向晶粒移位。
圖6d顯示另一BOL實施例，其係具有凸塊材料174形成在傳導軌跡176的邊緣上，亦即部份凸塊材料在傳導軌跡上面，且部份凸塊材料不在傳導軌跡上面。壓力或力F會被施加到半導體晶粒124的背表面128，以將凸塊材料174壓到傳導軌跡176與平坦表面之突點180上。力F可隨著升高溫度被施加。由於凸塊材料174的適用特性，凸塊材料會於傳導軌跡176與平坦表面之突點180之頂表面與側表面上變形或擠壓。特別是，壓力的施加會造成凸塊材料174受到塑膠變形並且覆蓋傳導軌跡176與平坦表面之突點180的頂表面與側表面。凸塊材料174的塑膠流會產生宏觀的機械互鎖點於凸塊材料以及傳導軌跡176與平坦表面之突點180的頂表面與側表面之間。在凸塊材料以及傳導軌跡176與平坦表面之突點180的頂表面與側表面之間的機械互鎖，其係會提供與各別表面之間之更大接觸區域的強韌連接，而沒有明顯增加接合力。凸塊材料與傳導軌跡176與平坦表面之突點180的頂表面與側表面之間的機械互鎖，其係亦會在隨後的製造製程(譬如封裝)期間內減少橫向晶粒移位。
圖7a-7c顯示具有凸塊材料184形成在接觸襯墊132上之半導體晶粒124的BOL實施例，其係類似圖3c。尖端186從凸塊材料184的體部延伸，以做為步進凸塊，尖端186則比凸塊材料184的體部更窄，如圖7a所示。半導體晶粒124的位置使得凸塊材料184能夠對準在基板190上之傳導軌跡188上的互連位置。更明確地，尖端186的中心在傳導軌跡188上的互連位置上。或者，凸塊材料184與尖端186可對準被形成在基板190上的傳導襯墊或其它互連位置。凸塊材料184係比在基板190上的傳導軌跡188更寬。
傳導軌跡188一般是適用的，其係並且在等於大約250公克垂直負載的力作用下，受到大於大約25μm的塑膠變形。壓力或力F會被施加到半導體晶粒124的背表面128，以將尖端184壓到傳導軌跡188上。力F可隨著升高溫度被施加。由於傳導軌跡188的適用特性，傳導軌跡會在尖端186周圍變形，如圖7b所示。特別是，壓力的施加會造成傳導軌跡188受到塑膠變形並且覆蓋尖端186的頂表面與側表面。
圖7c顯示具有圓形凸塊材料194形成在接觸襯墊132上的另一個BOL實施例。尖端196從凸塊材料194的體部延伸，以形成一柱形凸塊，其尖端則比凸塊材料194的體部更窄。半導體晶粒124的位置使得凸塊材料194能夠對準在基板200上之傳導軌跡198上的互連位置。更明確地，尖端196的中心在傳導軌跡198上的互連位置上。或者，凸塊材料194與尖端196可對準被形成在基板200上的傳導襯墊或其它互連位置。凸塊材料194係比在基板200上的傳導軌跡198更寬。
傳導軌跡198一般是適用的，其係並且在等於大約250公克垂直負載的力作用下，受到大於大約25μm的塑膠變形。壓力或力F會被施加到半導體晶粒124的背表面128，以將尖端196壓到傳導軌跡198上。力F可隨著升高溫度被施加。由於傳導軌跡198的適用特性，傳導軌跡會在尖端196周圍變形。特別是，壓力的施加會造成傳導軌跡198受到塑膠變形並且覆蓋尖端196的頂表面與側表面。
在圖4a-4g、5a-5d與6a-6d中所說明的傳導軌跡，其係亦為在圖7a-7c中所說明的適用材料。
圖8a-8b顯示具有凸塊材料204形成在接觸襯墊132上之半導體晶粒124的BOL實施例，其係類似圖3c。凸塊材料204一般是適用的，其係並且在等於大約250公克垂直負載的力作用下，受到大於大約25μm的塑膠變形。凸塊材料204比在基板208上的傳導軌跡206更寬。傳導通道210係形成經過具有開口212與傳導邊牆214的傳導軌跡206，如圖8a所示。
半導體晶粒124的位置使得凸塊材料204對準傳導軌跡206上的互連位置，如圖12a-12g所示。或者，凸塊材料204可對準形成在基板208上的傳導襯墊或其它互連位置。壓力或力F可被施加到半導體晶粒124的背表面128，以將凸塊材料204壓到傳導軌跡206上以及到傳導通道210的開口212內。力F可隨著升高溫度被施加。由於凸塊材料204的適用特性，凸塊材料會於傳導軌跡176之頂表面與側表面周圍以及傳導通道210的開口212內變形或擠壓，如圖8b所示。特別是，壓力的施加會造成凸塊材料204受到塑膠變形並且覆蓋傳導軌跡206的頂表面與側表面並且到傳導通道210的開口212內。凸塊材料204因此會被電性連接到傳導軌跡206與傳導邊牆214，以用於經由基板208的z-方向垂直互連。凸塊材料204的塑膠流會產生機械互鎖於凸塊材料以及傳導軌跡206的頂表面與側表面以及傳導通道210的開口212之間。在凸塊材料以及傳導軌跡206的頂表面與側表面以及傳導通道210的開口212之間的機械互鎖，其係會提供與各別表面之間之更大接觸區域的強韌連接，而沒有明顯增加接合力。在凸塊材料以及傳導軌跡206的頂表面與側表面以及傳導通道210的開口212之間的機械互鎖，其係亦會在隨後的製造製程(譬如封裝)期間內減少橫向晶粒移位。因為傳導通道210係形成在具有凸塊材料204的互連位置內，所以總基板互連區域會被減少。
在圖4a-4g、5a-5d、6a-6d、7a-7c與8a-8b的BOL實施例中，藉由使傳導軌跡比互連結構更窄，傳導軌跡節距會被減少，以增加路由密度與I/O數目。較窄的傳導軌跡會減少使傳導軌跡周圍之互連結構變形所需要的力F。例如，必要力F係為使凸塊對著比凸塊更寬之傳導軌跡或襯墊變形所需力的30─50%。低壓縮力F可使用於精細的節距互連與小晶粒，以得到在規定容差內的共面性，並且得到均勻的z-方向變形以及高可靠度互連單元。此外，將傳導軌跡周圍的互連結構變形，其係可將凸塊機械性地鎖到軌跡，以避免在回流期間內的晶粒移位或晶粒浮動。
圖9a-9c顯示使封裝物沈積在半導體晶粒與基板之間凸塊周圍的一種鑄模下填(MUF)製程。圖9a顯示使用來自圖4b之凸塊材料134而被安裝到基板154的半導體晶粒124，其係並且放置在切線模220的上鑄模支撐216與下鑄模支撐218之間。來自圖4a-4g、5a-5d、6a-6d、7a-7c與8a-8b的其他半導體晶粒與基板組合，其係可被放置在切線模220的上鑄模支撐216與下鑄模支撐218之間。上鑄模支撐216包括可壓縮釋放膜222。
在圖9b中，上鑄模支撐216與下鑄模支撐218被引領在一起，以密封半導體晶粒124與基板154，其係在基板上與半導體晶粒與基板之間具有一開啟空間。可壓縮釋放膜222遵守半導體晶粒124的背表面128與側表面，以阻障封裝物形成在這些表面上。呈液體狀態的封裝物224會以噴嘴226而被注入於切線模220的一側內，同時任選真空輔助228會從相反側汲取壓力，以用封裝物均勻充填在基板154上的開啟空間以及在半導體晶粒124與基板154之間的開啟空間。封裝物224係為聚合物合成材料，譬如具有充填物的環氧樹脂、具有充填物的環氧丙烯酸、或具有適當充填物的聚合物。封裝物224係為非傳導性，其係並且在環境上保護半導體裝置免於受到外部元件與污染。可壓縮材料222避免封裝物224流到半導體晶粒124的背表面128上面，以及側表面周圍。封裝物224可被固化。半導體晶粒124的背表面128與側表面仍然可從封裝物224曝光。
圖9c顯示在不具有可壓縮材料222時鑄模下填與鑄模上填(MOF)的實施例。半導體晶粒124與基板154係被放置在切線模220的上鑄模支撐216與下鑄模支撐218之間。上鑄模支撐216與下鑄模支撐218被引領在一起，以密封半導體晶粒124與基板154，其係在基板上、半導體晶粒周圍與半導體晶粒與基板之間具有一開啟空間。呈液體狀態的封裝物224會以噴嘴226而被注入於切線模220的一側內，同時任選真空輔助228會從相反側汲取壓力，以用封裝物均勻充填在半導體晶粒124周圍與基板154上的開啟空間以及在半導體晶粒124與基板154之間的開啟空間。封裝物224可被固化。
在另一個實施例中，噴嘴亦可放置在切線模或晶粒條的中心區域，以將封裝物向外分佈到半導體晶粒與基板的邊緣。
圖10顯示將封裝物沈積在半導體晶粒124周圍以及半導體晶粒124與基板154之間間隙的另一個實施例。半導體晶粒124與基板154係由屏障230所密封。封裝物232係呈液體狀態地從噴嘴234分配入屏障230內，以充填基板154上的開啟空間，以及半導體晶粒124與基板154之間的開啟空間。從噴嘴234分配的封裝物體積會被控制，以填滿屏障230，而沒有覆蓋半導體晶粒124的背表面128或側表面。封裝物232則會被固化。
圖11顯示在來自圖9a、9c與10之鑄模下填製程以後的半導體晶粒124與基板154。封裝物224會被均勻分佈於基板154上以及在半導體晶粒124與基板154之間的凸塊材料134周圍。
圖12a-12g顯示在基板或PCB240上之種種傳導軌跡佈局的頂部視圖。在圖12a中，傳導軌跡242係為具有積體凸塊襯墊或互連位置224形成在基板240上的直導體。基板凸塊襯墊244的邊側係與傳導軌跡242共線。在先前技術中，銲料登記開啟(SRO)基本上係形成在互連位置上，以包含在回流期間內的凸塊材料。SRO增加互連節距並且減少輸入/輸出數目。反之，遮罩層246可形成在一部份基板240上；然而，遮罩層並沒有形成在傳導軌跡242的基板凸塊襯墊244周圍。亦即是，被設計以匹配凸塊材料的傳導軌跡242部份，其係缺乏在回流期間內被使用於凸塊污染之遮罩層246的任何SRO。
半導體晶粒124會被放置在基板240上，且凸塊材料134會對準基板凸塊襯墊244。藉由引領凸塊材料物理性地接觸凸塊襯墊，隨後並且在回流溫度下使凸塊材料回流，可使凸塊材料134電性且粉末冶金地連接到基板凸塊襯墊244。
在另一個實施例中，導電凸塊材料係使用蒸發、電解電鍍、無電電鍍、球下降或網版印刷製程而被沈積在基板凸塊襯墊244上。凸塊材料係為鋁、錫、鎳、金、銀、鉛、鉍、銅、銲料與其組合，其係具有選擇性的溶液流。例如，凸塊材料係為共晶錫/鉛、高鉛銲料或無鉛銲料。凸塊材料會使用適當的附著或接合製程被接合到基板凸塊襯墊244。在一個實施例中，凸塊材料係藉由將該材料加熱到其熔點以上而被回流，以形成凸塊或互連248，如圖12b所示。在一些應用中，凸塊248會被再次回流，以改善到基板凸塊襯墊244的電性接觸。在窄基板凸塊襯墊244周圍的凸塊材料會在回流期間內維持晶粒的位置。
在高路由密度的應用中，將傳導軌跡242的逃脫節距最小化是令人希望的。在傳導軌跡242之間的逃脫節距可藉由為了回流污染之目的而來移除遮罩層而減少，亦即，藉由在沒有遮罩層之下使該凸塊材料回流。因為沒有任何SRO形成在晶粒凸塊襯墊132或基板凸塊襯墊244周圍，所以傳導軌跡242則可形成具有更精細的節距，亦即，傳導軌跡242可被更近地配置在一起或配置到鄰近的結構。由於在基板凸塊襯墊244周圍沒有SRO，所以在傳導軌跡242之間的節距係由P=D+PLT+W/2所產生，其中D係為凸塊248的基部直徑，PLT係為晶粒放置容差，且W係為傳導軌跡242的寬度。在一個實施例中，已知凸塊基部直徑100μm、PLT 10μm以及軌跡線寬度30μm，所以傳導軌跡242的最小逃脫節距則是125μm。無遮罩凸塊形成會將考慮相鄰開口、銲料遮罩註冊(SRT)、以及最小可解決SRO之間遮罩材料之韌帶間隔(在先前技術中發現)的需求排除。
當在遮罩層沒有將晶粒凸塊襯墊132粉末冶金且電性連接到基板凸塊襯墊264之下而使凸塊材料回流時，濕潤與表面張力會使凸塊材料維持自動侷限，並且保持在與實質在凸塊襯墊足跡內之傳導軌跡242緊鄰的晶粒凸塊襯墊132與基板凸塊襯墊244與部份基板240之間的空間內。
為了得到所希望的自動侷限特性，凸塊材料可在放置於晶粒凸塊襯墊132或基板凸塊襯墊244以前被浸漬於溶液流，以選擇性地使凸塊材料所接觸的區域比傳導軌跡242的周圍區域更濕。由於溶液流的濕潤特性，溶化的凸塊材料仍然會實質維持侷限於凸塊襯墊所定義的區域內。凸塊材料並沒有跑出較不濕潤的區域。薄氧化物層或其他絕緣層則可形成在凸塊材料並沒有打算使該區域更不濕潤的區域上。因此，遮罩層240不一定是在晶粒凸塊襯墊132或基板凸塊襯墊244周圍。
圖12c顯示為直線導體之平行傳導軌跡252的另一實施例，其係為具有積體矩型凸塊襯墊或互連位置254形成在基板250上的直線導體。在此情形中，基板凸塊襯墊254會比傳導軌跡242更寬，但卻小於匹配凸塊的寬度。基板凸塊襯墊254的邊側會平行傳導軌跡252。遮罩層256可被形成在一部份基板250上；然而，遮罩層並沒有形成在傳導軌跡252的基板凸塊襯墊254周圍。亦即是，被設計以匹配凸塊材料的傳導軌跡252部份，其係缺乏在回流期間內被使用於凸塊污染之遮罩層246的任何SRO。
圖12d顯示呈複數行陣列來排列之傳導軌跡260與262的另一個實施例，其係具有補償積體凸塊襯墊或互連位置264形成在基板266上，以用於最大互連密度與容量。替代的傳導軌跡260與262包括用來路由到凸塊襯墊264的彎管。每一基板凸塊襯墊264的邊側係與傳導軌跡260與262共線。遮罩層268可形成在一部份基板266上；然而，遮罩層268並沒有形成在傳導軌跡260與262的基板凸塊襯墊264周圍。亦即是，被設計以匹配凸塊材料的傳導軌跡260與262部份，其係缺乏在回流期間內被使用於凸塊污染之遮罩層268的任何SRO。
圖12e顯示呈複數行陣列來排列之傳導軌跡270與272的另一個實施例，其係具有補償積體凸塊襯墊或互連位置274形成在基板276上，以用於最大互連密度與容量。替代的傳導軌跡270與272包括用來路由到凸塊襯墊274的彎管。在此情形中，基板凸塊襯墊274會被圍繞並且比傳導軌跡270與272更寬，但卻小於匹配互連凸塊材料的寬度。遮罩層278可形成在一部份基板276上；然而，遮罩層278並沒有形成在傳導軌跡270與272的基板凸塊襯墊274周圍。亦即是，被設計以匹配凸塊材料的傳導軌跡270與272部份，其係缺乏在回流期間內被使用於凸塊污染之遮罩層278的任何SRO。
圖12f顯示呈複數行陣列來排列之傳導軌跡280與282的另一個實施例，其係具有補償積體凸塊襯墊或互連位置284形成在基板286上，以用於最大互連密度與容量。替代的傳導軌跡280與282包括用來路由到凸塊襯墊284的彎管。在此情形中，基板凸塊襯墊254係為矩型並且比傳導軌跡280與282更寬，但卻小於匹配互連凸塊材料的寬度。遮罩層288可形成在一部份基板286上；然而，遮罩層288並沒有形成在傳導軌跡280與282的基板凸塊襯墊284周圍。亦即是，被設計以匹配凸塊材料的傳導軌跡280與282部份，其係缺乏在回流期間內被使用於凸塊污染之遮罩層288的任何SRO。
做為互連製程的一個實例，半導體晶粒124會被放置在基板266上，且凸塊材料134會對準來自圖12d的基板凸塊襯墊264。藉由擠壓凸塊材料或引領凸塊材料物理接觸凸塊襯墊，隨後並且在回流溫度下使凸塊材料回流，凸塊材料134可電性與粉末冶金地連接到基板凸塊襯墊264，如圖4a-4g、5a-5d、6a-6d、7a-7c與8a-8b所說明。
在另一個實施例中，導電凸塊材料係使用蒸發、電解電鍍、無電電鍍、球下降或網版印刷製程而被沈積在基板凸塊襯墊264上。凸塊材料係為鋁、錫、鎳、金、銀、鉛、鉍、銅、銲料與其組合，其係具有選擇性的溶液流。例如，凸塊材料係為共晶錫/鉛、高鉛銲料或無鉛銲料。凸塊材料會被接合到基板凸塊襯墊264，其係使用適當的附著或接合製程。在一個實施例中，凸塊材料係藉由將材料加熱到超過其熔點以形成凸塊或互連290而被回流，如圖12g所示。在一些應用中，凸塊136會被再次回流，以改善到基板凸塊襯墊264的電性接觸。在窄基板凸塊襯墊264周圍的凸塊材料會維持在回流期間內的晶粒位置。凸塊材料134或凸塊290亦可被形成在圖12a-12g的基板凸塊襯墊架構上。
在高路由密度應用中，將傳導軌跡260與262或圖12a-12g之其他傳導軌跡架構的逃脫節距最小化是令人希望的。在傳導軌跡260與262之間的逃脫節距可藉由為了回流污染之目的來移除遮罩層而減少，亦即，藉由在沒有遮罩層之下使該凸塊材料回流。因為沒有任何SRO形成在晶粒凸塊襯墊132或基板凸塊襯墊264周圍，所以傳導軌跡260與262則可形成具有更精細的節距，亦即，傳導軌跡260與262可被更近地被配置在一起或配置到鄰近的結構。由於在基板凸塊襯墊264周圍沒有SRO，所以在傳導軌跡260與262之間的節距係由P=D+PLT+W/2所產生，其中D係為凸塊290的基部直徑，PLT係為晶粒放置容差，且W係為傳導軌跡260與262的寬度。在一個實施例中，已知凸塊基部直徑100μm、PLT 10μm以及軌跡線寬度30μm，所以傳導軌跡260與262的最小逃脫節距則是125μm。無遮罩凸塊形成會將考慮相鄰開口、銲料遮罩註冊(SRT)、以及最小可解決SRO之間遮罩材料之韌帶間隔(在先前技術中發現)的需求排除。
當在遮罩層沒有將晶粒凸塊襯墊132粉末冶金且電性連接到基板凸塊襯墊264之下而使凸塊材料回流時，濕潤與表面張力會使凸塊材料維持自動侷限，並且保持在與實質在凸塊襯墊足跡內之傳導軌跡260與262緊鄰的晶粒凸塊襯墊132與基板凸塊襯墊264與部份基板266之間的空間內。
為了得到所希望的自動侷限特性，凸塊材料可在放置於晶粒凸塊襯墊132或基板凸塊襯墊264以前被浸漬於溶液流，以選擇性地使凸塊材料所接觸的區域比傳導軌跡260與262的周圍區域更濕。由於溶液流的濕潤特性，溶化的凸塊材料仍然會實質維持侷限於凸塊襯墊所定義的區域內。凸塊材料並沒有跑出較不濕潤的區域。薄氧化物層或其他絕緣層則可形成在凸塊材料並沒有打算使該區域更不濕潤的區域上。因此，遮罩層268不一定是在晶粒凸塊襯墊132或基板凸塊襯墊264周圍。
在圖13a中，遮罩層292係被沈積在一部份傳導軌跡294與296上。然而，遮罩層292並沒有被形成在積體凸塊襯墊298上。結果，基板300上的每一凸塊襯墊298，則沒有任何SRO。非濕潤遮罩補片302係形成在間質性地在積體凸塊襯墊298陣列內的基板300上，亦即，在相鄰凸塊 襯墊之間。遮罩補片302亦可形成在間質性地在晶粒凸塊襯墊132陣列內的半導體晶粒124上。更一般地，遮罩補片係緊鄰地形成在任何排列中的積體凸塊襯墊，以避免跑出到較不濕潤區域。
半導體晶粒124會被放置在基板300上，且凸塊材料134會對準基板凸塊襯墊298。藉由擠壓凸塊材料或引領凸塊材料物理接觸凸塊襯墊，隨後並且在回流溫度下使凸塊材料回流，凸塊材料134可電性與粉末冶金地連接到基板凸塊襯墊298，如圖4a-4g、5a-5d、6a-6d、7a-7c與8a-8b所說明。
在另一個實施例中，導電凸塊材料係使用蒸發、電解電鍍、無電電鍍、球下降或網版印刷製程而被沈積在晶粒積體凸塊襯墊298上。凸塊材料係為鋁、錫、鎳、金、銀、鉛、鉍、銅、銲料與其組合，其係具有選擇性的溶液流。例如，凸塊材料係為共晶錫/鉛、高鉛銲料或無鉛銲料。凸塊材料會使用適當的附著或接合製程被接合到基板凸塊襯墊298。在一個實施例中，凸塊材料係藉由將該材料加熱到其熔點以上而被回流，以形成圓球或凸塊304。在一些應用中，凸塊304會被再次回流，以改善到基板凸塊襯墊298的電性接觸。該凸塊亦可被壓縮接合到積體凸塊襯墊298。凸塊304代表一種可被形成在積體凸塊襯墊298上的互連結構。該互連結構亦可使用柱形凸塊、微型凸塊或其它電性互連。
在高路由密度應用中，將逃脫節距最小化是令人希望 的。為了減少傳導軌跡294與296之間的節距，凸塊材料可在積體凸塊襯墊298周圍沒有遮罩層之下被回流。在傳導軌跡294與296之間的逃脫節距可藉由為了回流污染之目的而來移除積體凸塊襯墊周圍的遮罩層與相關SRO而減少，亦即，藉由在沒有遮罩層之下使該凸塊材料回流。遮罩層292可形成在遠離積體凸塊襯墊298的一部份傳導軌跡294與296與基板300上；然而，遮罩層292並沒有形成在積體凸塊襯墊298周圍。亦即是，被設計以匹配凸塊材料的傳導軌跡294與296部份，其係缺乏在回流期間內被使用於凸塊污染之遮罩層292的任何SRO。
此外，遮罩補片302係形成在間質性地在積體凸塊襯墊298陣列內的基板300上。遮罩補片302係為非濕潤材料。遮罩補片302係為與遮罩層292相同以及在相同製程步驟內被施加的材料，或者在不同製程步驟內的不同材料。遮罩補片302可藉由在積體凸塊襯墊298陣列內軌跡或襯墊部份的選擇性氧化、電鍍或其它處理而被形成。遮罩補片302限制凸塊材料流到積體凸塊襯墊298，並且避免傳導凸塊材料到相鄰結構的濾出。
當凸塊材料以間質性地配置在積體凸塊襯墊298之陣列內的遮罩補片302而被回流時，濕潤性與表面張力會造成凸塊材料被侷限並且保持在晶粒凸塊襯墊132與積體凸塊襯墊298以及緊鄰傳導軌跡294與296且實質在積體凸塊襯墊298足跡內的部份基板300之間的空間內。
為了得到所希望的侷限特性，凸塊材料可在放置於晶 粒凸塊襯墊132或積體凸塊襯墊298以前被浸漬於溶液流，以選擇性地使凸塊材料所接觸的區域比傳導軌跡294與296的周圍區域更濕。由於溶液流的濕潤特性，溶化的凸塊材料仍然會實質維持侷限於凸塊襯墊所定義的區域內。凸塊材料並沒有跑出較不濕潤的區域。薄氧化物層或其他絕緣層則可形成在凸塊材料並沒有打算使該區域更不濕潤的區域上。因此，遮罩層292不一定是在晶粒凸塊襯墊132或基板凸塊襯墊298周圍。
因為沒有任何SRO形成在晶粒凸塊襯墊132或積體凸塊襯墊298周圍，所以傳導軌跡294與296則可形成具有更精細的節距，亦即，傳導軌跡可被更靠近相鄰結構地被配置而沒有進行接觸與形成電性短路。假設相同的銲料註冊設計規則，那麼在傳導軌跡294與296之間的節距係由P=(1.1D+W)/2所產生，在此D係為凸塊304的基部直徑，且W係為傳導軌跡294與296的寬度。在一個實施例中，已知凸塊直徑100μm且軌跡線寬度20μm、傳導軌跡294與296的最小逃脫節距則是65μm。凸塊形成會將考慮相鄰開口、以及最小可解決SRO之間遮罩材料之韌帶間隔(在先前技術中發現)的需求排除。
圖14顯示疊層封裝(PoP)305，其係具有使用晶粒附著黏著劑310而堆疊在半導體晶粒308上的半導體晶粒306。半導體晶粒306與308各具有一主動表面，其係包含實施當作形成在晶粒內之主動裝置、被動裝置、傳導層與介質層的類比或數位電路，其係並且根據該晶粒的電性設計與功能而被電性互連。例如，該電路包括形成在主動表面內的一或更多電晶體、二極體、與其他電路元件，以實施類比電路或數位電路，譬如數位訊號處理、特殊應用積體電路、記憶體或其它訊號處理電路。半導體晶粒306與308亦包含積體被動裝置(IPD)，譬如電感器、電容器與電阻器，以用於射頻訊號處理。
半導體晶粒306被安裝在形成於基板314上的傳導軌跡312，其係使用形成在接觸襯墊318上的凸塊材料316，使用來自圖4a-4g、5a-5d、6a-6d、7a-7c或8a-8b的任一個實施例。半導體晶粒308係使用接合佈線322而被電性連接到形成在基板314上的接觸襯墊320。接合佈線322的相反端會被接合到在半導體晶粒306上的接觸襯墊324。
遮罩層326係形成在基板314上，並且在半導體晶粒306的足跡更遠處開啟。雖然遮罩層326沒有在回流期間內將凸塊材料316侷限於傳導軌跡312，但是開啟遮罩則可操作當作一屏障，以避免封裝物328在MUF期間內遷移到接觸襯墊320或接合佈線322。封裝物328會被沈積在半導體晶粒308與基板314之間，其係類似圖9a-9c。遮罩層326阻擋MUF封裝物328到達接觸襯墊320與接合佈線322，其係會導致缺陷。在沒有封裝物328洩放到接觸襯墊320上的風險下，遮罩層326會允許更大的半導體晶粒被放置在已知基板上。
雖然本發明的一或更多實施例已經被詳細說明，但是熟諳該技藝者將理解，那些實施例的變更與適應性可在不背離以下申請專利範圍所陳述的本發明範圍下進行。
50．．．電子裝置
52．．．印刷電路板
54．．．軌跡
56．．．佈線接合封裝物
58．．．覆晶
60．．．球柵陣列
62．．．凸塊晶片載體
64．．．雙列直插式封裝物
66．．．基板柵格陣列
68．．．多晶片模組
70．．．四側扁平無引線封裝物
72．．．四側扁平封裝物
74．．．半導體晶粒
76．．．接觸襯墊
78．．．中間載體
80．．．導體引線
82．．．接合佈線
84．．．封裝材料
88．．．半導體晶粒
90．．．載體
92．．．下填或環氧樹脂黏著材料
94．．．接合佈線
96．．．接觸襯墊
98．．．接觸襯墊
100．．．鑄模化合物或封裝材料
102．．．接觸襯墊
104．．．凸塊
106．．．中間載體
108．．．主動區域
110．．．凸塊
112．．．凸塊
114．．．訊號線
116．．．鑄模化合物或封裝材料
120．．．半導體晶圓
122．．．基部基板材料
124．．．半導體晶粒
126．．．鋸齒街
128．．．背表面
130．．．主動表面
132．．．導電層
134．．．凸塊材料
136．．．凸塊
138．．．合成物凸塊
140．．．非可熔或非可拆卸部份
142．．．可熔或可拆卸部份
144．．．凸塊
146．．．傳導柱
148．．．凸塊材料
150．．．平坦表面之突點
152．．．鋸刀或雷射切割工具
154．．．基板或印刷電路板
156．．．傳導軌跡
158．．．基板或印刷電路板
160．．．傳導軌跡
161．．．凸塊材料
162．．．合成物凸塊
164．．．非可熔或非可拆卸部份
166．．．可熔或可拆卸部份
168．．．傳導軌跡
170．．．基板
174．．．凸塊材料
176．．．傳導軌跡
178．．．基板
180．．．平坦表面之突點
184．．．凸塊材料
186．．．尖端
188．．．傳導軌跡
190．．．基板
194．．．凸塊材料
196．．．尖端
198．．．傳導軌跡
200．．．基板
204．．．凸塊材料
206．．．傳導軌跡
208．．．基板
210．．．傳導通道
212．．．開口
214．．．傳導邊牆
216．．．上鑄模支撐
218．．．下鑄模支撐
220．．．切線模
222．．．可壓縮材料
224．．．封裝材料
226．．．噴嘴
228．．．任選真空輔助
230．．．屏障
232．．．封裝材料
234．．．噴嘴
240．．．基板或印刷電路板
242．．．傳導軌跡
244．．．凸塊襯墊或互連位置
246．．．遮罩層
248．．．凸塊或互連
250．．．基板
252．．．傳導軌跡
254．．．基板凸塊襯墊
256．．．遮罩層
260．．．傳導軌跡
262．．．傳導軌跡
264．．．凸塊襯墊或互連位置
266．．．基板
268．．．遮罩層
270．．．傳導軌跡
272．．．傳導軌跡
274．．．凸塊襯墊或互連位置
276．．．基板
278．．．遮罩層
280．．．傳導軌跡
282．．．傳導軌跡
284．．．凸塊襯墊或互連位置
286．．．基板
288．．．遮罩層
290．．．凸塊
292．．．遮罩層
294．．．傳導軌跡
296．．．傳導軌跡
298．．．凸塊襯墊
300．．．基板
302．．．遮罩補片
304．．．圓球或凸塊
305．．．疊層封裝
306．．．半導體晶粒
308．．．半導體晶粒
310．．．晶粒黏接黏合劑
312．．．傳導軌跡
314．．．基板
316．．．凸塊材料
318．．．接觸襯墊
320．．．接觸襯墊
322．．．接合佈線
324．．．接觸襯墊
326．．．遮罩層
328．．．封裝材料
圖1顯示一印刷電路板，其係具有不同種類的包裝物被安裝到其表面；
圖2a-2c顯示安裝在印刷電路板之半導體封裝物的進一步細節；
圖3a-3h顯示形成在半導體晶粒上的種種互連結構，以用來接合到基板上的傳導軌跡；
圖4a-4g顯示接合到半導體軌跡的半導體晶粒與互連結構；
圖5a-5d顯示具有接合到傳導軌跡之尖形互連結構的半導體晶粒；
圖6a-6d顯示接合到傳導軌跡之半導體晶粒與互連結構的另一實施例；
圖7a-7c顯示接合到傳導軌跡的步進凸塊與柱形凸塊互連結構；
圖8a-8b顯示具有傳導通道的傳導軌跡；
圖9a-9c顯示半導體晶粒與基板之間的鑄模下填；
圖10顯示半導體晶粒與基板之間的另一鑄模下填；
圖11顯示在鑄模下填以後的半導體晶粒與基板；
圖12a-12g顯示具有開啟銲料註冊之傳導軌跡的種種排列情形；
圖13a-13b顯示在傳導軌跡之間具有補片的開啟銲料註冊；以及
圖14顯示具有遮罩層屏障的POP，以限制在鑄模下填期間內的封裝物。
124．．．半導體晶粒
128．．．背表面
130．．．主動表面
132．．．導電層
134．．．凸塊材料
154．．．基板或印刷電路板
156．．．傳導軌跡
216．．．上鑄模支撐
218．．．下鑄模支撐
220．．．切線模
222．．．可壓縮材料
224．．．封裝材料
226．．．噴嘴
228．．．任選真空輔助

Claims (15)

  1. 一種製造半導體裝置的方法，包括：提供一半導體晶粒，其包含形成在該半導體晶粒的一表面上的複數個凸塊；提供一基板；形成包含互連位置的複數個傳導軌跡於該基板上，該凸塊比該互連位置更寬；形成複數個遮罩補片於該基板之該互連位置間隙中的一區域上；將該凸塊接合到該互連位置，以致於該凸塊能夠覆蓋該互連位置的一頂表面與側表面；以及將一封裝物沈積在該半導體晶粒上、在該半導體晶粒外部的該基板上以及在該半導體晶粒與基板之間的該凸塊周圍。
  2. 如申請專利範圍第1項之方法，進一步包括在壓力或回流溫度下將該凸塊接合到該互連位置。
  3. 如申請專利範圍第1項之方法，進一步包括形成平坦表面之突點於該互連位置或凸塊上。
  4. 如申請專利範圍第1項之方法，其中該凸塊包括一可熔化部份與一非可熔化部份。
  5. 一種製造半導體裝置的方法，包括：提供一半導體晶粒，其係包含形成在該半導體晶粒的一表面上的複數個互連結構；提供一基板； 形成包含互連位置的複數個傳導軌跡在該基板上，該互連結構會比該互連位置更寬；形成複數個遮罩補片於該基板之該互連位置間隙中的一區域上；將該互連結構接合到該互連位置，以覆蓋該互連位置的一頂表面與側表面；以及將一封裝物沈積在該半導體晶粒上以及在該半導體晶粒與基板之間的該互連結構周圍。
  6. 如申請專利範圍第5項之方法，進一步包括在壓力或回流溫度下，將該互連結構接合到該互連位置。
  7. 如申請專利範圍第5項之方法，其中該互連結構包含一凸塊或凸塊材料。
  8. 如申請專利範圍第5項之方法，其中該互連結構包括一可熔化部份與非可熔化部份。
  9. 如申請專利範圍第5項之方法，其中該互連結構包括形成在傳導柱上的一傳導柱與凸塊。
  10. 一種半導體裝置，包括：一半導體晶粒，包含形成在該半導體晶粒的一表面上的複數個互連結構；一基板；包含互連位置形成在該基板上的複數個傳導軌跡，該互連位置會比該互連結構更窄，將該互連結構接合到該互連位置，以致於該互連結構能夠覆蓋該互連位置的一頂表面與側表面；以及 一封裝物，沈積在該半導體晶粒上、在該半導體晶粒外部的該基板上以及在在該半導體晶粒與基板之間的該互連結構周圍。
  11. 如申請專利範圍第10項之半導體裝置，其中在壓力或回流溫度下，該互連結構會被接合到該互連位置。
  12. 如申請專利範圍第10項之半導體裝置，其中該互連結構包括一可熔化部份與非可熔化部份。
  13. 如申請專利範圍第10項之半導體裝置，其中該互連結構包括一傳導柱與形成在該傳導柱上的凸塊。
  14. 如申請專利範圍第10項之半導體裝置，進一步包括形成平坦表面之突點於該互連位置或互連結構上。
  15. 如申請專利範圍第10項之半導體裝置，進一步包括複數個遮罩補片，形成在該基板之該互連位置間隙中的一區域上。
TW100102096A 2010-11-16 2011-01-20 形成覆晶互連結構的半導體裝置和方法 TWI541916B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US12/947,414 US10388626B2 (en) 2000-03-10 2010-11-16 Semiconductor device and method of forming flipchip interconnect structure

Publications (2)

Publication Number Publication Date
TW201225193A TW201225193A (en) 2012-06-16
TWI541916B true TWI541916B (zh) 2016-07-11

Family

ID=43779387

Family Applications (1)

Application Number Title Priority Date Filing Date
TW100102096A TWI541916B (zh) 2010-11-16 2011-01-20 形成覆晶互連結構的半導體裝置和方法

Country Status (6)

Country Link
US (1) US10388626B2 (zh)
JP (1) JP5952523B2 (zh)
KR (1) KR101785729B1 (zh)
CN (1) CN102468197B (zh)
SG (3) SG10201809052TA (zh)
TW (1) TWI541916B (zh)

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9029196B2 (en) * 2003-11-10 2015-05-12 Stats Chippac, Ltd. Semiconductor device and method of self-confinement of conductive bump material during reflow without solder mask
US9142533B2 (en) 2010-05-20 2015-09-22 Taiwan Semiconductor Manufacturing Company, Ltd. Substrate interconnections having different sizes
US8633588B2 (en) 2011-12-21 2014-01-21 Mediatek Inc. Semiconductor package
US9659893B2 (en) 2011-12-21 2017-05-23 Mediatek Inc. Semiconductor package
US9425136B2 (en) 2012-04-17 2016-08-23 Taiwan Semiconductor Manufacturing Company, Ltd. Conical-shaped or tier-shaped pillar connections
US9299674B2 (en) 2012-04-18 2016-03-29 Taiwan Semiconductor Manufacturing Company, Ltd. Bump-on-trace interconnect
KR101492603B1 (ko) * 2012-07-25 2015-02-12 모글루(주) 전자문서 제작 시스템과 그 제어 방법
US9461008B2 (en) 2012-08-16 2016-10-04 Qualcomm Incorporated Solder on trace technology for interconnect attachment
US9111817B2 (en) 2012-09-18 2015-08-18 Taiwan Semiconductor Manufacturing Company, Ltd. Bump structure and method of forming same
CN104599978B (zh) * 2014-12-31 2017-08-01 广州兴森快捷电路科技有限公司 一种在倒装芯片基板上小间距之间制备高凸点锡球的制备方法
DE102015105752B4 (de) * 2015-04-15 2021-08-05 OSRAM Opto Semiconductors Gesellschaft mit beschränkter Haftung Halbleiteranordnung mit Reservoir für Markermaterial
JP6744870B2 (ja) * 2015-07-14 2020-08-19 ゴルテック．インク マイクロ発光ダイオードの転写方法、製造方法、マイクロ発光ダイオード装置、及び電子機器
US20170271175A1 (en) * 2016-03-16 2017-09-21 Qualcomm Incorporated Exposed die mold underfill (muf) with fine pitch copper (cu) pillar assembly and bump density
TWI641097B (zh) * 2016-08-12 2018-11-11 南茂科技股份有限公司 半導體封裝
US10050021B1 (en) * 2017-02-16 2018-08-14 Nanya Technology Corporation Die device, semiconductor device and method for making the same
KR102446203B1 (ko) 2017-12-12 2022-09-23 삼성디스플레이 주식회사 구동칩 및 이를 포함하는 표시 장치
TW202042359A (zh) * 2019-05-02 2020-11-16 南茂科技股份有限公司 薄膜覆晶封裝結構
CN112687629B (zh) * 2020-12-25 2024-02-23 上海易卜半导体有限公司 半导体封装方法、半导体组件以及包含其的电子设备

Family Cites Families (134)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3665590A (en) * 1970-01-19 1972-05-30 Ncr Co Semiconductor flip-chip soldering method
JPS54105774A (en) * 1978-02-08 1979-08-20 Hitachi Ltd Method of forming pattern on thin film hybrid integrated circuit
US4813129A (en) 1987-06-19 1989-03-21 Hewlett-Packard Company Interconnect structure for PC boards and integrated circuits
JPH01226160A (ja) 1988-03-07 1989-09-08 Nippon Telegr & Teleph Corp <Ntt> 電子部品接続用の端子装置および端子の製造方法
US5323035A (en) 1992-10-13 1994-06-21 Glenn Leedy Interconnection structure for integrated circuits and method for making same
US4937653A (en) 1988-07-21 1990-06-26 American Telephone And Telegraph Company Semiconductor integrated circuit chip-to-chip interconnection scheme
US5634267A (en) * 1991-06-04 1997-06-03 Micron Technology, Inc. Method and apparatus for manufacturing known good semiconductor die
JPH0797597B2 (ja) 1989-06-02 1995-10-18 松下電器産業株式会社 半導体装置
JPH0429338A (ja) * 1990-05-24 1992-01-31 Nippon Mektron Ltd Ｉｃの搭載用回路基板及びその搭載方法
US5011066A (en) 1990-07-27 1991-04-30 Motorola, Inc. Enhanced collapse solder interconnection
JPH04355933A (ja) 1991-02-07 1992-12-09 Nitto Denko Corp フリツプチツプの実装構造
US5865365A (en) * 1991-02-19 1999-02-02 Hitachi, Ltd. Method of fabricating an electronic circuit device
US5686317A (en) * 1991-06-04 1997-11-11 Micron Technology, Inc. Method for forming an interconnect having a penetration limited contact structure for establishing a temporary electrical connection with a semiconductor die
JP3225062B2 (ja) * 1991-08-05 2001-11-05 ローム株式会社 熱硬化性樹脂シート及びそれを用いた半導体素子の実装方法
US5219117A (en) * 1991-11-01 1993-06-15 Motorola, Inc. Method of transferring solder balls onto a semiconductor device
JP2678958B2 (ja) * 1992-03-02 1997-11-19 カシオ計算機株式会社 フィルム配線基板およびその製造方法
US5314651A (en) * 1992-05-29 1994-05-24 Texas Instruments Incorporated Fine-grain pyroelectric detector material and method
JP3086081B2 (ja) 1992-08-20 2000-09-11 日本特殊陶業株式会社 配線基板とその製造方法
US5346857A (en) * 1992-09-28 1994-09-13 Motorola, Inc. Method for forming a flip-chip bond from a gold-tin eutectic
JP2518508B2 (ja) 1993-04-14 1996-07-24 日本電気株式会社 半導体装置
US5386624A (en) * 1993-07-06 1995-02-07 Motorola, Inc. Method for underencapsulating components on circuit supporting substrates
US5326428A (en) 1993-09-03 1994-07-05 Micron Semiconductor, Inc. Method for testing semiconductor circuitry for operability and method of forming apparatus for testing semiconductor circuitry for operability
US5592736A (en) * 1993-09-03 1997-01-14 Micron Technology, Inc. Fabricating an interconnect for testing unpackaged semiconductor dice having raised bond pads
JP3283977B2 (ja) 1993-10-18 2002-05-20 三菱電機株式会社 半導体装置およびその製造方法
JPH07122846A (ja) 1993-10-21 1995-05-12 Advantest Corp 微小表面実装部品のハンダ付け方法
US5508561A (en) * 1993-11-15 1996-04-16 Nec Corporation Apparatus for forming a double-bump structure used for flip-chip mounting
JPH07142488A (ja) 1993-11-15 1995-06-02 Nec Corp バンプ構造及びその製造方法並びにフリップチップ実装 構造
US6835898B2 (en) * 1993-11-16 2004-12-28 Formfactor, Inc. Electrical contact structures formed by configuring a flexible wire to have a springable shape and overcoating the wire with at least one layer of a resilient conductive material, methods of mounting the contact structures to electronic components, and applications for employing the contact structures
JPH07201917A (ja) 1993-12-28 1995-08-04 Matsushita Electric Ind Co Ltd 回路形成基板とその製造方法
JP2664878B2 (ja) * 1994-01-31 1997-10-22 インターナショナル・ビジネス・マシーンズ・コーポレイション 半導体チップパッケージおよびその製造方法
JP2830734B2 (ja) 1994-04-04 1998-12-02 松下電器産業株式会社 配線基板とその製造方法
US5802699A (en) * 1994-06-07 1998-09-08 Tessera, Inc. Methods of assembling microelectronic assembly with socket for engaging bump leads
US5519580A (en) * 1994-09-09 1996-05-21 Intel Corporation Method of controlling solder ball size of BGA IC components
FR2726397B1 (fr) * 1994-10-28 1996-11-22 Commissariat Energie Atomique Film conducteur anisotrope pour la microconnectique
DE19524739A1 (de) * 1994-11-17 1996-05-23 Fraunhofer Ges Forschung Kernmetall-Lothöcker für die Flip-Chip-Technik
JP3353508B2 (ja) * 1994-12-20 2002-12-03 ソニー株式会社 プリント配線板とこれを用いた電子装置
JPH08236654A (ja) * 1995-02-23 1996-09-13 Matsushita Electric Ind Co Ltd チップキャリアとその製造方法
JP3209875B2 (ja) * 1995-03-23 2001-09-17 株式会社日立製作所 基板の製造方法及び基板
JP2796070B2 (ja) * 1995-04-28 1998-09-10 松下電器産業株式会社 プローブカードの製造方法
US5650595A (en) * 1995-05-25 1997-07-22 International Business Machines Corporation Electronic module with multiple solder dams in soldermask window
US5874780A (en) * 1995-07-27 1999-02-23 Nec Corporation Method of mounting a semiconductor device to a substrate and a mounted structure
JP2770821B2 (ja) 1995-07-27 1998-07-02 日本電気株式会社 半導体装置の実装方法および実装構造
DE19527661C2 (de) * 1995-07-28 1998-02-19 Optrex Europ Gmbh Elektrische Leiter aufweisender Träger mit einem elektronischen Bauteil und Verfahen zum Kontaktieren von Leitern eines Substrates mit Kontaktwarzen eines elektronischen Bauteils
US5872051A (en) * 1995-08-02 1999-02-16 International Business Machines Corporation Process for transferring material to semiconductor chip conductive pads using a transfer substrate
DE69622412T2 (de) * 1995-08-29 2003-03-20 Minnesota Mining & Mfg Verfahren zur herstellung einer elektronischen anordnung mit klebeverbindung mittels eines nachgiebigen substrats
US5710071A (en) * 1995-12-04 1998-01-20 Motorola, Inc. Process for underfilling a flip-chip semiconductor device
KR0182073B1 (ko) * 1995-12-22 1999-03-20 황인길 반도체 칩 스케일 반도체 패키지 및 그 제조방법
JP3558459B2 (ja) 1996-02-08 2004-08-25 沖電気工業株式会社 インナーリード接続方法
US5889326A (en) * 1996-02-27 1999-03-30 Nec Corporation Structure for bonding semiconductor device to substrate
JPH09237802A (ja) 1996-02-28 1997-09-09 Fujitsu Ltd 電子部品
JPH09260552A (ja) * 1996-03-22 1997-10-03 Nec Corp 半導体チップの実装構造
KR100216839B1 (ko) * 1996-04-01 1999-09-01 김규현 Bga 반도체 패키지의 솔더 볼 랜드 메탈 구조
US5940729A (en) * 1996-04-17 1999-08-17 International Business Machines Corp. Method of planarizing a curved substrate and resulting structure
JP2828021B2 (ja) * 1996-04-22 1998-11-25 日本電気株式会社 ベアチップ実装構造及び製造方法
US5755909A (en) * 1996-06-26 1998-05-26 Spectra, Inc. Electroding of ceramic piezoelectric transducers
JP2870497B2 (ja) 1996-08-01 1999-03-17 日本電気株式会社 半導体素子の実装方法
JPH1098075A (ja) 1996-09-20 1998-04-14 Toshiba Corp 半導体実装方法、半導体実装装置および半導体実装構造
US5729896A (en) * 1996-10-31 1998-03-24 International Business Machines Corporation Method for attaching a flip chip on flexible circuit carrier using chip with metallic cap on solder
US5796590A (en) 1996-11-05 1998-08-18 Micron Electronics, Inc. Assembly aid for mounting packaged integrated circuit devices to printed circuit boards
JP2924830B2 (ja) * 1996-11-15 1999-07-26 日本電気株式会社 半導体装置及びその製造方法
US5952840A (en) * 1996-12-31 1999-09-14 Micron Technology, Inc. Apparatus for testing semiconductor wafers
US5931371A (en) * 1997-01-16 1999-08-03 Ford Motor Company Standoff controlled interconnection
JPH10233413A (ja) * 1997-02-21 1998-09-02 Nec Kansai Ltd 半導体装置およびその製造方法並びに配線基板
JP3500032B2 (ja) 1997-03-13 2004-02-23 日本特殊陶業株式会社 配線基板及びその製造方法
JP3346263B2 (ja) * 1997-04-11 2002-11-18 イビデン株式会社 プリント配線板及びその製造方法
JP3070514B2 (ja) * 1997-04-28 2000-07-31 日本電気株式会社 突起電極を有する半導体装置、半導体装置の実装方法およびその実装構造
JPH10303252A (ja) * 1997-04-28 1998-11-13 Nec Kansai Ltd 半導体装置
DE69835747T2 (de) * 1997-06-26 2007-09-13 Hitachi Chemical Co., Ltd. Substrat zur montage von halbleiterchips
JPH1126919A (ja) * 1997-06-30 1999-01-29 Fuji Photo Film Co Ltd プリント配線板
US6337522B1 (en) * 1997-07-10 2002-01-08 International Business Machines Corporation Structure employing electrically conductive adhesives
US6335571B1 (en) * 1997-07-21 2002-01-01 Miguel Albert Capote Semiconductor flip-chip package and method for the fabrication thereof
DE1025587T1 (de) * 1997-07-21 2001-02-08 Aguila Technologies Inc Halbleiter-flipchippackung und herstellungsverfahren dafür
US5985456A (en) * 1997-07-21 1999-11-16 Miguel Albert Capote Carboxyl-containing polyunsaturated fluxing adhesive for attaching integrated circuits
JP3028791B2 (ja) 1997-08-06 2000-04-04 日本電気株式会社 チップ部品の実装方法
US6121143A (en) * 1997-09-19 2000-09-19 3M Innovative Properties Company Abrasive articles comprising a fluorochemical agent for wafer surface modification
US6448665B1 (en) * 1997-10-15 2002-09-10 Kabushiki Kaisha Toshiba Semiconductor package and manufacturing method thereof
SG71734A1 (en) * 1997-11-21 2000-04-18 Inst Materials Research & Eng Area array stud bump flip chip and assembly process
JP3381593B2 (ja) 1997-12-22 2003-03-04 松下電器産業株式会社 バンプ付電子部品の実装方法
JP3819576B2 (ja) * 1997-12-25 2006-09-13 沖電気工業株式会社 半導体装置及びその製造方法
US6200143B1 (en) 1998-01-09 2001-03-13 Tessera, Inc. Low insertion force connector for microelectronic elements
JPH11204913A (ja) 1998-01-09 1999-07-30 Sony Corp 回路基板及び実装方法並びにプリント配線板
US6037192A (en) * 1998-01-22 2000-03-14 Nortel Networks Corporation Process of assembling an integrated circuit and a terminal substrate using solder reflow and adhesive cure
US6426636B1 (en) * 1998-02-11 2002-07-30 International Business Machines Corporation Wafer probe interface arrangement with nonresilient probe elements and support structure
US5953814A (en) * 1998-02-27 1999-09-21 Delco Electronics Corp. Process for producing flip chip circuit board assembly exhibiting enhanced reliability
US6324754B1 (en) * 1998-03-25 2001-12-04 Tessera, Inc. Method for fabricating microelectronic assemblies
US6329605B1 (en) * 1998-03-26 2001-12-11 Tessera, Inc. Components with conductive solder mask layers
JP2000031204A (ja) 1998-07-07 2000-01-28 Ricoh Co Ltd 半導体パッケージの製造方法
US6189208B1 (en) * 1998-09-11 2001-02-20 Polymer Flip Chip Corp. Flip chip mounting technique
JP2000133672A (ja) * 1998-10-28 2000-05-12 Seiko Epson Corp 半導体装置及びその製造方法、回路基板並びに電子機器
JP3346320B2 (ja) * 1999-02-03 2002-11-18 カシオ計算機株式会社 半導体装置及びその製造方法
SG88747A1 (en) * 1999-03-01 2002-05-21 Motorola Inc A method and machine for underfilling an assembly to form a semiconductor package
US6483195B1 (en) * 1999-03-16 2002-11-19 Sumitomo Bakelite Company Limited Transfer bump street, semiconductor flip chip and method of producing same
US6225206B1 (en) * 1999-05-10 2001-05-01 International Business Machines Corporation Flip chip C4 extension structure and process
US6181569B1 (en) * 1999-06-07 2001-01-30 Kishore K. Chakravorty Low cost chip size package and method of fabricating the same
US6173887B1 (en) * 1999-06-24 2001-01-16 International Business Machines Corporation Method of making electrically conductive contacts on substrates
JP2001068836A (ja) * 1999-08-27 2001-03-16 Mitsubishi Electric Corp プリント配線基板及び半導体モジュール並びに半導体モジュールの製造方法
TW429492B (en) * 1999-10-21 2001-04-11 Siliconware Precision Industries Co Ltd Ball grid array package and its fabricating method
US6815252B2 (en) 2000-03-10 2004-11-09 Chippac, Inc. Method of forming flip chip interconnection structure
JP2001339011A (ja) * 2000-03-24 2001-12-07 Shinko Electric Ind Co Ltd 半導体装置およびその製造方法
WO2001086716A1 (en) * 2000-05-12 2001-11-15 Matsushita Electric Industrial Co., Ltd. Semiconductor device mounting circuit board, method of producing the same, and method of producing mounting structure using the same
US6573610B1 (en) * 2000-06-02 2003-06-03 Siliconware Precision Industries Co., Ltd. Substrate of semiconductor package for flip chip package
US6201305B1 (en) * 2000-06-09 2001-03-13 Amkor Technology, Inc. Making solder ball mounting pads on substrates
JP3554533B2 (ja) * 2000-10-13 2004-08-18 シャープ株式会社 チップオンフィルム用テープおよび半導体装置
JP2002134541A (ja) 2000-10-23 2002-05-10 Citizen Watch Co Ltd 半導体装置とその製造方法ならびに半導体装置の実装構造
US6818545B2 (en) * 2001-03-05 2004-11-16 Megic Corporation Low fabrication cost, fine pitch and high reliability solder bump
US7242099B2 (en) * 2001-03-05 2007-07-10 Megica Corporation Chip package with multiple chips connected by bumps
US8158508B2 (en) * 2001-03-05 2012-04-17 Megica Corporation Structure and manufacturing method of a chip scale package
US6808958B2 (en) * 2001-03-07 2004-10-26 Tessera, Inc. Methods of bonding microelectronic elements
US6893901B2 (en) * 2001-05-14 2005-05-17 Fairchild Semiconductor Corporation Carrier with metal bumps for semiconductor die packages
JP4663165B2 (ja) * 2001-06-27 2011-03-30 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
JP3787295B2 (ja) 2001-10-23 2006-06-21 ローム株式会社 半導体装置
TW507341B (en) * 2001-11-01 2002-10-21 Siliconware Precision Industries Co Ltd Substrate capable of preventing delamination of chip and semiconductor encapsulation having such a substrate
US6952047B2 (en) * 2002-07-01 2005-10-04 Tessera, Inc. Assemblies having stacked semiconductor chips and methods of making same
US6969914B2 (en) * 2002-08-29 2005-11-29 Micron Technology, Inc. Electronic device package
JP4114483B2 (ja) 2003-01-10 2008-07-09 セイコーエプソン株式会社 半導体チップの実装方法、半導体実装基板、電子デバイスおよび電子機器
US7271497B2 (en) 2003-03-10 2007-09-18 Fairchild Semiconductor Corporation Dual metal stud bumping for flip chip applications
US7005751B2 (en) * 2003-04-10 2006-02-28 Formfactor, Inc. Layered microelectronic contact and method for fabricating same
US7758351B2 (en) * 2003-04-11 2010-07-20 Neoconix, Inc. Method and system for batch manufacturing of spring elements
TWI225701B (en) * 2003-09-17 2004-12-21 Advanced Semiconductor Eng Process for forming bumps in adhesive layer in wafer level package
KR101237172B1 (ko) 2003-11-10 2013-02-25 스태츠 칩팩, 엘티디. 범프-온-리드 플립 칩 인터커넥션
US20070145548A1 (en) * 2003-12-22 2007-06-28 Amkor Technology, Inc. Stack-type semiconductor package and manufacturing method thereof
US7368695B2 (en) * 2004-05-03 2008-05-06 Tessera, Inc. Image sensor package and fabrication method
US7576427B2 (en) * 2004-05-28 2009-08-18 Stellar Micro Devices Cold weld hermetic MEMS package and method of manufacture
WO2006105015A2 (en) 2005-03-25 2006-10-05 Stats Chippac Ltd. Flip chip interconnection having narrow interconnection sites on the substrate
JP2007064841A (ja) 2005-08-31 2007-03-15 Advantest Corp 電子部品試験装置用のキャリブレーションボード
KR100691443B1 (ko) 2005-11-16 2007-03-09 삼성전기주식회사 플립칩 패키지 및 그 제조방법
JP2007214230A (ja) 2006-02-08 2007-08-23 Cmk Corp プリント配線板
US7829998B2 (en) 2007-05-04 2010-11-09 Stats Chippac, Ltd. Semiconductor wafer having through-hole vias on saw streets with backside redistribution layer
WO2009001621A1 (ja) * 2007-06-26 2008-12-31 Murata Manufacturing Co., Ltd. 部品内蔵基板の製造方法
JP5550102B2 (ja) 2008-01-17 2014-07-16 株式会社村田製作所 電子部品
JP2009177061A (ja) * 2008-01-28 2009-08-06 Nec Electronics Corp 半導体装置及び半導体装置の製造方法
JP2010141055A (ja) 2008-12-10 2010-06-24 Sanyo Electric Co Ltd 半導体モジュール、半導体モジュールの製造方法および携帯機器
US8338945B2 (en) * 2010-10-26 2012-12-25 Taiwan Semiconductor Manufacturing Company, Ltd. Molded chip interposer structure and methods
US9599665B2 (en) 2013-05-21 2017-03-21 Advantest Corporation Low overdrive probes with high overdrive substrate

Also Published As

Publication number Publication date
TW201225193A (en) 2012-06-16
JP5952523B2 (ja) 2016-07-13
KR20120052844A (ko) 2012-05-24
KR101785729B1 (ko) 2017-11-06
CN102468197B (zh) 2017-04-26
JP2012109507A (ja) 2012-06-07
US10388626B2 (en) 2019-08-20
CN102468197A (zh) 2012-05-23
US20120241945A9 (en) 2012-09-27
SG10201809052TA (en) 2018-11-29
US20110074022A1 (en) 2011-03-31
SG10201402214VA (en) 2014-09-26
SG181205A1 (en) 2012-06-28

Similar Documents

Publication Publication Date Title
TWI541916B (zh) 形成覆晶互連結構的半導體裝置和方法
US9899286B2 (en) Semiconductor device and method of self-confinement of conductive bump material during reflow without solder mask
US9679811B2 (en) Semiconductor device and method of confining conductive bump material with solder mask patch
US8877567B2 (en) Semiconductor device and method of forming uniform height insulating layer over interposer frame as standoff for semiconductor die
US9345148B2 (en) Semiconductor device and method of forming flipchip interconnection structure with bump on partial pad
US9385101B2 (en) Semiconductor device and method of forming bump-on-lead interconnection
US9418913B2 (en) Semiconductor device and method of forming insulating layer on conductive traces for electrical isolation in fine pitch bonding
US8741766B2 (en) Semiconductor device and method of confining conductive bump material during reflow with solder mask patch
US9258904B2 (en) Semiconductor device and method of forming narrow interconnect sites on substrate with elongated mask openings
KR101979024B1 (ko) 반도체 소자 및 그 제조 방법
KR20120064601A (ko) 반도체 소자 및 그 제조 방법