TWI535022B - Manufacturing method of high voltage device - Google Patents
Manufacturing method of high voltage device Download PDFInfo
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- TWI535022B TWI535022B TW103121653A TW103121653A TWI535022B TW I535022 B TWI535022 B TW I535022B TW 103121653 A TW103121653 A TW 103121653A TW 103121653 A TW103121653 A TW 103121653A TW I535022 B TWI535022 B TW I535022B
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Description
本發明係有關一種高壓元件製造方法，特別是指一種增強崩潰防護電壓之高壓元件製造方法。 The present invention relates to a method of manufacturing a high voltage component, and more particularly to a method of manufacturing a high voltage component that enhances a breakdown protection voltage.
第1圖顯示先前技術之橫向雙擴散金屬氧化物半導體(lateral double diffused metal oxide semiconductor,LDMOS)元件剖視圖。如第1圖所示，P型基板11中具有複數絕緣區12，以定義元件區100，絕緣區12例如為淺溝槽絕緣(shallow trench isolation,STI)結構或如圖所示之區域氧化(local oxidation of silicon,LOCOS)結構；P型基板11還包含N型埋層14。LDMOS元件形成於元件區100中，除N型埋層14外，還包含閘極13、汲極15、源極16、P型井區17、以及N型井區18。其中，N型埋層14、汲極15、源極16、以及N型井區18係由微影技術或以部分或全部之閘極13、絕緣區12為遮罩，以定義各區域，並分別以離子植入技術，將N型雜質，以加速離子的形式，植入定義的區域內所形成；而P型井區17則是由微影技術，定義該區域，並以離子植入技術，將P型雜質，以加速離子的形式，植入定義的區域內所形成。其中，汲極15與源極16分別位於閘極13兩側下方。而且LDMOS元件中，閘極13有一部分位於場氧化區22上。 Figure 1 shows a cross-sectional view of a prior art lateral double diffused metal oxide semiconductor (LDMOS) device. As shown in FIG. 1, the P-type substrate 11 has a plurality of insulating regions 12 therein to define an element region 100, such as a shallow trench isolation (STI) structure or an area oxidation as shown in the figure ( The local oxidation of silicon (LOCOS) structure; the P-type substrate 11 further includes an N-type buried layer 14. The LDMOS device is formed in the element region 100, and includes a gate 13, a drain 15, a source 16, a P-type well region 17, and an N-type well region 18 in addition to the N-type buried layer 14. Wherein, the N-type buried layer 14, the drain 15, the source 16, and the N-well 18 are masked by lithography or with some or all of the gate 13 and the insulating region 12 to define regions, and The ion implantation technique is used to implant N-type impurities into the defined region in the form of accelerated ions. The P-type well region 17 is defined by lithography, and the region is defined by ion implantation. P-type impurities are formed in the form of accelerated ions implanted in defined regions. The drain 15 and the source 16 are respectively located below the two sides of the gate 13 . Also, in the LDMOS device, a portion of the gate 13 is located on the field oxide region 22.
第2圖顯示先前技術之雙擴散汲極金屬氧化物半導體(double diffused drain metal oxide semiconductor,DDDMOS)元件剖視圖。與前述LDMOS元件不同的是，DDDMOS元件之閘極13a並非有一部分位於場氧化區22上，而是完全位於P型基板11表面上。 Figure 2 is a cross-sectional view showing a prior art double diffused drain metal oxide semiconductor (DDDMOS) device. Unlike the aforementioned LDMOS device, the gate 13a of the DDDMOS device is not partially located on the field oxide region 22, but is entirely on the surface of the P-type substrate 11.
LDMOS與DDDMOS元件為高壓元件，亦即其係設計供應用於較高的操作電壓，但當高壓元件需要與一般較低操作電壓之元件整合於同一基板上時，為配合較低操作電壓之元件製程，需要以相同的離子植入參數來製作高壓元件和低壓元件，使得高壓元件的離子植入參數受到限制，因而降低了高壓元件崩潰防護電壓，限制了元件的應用範圍。若不犧牲高壓元件崩潰防護電壓，則必須增加製程步驟，另行以不同離子植入參數的步驟來製作高壓元件，但如此一來將提高製造成本，才能達到所欲的崩潰防護電壓。 The LDMOS and DDDMOS components are high voltage components, that is, they are designed to supply higher operating voltages, but when the high voltage components need to be integrated on the same substrate as the generally lower operating voltage components, they are used for components with lower operating voltage. The process requires high-voltage components and low-voltage components to be fabricated with the same ion implantation parameters, so that the ion implantation parameters of the high-voltage components are limited, thereby reducing the breakdown voltage of the high-voltage components and limiting the application range of the components. If the high voltage component collapse protection voltage is not sacrificed, the process step must be added, and the high voltage component is separately fabricated by the steps of different ion implantation parameters, but this will increase the manufacturing cost to achieve the desired collapse protection voltage.
有鑑於此，本發明即針對上述先前技術之不足，提出一種高壓元件製造方法，在不增加製程步驟的情況下，提高元件操作之崩潰防護電壓，增加元件的應用範圍，並可整合於低壓元件之製程。 In view of the above, the present invention is directed to the deficiencies of the prior art described above, and provides a method for manufacturing a high voltage component, which improves the breakdown protection voltage of the component operation, increases the application range of the component, and can be integrated into the low voltage component without increasing the process steps. Process.
本發明目的在提供一種高壓元件及其製造方法。 It is an object of the present invention to provide a high voltage component and a method of manufacturing the same.
為達上述之目的，本發明提供了一種高壓元件，形成於一第一導電型基板中，該第一導電型基板具有一基板上表面，該高壓元件包含：一第二導電型埋層，形成於該第一導電型基板中；一第一導電型井區，形成於該基板上表面下方，且由剖視圖視之，該第一導電型井區介於該基板上表面與該第二導電型埋層之間；以及一第二導電型井區，形成於該基板上表面下方，且該第二導電型井區與該第一導電型井區在水平方向上位於不同位置並相鄰接，其中，該第二導電型井區包括一井區下表面，且該井區下表面具有第一部分與第二部分，該第一部分位於該第二導電型埋層上方，並與該第二導電型埋層電性耦接，且該第二部分不在該第二導電型埋層上方，並與該第一導電型基板形成PN接面。 In order to achieve the above object, the present invention provides a high voltage component formed in a first conductivity type substrate having a substrate upper surface, the high voltage component comprising: a second conductivity type buried layer formed In the first conductive type substrate, a first conductive type well region is formed under the upper surface of the substrate, and the first conductive type well region is interposed between the upper surface of the substrate and the second conductive type. Between the buried layers; and a second conductive type well region formed under the upper surface of the substrate, and the second conductive type well region and the first conductive type well region are located at different positions in the horizontal direction and adjacent to each other, Wherein the second conductive type well region includes a lower surface of the well region, and the lower surface of the well region has a first portion and a second portion, the first portion is located above the second conductive type buried layer, and the second conductive type The buried layer is electrically coupled, and the second portion is not above the second conductive type buried layer, and forms a PN junction with the first conductive type substrate.
就另一觀點，本發明也提供了一種高壓元件製造方法，包含：提供一第一導電型基板，其具有一基板上表面；形成一第二導電型埋 層於該第一導電型基板中；形成一第一導電型井區於該基板上表面下方，且由剖視圖視之，該第一導電型井區介於該基板上表面與該第二導電型埋層之間；以及形成一第二導電型井區於該基板上表面下方，且該第二導電型井區與該第一導電型井區在水平方向上位於不同位置並相鄰接，其中，該第二導電型井區包括一井區下表面，且該井區下表面具有第一部分與第二部分，該第一部分位於該第二導電型埋層上方，並與該第二導電型埋層電性耦接，且該第二部分不在該第二導電型埋層上方，並與該第一導電型基板形成PN接面。 In another aspect, the present invention also provides a method for manufacturing a high voltage component, comprising: providing a first conductive type substrate having a substrate upper surface; forming a second conductive type buried Layered in the first conductive type substrate; forming a first conductive type well region below the upper surface of the substrate, and viewed from a cross-sectional view, the first conductive type well region is interposed between the upper surface of the substrate and the second conductive type Between the buried layers; and forming a second conductive type well region below the upper surface of the substrate, and the second conductive type well region and the first conductive type well region are located at different positions in the horizontal direction and adjacent to each other, wherein The second conductive type well region includes a lower surface of the well region, and the lower surface of the well region has a first portion and a second portion, the first portion is located above the second conductive type buried layer, and is buried with the second conductive type The layer is electrically coupled, and the second portion is not above the buried layer of the second conductive type, and forms a PN junction with the first conductive type substrate.
其中一種較佳的實施例中，該第二導電型井區宜於該高壓元件操作於一不導通狀態時，大致空乏。 In a preferred embodiment, the second conductive well region is substantially depleted when the high voltage component is operated in a non-conducting state.
另一種較佳實施例中，該高壓元件宜更包含一第二導電型漂移區，位於該第二導電型井區中，且在水平方向上定義於該第一導電型井區與一汲極之間，其中當該高壓元件操作於一不導通狀態時，該第二導電型漂移區完全空乏。 In another preferred embodiment, the high voltage component further includes a second conductivity type drift region, located in the second conductivity type well region, and defined in the horizontal direction in the first conductivity type well region and a drain electrode Between the two conductive type drift regions is completely depleted when the high voltage device operates in a non-conducting state.
又一種較佳實施例中，該高壓元件係一橫向雙擴散金屬氧化物半導體(lateral double diffused metal oxide semiconductor,LDMOS)元件或雙擴散汲極金屬氧化物半導體(double diffused drain metal oxide semiconductor,DDDMOS)元件。 In another preferred embodiment, the high voltage component is a lateral double diffused metal oxide semiconductor (LDMOS) device or a double diffused drain metal oxide semiconductor (DDDMOS). element.
再又一種較佳實施例中，該第一導電型基板宜包括一第一導電型裸基板、一第一導電型埋層、或一第一導電型磊晶層；其中該第一導電型埋層由離子植入製程步驟植入第一導電型雜質所形成，且該第一導電型磊晶層由磊晶技術所形成。 In a further preferred embodiment, the first conductive type substrate preferably includes a first conductive type bare substrate, a first conductive type buried layer, or a first conductive type epitaxial layer; wherein the first conductive type is buried The layer is formed by implanting a first conductivity type impurity by an ion implantation process step, and the first conductivity type epitaxial layer is formed by an epitaxial technique.
底下藉由具體實施例詳加說明，當更容易瞭解本發明之目的、技術內容、特點及其所達成之功效。 The purpose, technical content, features and effects achieved by the present invention will be more readily understood by the detailed description of the embodiments.
11‧‧‧基板 11‧‧‧Substrate
12‧‧‧絕緣區 12‧‧‧Insulated area
13,13a‧‧‧閘極 13,13a‧‧‧ gate
14‧‧‧N型埋層 14‧‧‧N type buried layer
14a‧‧‧光阻 14a‧‧‧Light resistance
15‧‧‧汲極 15‧‧‧汲polar
16‧‧‧源極 16‧‧‧ source
17‧‧‧P型井區 17‧‧‧P type well area
18‧‧‧N型井區 18‧‧‧N type well area
18a‧‧‧第一部分 18a‧‧‧Part 1
18b‧‧‧第二部分 18b‧‧‧Part II
18c‧‧‧漂移區 18c‧‧‧drift zone
22‧‧‧場氧化區 22‧‧‧Field Oxidation Zone
100‧‧‧元件區 100‧‧‧Component area
第1圖顯示先前技術之LDMOS元件剖視圖。 Figure 1 shows a cross-sectional view of a prior art LDMOS device.
第2圖顯示先前技術之DDDMOS元件剖視圖。 Figure 2 shows a cross-sectional view of a prior art DDDMOS device.
第3圖顯示本發明的第一個實施例。 Figure 3 shows a first embodiment of the invention.
第4圖顯示本發明的第二個實施例。 Figure 4 shows a second embodiment of the invention.
第5A圖與第5B圖顯示先前技術與本發明第一個實施例中LDMOS 元件不導通(OFF)狀態時之電場模擬圖的比較。 5A and 5B show prior art and LDMOS in the first embodiment of the present invention Comparison of electric field simulations when the component is not in the OFF state.
第6A-6D圖舉例說明利用本發明之高壓元件的製造方法。 Figures 6A-6D illustrate a method of making a high voltage component utilizing the present invention.
本發明中的圖式均屬示意，主要意在表示製程步驟以及各層之間之上下次序關係，至於形狀、厚度與寬度則並未依照比例繪製。 The drawings in the present invention are schematic and are mainly intended to represent the process steps and the relationship between the layers, and the shapes, thicknesses, and widths are not drawn to scale.
請參閱第3圖，顯示本發明的第一個實施例，本實施例顯示本發明應用於LDMOS元件之剖視示意圖。於基板11中，形成絕緣區12以定義元件區100，其中基板11例如為P型但不限於為P型(在其他實施型態中亦可以為N型)；絕緣區12例如為STI結構或如圖所示之區域氧化LOCOS結構，並且，基板11中，包含導電型與基板11不相同之N型(在其他實施型態中亦可以為P型)埋層14。此外，如第3圖所示，於基板11中，形成P型(在其他實施型態中亦可以為N型)井區17與N型(在其他實施型態中亦可以為P型)井區18。其中，P型井區17介於基板11上表面與N型埋層14之間；N型井區18形成於基板11上表面下方，且N型井區與P型井區在水平方向上位於不同位置並相鄰接。於基板11表面，元件區100中，以氧化技術於該基板11表面上形成場氧化區22，其例如為STI結構或區域氧化LOCOS結構；並且，場氧化區22可利用但不限於與絕緣區12相同製程步驟形成。接著於元件區100中，形成閘極13、汲極15、與源極16；其中，汲極15與源極16例如為N 型但不限於為N型(在其他實施型態中亦可以為P型)，分別位於元件區100中之閘極13兩側，且由上視圖(未示出)視之，汲極15與源極16由閘極13與場氧化區22隔開。 Referring to Figure 3, there is shown a first embodiment of the present invention. This embodiment shows a schematic cross-sectional view of the present invention applied to an LDMOS device. In the substrate 11, an insulating region 12 is formed to define an element region 100, wherein the substrate 11 is, for example, P-type but not limited to being P-type (it may also be N-type in other embodiments); the insulating region 12 is, for example, an STI structure or The region shown in the figure oxidizes the LOCOS structure, and the substrate 11 includes a buried layer 14 of an N-type (which may also be a P-type in other embodiments) whose conductivity type is different from that of the substrate 11. Further, as shown in FIG. 3, in the substrate 11, a P-type (N-type in other embodiments may be used) well 17 and an N-type (P-type in other embodiments) may be formed. District 18. Wherein, the P-type well region 17 is interposed between the upper surface of the substrate 11 and the N-type buried layer 14; the N-type well region 18 is formed below the upper surface of the substrate 11, and the N-type well region and the P-type well region are located horizontally Different locations and adjacent. On the surface of the substrate 11, in the element region 100, a field oxide region 22 is formed on the surface of the substrate 11 by an oxidation technique, which is, for example, an STI structure or a region oxide LOCOS structure; and the field oxide region 22 can utilize, but is not limited to, an insulating region. 12 identical process steps are formed. Next, in the element region 100, a gate 13, a drain 15 and a source 16 are formed; wherein the drain 15 and the source 16 are, for example, N Type, but not limited to, N-type (P-type in other embodiments), respectively located on both sides of the gate 13 in the element region 100, and viewed from the top view (not shown), the drain 15 and Source 16 is separated from field oxide region 22 by gate 13.
與先前技術不同的是，在本實施例中，N型井區18之下表面具有第一部分18a與第二部分18b，由橢圓形虛線所示意，其中第一部分18a位於N型埋層14上方，並與N型埋層電性耦接，且第二部分18b不在N型埋層14上方，並與P型基板11形成PN接面。 Different from the prior art, in the present embodiment, the lower surface of the N-type well region 18 has a first portion 18a and a second portion 18b, which are indicated by an elliptical dotted line, wherein the first portion 18a is located above the N-type buried layer 14, And electrically coupled to the N-type buried layer, and the second portion 18b is not above the N-type buried layer 14, and forms a PN junction with the P-type substrate 11.
此種安排方式的優點包括：在元件規格上，可提高高壓元件的崩潰防護電壓，其原因將詳述於後；在製程上，可以但不限於利用形成N型埋層14之製程與光罩，於離子植入製程步驟時，將第二部分18b下方以光阻或其他遮罩遮住，阻擋加速離子植入第二部分18b下方，而不需要另外新增光罩或製程步驟，故可降低製造成本。 The advantages of this arrangement include: in the component specification, the collapse protection voltage of the high voltage component can be increased, the reason will be described later; in the process, the process and the mask for forming the N-type buried layer 14 can be used, but not limited to In the ion implantation process step, the second portion 18b is covered by a photoresist or other mask to block the accelerated ion implantation under the second portion 18b without additional mask or process steps. Reduce manufacturing costs.
第4圖顯示本發明的第二個實施例。與第一個實施例不同的是，本實施例係應用本發明於DDDMOS元件而非LDMOS元件。DDDMOS元件之閘極13a並非有一部分位於場氧化區22上，而是完全位於P型基板11表面上。 Figure 4 shows a second embodiment of the invention. Unlike the first embodiment, this embodiment applies the present invention to a DDDMOS device instead of an LDMOS device. The gate 13a of the DDDMOS device is not partially located on the field oxide region 22, but is entirely on the surface of the P-type substrate 11.
第5A圖與第5B圖顯示先前技術與本發明第一個實施例中LDMOS元件不導通(OFF)狀態時之電場模擬圖的比較。並進而說明如何利用本發明增強高壓元件之崩潰防護電壓。請參閱電場模擬圖第5A圖，顯示先前技術之LDMOS元件不導通狀態時之電場模擬圖。以N型LDMOS元件為例，操作於不導通狀態時，閘極13電壓例如為零電位，而P型井區17與N型埋層14間、P型井區17與N型井區18間、以及N型井區18與P型基板11間之PN接面皆為逆向偏壓，因而存在寬度不同之空乏區，如第5A圖中之電場線所示意，而無電場線分佈的區域，則代表其為零電位。 Fig. 5A and Fig. 5B show a comparison of the electric field simulation maps of the prior art and the LDMOS device in the non-conducting (OFF) state in the first embodiment of the present invention. Furthermore, it is explained how to use the present invention to enhance the collapse protection voltage of the high voltage component. Please refer to Figure 5A of the electric field simulation diagram to show the electric field simulation of the prior art LDMOS device in a non-conducting state. Taking an N-type LDMOS device as an example, when operating in a non-conducting state, the gate 13 voltage is, for example, zero potential, and between the P-type well region 17 and the N-type buried layer 14, between the P-type well region 17 and the N-type well region 18 And the PN junction between the N-type well region 18 and the P-type substrate 11 are reverse biased, so that there are depletion regions having different widths, as indicated by the electric field lines in FIG. 5A, and no electric field lines are distributed, It represents its zero potential.
請繼續參閱第5B圖，顯示本發明第一個實施例中LDMOS 元件不導通(OFF)狀態時之電場模擬圖。與第5A圖所示之先前技術不同的是，由於N型井區18下表面具有第一部分18a與N型埋層14耦接，以及第二部分18b與P型基板11耦接，此第二部分18b與P型基板11間，於LDMOS元件不導通時，形成逆向偏壓狀態的PN接面。由圖中電場線的分布狀況可以推知，N型井區18大致上因三個PN接面(P型井區17與N型井區18間、以及N型井區18的側表面和下表面中的第二部分18b與P型基板11間)的逆向偏壓狀態而完全空乏。 Please refer to FIG. 5B to show the LDMOS in the first embodiment of the present invention. The electric field simulation of the component when it is not in the OFF state. Different from the prior art shown in FIG. 5A, since the lower surface of the N-type well region 18 has the first portion 18a coupled to the N-type buried layer 14, and the second portion 18b is coupled to the P-type substrate 11, the second portion Between the portion 18b and the P-type substrate 11, when the LDMOS device is not turned on, a PN junction in a reverse bias state is formed. It can be inferred from the distribution of the electric field lines in the figure that the N-type well region 18 is substantially due to three PN junctions (the side surface and the lower surface of the P-type well region 17 and the N-type well region 18, and the N-type well region 18). The reverse bias state between the second portion 18b and the P-type substrate 11 is completely depleted.
比較第5A與第5B圖，可以看出利用本發明的第5B圖相較於先前技術第5A圖，於高壓元件不導通時，其N型井區18大致上完全空乏。因此，其可承受的操作電壓較高，也就是其崩潰防護電壓較高。這舉例說明了本發明可提高高壓元件的崩潰防護電壓的優點。其中，第5B圖中，矩形需線標示出N型漂移區18c，其位於N型井區18中，可以但不限於由形成N型井區18相同的製程步驟完成，且在水平方向上定義於P井區17與汲極15之間，其中當高壓元件操作於不導通狀態時，N型漂移區18c完全空乏，以加強高壓元件之崩潰防護電壓。需說明的是，N型漂移區18c為高壓元件於導通(ON)狀態時電流所經過的區域，且緊接汲極15所耦接之高電壓之操作電壓，因此，是最容易發生崩潰的區域。 Comparing Figures 5A and 5B, it can be seen that with Figure 5B of the present invention, the N-type well region 18 is substantially completely depleted when the high voltage component is not conducting, as compared to prior art Figure 5A. Therefore, it can withstand higher operating voltages, that is, its collapse protection voltage is higher. This exemplifies the advantage of the present invention to increase the collapse protection voltage of the high voltage component. Wherein, in FIG. 5B, the rectangular line needs to indicate the N-type drift region 18c, which is located in the N-type well region 18, and may be, but is not limited to, the same process steps as forming the N-type well region 18, and is defined in the horizontal direction. Between the P well region 17 and the drain 15, wherein the N-type drift region 18c is completely depleted when the high voltage component is operated in a non-conducting state to enhance the collapse protection voltage of the high voltage component. It should be noted that the N-type drift region 18c is the region where the current passes when the high-voltage device is in the ON state, and is close to the operating voltage of the high voltage to which the drain electrode 15 is coupled, and therefore, is the most prone to collapse. region.
第6A-6D圖舉例說明利用本發明之高壓元件的製造方法。如第6A圖所示，首先提供例如但不限於P型基板11(在其他實施型態中亦可以為N型)，其具有基板上表面；接著於P型基板11中，如圖所示利用光阻14a或其他遮罩遮住，阻擋如虛線箭頭所示意之N型雜質加速離子植入P型基板11中，以形成N型埋層14。 Figures 6A-6D illustrate a method of making a high voltage component utilizing the present invention. As shown in FIG. 6A, first, for example, but not limited to, a P-type substrate 11 (which may also be an N-type in other embodiments) having a substrate upper surface; and then in the P-type substrate 11, as utilized in the drawing The photoresist 14a or other mask is shielded from blocking the N-type impurity as indicated by the dashed arrow to accelerate ion implantation into the P-type substrate 11 to form the N-type buried layer 14.
接下來，如第6B圖所示，分別利用光阻或其他遮罩定義P型井區17與N型井區18，並分別以P型與N型雜質之加速離子，形成P型井區17與N型井區18。其中，由剖視圖第6B圖視之，P型井區 17介於基板11上表面與N型埋層14之間，且N型井區18於基板11上表面下方，且N型井區18與P型井區17在水平方向上位於不同位置並相鄰接。 Next, as shown in FIG. 6B, the P-type well region 17 and the N-type well region 18 are respectively defined by photoresists or other masks, and the P-type well regions 17 are formed by accelerating ions of P-type and N-type impurities, respectively. With the N-type well area 18. Among them, as shown in section 6B of the cross-sectional view, the P-type well area 17 is between the upper surface of the substrate 11 and the N-type buried layer 14, and the N-type well region 18 is below the upper surface of the substrate 11, and the N-type well region 18 and the P-type well region 17 are located at different positions in the horizontal direction and phase Adjacent.
再接下來，如第6C圖所示，於基板11中，形成絕緣區12以定義元件區100，並例如但不限於利用同樣的製程步驟，形成場氧化區22。其中，N井區18包括井區下表面，且該井區下表面具有第一部分18a與第二部分18b，第一部分18a位於N型埋層14上方，並與N型埋層14電性耦接，且第二部分18b不在N型埋層14上方，並與P型基板11形成PN接面。 Next, as shown in FIG. 6C, in the substrate 11, an insulating region 12 is formed to define the element region 100, and the field oxide region 22 is formed, for example, but not limited to, by the same process steps. The N-well region 18 includes a lower surface of the well region, and the lower surface of the well region has a first portion 18a and a second portion 18b. The first portion 18a is located above the N-type buried layer 14 and is electrically coupled to the N-type buried layer 14. And the second portion 18b is not above the N-type buried layer 14, and forms a PN junction with the P-type substrate 11.
最後請參閱第6D圖，於元件區100中，形成閘極13、汲極15、與源極16；其中，汲極15與源極16例如為N型但不限於為N型(在其他實施型態中亦可以為P型)，分別位於元件區100中之閘極13兩側，且由上視圖(未示出)視之，汲極15與源極16由閘極13與場氧化區22隔開。 Finally, referring to FIG. 6D, in the element region 100, the gate 13, the drain 15 and the source 16 are formed; wherein the drain 15 and the source 16 are, for example, N-type but not limited to N-type (in other implementations) The type may also be P-type), respectively located on both sides of the gate 13 in the element region 100, and viewed from the top view (not shown), the drain 15 and the source 16 are separated by the gate 13 and the field oxide region. 22 separated.
需說明的是，P型基板11例如可為P型裸基板，也就是直接利用P型晶圓作為P型基板11；P型基板11亦可以為P型埋層，例如但不限於以離子植入技術來形成；或是，P型基板11亦可以為P型磊晶層，由磊晶技術所形成。 It should be noted that the P-type substrate 11 can be, for example, a P-type bare substrate, that is, a P-type wafer is directly used as the P-type substrate 11; and the P-type substrate 11 can also be a P-type buried layer, such as but not limited to ion implantation. The technology can be formed; or the P-type substrate 11 can also be a P-type epitaxial layer formed by epitaxial technology.
以上已針對較佳實施例來說明本發明，唯以上所述者，僅係為使熟悉本技術者易於了解本發明的內容而已，並非用來限定本發明之權利範圍。在本發明之相同精神下，熟悉本技術者可以思及各種等效變化。例如，在不影響元件主要的特性下，可加入其他製程步驟或結構，如深井區等；又如，微影技術並不限於光罩技術，亦可包含電子束微影技術；再如，所示之電場模擬圖為其中一種實施例之模擬結果，亦可以不需將N型井區完全空乏而僅有部分空乏，只要相較於先前技術，具有增強之崩潰防護電壓即可。本發明的範圍應涵蓋上述及其他所有等 效變化。 The present invention has been described with reference to the preferred embodiments thereof, and the present invention is not intended to limit the scope of the present invention. In the same spirit of the invention, various equivalent changes can be conceived by those skilled in the art. For example, other process steps or structures, such as deep well areas, may be added without affecting the main characteristics of the components; for example, lithography is not limited to reticle technology, and may include electron beam lithography; The electric field simulation diagram shown is a simulation result of one of the embodiments, and it is also possible to eliminate the N-type well region from being completely depleted and only partially depleted, as long as it has an enhanced collapse protection voltage compared to the prior art. The scope of the invention should cover the above and all other Effect changes.
11‧‧‧基板 11‧‧‧Substrate
12‧‧‧絕緣區 12‧‧‧Insulated area
13‧‧‧閘極 13‧‧‧ gate
14‧‧‧N型埋層 14‧‧‧N type buried layer
15‧‧‧汲極 15‧‧‧汲polar
16‧‧‧源極 16‧‧‧ source
17‧‧‧P型井區 17‧‧‧P type well area
18‧‧‧N型井區 18‧‧‧N type well area
18a‧‧‧第一部分 18a‧‧‧Part 1
18b‧‧‧第二部分 18b‧‧‧Part II
22‧‧‧場氧化區 22‧‧‧Field Oxidation Zone
100‧‧‧元件區 100‧‧‧Component area
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