TWI440181B - High voltage metal oxide semiconductor device and method for making same - Google Patents
High voltage metal oxide semiconductor device and method for making same Download PDFInfo
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Description
本發明係有關一種高壓金屬氧化物半導體元件,特別是指一種定義P型摻雜區範圍,以加強元件崩潰防護電壓(breakdown voltage)之N型高壓金屬氧化物半導體元件,或降低元件導通阻值(ON resistance)之P型該高壓金屬氧化物半導體元件。本發明也有關於一種高壓金屬氧化物半導體元件的製作方法。The present invention relates to a high voltage metal oxide semiconductor device, and more particularly to an N-type high voltage metal oxide semiconductor device which defines a P-type doping region range to enhance a breakdown voltage of a device, or reduces the conduction resistance of the device. (ON resistance) P-type high voltage metal oxide semiconductor device. The invention also relates to a method of fabricating a high voltage metal oxide semiconductor device.
金屬氧化物半導體元件源極與汲極間的崩潰防護電壓取決於源極與汲極間的PN接面。舉例而言,突崩潰(avalanche breakdown)的發生肇因於PN接面空乏區電場的升高,因此也限制了源極與汲極所能施加的電壓。若崩潰發生於源極與汲極間的PN接面,會使源極與汲極間的電流急速升高,且造成PN接面的損壞以及MOS元件的功能失常。The breakdown protection voltage between the source and the drain of the MOS device depends on the PN junction between the source and the drain. For example, the occurrence of avalanche breakdown is due to the increase in the electric field in the depletion region of the PN junction, thus limiting the voltage that can be applied by the source and the drain. If the crash occurs at the PN junction between the source and the drain, the current between the source and the drain will rise rapidly, causing damage to the PN junction and malfunction of the MOS device.
第1圖顯示先前技術N型高壓金屬氧化物半導體元件的架構,包括:半導體基板11、P型井區12a、N型漂移區(drift region)14a、N型源極15a、N型汲極18a、N型淡摻雜區16a、臨界電壓調整P型摻雜區19a、以及閘極結構17。其中,N型淡摻雜區16a以及N型漂移區14a都有加強該N型高壓金屬氧化物半導體元件崩潰防護電壓的作用。兩者皆是在濃摻雜區源極15a或汲極15b與P型井區12a間的PN接面,摻雜濃度較淡的N型雜質,以增加PN接面空乏區寬度,以加強該N型高壓金屬氧化物半導體元件崩潰防護電壓。1 shows the structure of a prior art N-type high voltage metal oxide semiconductor device, including: a semiconductor substrate 11, a P-type well region 12a, an N-type drift region 14a, an N-type source 15a, and an N-type drain 18a. The N-type lightly doped region 16a, the threshold voltage-adjusted P-type doped region 19a, and the gate structure 17. Among them, the N-type lightly doped region 16a and the N-type drift region 14a both have the effect of strengthening the collapse protection voltage of the N-type high voltage metal oxide semiconductor device. Both of them are PN junctions between the source 15a or the drain 15b of the heavily doped region and the P-type well region 12a, and are doped with a lighter N-type impurity to increase the width of the PN junction depletion region to enhance the N-type high voltage metal oxide semiconductor device breakdown protection voltage.
隨著元件尺寸的縮小與高壓元件所需承受的電壓的增加,上述的先前技術也遇到無法突破的瓶頸。因為上述的先前技術雖然增強了崩潰防護電壓,卻犧牲了另一個重要的元件操作參數,即導通電阻。As the size of the component shrinks and the voltage that the high voltage component is required to withstand increases, the prior art described above also encounters a bottleneck that cannot be broken. Because the prior art described above enhances the crash protection voltage, it sacrifices another important component operating parameter, the on-resistance.
反過來說,P型高壓金屬氧化物半導體元件則有降低導通電阻的瓶頸。Conversely, P-type high-voltage MOS devices have a bottleneck that reduces on-resistance.
有鑑於此,本發明即針對上述先前技術之不足,提出一種能夠增強N型高壓金屬氧化物半導體元件崩潰防護電壓且不犧牲導通電阻,以及能夠降低P型高壓金屬氧化物半導體元件導通電阻且不犧牲崩潰防護電壓的高壓金屬氧化物半導體元件與製作方法。In view of the above, the present invention is directed to the deficiencies of the prior art described above, and provides an enhancement of the N-type high voltage metal oxide semiconductor device breakdown protection voltage without sacrificing on-resistance, and can reduce the on-resistance of the P-type high-voltage metal oxide semiconductor device without A high voltage metal oxide semiconductor device that sacrifices a breakdown protection voltage and a method of fabricating the same.
本發明目的之一在提供一種N型高壓金屬氧化物半導體元件,能夠增強元件崩潰防護電壓且不犧牲導通電阻。SUMMARY OF THE INVENTION One object of the present invention is to provide an N-type high voltage metal oxide semiconductor device capable of enhancing a device breakdown protection voltage without sacrificing on-resistance.
本發明目的之一在提供一種P型高壓金屬氧化物半導體元件,能夠降低導通電阻且不犧牲元件崩潰防護電壓。SUMMARY OF THE INVENTION One object of the present invention is to provide a P-type high voltage metal oxide semiconductor device capable of reducing on-resistance without sacrificing component breakdown protection voltage.
本發明的另一目的在提供一種製作高壓金屬氧化物半導體元件之方法。Another object of the present invention is to provide a method of fabricating a high voltage metal oxide semiconductor device.
為達上述之目的,就其中一個觀點言,本發明提供了一種高壓金屬氧化物半導體元件,包含:一基板;位於該基板表面上之一閘極結構;位於該基板內部之一P型井區,從頂面視之此P型井區在水平面上構成一元件區;位於該P型井區內部之一第一N型漂移區;位於該P型井區內部之一N型源極;位於該第一N型漂移區內部之一N型汲極,其與該閘極結構以該第一N型漂移區隔開;以及位於該P型井區與該第一N型漂移區交界處且僅涵蓋部份元件區之一第一P型摻雜區,該第一P型摻雜區係以離子植入技術,植入P型雜質,以加強該高壓金屬氧化物半導體元件之崩潰電壓。In order to achieve the above object, in one aspect, the present invention provides a high voltage metal oxide semiconductor device comprising: a substrate; a gate structure on the surface of the substrate; and a P-type well region inside the substrate From the top view, the P-type well region constitutes an element region on a horizontal plane; a first N-type drift region located inside the P-type well region; and an N-type source electrode located inside the P-type well region; An N-type drain inside the first N-type drift region, separated from the gate structure by the first N-type drift region; and at a boundary between the P-type well region and the first N-type drift region Only one of the first P-type doped regions is covered, and the first P-type doped region is implanted with P-type impurities by an ion implantation technique to enhance the breakdown voltage of the high-voltage MOS device.
在其中一種實施型態中,從剖面圖視之,該第一P型摻雜區之一端至多延伸至該N型汲極中點,另一端至少延伸至該閘極結構下方一部份。In one embodiment, from the cross-sectional view, one end of the first P-type doped region extends at most to the midpoint of the N-type drain, and the other end extends at least to a portion below the gate structure.
上述高壓金屬氧化物半導體元件可為對稱元件或非對稱元件,當其為非對稱元件時,宜設置一與該N型源極部分重疊且部分位於該閘極下方之N型輕摻雜區。當其為對稱元件時,宜設置一位於該P型井區內部之一第二N型漂移區,以隔開該N型源極與該閘極結構;以及位於該P型井區與該第二N型漂移區交界處且僅涵蓋部份元件區之一第二P型摻雜區。The high-voltage metal oxide semiconductor device may be a symmetric element or an asymmetric element. When it is an asymmetric element, an N-type lightly doped region partially overlapping the N-type source portion and partially under the gate is preferably disposed. When it is a symmetrical element, a second N-type drift region located inside the P-type well region is preferably disposed to separate the N-type source from the gate structure; and the P-type well region and the first The junction of the two N-type drift regions covers only one of the second P-type doped regions of the partial device region.
就另一個觀點言,本發明也提供了一種高壓金屬氧化物半導體元件,包含:一基板;位於該基板表面上之一閘極結構;位於該基板內部之一N型井區,從頂面視之此N型井區在水平面上構成一元件區;位於該N型井區內部之一第一P型漂移區;位於該N型井區內部之一P型源極;位於該第一P型漂移區內部之一P型汲極,其與該閘極結構以該第一P型漂移區隔開;以及位於該P型汲極與該第一P型漂移區交界處且僅涵蓋部份元件區之一第一P型摻雜區,該第一P型摻雜區係以離子植入技術,植入P型雜質,以降低該高壓金屬氧化物半導體元件之導通阻值。In another aspect, the present invention also provides a high voltage metal oxide semiconductor device comprising: a substrate; a gate structure on the surface of the substrate; and an N-type well region inside the substrate, viewed from the top surface The N-type well region constitutes an element region on a horizontal surface; a first P-type drift region located inside the N-type well region; and a P-type source region inside the N-type well region; and the first P-type a P-type drain inside the drift region, separated from the gate structure by the first P-type drift region; and at a boundary between the P-type drain and the first P-type drift region and covering only some components A first P-type doped region of the first P-type doped region is implanted with a P-type impurity by an ion implantation technique to reduce the on-resistance of the high-voltage MOS device.
在其中一種實施型態中,從剖面圖視之,該第一P型摻雜區之一端至多延伸至該N型井區與第一P型漂移區之交界處。In one embodiment, from the cross-sectional view, one end of the first P-type doped region extends at most to the junction of the N-type well region and the first P-type drift region.
上述高壓金屬氧化物半導體元件可為對稱元件或非對稱元件,當其為非對稱元件時,宜設置一與該P型源極部分重疊且部分位於該閘極下方之P型輕摻雜區。當其為對稱元件時,宜設置一位於該N型井區內部之一第二P型漂移區,以隔開該P型源極與該閘極結構;以及位於該N型井區與該第二P型漂移區交界處且僅涵蓋部份元件區之一第二P型摻雜區,其中從剖面圖視之,該第二P型摻雜區之一端至多延伸至該N型井區與第二P型漂移區之交界處。The high-voltage MOS device may be a symmetrical element or an asymmetrical element. When it is an asymmetrical element, a P-type lightly doped region partially overlapping the P-type source and partially under the gate is preferably provided. When it is a symmetrical element, a second P-type drift region located inside the N-type well region is preferably disposed to separate the P-type source from the gate structure; and the N-type well region and the first a second P-type doped region at a junction of the second P-type drift region and covering only one of the component regions, wherein one end of the second P-type doped region extends at most to the N-type well region The junction of the second P-type drift region.
就再另一個觀點言,本發明提供了一種製作高壓金屬氧化物半導體元件之方法,包含以下步驟:提供一基板;於該基板內部形成一第一導電型井區,從頂面視之此第一導電型井區在水平面上構成一元件區;於該第一導電型井區內部形成一第二導電型之漂移區;位於該基板表面上,形成一閘極結構;於該第一導電型井區內部形成一第二導電型源極;於該第一漂移區內部形成一第二導電型汲極,其與該閘極結構以該漂移區隔開;以及以離子植入技術,植入P型雜質,以於該基板表面下方形成一不涵蓋整個元件區的P型摻雜區,以在調整臨界電壓的同時加強該半導體元件之崩潰防護電壓或降低該半導體元件之導通阻值。In still another aspect, the present invention provides a method of fabricating a high voltage metal oxide semiconductor device, comprising the steps of: providing a substrate; forming a first conductive well region inside the substrate, viewed from the top surface a conductive well region forms an element region on a horizontal surface; a second conductivity type drift region is formed inside the first conductivity type well region; a gate structure is formed on the surface of the substrate; and the first conductivity type is formed Forming a second conductive type source inside the well region; forming a second conductive type drain inside the first drift region, which is separated from the gate structure by the drift region; and implanting by ion implantation technology The P-type impurity forms a P-type doped region not covering the entire element region under the surface of the substrate to enhance the breakdown voltage of the semiconductor element or reduce the on-resistance of the semiconductor element while adjusting the threshold voltage.
上述製作高壓金屬氧化物半導體元件之方法中,第一導電型可為P型,第二導電型可為N型;或該第一導電型為N型,第二導電型為P型。其中形成該P型摻雜區之離子植入技術之參數範圍宜為:加速電壓範圍一萬電子伏特至二十萬電子伏特;植入之離子為含硼或銦之離子;植入劑量為每平方公分1E12至1E14個離子。In the above method of fabricating a high voltage metal oxide semiconductor device, the first conductivity type may be a P type, the second conductivity type may be an N type; or the first conductivity type may be an N type, and the second conductivity type may be a P type. The parameter of the ion implantation technique for forming the P-type doping region is preferably: an acceleration voltage range of 10,000 electron volts to 200,000 electron volts; the implanted ions are ions containing boron or indium; the implantation dose is per Square centimeters 1E12 to 1E14 ions.
底下藉由具體實施例詳加說明,當更容易瞭解本發明之目的、技術內容、特點及其所達成之功效。The purpose, technical content, features and effects achieved by the present invention will be more readily understood by the detailed description of the embodiments.
本發明中的圖式均屬示意,主要意在表示製程步驟以及各層之間之上下次序關係,至於形狀、厚度與寬度則並未依照比例繪製。The drawings in the present invention are schematic and are mainly intended to represent the process steps and the relationship between the layers, and the shapes, thicknesses, and widths are not drawn to scale.
請參閱第2A-2F之剖面流程圖,顯示本發明的第一實施例,本實施例顯示N型高壓金屬氧化物半導體元件之結構與製作方法。如第2A圖所示,首先提供一基板11,接著以微影技術與離子植入技術於基板11中定義出P型井區12a,從頂面視之,此P型井區在水平面上構成一元件區100。接下來,如第2B圖所示,於基板11中形成隔離區13,該隔離區13可以為區域氧化(LOCOS)或淺溝槽絕緣(STI)製程技術所形成。接下來,如第2C圖所示,以微影技術與離子植入技術於P型井區12a中定義出N型第一漂移區14a。Referring to the cross-sectional flowchart of FIGS. 2A-2F, a first embodiment of the present invention is shown. This embodiment shows the structure and fabrication method of an N-type high voltage metal oxide semiconductor device. As shown in FIG. 2A, a substrate 11 is first provided, and then a P-type well region 12a is defined in the substrate 11 by lithography and ion implantation technology. From the top surface, the P-type well region is formed on a horizontal surface. An element area 100. Next, as shown in FIG. 2B, an isolation region 13 is formed in the substrate 11, and the isolation region 13 may be formed by a region oxidation (LOCOS) or shallow trench isolation (STI) process technology. Next, as shown in FIG. 2C, the N-type first drift region 14a is defined in the P-type well region 12a by lithography and ion implantation techniques.
再接下來,如第2D圖所示,以微影技術與離子植入技術於P型井區12a與N型第一漂移區14a交界處,形成一第一P型摻雜區19b,該第一P型摻雜區19b係以離子植入技術,植入P型雜質所形成;此第一P型摻雜區19b可提高該N型高壓金屬氧化物半導體元件之崩潰防護電壓,且不犧牲導通電阻。不但如此,形成此第一P型摻雜區19b的步驟可以與調整臨界電壓的離子植入步驟(VT implant)整合,亦即利用原本元件所需的臨界電壓調整步驟,在不增加光罩與製程步驟的情況下,僅是更動光罩的佈局,即可達成本發明的效果。詳言之,先前技術中之臨界電壓調整步驟係暴露出整個元件,對元件區作全面性植入,本發明則是僅打開該P型井區12a與該N型第一漂移區14a交界處,其範圍請先參照第2F圖,一端至多延伸至汲極區18a中點,另一端則至少延伸至閘極結構17下方的一部分,如第2F圖中之虛線部分所定義之區域。而其離子植入步驟之製程參數,亦可以採用臨界電壓調整之參數,其較佳之參數設定為:加速電壓範圍一萬電子伏特至二十萬電子伏特;植入之離子為含硼或銦之離子;植入劑量為每平方公分1E12至1E14個離子。此步驟利用通道中橫向濃度的變化,既可增加該N型高壓金屬氧化物半導體元件之崩潰防護電壓,且不犧牲導通電阻,更不需要增加光罩、製程步驟、或改變其他製程參數(例如並未改變整合製程的熱預算(thermal budget)等),是本發明優於先前技術的特點之一。Next, as shown in FIG. 2D, a first P-type doped region 19b is formed by a lithography technique and an ion implantation technique at a boundary between the P-type well region 12a and the N-type first drift region 14a. A P-type doping region 19b is formed by implanting a P-type impurity by an ion implantation technique; the first P-type doping region 19b can improve the breakdown protection voltage of the N-type high-voltage MOS device without sacrificing On resistance. Moreover, the step of forming the first P-type doping region 19b can be integrated with the VT implant step of adjusting the threshold voltage, that is, using the threshold voltage adjustment step required by the original component, without adding a mask and In the case of the process step, the effect of the present invention can be achieved only by the layout of the moving mask. In detail, the threshold voltage adjustment step in the prior art exposes the entire component and comprehensively implants the component region, and the present invention opens only the junction of the P-type well region 12a and the N-type first drift region 14a. For the range, please refer to the 2F figure. One end extends at most to the midpoint of the drain region 18a, and the other end extends at least to a portion below the gate structure 17, as defined by the broken line portion in FIG. 2F. The process parameters of the ion implantation step can also adopt the parameters of the threshold voltage adjustment, and the preferred parameters are set as: the acceleration voltage range is 10,000 electron volts to 200,000 electron volts; the implanted ions are boron or indium. Ion; implant dose is 1E12 to 1E14 ions per square centimeter. This step utilizes variations in lateral concentration in the channel to increase the collapse protection voltage of the N-type high voltage MOS device without sacrificing on-resistance, eliminating the need to add masks, process steps, or other process parameters (eg, Not changing the thermal budget of the integrated process, etc., is one of the features of the present invention over the prior art.
接下來如第2E圖所示,於基板11上形成閘極結構17的一部分,包含閘極介電層17a與閘極導電層17b。第2F圖顯示以自我對準技術、微影技術、蝕刻技術、與離子植入技術形成N型淡摻雜區16a、於閘極側壁形成閘極間隔層17c(此為閘極結構17的一部分)、以及形成N型源極15a與N型汲極18a。其中,N型淡摻雜區16a與N型源極15a部分重疊且部分位於該閘極結構17的下方。Next, as shown in FIG. 2E, a portion of the gate structure 17 is formed on the substrate 11, and includes a gate dielectric layer 17a and a gate conductive layer 17b. 2F shows a N-type lightly doped region 16a formed by self-alignment technology, lithography, etching, and ion implantation techniques, and a gate spacer layer 17c formed on the gate sidewall (this is part of the gate structure 17). And forming an N-type source 15a and an N-type drain 18a. The N-type lightly doped region 16a partially overlaps the N-type source 15a and is partially located below the gate structure 17.
第3圖示出本發明的第二實施例,本實施例為一P型高壓金屬氧化物半導體元件。該P型高壓金屬氧化物半導體元件之製作流程與本發明的第一實施例主要的差異,除了本實施例包含N型井區12b、第一P型漂移區14b、P型源極15b、P型汲極18b、以及P型淡摻雜區16b與前述N型高壓金屬氧化物半導體元件不同之外,主要在於:第一P型摻雜區19b是定義於P型汲極18b與P型第一漂移區14b交界處,其範圍一端至多延伸至N型井區12b與第一P型漂移區14b的交界處,另一端則沒有限制(如虛線與箭號所示),而其離子植入步驟之製程參數,亦可以採用臨界電壓調整之參數,其較佳之參數設定為:加速電壓範圍一萬電子伏特至二十萬電子伏特;植入之離子為含硼或銦之離子;植入劑量為每平方公分1E12至1E14個離子。此步驟利用通道中橫向濃度的變化,用以降低導通阻值卻不犧牲崩潰電壓。同樣地,形成此第一P型摻雜區19b的步驟可以與調整臨界電壓的離子植入步驟整合,只需更動光罩的佈局,達成本發明的效果。Fig. 3 shows a second embodiment of the present invention, which is a P-type high voltage metal oxide semiconductor device. The manufacturing process of the P-type high-voltage metal oxide semiconductor device is mainly different from the first embodiment of the present invention, except that the present embodiment includes the N-type well region 12b, the first P-type drift region 14b, and the P-type source 15b, P. The type drain electrode 18b and the P type lightly doped region 16b are different from the N-type high voltage metal oxide semiconductor device described above, mainly in that the first P type doping region 19b is defined by the P type drain electrode 18b and the P type. At the junction of a drift region 14b, one end of the range extends at most to the junction of the N-type well region 12b and the first P-type drift region 14b, and the other end is not limited (as indicated by a broken line and an arrow), and its ion implantation The process parameters of the step can also adopt the parameters of the threshold voltage adjustment, and the preferred parameters are set as: the acceleration voltage range is 10,000 electron volts to 200,000 electron volts; the implanted ions are ions containing boron or indium; the implantation dose It is 1E12 to 1E14 ions per square centimeter. This step takes advantage of changes in the lateral concentration in the channel to reduce the on-resistance without sacrificing the breakdown voltage. Similarly, the step of forming the first P-type doping region 19b can be integrated with the ion implantation step of adjusting the threshold voltage, and only the layout of the photomask is changed to achieve the effect of the present invention.
前述兩實施例為非對稱元件,第4圖顯示本發明的另一個實施例,本實施例為一N型高壓金屬氧化物半導體對稱元件,與第一實施例的主要差異,在於P型井區12a內省略N型淡摻雜區16a,但增加一第二N型漂移區14c,隔開閘極結構17與N型源極15a,使源極15a也可以施加高電壓。此外本實施例亦增加位於P型井區12a與第二N型漂移區14c交界處之第二P型摻雜區19c,此第二P型摻雜區19c係以離子植入技術,植入P型雜質,以加強該高壓N型金屬氧化物半導體對稱元件之崩潰電壓。同樣地,此第二P型摻雜區19c一端至多延伸至源極區15a中點,另一端則至少延伸至閘極結構17下方的一部分。The foregoing two embodiments are asymmetrical elements, and FIG. 4 shows another embodiment of the present invention. This embodiment is an N-type high-voltage metal oxide semiconductor symmetrical element. The main difference from the first embodiment lies in the P-type well region. The N-type lightly doped region 16a is omitted in 12a, but a second N-type drift region 14c is added to separate the gate structure 17 from the N-type source 15a, so that the source 15a can also apply a high voltage. In addition, the second P-type doping region 19c at the intersection of the P-type well region 12a and the second N-type drift region 14c is also added in the embodiment. The second P-type doping region 19c is implanted by ion implantation technology. P-type impurity to strengthen the breakdown voltage of the high-voltage N-type metal oxide semiconductor symmetrical element. Similarly, one end of the second P-type doping region 19c extends at most to the midpoint of the source region 15a, and the other end extends at least to a portion below the gate structure 17.
第5圖顯示為本發明的又一個實施例,本實施例為一P型高壓金屬氧化物半導體對稱元件,與第二實施例的主要差異,在於N型井區12b內省略P型淡摻雜區16b,但增加一P型第二漂移區14d,隔開閘極結構17與P型源極15b,此外本實施例亦增加位於P型源極15b與第二P型漂移區14d交界處之第二P型摻雜區19c,該第二P型摻雜區19c係以離子植入技術,植入P型雜質,以進一步降低該高壓P型金屬氧化物半導體對稱元件之導通阻值。Fig. 5 is a view showing still another embodiment of the present invention. This embodiment is a P-type high-voltage metal oxide semiconductor symmetrical element. The main difference from the second embodiment is that the P-type light doping is omitted in the N-type well region 12b. a region 16b, but a P-type second drift region 14d is added to separate the gate structure 17 from the P-type source 15b. In addition, the present embodiment also increases the boundary between the P-type source 15b and the second P-type drift region 14d. The second P-type doping region 19c is implanted with a P-type impurity by an ion implantation technique to further reduce the on-resistance value of the high-voltage P-type metal oxide semiconductor symmetrical element.
以上已針對較佳實施例來說明本發明,唯以上所述者,僅係為使熟悉本技術者易於了解本發明的內容而已,並非用來限定本發明之權利範圍。在本發明之相同精神下,熟悉本技術者可以思及各種等效變化。例如,在不影響元件主要的特性下,可加入其他製程步驟或結構,如深井區等;又如,微影技術並不限於光罩技術,亦可包含電子束微影技術。此外,在第1-5圖中,汲極18a/18b係與閘極間隔層17c對齊,此暗示各實施例中之汲極18a/18b係使用自我對準方式,以閘極結構為遮罩作離子植入所形成,但本發明不限於此,汲極18a/18b不使用自我對準方式形成,亦屬可行,例如第6、7圖。因此,本發明的範圍應涵蓋上述及其他所有等效變化。The present invention has been described with reference to the preferred embodiments thereof, and the present invention is not intended to limit the scope of the present invention. In the same spirit of the invention, various equivalent changes can be conceived by those skilled in the art. For example, other process steps or structures, such as deep well areas, may be added without affecting the main characteristics of the components; for example, lithography is not limited to reticle technology, and may include electron beam lithography. Further, in Figs. 1-5, the drain electrodes 18a/18b are aligned with the gate spacer layer 17c, which implies that the drain electrodes 18a/18b in the respective embodiments are self-aligned, with the gate structure as a mask. It is formed by ion implantation, but the present invention is not limited thereto, and it is also possible to form the drains 18a/18b without self-alignment, for example, Figures 6 and 7. Therefore, the scope of the invention should be construed as covering the above and all other equivalents.
11...基板11. . . Substrate
12a...P型井區12a. . . P type well area
12b...N型井區12b. . . N type well area
13...隔離區13. . . quarantine area
14a...第一N型漂移區14a. . . First N-type drift region
14b...第一P型漂移區14b. . . First P-type drift region
14c...第二N型漂移區14c. . . Second N-type drift region
14d...第二P型漂移區14d. . . Second P-type drift region
15a...N型源極15a. . . N-type source
15b...P型源極15b. . . P-type source
16a‧‧‧N型淡摻雜區16a‧‧‧N type lightly doped area
16b‧‧‧P型淡摻雜區16b‧‧‧P type lightly doped area
17‧‧‧閘極結構17‧‧‧ gate structure
17a‧‧‧閘極介電層17a‧‧‧ Gate dielectric layer
17b‧‧‧閘極導電層17b‧‧‧ gate conductive layer
17c‧‧‧閘極間隔層17c‧‧‧gate spacer
18a‧‧‧N型汲極18a‧‧‧N type bungee
18b‧‧‧P型汲極18b‧‧‧P type bungee
19a‧‧‧臨界電壓調整P型摻雜區19a‧‧‧Critical voltage adjustment P-doped region
19b‧‧‧第一P型摻雜區19b‧‧‧First P-doped region
19c‧‧‧第二P型摻雜區19c‧‧‧Second P-doped region
第1圖示出先前技術之N型高壓金屬氧化物半導體元件的剖視圖。Fig. 1 is a cross-sectional view showing a prior art N-type high voltage metal oxide semiconductor device.
第2A-2F圖示出本發明的第一實施例的剖視圖。2A-2F are cross-sectional views showing the first embodiment of the present invention.
第3-5圖示出本發明的另外三種實施例的剖視圖。Figures 3-5 show cross-sectional views of three other embodiments of the invention.
第6-7圖示出本發明的其他實施例的剖視圖,其中汲極18a/18b不使用自我對準方式形成。Figures 6-7 illustrate cross-sectional views of other embodiments of the present invention in which the drains 18a/18b are formed without self-alignment.
11...基板11. . . Substrate
12a...P型井區12a. . . P type well area
13...隔離區13. . . quarantine area
14a...第一N型漂移區14a. . . First N-type drift region
15a...N型源極15a. . . N-type source
16a...N型淡摻雜區16a. . . N type lightly doped area
17a...閘極介電層17a. . . Gate dielectric layer
17b...閘極導電層17b. . . Gate conductive layer
17c...閘極間隔層17c. . . Gate spacer
18a...N型汲極18a. . . N-type bungee
19b...第一P型摻雜區19b. . . First P-doped region
100...元件區100. . . Component area
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