TWI531001B - Plasma activated conformal dielectric film deposition - Google Patents

Plasma activated conformal dielectric film deposition Download PDF

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Publication number
TWI531001B
TWI531001B TW101134692A TW101134692A TWI531001B TW I531001 B TWI531001 B TW I531001B TW 101134692 A TW101134692 A TW 101134692A TW 101134692 A TW101134692 A TW 101134692A TW I531001 B TWI531001 B TW I531001B
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Taiwan
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film
substrate
reaction chamber
dopant
depositing
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TW101134692A
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Chinese (zh)
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TW201330096A (en
Inventor
珊卡 史旺明內森
強 亨利
丹尼斯Ｍ 豪斯曼恩
普拉莫 瑟藍莫尼恩
漫德彥 西里蘭
費許旺納森 藍格拉傑
克西Ｋ 凱帝吉
史貴凡迪 巴頓Ｊ 凡
安組Ｊ 瑪克羅
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諾發系統有限公司
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Priority claimed from US13/242,084 external-priority patent/US8637411B2/en
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Publication of TW201330096A publication Critical patent/TW201330096A/en
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Publication of TWI531001B publication Critical patent/TWI531001B/en

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    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H01L21/02129—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being boron or phosphorus doped silicon oxides, e.g. BPSG, BSG or PSG
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    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
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    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

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Description

電漿活化之保形介電薄膜沉積 Plasma-activated conformal dielectric thin film deposition

本發明有關於保形介電薄膜沉積，且尤其關於電漿活化之保形介電薄膜沉積。 This invention relates to conformal dielectric thin film deposition, and more particularly to plasma-assisted conformal dielectric thin film deposition.

各種用於半導體之薄膜層可用原子層沉積(ALD)製程來沉積。然而，現有的ALD製程可能不合適用來沉積高度保形之介電薄膜。 Various thin film layers for semiconductors can be deposited by an atomic layer deposition (ALD) process. However, existing ALD processes may not be suitable for depositing highly conformal dielectric films.

於本文中揭露之各種實施態樣涉及在基板表面上沉積薄膜的方法及設備。在一些實施例中，該方法包含藉由薄膜在反應物吸附及反應之一或更多循環期間生長之表面介導反應來沉積薄膜。在一實施態樣中，該方法具有在吸附及反應的循環之間間歇遞送摻雜物種至薄膜之特徵。在一些情況下，可驅使摻雜物物種橫越基板表面至基板的摻雜區域。 Various embodiments disclosed herein relate to methods and apparatus for depositing a film on a surface of a substrate. In some embodiments, the method comprises depositing a thin film by a surface-mediated reaction in which the film is grown during one or more cycles of reactant adsorption and reaction. In one embodiment, the method has the feature of intermittently delivering a dopant species to a film between cycles of adsorption and reaction. In some cases, the dopant species can be driven across the substrate surface to the doped regions of the substrate.

在一實施態樣中，所揭露之方法在反應腔室中於基板表面上沉積薄膜。該方法可具有以下操作之特徵：(a)在允許第一反應物吸附至基板表面上的條件下，將第一反應物導入反應腔室中；(b)在第一反應物吸附在基板表面上時，將第二反應物導入反應腔室中；(c)使基板表面曝露至電漿以驅動基板表面上第一及第二反應物之間的反應，從而形成薄膜的一部份；(d)重複(a)-(c)至少一次；(e)在允許含摻雜物材料接觸薄膜之曝露表面的條件下，將未在(a)-(d)期間導入之含摻雜物材料導入反應腔室中；以及(f)自含摻雜物材料將摻雜物導入薄膜中。將摻雜物導入薄膜中可涉及使含摻雜物材料曝露至電漿。 In one embodiment, the disclosed method deposits a thin film on the surface of the substrate in the reaction chamber. The method can be characterized by: (a) introducing a first reactant into the reaction chamber while allowing the first reactant to adsorb onto the surface of the substrate; (b) adsorbing the first reactant on the surface of the substrate Upper, introducing a second reactant into the reaction chamber; (c) exposing the surface of the substrate to the plasma to drive a reaction between the first and second reactants on the surface of the substrate to form a portion of the film; d) repeating (a)-(c) at least once; (e) introducing a dopant-containing material that is not introduced during (a)-(d), while allowing the dopant-containing material to contact the exposed surface of the film. Introduced into the reaction chamber; and (f) introducing dopants into the film from the dopant-containing material. Introducing the dopant into the film can involve exposing the dopant-containing material to the plasma.

在各種實施例中，該方法額外包含自薄膜將摻雜物驅入其上存留薄膜之基板表面的特徵部中。可藉由回火該薄膜來完成自薄膜驅入摻雜物。在 一些應用中，薄膜存留在基板表面之三維特徵部上並從而自該薄膜驅入摻雜物提供摻雜物進入該特徵部之保形擴散。在一特定的應用中，特徵部具有不大於約40奈米的寬度。 In various embodiments, the method additionally includes driving the dopant from the film into features on the surface of the substrate on which the film remains. The self-film drive dopant can be accomplished by tempering the film. in In some applications, the film remains on the three-dimensional features of the surface of the substrate and thereby drives dopants from the film to provide conformal diffusion of dopants into the feature. In a particular application, the features have a width of no more than about 40 nanometers.

在一些實施例中，該薄膜係介電薄膜。在一些情況下，總薄膜厚度介於約10-100埃(Angstroms)之間。在各種實施例中，薄膜中摻雜物的濃度介於約0.01及10重量百分率之間。 In some embodiments, the film is a dielectric film. In some cases, the total film thickness is between about 10-100 Angstroms. In various embodiments, the concentration of dopant in the film is between about 0.01 and 10 weight percent.

在一些實施例中，此實施態樣之方法額外包含在(e)或(f)之後重複(a)-(c)。在一些實施例中，此實施態樣之方法額外包含在重複(a)-(e)。在一些實施例中，於(a)-(c)期間所沉積之薄膜數量介於約0.5至1埃之間。 In some embodiments, the method of this embodiment additionally comprises repeating (a)-(c) after (e) or (f). In some embodiments, the method of this embodiment is additionally included in repeats (a)-(e). In some embodiments, the amount of film deposited during (a)-(c) is between about 0.5 and 1 angstrom.

在一些實施例中，該方法額外包含在使基板表面曝露至電漿之前自反應腔室清除第二反應物。可藉由使包含氧化劑之氣體流入反應腔室中來完成該清除。在一些實施例中，第一及第二反應物以氣相共存於反應腔室中，並且第一及第二反應物在反應腔室中不明顯互相反應直到在(c)之中曝露至電漿為止。 In some embodiments, the method additionally includes removing the second reactant from the reaction chamber prior to exposing the surface of the substrate to the plasma. This removal can be accomplished by flowing a gas containing an oxidant into the reaction chamber. In some embodiments, the first and second reactants coexist in the reaction chamber in a gas phase, and the first and second reactants do not significantly react with each other in the reaction chamber until exposed to electricity in (c) So far.

在一些實施例中，第一反應物係例如一氧化二氮之氧化劑。在一些實施例中，第二反應物係介電質前驅物，例如(i)烷胺基矽烷(alkylamino silanes)(SiHx(NR2)4-x)，其中x=1-3，並且R包含烷基；或(ii)鹵素矽烷(halosilanes)(SiHxY4-x)，其中x=1-3，並且Y包含Cl、Br、以及I。在一具體實施例中，第二反應物係BTBAS。在一些實施例中，含摻雜物材料係磷化氫、砷化氫、烷基硼、烷基鎵、烷基磷、磷鹵化物、砷鹵化物、鎵鹵化物、硼鹵化物、烷基硼、或乙硼烷。 In some embodiments, the first reactant is an oxidizing agent such as nitrous oxide. In some embodiments, the second reactant is a dielectric precursor, such as (i) alkylamino silanes (SiH x (NR 2 ) 4-x ), where x = 1-3, and R Containing an alkyl group; or (ii) halosilanes (SiH x Y 4-x ), where x = 1-3, and Y comprises Cl, Br, and I. In a specific embodiment, the second reactant is BTBAS. In some embodiments, the dopant-containing material is phosphine, arsine, alkyl boron, alkyl gallium, alkyl phosphorus, phosphorus halide, arsenic halide, gallium halide, boron halide, alkyl Boron, or diborane.

在另一實施態樣中，所揭露之方法在反應腔室中於基板表面上沉積介電薄膜。此方法可具有以下操作之特徵：(a)在允許第一反應物吸附至基板表面上的條件下，使氧化劑流入反應腔室中；(b)在氧化劑持續流入反應腔室時，將介電質前驅物導入反應腔室中；(c)使基板表面曝露至電漿以驅動基板表面上介電質前驅物及氧化劑之間的反應，從而形成薄膜的一部份；(d)在允許含摻雜物材料接觸薄膜之曝露表面的條件下，將未在(a)-(c)期間導入之含摻雜物材料導入反應腔室中；以及(e)使摻雜物自含摻雜物材料結合至介電薄膜中。在一實施例中，介電質前驅物係BTBAS或如先前實施態樣中 所確認之另一前驅物。 In another embodiment, the disclosed method deposits a dielectric film on the surface of the substrate in the reaction chamber. The method can be characterized by (a) flowing an oxidant into the reaction chamber while allowing the first reactant to adsorb onto the surface of the substrate; (b) dielectrically flowing as the oxidant continues to flow into the reaction chamber The precursor is introduced into the reaction chamber; (c) exposing the surface of the substrate to the plasma to drive a reaction between the dielectric precursor and the oxidant on the surface of the substrate to form a portion of the film; (d) allowing The dopant-containing material introduced during (a)-(c) is introduced into the reaction chamber under conditions in which the dopant material contacts the exposed surface of the film; and (e) the dopant is self-contained The material is incorporated into the dielectric film. In one embodiment, the dielectric precursor system BTBAS or as in the previous embodiment Another precursor identified.

此外，該方法可能需要重複操作(a)-(c)一或更多次。在一具體範例中，當(a)最先執行時，氧化劑包含氧對氮之第一比率；然而當(a)隨後才執行時，氧化劑包含氧對氮之第二比率。第二比率小於第一比率。舉例而言，當(a)最先執行時，氧化劑可包含元素氧；然而當(a)重複時，氧化劑包含一氧化二氮。在一些實施例中，當(c)最先執行時，基板處於第一溫度下；而且當(c)重複時，基板處於第二溫度下，其高於第一溫度。 In addition, the method may require repeated operations (a)-(c) one or more times. In a specific example, when (a) is first performed, the oxidant comprises a first ratio of oxygen to nitrogen; however, when (a) is subsequently performed, the oxidant comprises a second ratio of oxygen to nitrogen. The second ratio is less than the first ratio. For example, when (a) is first performed, the oxidant may comprise elemental oxygen; however, when (a) is repeated, the oxidant comprises nitrous oxide. In some embodiments, when (c) is first performed, the substrate is at a first temperature; and when (c) is repeated, the substrate is at a second temperature that is higher than the first temperature.

在一些情況下，該方法更包含將摻雜物自介電薄膜驅入基板中。在一些實施例中，該方法更包含在(a)之前使基板表面與含摻雜物材料接觸。 In some cases, the method further includes driving the dopant from the dielectric film into the substrate. In some embodiments, the method further comprises contacting the surface of the substrate with the dopant-containing material prior to (a).

在另一實施態樣中，所揭露之方法根據以下操作在反應腔室中於基板表面上沉積薄膜：(a)在允許前驅物吸附至基板表面上的條件下，將介電質前驅物導入反應腔室中；(b)之後在前驅物保持吸附在基板表面上時，自反應腔室清除介電質前驅物；(c)使基板表面曝露至電漿以驅動基板表面上介電質前驅物的反應，從而形成介電薄膜的一部份；以及(d)在允許摻雜物前驅物接觸部份介電薄膜的條件下，將未在(a)-(c)期間導入之摻雜物前驅物導入反應腔室中。在一些實施例中，該方法額外涉及在(a)-(c)之前及期間使氧化劑流入反應腔室中。在一些情況下，該方法額外涉及使摻雜物前驅物反應以將摻雜物併入至薄膜中。 In another embodiment, the disclosed method deposits a thin film on a surface of a substrate in a reaction chamber according to the following operation: (a) introducing a dielectric precursor under conditions that allow adsorption of the precursor onto the surface of the substrate (b) after removing the dielectric precursor from the reaction chamber while the precursor remains adsorbed on the surface of the substrate; (c) exposing the surface of the substrate to the plasma to drive the dielectric precursor on the surface of the substrate The reaction of the substance to form a portion of the dielectric film; and (d) the doping introduced during (a)-(c) under conditions that allow the dopant precursor to contact a portion of the dielectric film The precursor is introduced into the reaction chamber. In some embodiments, the method additionally involves flowing an oxidant into the reaction chamber before and during (a)-(c). In some cases, the method additionally involves reacting a dopant precursor to incorporate the dopant into the film.

又另一實施態樣涉及用以在基板表面上沉積薄膜之設備。該設備可具有以下特徵部之特徵：一反應腔室包含摻雜介電薄膜的沉積期間用以夾持基板之裝置；耦接至反應腔室之一或更多處理氣體進氣口；以及一控制器。該控制器係設計或配置以造成該設備執行以下操作：(a)在允許第一反應物吸附至基板表面上的條件下，將第一反應物導入反應腔室中；(b)在第一反應物吸附在基板表面上時，將第二反應物導入反應腔室中；(c)使基板表面曝露至電漿以驅動基板表面上第一及第二反應物之間的反應，從而形成薄膜的一部份；(d)重複(a)-(c)至少一次；(e)在允許含摻雜物材料接觸薄膜之曝露表面的條件下，將未在(a)-(d)期間導入之含摻雜物材料導入反應腔室中；以及(f)將摻雜物自含摻雜物材料導入薄膜中。控制器可設計或配置以指示例如那些依據其他實施態樣所討論的其他方法之實行。 Yet another embodiment relates to an apparatus for depositing a thin film on a surface of a substrate. The apparatus can be characterized by: a reaction chamber comprising means for holding a substrate during deposition of a doped dielectric film; one or more process gas inlets coupled to the reaction chamber; and Controller. The controller is designed or configured to cause the apparatus to: (a) introduce the first reactant into the reaction chamber while allowing the first reactant to adsorb onto the surface of the substrate; (b) at the first When the reactant is adsorbed on the surface of the substrate, the second reactant is introduced into the reaction chamber; (c) exposing the surface of the substrate to the plasma to drive the reaction between the first and second reactants on the surface of the substrate to form a film Part (a) repeating (a)-(c) at least once; (e) not being introduced during (a)-(d) under conditions that allow the dopant-containing material to contact the exposed surface of the film The dopant-containing material is introduced into the reaction chamber; and (f) the dopant is introduced into the film from the dopant-containing material. The controller can be designed or configured to indicate the implementation of other methods, such as those discussed in accordance with other implementations.

在一些實施例中，控制器更設計或配置以造成該設備在(a)-(d)之前及期間使氧化劑流入反應腔室中。在一些實施例中，該控制器更設計或配置以造成在(e)或(f)之後重複(a)-(c)。在一些實施例中，該控制器更設計或配置以造成將摻雜物自薄膜驅入其上存留薄膜之基板表面的特徵部中。可藉由回火該薄膜來完成自薄膜驅入摻雜物。在一些實施例中，該控制器更設計或配置以造成在(a)-(d)之一或更多重複之間的間隔執行(e)，且其中該間隔在沉積薄膜的過程中改變。 In some embodiments, the controller is more designed or configured to cause the device to flow oxidant into the reaction chamber before and during (a)-(d). In some embodiments, the controller is more designed or configured to cause (a)-(c) to be repeated after (e) or (f). In some embodiments, the controller is more designed or configured to cause the dopant to be driven from the film into the features of the substrate surface on which the film remains. The self-film drive dopant can be accomplished by tempering the film. In some embodiments, the controller is more designed or configured to cause (e) to be performed at intervals between one or more of (a)-(d), and wherein the spacing changes during deposition of the film.

在各種實施例中，該控制器更設計或配置以造成在使基板表面曝露至電漿之前自反應腔室清除第二反應物。在一範例中，藉由在控制器的指示下使包含氧化劑之氣體流入反應腔室中來完成清除。 In various embodiments, the controller is more designed or configured to cause the second reactant to be purged from the reaction chamber prior to exposing the surface of the substrate to the plasma. In one example, the purge is accomplished by flowing a gas containing an oxidant into the reaction chamber under the direction of a controller.

以下將參考相關的圖式更詳細地敘述這些及其他特徵。 These and other features are described in more detail below with reference to the associated drawings.

100‧‧‧時序圖 100‧‧‧ Timing diagram

110A、110B‧‧‧沉積循環 110A, 110B‧‧‧deposition cycle

120A、120B‧‧‧A曝露階段 120A, 120B‧‧A exposure stage

130‧‧‧反應物A後飽和曝露時間 130‧‧‧Saturated exposure time after reactant A

140A、140B‧‧‧B曝露階段 140A, 140B‧‧B exposure stage

150‧‧‧反應物B後飽和曝露時間 150‧‧‧Saturated exposure time after reactant B

160A‧‧‧清除階段 160A‧‧‧Clearing phase

160B‧‧‧清除階段 160B‧‧‧Clearing phase

180A、180B‧‧‧電漿活化階段 180A, 180B‧‧‧ Plasma activation stage

190‧‧‧電漿後飽和曝露時間 190‧‧•Saturated exposure time after plasma

200‧‧‧時序圖 200‧‧‧ Timing diagram

210‧‧‧沉積循環 210‧‧‧Sedimentation cycle

240A、240B‧‧‧B曝露階段 240A, 240B‧‧B exposure stage

260A‧‧‧清除階段 260A‧‧‧clearing stage

300‧‧‧時序圖 300‧‧‧ Timing diagram

310‧‧‧沉積階段 310‧‧‧Deposition stage

380‧‧‧電漿活化階段 380‧‧‧Plastic activation stage

390‧‧‧電漿處理循環 390‧‧‧ Plasma processing cycle

390A‧‧‧電漿處理清除階段 390A‧‧‧Plastic treatment removal stage

390B‧‧‧電漿處理活化階段 390B‧‧‧Plastic treatment activation stage

400‧‧‧時序圖 400‧‧‧ Timing diagram

500‧‧‧比較 500‧‧‧ comparison

502、504‧‧‧CFD薄膜 502, 504‧‧‧CFD film

600‧‧‧相關性 600‧‧‧ Relevance

700‧‧‧相關性 700‧‧‧ Relevance

702、704‧‧‧CFD二氧化矽薄膜 702, 704‧‧‧CFD ruthenium dioxide film

800‧‧‧非平面基板 800‧‧‧Non-planar substrate

802、802A、802B、802C‧‧‧間隙 802, 802A, 802B, 802C‧‧‧ gap

804‧‧‧保形薄膜 804‧‧‧Conformal film

900‧‧‧時序圖 900‧‧‧ Timing diagram

902‧‧‧CFD製程階段 902‧‧‧CFD process stage

904‧‧‧過渡階段 904‧‧‧Transition phase

904A‧‧‧B曝露階段 904A‧‧‧B exposure stage

904B‧‧‧電漿活化階段 904B‧‧‧Plastic activation phase

906‧‧‧PECVD製程階段 906‧‧‧PECVD process stage

1000‧‧‧結構 1000‧‧‧ structure

1002‧‧‧基板 1002‧‧‧Substrate

1006‧‧‧較厚之薄膜 1006‧‧‧Thicker film

1008‧‧‧孔洞 1008‧‧‧ hole

1100‧‧‧時序圖 1100‧‧‧ Timing diagram

1102‧‧‧沉積階段 1102‧‧‧Deposition stage

1104‧‧‧蝕刻階段 1104‧‧‧etching stage

1106‧‧‧沉積階段 1106‧‧‧Deposition stage

1200‧‧‧非平面基板 1200‧‧‧Non-planar substrate

1202‧‧‧間隙 1202‧‧‧ gap

1204‧‧‧薄膜 1204‧‧‧film

1204A‧‧‧上部區域 1204A‧‧‧Upper area

1204B‧‧‧下部區域 1204B‧‧‧lower area

1206‧‧‧凹入部 1206‧‧‧ recessed part

1300‧‧‧處理站 1300‧‧ ‧ processing station

1301‧‧‧反應物遞送系統 1301‧‧Recipient delivery system

1302‧‧‧處理腔室本體 1302‧‧‧Processing chamber body

1303‧‧‧汽化點 1303‧‧‧vaporization point

1304‧‧‧混合容器 1304‧‧‧Mixed container

1306‧‧‧噴淋頭 1306‧‧‧Sprinkler

1308‧‧‧基座 1308‧‧‧Base

1310‧‧‧加熱器 1310‧‧‧heater

1314‧‧‧RF電力供應 1314‧‧‧RF power supply

1316‧‧‧匹配網路 1316‧‧‧matching network

1318‧‧‧蝶形閥 1318‧‧‧Butterfly valve

1320‧‧‧混合容器進氣閥 1320‧‧‧Mixed container intake valve

2400‧‧‧處理工具 2400‧‧‧Processing tools

2402‧‧‧入站裝載鎖 2402‧‧‧Inbound load lock

2404‧‧‧出站裝載鎖 2404‧‧‧Outbound load lock

2406‧‧‧機械臂 2406‧‧‧ Robotic arm

2408‧‧‧箱體 2408‧‧‧ cabinet

2410‧‧‧大氣口 2410‧‧‧ atmosphere

2412‧‧‧基座 2412‧‧‧Base

2414‧‧‧處理腔室 2414‧‧‧Processing chamber

2416‧‧‧腔室運送口 2416‧‧‧Cell transport port

2418‧‧‧加熱基座 2418‧‧‧heated base

2450‧‧‧系統控制器 2450‧‧‧System Controller

2452‧‧‧處理器 2452‧‧‧ Processor

2454‧‧‧大量儲存裝置 2454‧‧‧Many storage devices

2456‧‧‧記憶體裝置 2456‧‧‧Memory device

2458‧‧‧系統控制軟體 2458‧‧‧System Control Software

2490‧‧‧晶圓搬運系統 2490‧‧‧ Wafer Handling System

2502‧‧‧介電隔離層 2502‧‧‧Dielectric isolation layer

圖1示意地顯示根據本發明之實施例之範例性保形薄膜沉積(CFD)製程的時序圖。 1 is a timing diagram showing an exemplary conformal thin film deposition (CFD) process in accordance with an embodiment of the present invention.

圖2示意地顯示根據本發明之實施例之另一範例性CFD製程的時序圖。 FIG. 2 schematically shows a timing diagram of another exemplary CFD process in accordance with an embodiment of the present invention.

圖3示意地顯示根據本發明之實施例之另一範例性CFD製程的時序圖。 FIG. 3 schematically shows a timing diagram of another exemplary CFD process in accordance with an embodiment of the present invention.

圖4示意地顯示根據本發明之實施例之包含電漿處理循環之範例性CFD製程的時序圖。 4 is a timing diagram showing an exemplary CFD process including a plasma processing cycle in accordance with an embodiment of the present invention.

圖5顯示根據本發明之實施例所沉積薄膜的濕蝕刻速率比率與沉積溫度之間的範例相關性。 Figure 5 shows an example correlation between the wet etch rate ratio and the deposition temperature of a deposited film in accordance with an embodiment of the present invention.

圖6顯示根據本發明之實施例所沉積薄膜的濕蝕刻速率比率與薄膜應力之間的範例相關性。 Figure 6 shows an example correlation between the wet etch rate ratio and film stress of a deposited film in accordance with an embodiment of the present invention.

圖7顯示根據本發明之實施例所沉積薄膜的薄膜污染物濃度與沉積溫度之間的範例相關性。 Figure 7 shows an exemplary correlation between film contaminant concentration and deposition temperature for a deposited film in accordance with an embodiment of the present invention.

圖8示意地顯示包含複數間隙之非平面基板的範例橫剖面。 Figure 8 shows schematically an exemplary cross section of a non-planar substrate comprising a plurality of gaps.

圖9示意地顯示根據本發明之實施例之包含過渡至PECVD製程的範例性CFD製程的時序圖。 9 is a timing diagram showing an exemplary CFD process including a transition to a PECVD process in accordance with an embodiment of the present invention.

圖10示意地顯示包含鎖眼孔洞之間隙填充的範例橫剖面。 Figure 10 shows schematically an example cross section of a gap fill comprising a keyhole.

圖11示意地顯示根據本發明之實施例之包含原位蝕刻的範例性CFD製 程的時序圖。 Figure 11 is a schematic illustration of an exemplary CFD system including in-situ etching in accordance with an embodiment of the present invention. Timing diagram of the process.

圖12A示意地顯示凹入間隙填充輪廓之範例橫剖面。 Figure 12A schematically shows an example cross section of a recessed gap fill profile.

圖12B示意地顯示根據本發明之實施例於原位蝕刻製程期間圖12A的凹入間隙填充輪廓的範例橫剖面。 Figure 12B schematically illustrates an example cross-section of the recessed gap fill profile of Figure 12A during an in situ etch process in accordance with an embodiment of the present invention.

圖12C示意地顯示根據本發明之實施例在原位蝕刻之後的沉積製程期間圖12B的間隙填充輪廓的範例橫剖面。 Figure 12C schematically illustrates an example cross-section of the gap fill profile of Figure 12B during a deposition process after in-situ etch in accordance with an embodiment of the present invention.

圖13示意地顯示根據本發明之實施例的範例處理站。 Figure 13 schematically shows an example processing station in accordance with an embodiment of the present invention.

圖14示意地顯示根據本發明之實施例之包含複數處理站及一控制器的範例處理工具。 Figure 14 is a schematic illustration of an example processing tool including a plurality of processing stations and a controller in accordance with an embodiment of the present invention.

圖15示意地顯示根據本發明之實施例於包含原位蝕刻的CFD製程期間直通矽穿孔的範例橫剖面圖。 Figure 15 is a schematic cross-sectional view showing an example of a through-boring perforation during a CFD process including in-situ etching, in accordance with an embodiment of the present invention.

圖16圖例說明具有三維閘極結構之電晶體，其中源極和汲極係形成為難以藉由習知離子植入技術來摻雜之細薄垂直結構。 Figure 16 illustrates a transistor having a three-dimensional gate structure in which the source and drain lines are formed into a thin vertical structure that is difficult to do by conventional ion implantation techniques.

圖17以沿著x軸前進時間由左至右呈現基線CFD操作的順序。 Figure 17 shows the sequence of baseline CFD operations from left to right with advance time along the x-axis.

圖18及19繪示其中將摻雜物沉積在與下方基板的界面處、後接以摻雜物遞送散置其中之CFD循環、並且選擇性地用可為CFD氧化物薄膜之未摻雜保護「覆蓋」層完成之實施例。 18 and 19 illustrate a CFD cycle in which dopants are deposited at the interface with the underlying substrate, followed by dopant delivery, and optionally with undoped protection that can be a CFD oxide film. The implementation of the "overlay" layer.

圖20顯示用以合成CFD BSG/PSG薄膜之典型沉積組塊。 Figure 20 shows a typical deposition block used to synthesize a CFD BSG/PSG film.

圖21顯示在密集和分離的結構上之CFD薄膜的階梯覆蓋估計為~100%。 Figure 21 shows that the step coverage of CFD films on dense and isolated structures is estimated to be ~100%.

圖22呈現之SIMS資料顯示CFD薄膜中的平均硼濃度可調整在約0.5-3.5 wt%硼的範圍中。 The SIMS data presented in Figure 22 shows that the average boron concentration in the CFD film can be adjusted in the range of about 0.5-3.5 wt% boron.

半導體裝置的製造通常涉及：在一整合製程中，於非平面基板上沉積一或更多薄膜。在一些整合製程的實施態樣中，沉積與基板表面狀態一致之薄膜是有幫助的。例如，可在提高之閘極堆疊的頂部上沉積氮化矽薄膜作為用以保護少量摻雜源極和汲極區域免於受到後續之離子植入製程影響的間隔層。 The fabrication of semiconductor devices typically involves depositing one or more thin films on a non-planar substrate in an integrated process. In some implementations of integrated processes, it is helpful to deposit a film that is consistent with the surface state of the substrate. For example, a tantalum nitride film can be deposited on top of the raised gate stack as a spacer layer to protect a small amount of doped source and drain regions from subsequent ion implantation processes.

在間隔層沉積製程中，化學氣相沉積(CVD)製程可用以在非平面基板上 形成氮化矽薄膜，接著將該氮化矽薄膜加以非等向蝕刻以形成間隔層。然而，隨著閘極堆疊之間的距離減小，CVD氣相反應的質量傳輸限制可能導致「麵包條」(“bread-loafing”)沉積效應。如此效應通常展現在閘極堆疊的頂面處之較厚沉積、以及在閘極堆疊的底角處之較薄沉積。此外，因為一些晶粒可具有不同裝置密度的區域，所以晶圓表面範圍之質量傳輸效應可導致晶粒內和晶圓內的薄膜厚度差異。這些厚度差異可導致一些區域的過蝕刻及其他區域的蝕刻不足。這可能降低裝置表現及/或晶粒良率。 In a spacer layer deposition process, a chemical vapor deposition (CVD) process can be used on a non-planar substrate A tantalum nitride film is formed, which is then anisotropically etched to form a spacer layer. However, as the distance between the gate stacks decreases, the mass transfer limitations of the CVD gas phase reaction may result in a "bread-loafing" deposition effect. Such effects typically exhibit thicker deposition at the top surface of the gate stack and thinner deposition at the bottom corners of the gate stack. In addition, because some of the dies can have regions of different device densities, the mass transfer effects of the wafer surface range can result in film thickness variations within the dies and within the wafer. These thickness differences can result in over-etching of some areas and under-etching of other areas. This may reduce device performance and/or grain yield.

對應這些問題的一些方法涉及原子層沉積(ALD)。與其中使用熱活化氣相反應以沉積薄膜之CVD製程相比，ALD製程使用表面介導沉積反應在逐層基礎上沉積薄膜。在一ALD製程的範例中，使包含表面活性部位之群體的基板表面曝露至第一薄膜前驅物(P1)之氣相分佈。一些P1的分子可在包含P1的化學吸附物種及物理吸附分子之基板表面的頂上形成凝相。然後排空反應器以移除氣相及物理吸附P1使得僅化學吸附物種存留。然後將第二薄膜前驅物(P2)導入反應器以使一些P2的分子吸附至基板表面。可再次將反應器排空，此次係用以移除未結合的P2。隨後，提供至基板之熱能使吸附之P1和P2的分子之間的表面反應活化，從而形成薄膜層。最後，將反應器排空以移除反應副產物以及可能未反應的P1和P2，而結束ALD循環。可包含額外ALD循環以增長薄膜厚度。 Some methods corresponding to these problems involve atomic layer deposition (ALD). The ALD process deposits a thin film on a layer-by-layer basis using a surface-mediated deposition reaction as compared to a CVD process in which a thermally activated gas phase reaction is used to deposit a thin film. In an example of an ALD process, the surface of the substrate comprising the population of surface active sites is exposed to the gas phase distribution of the first film precursor (P1). Some of the molecules of P1 can form a condensed phase on top of the surface of the substrate containing the chemisorbed species of P1 and the physically adsorbed molecules. The reactor is then vented to remove the gas phase and physically adsorb P1 such that only chemisorbed species remain. The second film precursor (P2) is then introduced into the reactor to adsorb some of the P2 molecules to the substrate surface. The reactor can be emptied again, this time to remove unbound P2. Subsequently, the heat supplied to the substrate activates the surface reaction between the adsorbed molecules of P1 and P2 to form a thin film layer. Finally, the reactor is vented to remove reaction byproducts and possibly unreacted P1 and P2, ending the ALD cycle. Additional ALD cycles can be included to increase film thickness.

依據前驅物施用步驟的曝露時間及前驅物的黏附係數，在一實例中每一ALD循環可沉積介於二分之一埃及三埃厚之薄膜層。因此，當沉積大於數奈米(nanometers)厚的薄膜時，ALD製程會很耗時。又，一些前驅物可具有長曝露時間以沉積保形薄膜，而其亦可減低晶圓吞吐量時間。 Depending on the exposure time of the precursor application step and the adhesion coefficient of the precursor, in one example each of the ALD cycles may deposit a film layer of one-half Egypt three angstroms thick. Therefore, the ALD process can be time consuming when depositing films larger than a few nanometers. Also, some precursors may have a long exposure time to deposit a conformal film, which may also reduce wafer throughput time.

亦可將保形薄膜沉積在平面基板上。例如，可由包含交替薄膜類型之平面堆疊形成用於微影圖案化應用之抗反射層。如此之抗反射層可為大約100至1000埃厚，因而使得ALD製程比CVD製程較不具吸引力。然而，如此之抗反射層亦可具有比許多CVD製程可提供較為低的晶圓內厚度差異之允差。例如，600埃厚的抗反射層可容許小於3埃的厚度範圍。 A conformal film can also be deposited on a planar substrate. For example, an anti-reflective layer for lithographic patterning applications can be formed from a planar stack comprising alternating thin film types. Such an anti-reflective layer can be about 100 to 1000 angstroms thick, making the ALD process less attractive than the CVD process. However, such an anti-reflective layer can also have a tolerance that provides a lower intra-wafer thickness difference than many CVD processes. For example, a 600 angstrom thick anti-reflective layer can tolerate a thickness range of less than 3 angstroms.

因此，在本文中提供之各種實施例提供用於在非平面及平面基板上之電漿活化保形薄膜沉積(CFD)的製程及設備。這些實施例包含部份但非全部 CFD製程中所採用的各種特徵。這些特徵之中為：(1)排除或減少自反應腔室「清除」反應物一者或二者所需的時間；(2)提供至少一反應物的連續流量，同時使一不同反應物間歇地流入反應腔室中；(3)在反應物其中一者存在於氣相中時，而不是當自反應腔室清除所有反應物時激發電漿；(4)用電漿處理所沉積之CFD薄膜以修改薄膜特性；(5)在藉由CFD沉積薄膜的第一部份之後，通常在相同的反應腔室中藉由PECVD來沉積薄膜的一部份；(6)在CFD階段之間蝕刻部份沉積之薄膜；以及(7)在僅薄膜沉積循環的情況下，藉由散佈摻雜物遞送循環來摻雜CFD薄膜。當然，此列表並非詳盡無遺。當考量到說明書的剩餘部份，則各種其他CFD特徵將顯而易見。 Accordingly, various embodiments provided herein provide processes and apparatus for plasma activated conformal thin film deposition (CFD) on non-planar and planar substrates. These embodiments include some but not all Various features used in the CFD process. Among these features are: (1) eliminating or reducing the time required to "clear" one or both of the reactants from the reaction chamber; (2) providing a continuous flow of at least one reactant while allowing a different reactant to be intermittent Inflow into the reaction chamber; (3) when one of the reactants is present in the gas phase, rather than exciting the plasma when all reactants are removed from the reaction chamber; (4) treating the deposited CFD with plasma a film to modify film properties; (5) after depositing a first portion of the film by CFD, typically depositing a portion of the film by PECVD in the same reaction chamber; (6) etching between CFD stages Partially deposited film; and (7) doping the CFD film by spreading the dopant delivery cycle in the case of only the film deposition cycle. Of course, this list is not exhaustive. Various other CFD features will be apparent when considering the remainder of the specification.

CFD「循環」的概念與本文中各種實施例的討論有關。通常一循環係執行一次表面沉積反應所需之最小一組操作。一循環的結果係在基板表面上產生至少一部份薄膜層。通常，CFD循環將僅包含那些遞送及吸附每一反應物至基板表面、且隨後使那些吸附之反應物發生反應以形成部份薄膜層之必要步驟。當然，該循環可包含一些輔助步驟，例如清除反應物或副產物之一者及/或處理所沉積之部份薄膜。一般而言，一循環僅包含唯一的操作序列之實例。作為一範例，一循環可包含以下操作：(i)反應物A之遞送/吸附；(ii)反應物B之遞送/吸附；(iii)將B清除至反應腔室外；以及(iv)施加電漿以驅動A和B之表面反應，從而在該表面上形成部份薄膜層。 The concept of CFD "loops" is related to the discussion of various embodiments herein. Usually one cycle is the minimum set of operations required to perform a surface deposition reaction. The result of a cycle is the creation of at least a portion of the film layer on the surface of the substrate. Typically, the CFD cycle will only include those steps necessary to deliver and adsorb each reactant to the surface of the substrate and subsequently react those adsorbed reactants to form a portion of the thin film layer. Of course, the cycle may include additional steps such as scavenging one of the reactants or by-products and/or treating the deposited portion of the film. In general, a loop contains only instances of a unique sequence of operations. As an example, a cycle can include the following operations: (i) delivery/adsorption of reactant A; (ii) delivery/adsorption of reactant B; (iii) scavenging B to the outside of the reaction chamber; and (iv) applying electricity The slurry drives the surface reactions of A and B to form a portion of the film layer on the surface.

此刻將進一步討論以上提及之七項特徵。在以下敘述中，考量其中使一或更多反應物吸附至基板表面、並隨後藉由與電漿相互作用而反應以便在該表面上形成薄膜之CFD反應。 The seven features mentioned above will be further discussed at this moment. In the following description, a CFD reaction in which one or more reactants are adsorbed to the surface of the substrate and then reacted by interaction with the plasma to form a thin film on the surface is considered.

特徵1(反應物之連續流量)-使反應物A在CFD循環之一或更多部份期間持續流入反應腔室，然而反應物通常不會流入習知ALD中。在習知ALD中，只為了使反應物吸附至基板表面上的目的而流入反應物A。在ALD循環的其他階段，不流入反應物A。然而依照本文中所述之一些CFD實施例，反應物A不僅在與其吸附相關聯之階段期間流入，也在CFD循環之執行其他非吸附A的操作之階段期間流入。例如在許多實施例中，在該設備正在施用第二反應物(本文中的反應物B)時，使反應物A流入反應器中。因此，於至少一部份之CFD循環期間，反應物A和B共存於氣相中。此外，當施 加電漿以驅動在基板表面處之反應時，可流入反應物A。注意到連續流入之反應物可連同例如氬之氣體載體遞送至反應腔室。 Feature 1 (continuous flow of reactants) - allows reactant A to continue to flow into the reaction chamber during one or more portions of the CFD cycle, however the reactants typically do not flow into conventional ALD. In the conventional ALD, the reactant A is flown only for the purpose of adsorbing the reactant onto the surface of the substrate. At other stages of the ALD cycle, reactant A does not flow. However, in accordance with some of the CFD embodiments described herein, reactant A not only flows during the phase associated with its adsorption, but also during the phase of the CFD cycle that performs other non-adsorbed A operations. For example, in many embodiments, reactant A is passed to the reactor while the apparatus is applying a second reactant (reactant B herein). Thus, during at least a portion of the CFD cycle, reactants A and B coexist in the gas phase. In addition, when When the plasma is applied to drive the reaction at the surface of the substrate, the reactant A can flow. It is noted that the continuously flowing reactants can be delivered to the reaction chamber along with a gaseous carrier such as argon.

連續流量實施例之優點為所建立之流量避免由與流量開啟和關閉相關聯之流量的暫態初始化及穩定化所引起之延遲及流量差異。 An advantage of the continuous flow embodiment is that the established traffic avoids delays and flow differences caused by transient initialization and stabilization of traffic associated with traffic on and off.

作為一具體範例，可藉由使用主要反應物(有時稱為「固體成分」前驅物，或於此範例中簡稱「反應物B」)的保形薄膜沉積製程來沉積氧化物薄膜。二(第三丁基胺基)矽烷(BTBAS，bis(tert-butylamino)silane)係一如此主要反應物。在此範例中，氧化物沉積製程涉及如氧或一氧化二氮之氧化劑的遞送，該氧化劑在不同的曝露階段於主要反應物的遞送期間初始並持續流入。氧化劑亦於不同的電漿曝露階段期間持續流入。參見例如描述於圖1之序列。為了比較，在習知ALD製程中，當固體成分前驅物遞送至反應器時，氧化劑的流量將停止。舉例而言，當遞送反應物B時，則反應物A的流量將停止。 As a specific example, an oxide film can be deposited by a conformal thin film deposition process using a primary reactant (sometimes referred to as a "solid component" precursor, or simply "reactant B" in this example). Bis(tert-butylamino)silane (BTBAS, bis(tert-butylamino)silane) is one such major reactant. In this example, the oxide deposition process involves the delivery of an oxidant such as oxygen or nitrous oxide that initially and continuously flows during delivery of the main reactants at different stages of exposure. The oxidant also continues to flow during different plasma exposure stages. See, for example, the sequence depicted in Figure 1. For comparison, in conventional ALD processes, when a solid component precursor is delivered to the reactor, the flow of oxidant will cease. For example, when reactant B is delivered, then the flow of reactant A will cease.

在一些具體範例中，持續流入之反應物係「輔助」反應物。如同本文中所使用，「輔助」反應物係不為主要反應物以外之任何反應物。如以上建議，主要反應物包含在室溫下為固態之元素，該元素對藉由CFD形成之薄膜有幫助。如此元素的例子為金屬(例如鋁和鈦)、半導體(例如矽和鍺)、以及非金屬或準金屬(例如硼)。輔助反應物的例子包括氧、臭氧、氫、一氧化碳、一氧化二氮、氨、烷基胺、及其類似者。 In some specific examples, the continuously flowing reactants are "auxiliary" reactants. As used herein, an "auxiliary" reactant is not any reactant other than the primary reactant. As suggested above, the primary reactants contain elements that are solid at room temperature and which contribute to the formation of films by CFD. Examples of such elements are metals (such as aluminum and titanium), semiconductors (such as tantalum and niobium), and non-metal or metalloids (such as boron). Examples of auxiliary reactants include oxygen, ozone, hydrogen, carbon monoxide, nitrous oxide, ammonia, alkylamines, and the like.

持續流入之反應物能以固定流速、或以變動但受控之流速來提供。在後者情況下，作為一範例，於曝露階段期間當主要反應物遞送時，可降低輔助反應物之流速。舉例而言，在氧化物沉積中，於整個沉積序列期間氧化劑(例如氧或一氧化二氮)可持續流入，但當主要反應物(例如BTBAS)遞送時，可降低其流速。此增大BTBAS於其施用期間之分壓，從而減少使基板表面飽和所需之曝露時間。就在激發電漿前，可增大氧化劑的流量以降低於電漿曝露階段期間BTBAS存在的可能性。再一些實施例中，持續流入之反應物在二或更多沉積循環的過程中以變動之流速流動。舉例而言，反應物可於第一CFD循環期間以第一流速流動，並且於第二CFD循環期間以第二流速流動。 The continuously flowing reactants can be provided at a fixed flow rate, or at a varying but controlled flow rate. In the latter case, as an example, the flow rate of the auxiliary reactant can be reduced when the primary reactant is delivered during the exposure phase. For example, in oxide deposition, an oxidant (eg, oxygen or nitrous oxide) can continue to flow throughout the deposition sequence, but when a primary reactant (eg, BTBAS) is delivered, its flow rate can be reduced. This increases the partial pressure of the BTBAS during its application, thereby reducing the exposure time required to saturate the surface of the substrate. Just prior to energizing the plasma, the flow of oxidant can be increased to reduce the likelihood of the presence of BTBAS during the plasma exposure phase. In still other embodiments, the continuously flowing reactants flow at varying flow rates during two or more deposition cycles. For example, the reactants can flow at a first flow rate during the first CFD cycle and at a second flow rate during the second CFD cycle.

當採用多數反應物且其中一者之流量為連續時，於部份CFD循環期間其至少二者將共存於氣相中。同樣地，在遞送第一反應物之後而沒有執行清除步驟時，二反應物將共存。因此，採用在不施加活化能的氣相中不明顯互相反應之反應物可能很重要。通常，反應物應不反應直到存在於基板表面上、且曝露至電漿或另一適當的非熱活化條件為止。選取如此之反應物涉及至少(1)所期望反應之熱力學合適性(thermodynamic favorability)(Gibb之自由能<0)、以及(2)該反應的活化能(其應足夠大以致於在所期望之沉積溫度下的反應可以忽略)之考量。 When a majority of the reactants are employed and one of the flows is continuous, at least two of them will coexist in the gas phase during the partial CFD cycle. Likewise, the two reactants will coexist after the first reactant is delivered without performing the scavenging step. Therefore, it may be important to employ a reactant that does not significantly react with each other in a gas phase in which no activation energy is applied. Generally, the reactants should not react until they are present on the surface of the substrate and exposed to the plasma or another suitable non-thermal activation condition. The selection of such a reactant involves at least (1) the thermodynamic favorability of the desired reaction (Gibb free energy < 0), and (2) the activation energy of the reaction (which should be large enough to be desired) The reaction at the deposition temperature is negligible).

特徵2(減少或排除清除步驟)-在一些實施例中，該製程免除或減少與通常會在習知ALD中執行之清除步驟相關聯的時間。習知ALD中，在每一反應物遞送及吸附至基板表面上之後執行各別的清除步驟。在習知ALD清除步驟中，極少或沒有吸附或反應發生。在CFD循環中，在遞送反應物至少一者之後減少或排除清除步驟。圖1呈現其中移除清除步驟之製程序列的範例。不執行自反應腔室清除反應物A之清除步驟。在一些情況下，在CFD循環中遞送第一反應物之後不執行清除步驟，但是在遞送第二或最後遞送的反應物之後選擇性地執行清除步驟。 Feature 2 (reducing or eliminating the clearing step) - In some embodiments, the process exempts or reduces the time associated with the clearing step that would normally be performed in conventional ALD. In conventional ALD, a separate removal step is performed after each reactant is delivered and adsorbed onto the surface of the substrate. In the conventional ALD removal step, little or no adsorption or reaction occurs. In the CFD cycle, the removal step is reduced or eliminated after at least one of the reactants is delivered. Figure 1 presents an example of a program column in which the removal step is removed. The removal step of the reactant A removal from the reaction chamber is not performed. In some cases, the scavenging step is not performed after delivery of the first reactant in the CFD cycle, but the scavenging step is selectively performed after delivery of the second or last delivered reactant.

CFD「清除」步驟或階段的概念出現在本文中所討論的各種實施例中。一般而言，清除階段自反應腔室移除或清除氣相反應物之一者，並且通常只在如此反應物之遞送完成之後發生。換言之，反應物於清除階段期間不再遞送至反應腔室。然而，反應物於清除階段期間仍然吸附在基板表面上。通常，該清除用以在反應物吸附在基板表面上達到所期望之程度後移除腔室中任何殘留的氣相反應物。清除階段亦可自基板表面移除微弱吸附之物種(例如一些前驅物配子或反應副產物)。在ALD中，清除階段已被視為對於防止二反應物之氣相交互作用，或一反應物與用於表面反應的熱、電漿、或其他驅動力之交互作用是必要的。一般而言，並且除非於本文中另外指明，否則清除階段可藉由(i)排空反應腔室，及/或(ii)使不包含欲清除物種之氣體流入通過反應腔室來實現。在(ii)的情況下，如此氣體可例如為惰性氣體或輔助反應物(如持續流入之輔助反應物)。 The concept of a CFD "clear" step or phase appears in the various embodiments discussed herein. In general, the purge phase removes or removes one of the gas phase reactants from the reaction chamber and typically occurs only after delivery of such reactants is complete. In other words, the reactants are no longer delivered to the reaction chamber during the purge phase. However, the reactants are still adsorbed on the surface of the substrate during the scavenging phase. Typically, the purge is used to remove any residual gas phase reactants in the chamber after the reactants have been adsorbed onto the surface of the substrate to the desired extent. The scavenging phase also removes weakly adsorbed species (eg, some precursor gametes or reaction byproducts) from the surface of the substrate. In ALD, the purge phase has been considered necessary to prevent vapor phase interaction of the two reactants, or the interaction of a reactant with heat, plasma, or other driving forces for surface reactions. In general, and unless otherwise indicated herein, the purge phase can be accomplished by (i) evacuating the reaction chamber, and/or (ii) flowing a gas that does not contain the species to be purged through the reaction chamber. In the case of (ii), such a gas may, for example, be an inert gas or an auxiliary reactant (such as an auxiliary reactant continuously flowing).

清除階段之排除可在具有或不具有其他反應物之連續流量的情況下來 實現。在圖1繪示之實施例中，並非將反應物A清除出去，而是在其吸附至基板表面上完成之後持續流入(由圖中之參考數字130圖示說明)。 Elimination of the purge phase can occur with or without continuous flow of other reactants achieve. In the embodiment illustrated in Figure 1, the reactant A is not removed, but continues to flow after it is adsorbed onto the surface of the substrate (illustrated by reference numeral 130 in the figure).

在其中採用二或更多反應物之各種實施例中，使其清除步驟被排除或減少之反應物係輔助反應物。作為一範例，輔助反應物為氧化劑或氮源，並且主要反應物為含有矽、硼、或鍺之前驅物。當然，主要反應物之清除也可減少或排除。在一些範例中，在遞送輔助反應物之後不執行清除步驟，但在遞送主要反應物之後選擇性地執行清除步驟。 In various embodiments in which two or more reactants are employed, the reactants that are excluded or reduced by the scavenging step are auxiliary reactants. As an example, the auxiliary reactant is an oxidant or a nitrogen source, and the primary reactant is a precursor containing cerium, boron, or cerium. Of course, the removal of major reactants can also be reduced or eliminated. In some examples, the scavenging step is not performed after delivery of the co-reactant, but the scavenging step is selectively performed after delivery of the primary reactant.

如所提及，清除階段不必完全排除，而是與習知ALD製程中的清除階段相比僅為減少持續時間。舉例而言，於CFD循環期間反應物(如輔助反應物)之清除階段可執行持續約0.2秒或更短，例如持續約0.001至0.1秒。 As mentioned, the purge phase need not be completely excluded, but is only a reduction in duration compared to the purge phase in the conventional ALD process. For example, the purge phase of a reactant (eg, an auxiliary reactant) during a CFD cycle can be performed for about 0.2 seconds or less, for example, for about 0.001 to 0.1 seconds.

特徵3(在反應物之一者存在於氣相中時激發電漿)-有此特徵的情況下，在已將所有反應物自反應腔室清除之前激發電漿。此與其中僅在氣相反應物不再存在於反應腔室中之後提供電漿活化或其他反應驅動操作之習知ALD相反。注意到當反應物A在如圖1所示之CFD循環的電漿部份期間持續流入時，此特徵將必然存在。然而，所揭露之實施例不受限於此方式。一或更多反應物可於CFD循環的電漿部份期間流入而不必在CFD循環期間持續流入。此外，於電漿活化期間呈氣相存在之反應物可為主要反應物或輔助反應物(當CFD循環中採用二個以上反應物時)。 Feature 3 (exciting plasma when one of the reactants is present in the gas phase) - With this feature, the plasma is excited before all of the reactants have been purged from the reaction chamber. This is in contrast to conventional ALD in which plasma activation or other reaction driven operation is provided only after the gas phase reactant is no longer present in the reaction chamber. It is noted that this characteristic will necessarily exist when reactant A continues to flow during the plasma portion of the CFD cycle as shown in FIG. However, the disclosed embodiments are not limited in this manner. One or more reactants may flow during the plasma portion of the CFD cycle without having to continue to flow during the CFD cycle. In addition, the reactants present in the gas phase during plasma activation may be primary or secondary reactants (when more than two reactants are employed in the CFD cycle).

舉例而言，一序列可為(i)導入反應物A、(ii)清除A、(iii)導入反應物B同時在B流動時撞擊電漿、以及(iv)清除。在如此之實施例中，該製程採用來自氣相之電漿活化反應物物種。此為其中CFD不限制在連續步驟之序列的一般範例。 For example, a sequence can be (i) introduction of reactant A, (ii) removal of A, (iii) introduction of reactant B while impinging on plasma as B flows, and (iv) removal. In such an embodiment, the process employs a plasma activated reactant species from the gas phase. This is a general example in which the CFD is not limited to the sequence of successive steps.

若在將固體成分前驅物(主要反應物)提供至反應器時的期間提供活化電漿，則階梯覆蓋可能變得較不保形，但沉積速率通常將增加。然而，若電漿活化僅於遞送一輔助反應物期間發生，則情況未必如此。電漿可活化氣相輔助成分以使其更易反應，並從而增加其在保形薄膜沉積反應中之反應性。在一些實施例中，在沉積如氧化物、氮化物、或碳化物之含矽薄膜時採用此特徵。 If the activated plasma is provided during the supply of the solid component precursor (primary reactant) to the reactor, the step coverage may become less conformal, but the deposition rate will generally increase. However, this is not necessarily the case if plasma activation occurs only during the delivery of an auxiliary reactant. The plasma activates the gas phase auxiliary component to make it more reactive and thereby increase its reactivity in the conformal film deposition reaction. In some embodiments, this feature is employed in the deposition of a ruthenium containing film such as an oxide, nitride, or carbide.

特徵4(沉積CFD薄膜之電漿處理)-在這些實施例中，電漿在保形薄膜 沉積製程中可作為二或更多作用。其作用之一為在每一CFD循環期間活化或驅動薄膜形成反應。其另一作用為在一或更多CFD循環過後CFD薄膜已部份或完全沉積之後處理該薄膜。電漿處理欲修改一或更多薄膜特性。通常(儘管非必然)電漿處理階段係在不同於那些用以活化薄膜形成反應(即驅動薄膜形成反應)之條件下實施。作為一範例，電漿處理可在還原或氧化環境之存在下(例如氫或氧之存在下)執行，然而在CFD循環的活化部份期間情況未必如此。 Feature 4 (plasma treatment of deposited CFD film) - in these examples, the plasma is in conformal film It can act as two or more in the deposition process. One of its functions is to activate or drive the film formation reaction during each CFD cycle. Another effect is that the film is treated after the CFD film has been partially or completely deposited after one or more CFD cycles. Plasma processing is intended to modify one or more film properties. Usually, although not necessarily, the plasma treatment stage is carried out under conditions different from those used to activate the film formation reaction (i.e., drive the film formation reaction). As an example, the plasma treatment can be performed in the presence of a reducing or oxidizing environment (e.g., in the presence of hydrogen or oxygen), although this is not necessarily the case during the activated portion of the CFD cycle.

電漿處理操作可在CFD製程的每一循環期間、在每隔一循環期間、或一些較不頻繁的基礎上執行。該處理可配合固定數目之CFD循環在規律間隔上執行，或其可變動地(例如以變動之CFD循環間隔)或甚至隨機地執行。在典型的範例中，執行數個CFD循環之薄膜沉積以達到適當的薄膜厚度，並隨後採用電漿處理。之後，於再次執行該處理之前，在沒有電漿處理的情況下再次執行數個CFD循環之薄膜沉積。後接電漿處理(薄膜修改)的此x數目個CFD循環之超級序列可重複直到藉由CFD完全形成薄膜為止。 The plasma processing operation can be performed during each cycle of the CFD process, during every other cycle, or on a less frequent basis. This process can be performed at regular intervals with a fixed number of CFD cycles, or it can be varied (e.g., at varying CFD cycle intervals) or even randomly. In a typical example, film deposition of several CFD cycles is performed to achieve a suitable film thickness, and then plasma treatment. Thereafter, before the process is performed again, film deposition of several CFD cycles is performed again without plasma treatment. The super sequence of the x number of CFD cycles followed by the plasma treatment (film modification) can be repeated until the film is completely formed by CFD.

在一些實施例中，可在CFD循環的初始化之前執行電漿處理以修改CFD薄膜沉積於其上之表面的一或更多特性。在各種實施例中，該表面係由矽(摻雜或未摻雜)或含矽材料製成。修改過的表面更能夠產生與隨後沉積之CFD薄膜的高品質介面。該介面可經由例如減少缺陷等等而提供例如良好附著性、可靠電特性。 In some embodiments, the plasma treatment can be performed prior to the initialization of the CFD cycle to modify one or more characteristics of the surface on which the CFD film is deposited. In various embodiments, the surface is made of tantalum (doped or undoped) or tantalum-containing material. The modified surface is more capable of producing a high quality interface with subsequently deposited CFD films. The interface can provide, for example, good adhesion, reliable electrical characteristics, such as by reducing defects or the like.

在CFD前的基板之預處理不限制在任何特定的電漿處理。在一些實施例中，預處理涉及在氦、氫、氬、氮、氫/氮形成氣體、及/或氨的存在下曝露至氫電漿、氮電漿、氮/氫電漿、氨電漿、氬電漿、氦電漿、氦回火、氫回火、氨回火、以及UV硬化。電漿處理可用包含(然而不限於)微波、ICP遠端、直接、以及其他本領域中具有通常技術者熟知的各種電漿產生器來實現。 Pretreatment of the substrate prior to CFD is not limited to any particular plasma treatment. In some embodiments, the pretreatment involves exposure to hydrogen plasma, nitrogen plasma, nitrogen/hydrogen plasma, ammonia plasma in the presence of helium, hydrogen, argon, nitrogen, hydrogen/nitrogen forming gases, and/or ammonia. , argon plasma, tantalum plasma, helium tempering, hydrogen tempering, ammonia tempering, and UV hardening. Plasma treatment can be accomplished with, but is not limited to, microwaves, ICP remotes, direct, and other plasma generators well known in the art as is well known in the art.

總體而言，該處理可出現在CFD循環之前、期間、以及之後。當出現在CFD循環期間時，可對於適當的沉積條件選取該處理之頻率。通常，該處理將不比每循環一次更頻繁地出現。 In general, this process can occur before, during, and after the CFD cycle. When present during a CFD cycle, the frequency of the process can be selected for appropriate deposition conditions. Typically, this process will not occur more frequently than once per cycle.

作為一範例，考量用以從具有一些碳存在之前驅物形成氮化矽的製 程。如此前驅物的例子包含BTBAS。碳出現在前驅物中的結果為如此沉積之氮化物薄膜包含一些碳雜質，其可降低氮化物的電特性。為了抵消此問題，在含碳前驅物的情況下於數個CFD循環後，在電漿存在下使部份沉積之薄膜曝露至氫以減少並最終移除碳雜質。 As an example, consider the system for forming tantalum nitride from a precursor with some carbon present. Cheng. An example of such a precursor includes BTBAS. The result of the presence of carbon in the precursor is that the nitride film thus deposited contains some carbon impurities which reduce the electrical properties of the nitride. To counteract this problem, after several CFD cycles in the presence of a carbonaceous precursor, a portion of the deposited film is exposed to hydrogen in the presence of a plasma to reduce and eventually remove carbon impurities.

可選取用以修改薄膜表面之電漿條件以達到所期望之薄膜特性及/或成分的改變。在用於所期望之修改的可選擇及/或修改的電漿條件之中為氧化條件、還原條件、蝕刻條件、用於產生電漿之功率、用於產生電漿之頻率、使用二或更多頻率來產生電漿、電漿密度、電漿和基板之間的距離等等。可藉由電漿處理加以修改之CFD薄膜特性的例子包括內部薄膜應力、抗蝕刻性、密度、硬度、光學特性(折射率、反射性、光密度等等)、介電常數、碳含量、電特性(Vfb散佈等等)、及其類似者。 The plasma conditions used to modify the surface of the film can be selected to achieve the desired change in film properties and/or composition. Among the selectable and/or modified plasma conditions for the desired modification are oxidizing conditions, reducing conditions, etching conditions, power for generating plasma, frequency for generating plasma, use two or more Multiple frequencies to produce plasma, plasma density, distance between plasma and substrate, and the like. Examples of CFD film properties that can be modified by plasma treatment include internal film stress, etch resistance, density, hardness, optical properties (refractive index, reflectivity, optical density, etc.), dielectric constant, carbon content, electricity Characteristics (Vfb spread, etc.), and the like.

在一些實施例中，採用除了電漿處理以外的處理來修改所沉積薄膜之特性。如此之處理包括電磁輻射處理、熱處理(例如回火或高溫脈衝)、及其類似者。這些處理之任一者可單獨或結合另一處理(包括電漿處理)來執行。如此處理之任一者可作為任一上述之電漿處理的替代。在一些具體實施例中，該處理涉及使薄膜曝露至紫外線輻射。如以下所述，在一具體實施例中，該方法涉及原位(即於薄膜的形成期間)施加UV輻射至氧化物CFD薄膜或氧化物之後沉積。如此之處理用以減少或消除缺陷結構，並提供改善之電性效能。 In some embodiments, processing other than plasma processing is employed to modify the properties of the deposited film. Such treatments include electromagnetic radiation treatment, heat treatment (eg, tempering or high temperature pulses), and the like. Either of these processes can be performed alone or in combination with another process, including plasma processing. Any of such treatments can be used as an alternative to any of the above described plasma treatments. In some embodiments, the treatment involves exposing the film to ultraviolet radiation. As described below, in one embodiment, the method involves depositing UV radiation to an oxide CFD film or oxide in situ (i.e., during formation of the film). Such treatment is used to reduce or eliminate defective structures and to provide improved electrical performance.

在一些具體實施例中，可將UV處理與電漿處理結合。此二操作可同時或相繼執行。在相繼的選項中，UV操作選擇性地首先發生。在同時的選項中，該二處理可由各自的源(例如用於電漿之RF電源與用於UV之燈)、或由單一源(如產生作為UV輻射之副產物的氦電漿)提供。 In some embodiments, UV treatment can be combined with plasma treatment. These two operations can be performed simultaneously or sequentially. In successive options, UV operation selectively occurs first. In a simultaneous option, the two treatments may be provided by a respective source (eg, an RF power source for plasma and a lamp for UV), or a single source (eg, a tantalum plasma that produces a by-product of UV radiation).

特徵5(藉由CFD沉積並隨後過渡至PECVD)-在如此之實施例中，所完成之薄膜係部份藉由CFD且部份藉由如PECVD之CVD製程而產生。通常，雖然並非必要，但若先執行沉積製程的CFD部份，則其次執行PECVD部份。混合之CFD/CVD製程可改善關於在單獨CVD的情況下所見之階梯覆蓋，並且額外改善關於在單獨CFD的情況下所見之沉積速率。在一些情況下，在一CFD反應物流入時施加電漿或其他活化作用以產生寄生CVD操 作，並從而達到更高的沉積速率、不同等級的薄膜等等。 Feature 5 (deposited by CFD and then transitioned to PECVD) - in such an embodiment, the completed film portion is produced by CFD and partially by a CVD process such as PECVD. Usually, although not necessary, if the CFD portion of the deposition process is performed first, the PECVD portion is performed second. The hybrid CFD/CVD process can improve the step coverage seen with CVD alone and additionally improve the deposition rate seen with individual CFDs. In some cases, plasma or other activation is applied to create a parasitic CVD operation when a CFD reaction is introduced. Work, and thus achieve higher deposition rates, different grades of film, and the like.

在一些實施例中，可採用二或更多CFD階段及/或可採用二或更多CVD階段。舉例而言，可藉由CFD沉積薄膜的初始部份、接著藉由CVD沉積薄膜中間部份、並且藉由CFD沉積薄膜的最後部份。在如此實施例中，在藉由CFD沉積薄膜的稍後部份之前，可能需要如藉由電漿處理或蝕刻來修改薄膜的CVD部份。 In some embodiments, two or more CFD stages may be employed and/or two or more CVD stages may be employed. For example, the initial portion of the film can be deposited by CFD, followed by deposition of the intermediate portion of the film by CVD, and the final portion of the film deposited by CFD. In such an embodiment, prior to depositing a later portion of the film by CFD, it may be desirable to modify the CVD portion of the film, such as by plasma processing or etching.

可在CFD和CVD階段之間採用過渡階段。在如此之過渡階段所採用的條件不同於那些在CFD或CVD階段所採用的條件。通常(儘管非必然)該條件允許同時的CFD表面反應與CVD型氣相反應。過渡階段通常涉及曝露至例如可為脈衝式之電漿。又，過渡階段可涉及以低流速(即明顯低於該製程之對應CFD階段中所採用速率之速率)遞送一或更多反應物。 A transition phase can be employed between the CFD and CVD phases. The conditions used in such a transition phase are different from those used in the CFD or CVD phase. Usually (although not necessarily) this condition allows simultaneous CFD surface reactions to react with CVD type gas phase. The transition phase typically involves exposure to, for example, a pulsed plasma. Again, the transition phase can involve delivering one or more reactants at a low flow rate (ie, at a rate that is significantly lower than the rate employed in the corresponding CFD stage of the process).

特徵6(藉由CFD沉積、蝕刻、並隨後更藉由CFD沉積)-在如此之實施例中，執行CFD沉積持續一或更多循環(通常為數次循環)，並隨後蝕刻所產生之薄膜以移除例如一些位於或接近凹部入口(尖端)之過量薄膜，後接更多CFD沉積的循環。在沉積之薄膜中的結構特徵之其他範例可用類似方式加以蝕刻。為此製程選取之蝕刻劑將取決於欲蝕刻之材料。在一些情況下，可用含氟蝕刻劑(例如NF3)或氫來執行蝕刻操作。 Feature 6 (deposited by CFD, etched, and then further deposited by CFD) - in such an embodiment, CFD deposition is performed for one or more cycles (typically several cycles) and the resulting film is subsequently etched Excess membranes, for example at or near the inlet (tip) of the recess, are removed, followed by a more CFD deposition cycle. Other examples of structural features in the deposited film can be etched in a similar manner. The etchant selected for this process will depend on the material to be etched. In some cases, the etching operation can be performed with a fluorine-containing etchant such as NF 3 or hydrogen.

在一些實施例中，採用遠端電漿以產生蝕刻劑。一般而言，遠端電漿以比直接電漿更等向的方式蝕刻。遠端電漿通常提供相對高的自由基分率至基板。這些自由基的反應性可隨凹部內的垂直位置而變化。在特徵部的頂部，自由基較集中且因此將以較高的速率蝕刻，而更往凹部下方且在底部處，一些自由基將喪失且因而其將以較低的速率蝕刻。這當然係用以應對過多沉積物出現在凹部開口的問題所期望之反應性曲線。於蝕刻中使用遠端電漿的額外益處為電漿相對和緩且因此不太會損壞基板層。這在下方基板層易受氧化或其他損壞影響時特別有利。 In some embodiments, a distal plasma is employed to produce an etchant. In general, the far end plasma is etched in a more isotropic manner than the direct plasma. The far end plasma typically provides a relatively high free radical fraction to the substrate. The reactivity of these free radicals can vary with the vertical position within the recess. At the top of the feature, the free radicals are more concentrated and will therefore etch at a higher rate, while below the recess and at the bottom some of the free radicals will be lost and thus they will etch at a lower rate. This is of course the reactivity curve desired to cope with the problem of excessive deposits appearing in the opening of the recess. An additional benefit of using a remote plasma in the etch is that the plasma is relatively gentle and therefore less likely to damage the substrate layer. This is particularly advantageous when the underlying substrate layer is susceptible to oxidation or other damage.

特徵7(以額外反應物修改薄膜成分)-本文中所提出的許多範例涉及採用一或二反應物之CFD製程。此外，許多範例在每一CFD循環採用相同的反應物。然而，情況未必如此。首先，許多CFD製程可採用三或更多反應物。例子包括(i)使用乙硼烷、六氟化鎢、和氫作為反應物之鎢CFD，以及(ii) 使用乙硼烷、BTBAS、和氧作為反應物之氧化矽CFD。可將乙硼烷從生長中的薄膜移除、或若適當的話可使其結合至該薄膜中。 Feature 7 (Modifying the Film Composition with Additional Reactants) - Many of the examples presented herein relate to CFD processes employing one or two reactants. In addition, many examples use the same reactants for each CFD cycle. However, this is not necessarily the case. First, many CFD processes can employ three or more reactants. Examples include (i) tungsten CFD using diborane, tungsten hexafluoride, and hydrogen as reactants, and (ii) Cerium oxide CFD using diborane, BTBAS, and oxygen as reactants. The diborane can be removed from the growing film or, if appropriate, incorporated into the film.

此外，一些範例可在僅一些CFD循環中採用額外反應物。在如此之範例中，基本CFD製程循環僅採用該反應物來產生基礎薄膜成分(例如氧化矽或碳化矽)。此基本製程在所有或幾乎所有CFD循環中執行。然而，CFD循環的部份執行作為變體循環，且其偏離正常沉積循環的條件。例如，其可採用一或更多額外反應物。這些變體循環也可採用基本CFD製程中所採用之相同反應物，雖然情況未必如此。 In addition, some examples may employ additional reactants in only a few CFD cycles. In such an example, the basic CFD process cycle uses only the reactants to produce a base film component (such as yttrium oxide or tantalum carbide). This basic process is executed in all or almost all CFD cycles. However, part of the CFD cycle is performed as a variant cycle and it deviates from the conditions of the normal deposition cycle. For example, it may employ one or more additional reactants. These variant cycles can also employ the same reactants used in the basic CFD process, although this is not necessarily the case.

如此之CFD製程特別有利於準備作為CFD薄膜之摻雜氧化物或其他摻雜材料。在一些實施例中，僅在CFD循環的一小部份中包含摻雜物前驅物作為「額外」反應物。添加摻雜物的頻率取決於所期望之摻雜物濃度。舉例而言，摻雜物前驅物可包含在基礎材料沉積的每第10個循環中。 Such a CFD process is particularly advantageous for preparing a doped oxide or other dopant material as a CFD film. In some embodiments, the dopant precursor is included as an "extra" reactant only in a small portion of the CFD cycle. The frequency at which dopants are added depends on the desired dopant concentration. For example, the dopant precursor can be included in every 10th cycle of deposition of the base material.

不同於許多其他沉積製程(特別是那些需要熱活化的沉積製程)，CFD製程可在相對低溫下實施。一般而言，CFD溫度將介於約20及400℃之間。可選取如此之溫度以允許在溫度敏感製程(如光阻芯(photoresist core)上之沉積)的情況下之沉積。在一具體實施例中，使用介於約20及100℃之間的溫度於雙圖案化應用(使用例如光阻芯)。在另一實施例中，採用介於約200及350℃之間的溫度於記憶體製作製程。 Unlike many other deposition processes (especially those that require thermal activation), CFD processes can be performed at relatively low temperatures. In general, the CFD temperature will be between about 20 and 400 °C. Such temperatures can be selected to allow for deposition in a temperature sensitive process such as deposition on a photoresist core. In a specific embodiment, a temperature between about 20 and 100 ° C is used for dual patterning applications (using, for example, a photoresist core). In another embodiment, a memory fabrication process is employed at a temperature between about 200 and 350 °C.

如以上所建議，CFD相當合適於先進技術節點中沉積薄膜。因此，例如可將CFD處理整合在32 nm節點、22 nm節點、16 nm節點、11 nm節點、以及其中任一者更往後的製程之中。這些節點敘述在國際半導體技術藍圖(ITRS)中，其為多年來於微電子技術需求上之業界共識。通常其參考記憶體單元間距的二分之一。在一具體範例中，CFD處理應用於「2X」裝置(具有20-29 nm範圍中之裝置特徵)以及其以上之裝置。 As suggested above, CFD is quite suitable for depositing thin films in advanced technology nodes. Thus, for example, CFD processing can be integrated into a 32 nm node, a 22 nm node, a 16 nm node, an 11 nm node, and any of the later processes. These nodes are described in the International Semiconductor Technology Blueprint (ITRS), which is an industry consensus on the needs of microelectronics technology for many years. Usually it is one-half of the reference memory cell spacing. In one specific example, CFD processing is applied to "2X" devices (with device features in the 20-29 nm range) and above.

雖然本文中所提出之CFD薄膜的大多數範例涉及矽基微電子裝置，但該薄膜亦可在其他領域中找到應用。使用非矽半導體(如GaAs及其他III-V族半導體，以及如HgCdTe之II-VI族材料)之微電子工程或光電工程可從使用揭露於本文中之CFD製程而獲益。至於保形介電薄膜在太陽能領域(如光伏裝置)、電致變色領域、及其他領域中的應用係可行的。 Although most of the examples of CFD films proposed herein relate to germanium-based microelectronic devices, the films can also find applications in other fields. Microelectronic engineering or optoelectronic engineering using non-antium semiconductors such as GaAs and other III-V semiconductors, as well as Group II-VI materials such as HgCdTe, may benefit from the use of the CFD process disclosed herein. As for conformal dielectric films, applications in the field of solar energy (such as photovoltaic devices), electrochromism, and other fields are feasible.

圖1示意地顯示電漿活化CFD製程之示範實施例的時序圖100。圖中繪示二個完全的CFD循環。如所示般，每一循環包含曝露至反應物A階段120A或120B、立刻後接曝露至反應物B階段140A或140B、反應物B清除階段160A或160B、以及最後電漿活化階段180A或180B。於電漿活化階段180A及180B期間所提供之電漿能量使表面吸附反應物種A及B之間的反應活化。在所描述之實施例中，在遞送一反應物(反應物A)之後不執行清除階段。事實上，此反應物於薄膜沉積製程期間持續流入。因此，在反應物A於該氣相中時激發電漿。以上特徵1-3體現於圖1的範例中。 FIG. 1 schematically shows a timing diagram 100 of an exemplary embodiment of a plasma activated CFD process. Two complete CFD cycles are shown. As shown, each cycle includes exposure to reactant A stage 120A or 120B, immediate subsequent exposure to reactant B stage 140A or 140B, reactant B removal stage 160A or 160B, and finally plasma activation stage 180A or 180B. . The plasma energy provided during the plasma activation phase 180A and 180B activates the reaction between the surface adsorption reaction species A and B. In the depicted embodiment, the purge phase is not performed after delivery of a reactant (Reactant A). In fact, this reactant continues to flow during the thin film deposition process. Thus, the plasma is excited as reactant A is in the gas phase. The above features 1-3 are embodied in the example of FIG.

所描述之實施例中，反應物氣體A和B可共存於氣相中而不互相反應。因此，在此示範CFD製程中可將ALD製程中所述之製程步驟的一或多者縮短或排除。例如，可排除在A曝露階段120A及120B之後的清除步驟。 In the depicted embodiment, reactant gases A and B can coexist in the gas phase without reacting with one another. Therefore, one or more of the process steps described in the ALD process can be shortened or eliminated in this exemplary CFD process. For example, the removal step after the A exposure stages 120A and 120B can be excluded.

CFD製程可用以沉積一些不同類型的薄膜之任一者。雖然本文中所提出之大多數範例涉及介電材料，但所揭露之CFD製程亦可用來形成導電或半導體材料之薄膜。氮化物及氧化物係主要的介電材料，但亦可形成碳化物、氧氮化物、碳摻雜氧化物、硼化物等等。氧化物包含範圍廣泛的材料，包括未摻雜矽酸鹽玻璃(USG)、摻雜矽酸鹽玻璃。摻雜玻璃的例子包含硼摻雜矽酸鹽玻璃(BSG)、磷摻雜矽酸鹽玻璃(PSG)、以及硼磷摻雜矽酸鹽玻璃(BPSG)。 The CFD process can be used to deposit any of a number of different types of films. While most of the examples presented herein relate to dielectric materials, the disclosed CFD process can also be used to form thin films of conductive or semiconducting materials. Nitrides and oxides are the main dielectric materials, but can also form carbides, oxynitrides, carbon doped oxides, borides, and the like. Oxides contain a wide range of materials, including undoped tellurite glass (USG), doped tellurite glass. Examples of doped glass include boron doped tellurite glass (BSG), phosphorus doped tellurite glass (PSG), and borophosphorus doped tellurite glass (BPSG).

在一些實施例中，氮化矽薄膜可由含矽反應物與一或更多之含氮反應物及/或含氮反應物混合物之反應而形成。範例性含矽反應物包含(但不限於)二(第三丁基胺基)矽烷(SiH2(NHC(CH3)3)2或BTBAS)、二氯矽烷(SiH2Cl2)、及氯矽烷(SiH3Cl)。範例性含氮反應物包含(但不限於)氨、氮、及第三丁基胺(tert-butyl amine)((CH3)3CNH2或三級丁基胺(t-butyl amine))。範例性含氮反應物混合物包含(但不限於)氮及氫的混合物。 In some embodiments, the tantalum nitride film can be formed from the reaction of a ruthenium containing reactant with one or more nitrogen-containing reactants and/or a nitrogen-containing reactant mixture. Exemplary silicon-containing reactants include (but are not limited to) bis (tertiary butylamino) Silane (SiH 2 (NHC (CH 3 ) 3) 2 or BTBAS), dichloro Silane (SiH 2 Cl 2), and chlorine Decane (SiH 3 Cl). Exemplary nitrogen-containing reactants include, but are not limited to, ammonia, nitrogen, and tert-butyl amine ((CH 3 ) 3 CNH 2 or t-butyl amine). Exemplary nitrogen-containing reactant mixtures include, but are not limited to, a mixture of nitrogen and hydrogen.

一或更多反應物之選擇可受各種薄膜及/或硬體考量所推動。舉例而言，在一些實施例中，氮化矽薄膜可由二氯矽烷和電漿活化氮的反應來形成。二氯矽烷化學吸附至氮化矽表面可產生矽氫末端表面(terminated surface)，從而釋放氯化氫(HCl)。此化學吸附反應之範例係示意性地描述在反應1中。 The choice of one or more reactants can be driven by various film and/or hardware considerations. For example, in some embodiments, a tantalum nitride film can be formed by the reaction of dichloromethane and plasma activated nitrogen. The chemical adsorption of methylene chloride to the surface of the tantalum nitride produces a hydrogen-terminated terminated surface, thereby releasing hydrogen chloride (HCl). An example of this chemisorption reaction is schematically depicted in Reaction 1.

反應1所示之環狀中間體隨後可經由與電漿活化氮之反應轉化成矽胺末端表面。 The cyclic intermediate shown in Reaction 1 can then be converted to the terminal surface of the indoleamine by reaction with a plasma-activated nitrogen.

然而，二氯矽烷的一些分子可藉由替代機制而化學吸附。例如，表面形態可妨礙反應1所述之環狀中間體的形成。另一化學吸附機制的範例係示意性地顯示於反應2。 However, some molecules of dichloromethane can be chemisorbed by an alternative mechanism. For example, the surface morphology can interfere with the formation of the cyclic intermediate described in Reaction 1. An example of another chemisorption mechanism is shown schematically in Reaction 2.

在後續的氮之電漿活化期間，反應2所示之中間體物種的剩餘氯原子可被釋放並可藉由電漿變得活化。此可造成氮化矽表面的蝕刻，而潛在性造成氮化矽薄膜變得粗糙或模糊。此外，殘留的氯原子可重新吸附(物理性及/或化學性)，而潛在性地污染所沉積的薄膜。此污染可改變氮化矽薄膜的物理及/或電特性。再者，活化之氯原子可造成處理站硬體之部份的蝕刻損壞，而潛在性減短處理站之部份的使用壽命。 During subsequent plasma activation of nitrogen, the remaining chlorine atoms of the intermediate species shown in Reaction 2 can be released and can be activated by the plasma. This can cause etching of the tantalum nitride surface, which potentially causes the tantalum nitride film to become rough or hazy. In addition, residual chlorine atoms can be resorbed (physical and/or chemical), potentially contaminating the deposited film. This contamination can alter the physical and/or electrical properties of the tantalum nitride film. Furthermore, the activated chlorine atoms can cause etch damage to portions of the processing station hardware, potentially reducing the useful life of portions of the processing station.

因此，在一些實施例中，氯矽烷可替代二氯矽烷。此可減少薄膜污染、薄膜損壞、及/或處理站損壞。氯矽烷之化學吸附的範例係示意性地顯示於反應3。 Thus, in some embodiments, chlorodecane can be substituted for dichlorodecane. This can reduce film contamination, film damage, and/or damage to the processing station. An example of chemisorption of chlorodecane is shown schematically in Reaction 3.

反應3： Reaction 3:

雖然反應3所述之範例使用氯矽烷作為含矽反應物，但應瞭解到可使用任何合適的單替代鹵素矽烷。 While the example described in Reaction 3 uses chlorodecane as the ruthenium containing reactant, it will be appreciated that any suitable single replacement halogen decane can be used.

如以上說明般，所描述之中間體結構可與氮源反應以形成氮化矽之矽胺末端表面。例如，可藉由電漿活化氨，從而形成各種氨自由基物種。該自由基物種與中間體反應，從而形成矽胺末端表面。 As explained above, the intermediate structure described can be reacted with a nitrogen source to form a guanidine tantalum end surface. For example, ammonia can be activated by plasma to form various ammonia radical species. The free radical species reacts with the intermediate to form the terminal surface of the indoleamine.

然而，氨可強烈地物理吸附至反應物遞送管線、處理站、以及排氣管之表面，其可導致延長之清除及排空時間。此外，氨可具有與一些氣相含矽反應物之高反應性。例如二氯矽烷(SiH2Cl2)和氨的氣相混合物可產生如二胺基矽烷(SiH2(NH2)2)之不穩定物種。如此物種可在氣相中分解，從而使小粒子成核。若氨與在鹵素矽烷之化學吸附期間所產生的氯化氫反應，則亦可形成小粒子。如此之粒子可累積在處理站中，在處理站中其可污染基板表面，而潛在導致整合裝置缺陷，並且在處理站中其可污染處理站硬體，而潛在導致工具停機時間及清理。小粒子亦可累積在排氣管中，而可堵塞泵及鼓風機，並且可產生對特殊環境排氣洗滌器及/或冷凝捕集器之需求。 However, ammonia can be strongly physically adsorbed to the reactant delivery line, the processing station, and the surface of the exhaust pipe, which can result in extended purge and evacuation times. In addition, ammonia can have high reactivity with some gas phase ruthenium containing reactants. For example, a gas phase mixture of dichlorodecane (SiH 2 Cl 2 ) and ammonia can produce unstable species such as diamino decane (SiH 2 (NH 2 ) 2 ). Such species can decompose in the gas phase, thereby nucleating small particles. Small particles can also be formed if ammonia reacts with hydrogen chloride generated during chemisorption of halogen decane. Such particles can accumulate in the processing station where they can contaminate the substrate surface, potentially leading to integration device defects, and which can contaminate the processing station hardware in the processing station, potentially causing tool downtime and cleaning. Small particles can also accumulate in the exhaust pipe, clogging the pump and blower, and can create a need for special ambient exhaust scrubbers and/or condensate traps.

因此，在一些實施例中，可使用替代胺作為含氮反應物。例如，可將由烷基替代胺(如三級丁基胺)之電漿活化形成的各種自由基供應至處理站。替代胺(如三級丁基胺)可具有較氨為低之製程硬體上的黏附係數，其可導致相對較低之物理吸附率以及相對較低之製程清除時間。 Thus, in some embodiments, a substituted amine can be used as the nitrogen-containing reactant. For example, various free radicals formed by the activation of a plasma of an alkyl replacement amine such as tertiary butylamine can be supplied to the processing station. Substituting amines, such as tertiary butylamine, can have an adhesion coefficient on process hardware that is lower than ammonia, which can result in relatively low physical adsorption rates and relatively low process purge times.

此外，如此之含氮反應物可形成相對於氯化銨更易揮發之鹵化鹽。舉例而言，三級丁基氯化銨可比氯化氨更易揮發。此可減短工具停機時間、裝置缺陷產生、以及環境紓減費用。 Additionally, such nitrogen-containing reactants can form halogenated salts that are more volatile relative to ammonium chloride. For example, tertiary butyl ammonium chloride can be more volatile than ammonium chloride. This reduces tool downtime, device defects, and environmental costs.

再者，如此之含氮反應物可經由各種副產物反應形成其他胺前驅物。舉例而言，三級丁基胺與二氯矽烷之反應可形成BTBAS。因此，副產物可 提供形成氮化矽的替代途徑，從而潛在地增加薄膜良率。在另一範例中，替代胺可提供氮化矽薄膜之低溫熱活化途徑。例如三級丁基胺在高於300℃的溫度下熱分解從而形成異丁烯及氨。 Again, such nitrogen-containing reactants can react to form other amine precursors via various by-products. For example, the reaction of tertiary butylamine with dichlorodecane can form BTBAS. Therefore, by-products can Providing an alternative way to form tantalum nitride, potentially increasing film yield. In another example, an alternative amine can provide a low temperature thermal activation pathway for a tantalum nitride film. For example, tertiary butylamine is thermally decomposed at temperatures above 300 ° C to form isobutylene and ammonia.

雖然以上所提供之說明性範例敘述使用三級丁基胺之氮化矽薄膜形成，但應瞭解在本發明之範圍內可採用任何合適的替代胺。在一些實施例中，合適的替代胺可基於反應物之熱力特性及/或反應性特性加以選擇。例如，可考量由反應物形成之鹵化鹽的相對揮發性，如同可考量在相關溫度下各種熱分解途徑的存在及選擇性。 While the illustrative examples provided above describe the formation of a tantalum nitride film using a tertiary butylamine, it should be understood that any suitable replacement amine may be employed within the scope of the invention. In some embodiments, suitable replacement amines can be selected based on the thermodynamic and/or reactive properties of the reactants. For example, the relative volatility of the halogenated salt formed from the reactants can be considered, as can be considered for the presence and selectivity of various thermal decomposition pathways at the relevant temperatures.

此外，雖然以上所提供之範例敘述氮化矽薄膜之沉積，但應瞭解以上討論之原理通常適用於其他薄膜的沉積。例如，一些實施例可使用合適的鹵素矽烷結合合適的含氧反應物物種(如氧電漿)來沉積氧化矽。 Moreover, while the examples provided above describe the deposition of tantalum nitride films, it should be understood that the principles discussed above are generally applicable to the deposition of other films. For example, some embodiments may use a suitable halogen decane in combination with a suitable oxygenated reactant species, such as an oxygen plasma, to deposit cerium oxide.

表1提供反應物、產物薄膜、以及薄膜和製程特性範圍之非限制性列表。 Table 1 provides a non-limiting list of reactants, product films, and ranges of film and process characteristics.

圖1亦顯示各種CFD製程參數之範例性CFD製程階段的時間進行之實施例。圖1繪示二範例性沉積循環110A和110B，然而應瞭解到任何合適數目的沉積循環可包含在CFD製程中以沉積所期望之薄膜厚度。範例性CFD製程參數包含(但不限於)惰性及反應物物種之流速、電漿功率及頻率、基板溫度、以及處理站壓力。表2提供使用BTBAS及氧之範例性二氧化矽沉積循環的非限制性參數範圍。 Figure 1 also shows an example of the timing of an exemplary CFD process stage for various CFD process parameters. 1 illustrates two exemplary deposition cycles 110A and 110B, although it should be understood that any suitable number of deposition cycles can be included in the CFD process to deposit the desired film thickness. Exemplary CFD process parameters include, but are not limited to, inert and reactant species flow rates, plasma power and frequency, substrate temperature, and station pressure. Table 2 provides a non-limiting range of parameters for an exemplary ceria deposition cycle using BTBAS and oxygen.

CFD循環通常包含蝕刻反應物之曝露階段。於此「曝露階段」期間，將反應物遞送至處理腔室以致使反應物吸附在基板表面上。通常，在曝露階段的開始時，基板表面沒有任何所吸附反應物之明顯數量。圖1中，在反應物A曝露階段120A和120B，以受控之流速將反應物A供應至處理站以使曝露之基板的表面飽和。反應物A可為任何合適的沉積反應物，例如主要反應物或輔助反應物。在其中CFD產生二氧化矽薄膜的範例中，反應物A可為氧。在圖1所示之實施例中，反應物A在沉積循環110A和110B自始至終持續流入。不同於其中分隔薄膜前驅物曝露以防止氣相反應之典型ALD製程，在CFD製程的一些實施例之氣相中允許反應物A和B混合。如以上所示，在一些實施例中選取反應物A和B以使其在施加電漿能量或活化表面反應之前於反應器中遭遇的條件下，可共存於氣相中而不明顯互相反應。在一些情況下，選取反應物以使(1)其間之反應適用於熱力學(即Gibb之自由能<0)，以及(2)該反應具有足夠高的活化能使得在所期望之沉積溫度下有可以忽略的反應。滿足這些準則之各種反應物組合將於本揭露內容中的其他位置確認。許多如此之組合包括提供在室溫下為固態之元素的主要反應物，以及不提供在室溫下為固態之元素的輔助反應物。在一些組合中使用之輔助反應物的例子包括氧、氮、烷基胺、以及氫。 The CFD cycle typically involves an exposure phase of the etch reactant. During this "exposure phase", the reactants are delivered to the processing chamber to cause the reactants to adsorb on the surface of the substrate. Typically, at the beginning of the exposure phase, the substrate surface does not have any significant amount of adsorbed reactants. In Figure 1, at Reactant A exposure stages 120A and 120B, reactant A is supplied to the processing station at a controlled flow rate to saturate the surface of the exposed substrate. Reactant A can be any suitable deposition reactant, such as a primary reactant or an auxiliary reactant. In an example in which the CFD produces a hafnium oxide film, the reactant A may be oxygen. In the embodiment shown in Figure 1, reactant A continues to flow in the deposition cycles 110A and 110B throughout. Unlike typical ALD processes in which the separator film precursor is exposed to prevent gas phase reactions, reactants A and B are allowed to mix in the gas phase of some embodiments of the CFD process. As indicated above, reactants A and B are selected in some embodiments to coexist in the gas phase without significant interaction with one another under conditions encountered in the reactor prior to application of plasma energy or activation surface reaction. In some cases, the reactants are selected such that (1) the reaction therebetween is suitable for thermodynamics (ie, Gibb's free energy < 0), and (2) the reaction has a sufficiently high activation energy to have a desired deposition temperature. Negligible response. Various combinations of reactants that meet these criteria will be identified elsewhere in this disclosure. Many such combinations include primary reactants that provide elements that are solid at room temperature, as well as auxiliary reactants that do not provide elements that are solid at room temperature. Examples of auxiliary reactants used in some combinations include oxygen, nitrogen, alkylamines, and hydrogen.

相較於其中先將反應物A開啟、隨後穩定並曝露至基板、然後關閉、以及最後自反應器移除之ALD製程，持續供應反應物A至處理站可減短或排除反應物A流速開啟及穩定時間。雖然圖1所示之實施例繪示反應物A曝露階段120A及120B為具有固定流速，但應瞭解到在本發明的範圍內可採用任何合適的反應物A流量(包括變動流量)。此外，雖然圖1顯示在整個CFD循環(沉積循環110A)期間反應物A具有固定流速，但情況未必如此。舉例而言，在B曝露階段140A和140B期間可減低反應物A的流速。這可增加B的分壓，並從而增加反應物B吸附在基板表面上的驅動力。 Continuous supply of reactant A to the treatment station may reduce or eliminate reactant A flow rate opening compared to an ALD process in which reactant A is first turned on, subsequently stabilized and exposed to the substrate, then closed, and finally removed from the reactor. And stabilization time. Although the embodiment illustrated in Figure 1 illustrates reactant A exposure stages 120A and 120B as having a fixed flow rate, it should be understood that any suitable reactant A flow (including varying flow rates) can be employed within the scope of the present invention. Furthermore, although Figure 1 shows that reactant A has a fixed flow rate throughout the CFD cycle (deposition cycle 110A), this is not necessarily the case. For example, the flow rate of reactant A can be reduced during the B exposure stages 140A and 140B. This can increase the partial pressure of B and thereby increase the driving force of the reactant B adsorbed on the surface of the substrate.

在一些實施例中，反應物A曝露階段120A可具有超過反應物A的基板表面飽和時間之持續時間。例如，圖1之實施例包含反應物A曝露階段120A中之反應物A後飽和曝露時間130。選擇性地，反應物A曝露階段120A包含惰性氣體的受控流速。惰性氣體範例包含(但不限於)氮、氬、及氦。可 提供惰性氣體以助於處理站的壓力及/或溫度控制、液態前驅物的蒸發、更多前驅物的快速遞送及/或作為用以自處理站及/或處理站管路移除處理氣體之清除氣體。 In some embodiments, the reactant A exposure stage 120A can have a duration that exceeds the substrate surface saturation time of the reactant A. For example, the embodiment of FIG. 1 includes a saturated exposure time 130 after reactant A in reactant A exposure stage 120A. Optionally, reactant A exposure stage 120A comprises a controlled flow rate of inert gas. Examples of inert gases include, but are not limited to, nitrogen, argon, and helium. can An inert gas is provided to assist in pressure and/or temperature control of the processing station, evaporation of the liquid precursor, rapid delivery of more precursors, and/or as a process gas to be removed from the processing station and/or the processing station line Remove the gas.

在圖1所示之實施例的反應物B曝露階段140A，將反應物B以受控之流速供應至處理站以使曝露之基板表面飽和。在一示範性二氧化矽薄膜中，反應物B可為BTBAS。雖然圖1之實施例繪示反應物B曝露階段140A為具有固定流速，但應瞭解到在本發明的範圍內可採用任何合適的反應物B流量(包括變動流量)。此外，應瞭解到反應物B曝露階段140A可具有任何合適的持續時間。在一些實施例中，反應物B曝露階段140A可具有超過反應物B的基板表面飽和時間之持續時間。例如，圖1所示之實施例繪示反應物B後飽和曝露時間150包含在反應物B曝露階段140A之中。選擇性地，反應物B曝露階段140A可包含合適的惰性氣體之受控流量，其如以上所述可助於處理站的壓力及/或溫度控制、液態前驅物的蒸發、更多前驅物的快速遞送，並且可防止處理站氣體的逆擴散。在圖1所示之實施例中，惰性氣體於反應物B曝露階段140A自始至終持續供應至處理站。 In the reactant B exposure stage 140A of the embodiment shown in Figure 1, reactant B is supplied to the processing station at a controlled flow rate to saturate the exposed substrate surface. In an exemplary ruthenium dioxide film, reactant B can be BTBAS. Although the embodiment of Figure 1 illustrates the reactant B exposure stage 140A as having a fixed flow rate, it should be understood that any suitable reactant B flow (including varying flow rates) can be employed within the scope of the present invention. Additionally, it should be understood that the reactant B exposure stage 140A can have any suitable duration. In some embodiments, the reactant B exposure stage 140A can have a duration that exceeds the substrate surface saturation time of the reactant B. For example, the embodiment illustrated in Figure 1 illustrates that the saturated exposure time 150 after reactant B is included in the reactant B exposure stage 140A. Alternatively, the reactant B exposure stage 140A can comprise a controlled flow of a suitable inert gas that can assist in pressure and/or temperature control of the processing station, evaporation of the liquid precursor, more precursors as described above. Fast delivery and prevent back-diffusion of the process station gases. In the embodiment illustrated in Figure 1, the inert gas is continuously supplied to the processing station throughout the reactant B exposure stage 140A.

在一些實施例中，沉積反應之電漿活化可導致較熱活化反應更低之沉積溫度，從而潛在地減少整合製程的可用熱預算之消耗。例如，在一些實施例中，電漿活化CFD製程可在室溫下發生。 In some embodiments, plasma activation of the deposition reaction can result in a lower deposition temperature for the hotter activation reaction, potentially reducing the consumption of available thermal budget for the integrated process. For example, in some embodiments, the plasma activated CFD process can occur at room temperature.

雖然圖1所述之CFD製程實施例為電漿活化，但應瞭解到在本發明的範圍內可使用其他非熱能源。非熱能源的非限制性範例包含(但不限於)紫外線燈、下游或遠端電漿源、感應耦合電漿、以及微波表面波電漿。 Although the CFD process embodiment illustrated in Figure 1 is plasma activated, it should be understood that other non-thermal energy sources may be utilized within the scope of the present invention. Non-limiting examples of non-thermal energy sources include, but are not limited to, ultraviolet lamps, downstream or distal plasma sources, inductively coupled plasma, and microwave surface wave plasma.

此外，雖然於本文中所討論的許多範例包含二反應物(A和B)，但應瞭解到在本發明的範圍內可採用任何合適數目的反應物。在一些實施例中，可使用單個反應物以及用以供應該反應物之表面分解反應的電漿能量之惰性氣體。或者，如以上所討論之特徵7的背景中，一些實施例可使用三或更多反應物來沉積薄膜。 Moreover, while many of the examples discussed herein include the two reactants (A and B), it should be understood that any suitable number of reactants may be employed within the scope of the present invention. In some embodiments, a single reactant and an inert gas to supply the plasma energy of the surface decomposition reaction of the reactant may be used. Alternatively, as in the context of feature 7 discussed above, some embodiments may use three or more reactants to deposit a film.

在一些情形中，表面吸附之B物種可如不連續島狀存在於基板表面上，而使其難以達到反應物B的表面飽和。各種表面條件可延遲反應物B於基板表面上的成核及飽和。舉例而言，在反應物A及/或B吸附時所釋放 之配位子可阻斷一些表面活性部位，而防止進一步吸附反應物B。因此，在一些實施例中，反應物B之連續吸附層可在反應物B曝露階段140A期間藉由調變反應物B的流量及/或離散地以脈衝輸送反應物B進入處理站來提供。此可為表面吸附及脫附過程提供額外時間，同時與固定流量情形相比更為節省反應物B。 In some cases, the surface adsorbed B species may exist on the surface of the substrate as a discontinuous island, making it difficult to achieve surface saturation of the reactant B. Various surface conditions can delay the nucleation and saturation of reactant B on the surface of the substrate. For example, when reactants A and/or B are adsorbed The ligand can block some surface active sites and prevent further adsorption of reactant B. Thus, in some embodiments, the continuous adsorption layer of reactant B can be provided during the reactant B exposure stage 140A by modulating the flow of reactant B and/or discretely pulsing reactant B into the processing station. This provides additional time for the surface adsorption and desorption process while saving reactant B compared to the fixed flow situation.

此外或選擇性地，在一些實施例中，可於反應物B的連續曝露之間包含一或更多清除階段。例如，圖2的實施例示意地顯示沉積循環210之範例性CFD製程時序圖200。在反應物B曝露階段240A，使反應物B曝露至基板表面。隨後，在清除階段260A，關閉反應物B，並且自處理站移除反應物B之氣相物種。在一情形中，氣相反應物B可被反應物A及/或惰性氣體之連續流量移開。在另一情形中，可藉由排空處理站來移除氣相反應物B。氣相反應物B之移除可改變吸附/脫附過程平衡，從而脫附配位子、促使所吸附B的表面重新排列以合併所吸附B之不連續島狀。在反應物B曝露階段240B，使反應物B再次曝露至基板表面。雖然圖2所示之實施例包含一反應物B清除及曝露循環的例子，但應瞭解到在本揭露內容的範圍內可採用交替清除及曝露循環的任何合適數目之重複。 Additionally or alternatively, in some embodiments, one or more purge stages may be included between successive exposures of reactant B. For example, the embodiment of FIG. 2 schematically shows an exemplary CFD process timing diagram 200 for a deposition cycle 210. At Reactant B exposure stage 240A, reactant B is exposed to the surface of the substrate. Subsequently, in purge stage 260A, reactant B is shut off and the gas phase species of reactant B is removed from the treatment station. In one instance, gas phase reactant B can be removed by continuous flow of reactant A and/or inert gas. In another case, the gas phase reactant B can be removed by evacuating the processing station. Removal of the gas phase reactant B can change the equilibrium of the adsorption/desorption process, thereby desorbing the ligand, causing the surface of the adsorbed B to rearrange to merge the discontinuous islands of the adsorbed B. At Reactant B exposure stage 240B, Reactant B is again exposed to the substrate surface. Although the embodiment illustrated in Figure 2 includes an example of a reactant B purge and exposure cycle, it should be understood that any suitable number of iterations of alternate purge and exposure cycles may be employed within the scope of the present disclosure.

回到圖1的實施例，在180A藉由電漿活化之前，在一些實施例中可於清除階段160A自處理站移除氣相反應物B。除了上述之曝露階段之外，CFD循環可包含一或更多清除階段。清除處理站可避免氣相反應，其中反應物B易受電漿活化影響。又，清除處理站可移除表面吸附之配位子，否則其可能餘留並污染薄膜。範例清除氣體包含(但不限於)氬、氦、以及氮。在圖1所示之實施例中，用於清除階段160A之清除氣體係由惰性氣體流所供應。在一些實施例中，清除階段160A可包含一或更多用以排空處理站之排空次階段。或者，應瞭解到在一些實施例中可省略清除階段160A。 Returning to the embodiment of Figure 1, the gas phase reactant B can be removed from the processing station in the purge stage 160A prior to activation of the plasma by 180A in some embodiments. In addition to the exposure stages described above, the CFD cycle can include one or more purge stages. The purge station can avoid gas phase reactions where reactant B is susceptible to plasma activation. Again, the scavenging station can remove surface-adsorbed ligands that might otherwise remain and contaminate the film. Exemplary purge gases include, but are not limited to, argon, helium, and nitrogen. In the embodiment illustrated in Figure 1, the purge gas system for purge stage 160A is supplied by an inert gas stream. In some embodiments, the purge phase 160A can include one or more emptying stages to evacuate the processing station. Alternatively, it should be appreciated that the purge phase 160A may be omitted in some embodiments.

清除階段160A可具有任何合適的持續時間。在一些實施例中，增加一或更多清除氣體的流速可減短清除階段160A的持續時間。例如，可根據各種反應物熱力特性、及/或處理站的幾何特性、及/或處理站管路來調整清除氣體流速從而修改清除階段160A的持續時間。在一非限制性範例中，可藉由調整清除氣體流速而使清除階段的持續時間最佳化。此可減短沉積循環 時間，從而可增進基板吞吐量。 The purge phase 160A can have any suitable duration. In some embodiments, increasing the flow rate of one or more purge gases may reduce the duration of the purge phase 160A. For example, the purge gas flow rate can be adjusted to modify the duration of purge phase 160A based on various reactant thermal characteristics, and/or geometry of the processing station, and/or processing station piping. In a non-limiting example, the duration of the purge phase can be optimized by adjusting the purge gas flow rate. This can reduce the deposition cycle Time, which increases substrate throughput.

CFD循環除了上述之曝露及選擇性的清除階段之外，通常還包含「活化階段」。活化階段用以驅動吸附在基板表面上之一或更多反應物的反應。在圖1所示之實施例的電漿活化階段180A，提供電漿能量以活化表面吸附反應物A和B之間的表面反應。例如，電漿可直接地或間接地活化反應物A的氣相分子以形成反應物A自由基。這些自由基隨後可與表面吸附反應物B交互作用，從而導致薄膜形成表面反應。沉積循環110A結束於電漿活化階段180A，在圖1之實施例中沉積循環110A後接以反應物A曝露階段120B為開始之沉積循環110B。 The CFD cycle typically includes an "activation phase" in addition to the exposure and selectivity removal stages described above. The activation phase is used to drive a reaction that adsorbs one or more reactants on the surface of the substrate. In the plasma activation phase 180A of the embodiment shown in Figure 1, plasma energy is provided to activate the surface reaction between the surface adsorbed reactants A and B. For example, the plasma can directly or indirectly activate the gas phase molecules of reactant A to form reactant A radicals. These free radicals can then interact with the surface adsorbent reactant B, causing the film to form a surface reaction. The deposition cycle 110A ends in a plasma activation phase 180A, in the embodiment of FIG. 1, a deposition cycle 110A followed by a deposition cycle 110B beginning with a reactant A exposure phase 120B.

在一些實施例中，於電漿活化階段180A中激發之電漿可直接在基板表面上方形成。此可提供更大的電漿密度以及反應物A和B之間的增加表面反應率。例如，可使用二電容式耦合板藉由施加射頻(RF)場至低壓氣體來產生用於CFD製程之電漿。在替代實施例中，可在主反應腔室之外產生遠端生成電漿。 In some embodiments, the plasma excited in the plasma activation phase 180A can be formed directly over the surface of the substrate. This provides greater plasma density and increased surface reaction rates between reactants A and B. For example, a two-capacitance coupling plate can be used to generate a plasma for a CFD process by applying a radio frequency (RF) field to a low pressure gas. In an alternate embodiment, a distally generated plasma can be generated outside of the main reaction chamber.

可使用任何合適的氣體來形成電漿。在第一範例中，可使用如氬或氦之惰性氣體來形成電漿。在第二範例中，可使用如氧或氨之反應物氣體來形成電漿。在第三範例中，可使用如氮之清除氣體來形成電漿。當然，亦可採用這些種類之氣體的組合。藉由RF場使平板之間的氣體離子化來激發電漿，從而在電漿放電區域產生自由電子。這些電子受到RF場加速，並且可與氣相反應物分子碰撞。這些電子與反應物分子的碰撞可形成參與沉積製程之自由基物種。應瞭解到RF場可經由任何合適的電極耦合。電極的非限制性例子包含處理氣體分佈噴淋頭及基板支撐基座。應瞭解到除了電容式耦合RF場至氣體之外還可藉由一或更多合適的方法來形成用於CFD製程之電漿。 Any suitable gas can be used to form the plasma. In the first example, an inert gas such as argon or helium may be used to form the plasma. In a second example, a reactant gas such as oxygen or ammonia can be used to form the plasma. In a third example, a purge gas such as nitrogen can be used to form the plasma. Of course, a combination of these types of gases can also be used. The plasma is excited by the ionization of the gas between the plates by the RF field, thereby generating free electrons in the plasma discharge region. These electrons are accelerated by the RF field and can collide with gas phase reactant molecules. Collisions of these electrons with reactant molecules can form free radical species involved in the deposition process. It will be appreciated that the RF field can be coupled via any suitable electrode. Non-limiting examples of electrodes include a process gas distribution showerhead and a substrate support pedestal. It will be appreciated that in addition to capacitively coupling the RF field to the gas, one or more suitable methods can be used to form the plasma for the CFD process.

電漿活化階段180A可具有任何合適的持續時間。在一些實施例中，電漿活化階段180A可具有超過電漿活化自由基與所有曝露之基板表面及被吸附物交互作用、從而在基板表面頂上形成連續薄膜之時間的持續時間。例如，圖1所示之實施例在電漿活化階段180A中包含電漿後飽和曝露時間190。 The plasma activation phase 180A can have any suitable duration. In some embodiments, the plasma activation stage 180A can have a duration that exceeds the time during which the plasma activated radical interacts with all exposed substrate surfaces and adsorbates to form a continuous film atop the substrate surface. For example, the embodiment shown in FIG. 1 includes a post-plasma saturated exposure time 190 in the plasma activation phase 180A.

如以下更完整地說明、且如以上特徵4之討論中所建議般，延長電漿曝露時間及/或提供複數電漿曝露階段可提供所沉積薄膜之主體及/或近表面部份的後反應處理。在一情形中，藉由電漿處理減少表面污染可使表面準備好對反應物A的吸附。例如，由含矽反應物與含氮反應物之反應形成的氮化矽薄膜可具有抵抗後續反應物之吸附的表面。以電漿處理氮化矽表面可產生用以促進後續吸附及反應事件之氫鍵。 As described more fully below, and as suggested in the discussion of feature 4 above, prolonging the plasma exposure time and/or providing a plurality of plasma exposure stages provides post-reaction of the bulk and/or near surface portions of the deposited film. deal with. In one case, surface contamination can be reduced by plasma treatment to prepare the surface for adsorption of reactant A. For example, a tantalum nitride film formed from the reaction of a rhodium-containing reactant with a nitrogen-containing reactant may have a surface that resists adsorption of subsequent reactants. Treatment of the tantalum nitride surface by plasma produces hydrogen bonds that promote subsequent adsorption and reaction events.

在一些實施例中，如薄膜應力、介電常數、折射率、及蝕刻速率之薄膜特性可藉由改變將於以下更詳細討論之電漿參數加以調整。表3提供關於三個在攝氏400度下沉積之範例CFD二氧化矽薄膜的各種薄膜特性之範例性列表。為了參考性目的，表3亦包含關於在攝氏400度下沉積之範例PECVD二氧化矽薄膜之薄膜資訊。 In some embodiments, film properties such as film stress, dielectric constant, refractive index, and etch rate can be adjusted by varying the plasma parameters that will be discussed in more detail below. Table 3 provides an exemplary list of various film characteristics for three exemplary CFD ceria films deposited at 400 degrees Celsius. For reference purposes, Table 3 also contains information on the film of a sample PECVD ceria film deposited at 400 degrees Celsius.

舉例而言，圖3示意地顯示CFD製程時序圖300之實施例，其包含沉積階段310後接電漿處理階段390。應瞭解到在電漿處理階段期間可使用任何合適的電漿。在第一情形中，在沉積循環中之活化期間可使用第一電漿氣體，並且在電漿處理階段期間可使用第二、不同的電漿氣體。在第二情形中，於電漿處理階段期間第二、不同的電漿氣體可補充第一電漿氣體。表4提供關於一範例性原位電漿處理循環之非限制性參數範圍。 For example, FIG. 3 schematically shows an embodiment of a CFD process timing diagram 300 that includes a deposition stage 310 followed by a plasma processing stage 390. It will be appreciated that any suitable plasma may be used during the plasma processing stage. In the first case, the first plasma gas may be used during activation in the deposition cycle, and a second, different plasma gas may be used during the plasma treatment phase. In the second scenario, a second, different plasma gas may replenish the first plasma gas during the plasma processing stage. Table 4 provides a range of non-limiting parameters for an exemplary in situ plasma processing cycle.

在圖3所示之電漿活化階段380，使基板表面曝露至電漿以活化薄膜沉積反應。如圖3所示之實施例中所繪示般，在電漿處理清除階段390A將處理站提供以反應物A(其可為例如輔助反應物(如氧))以及惰性氣體之連續流量。清除處理站可自處理站移除揮發性污染物。雖然圖3顯示一清除氣體，但應瞭解到在本發明的範圍內可使用任何合適的反應物移除方法。在電漿處理活化階段390B，激發電漿以處理新沉積之薄膜的主體及/或近表面區域。 In the plasma activation phase 380 shown in Figure 3, the surface of the substrate is exposed to a plasma to activate the thin film deposition reaction. As depicted in the embodiment illustrated in Figure 3, the processing station provides a continuous flow rate of reactant A (which may be, for example, an auxiliary reactant (e.g., oxygen)) and an inert gas during the plasma treatment purge stage 390A. The purge station can remove volatile contaminants from the processing station. While Figure 3 shows a purge gas, it should be understood that any suitable reactant removal method can be used within the scope of the present invention. At the plasma treatment activation stage 390B, the plasma is excited to treat the body and/or near surface regions of the newly deposited film.

雖然圖3之實施例包含一包括一電漿處理階段之CFD循環的例子，但應瞭解到在本發明的範圍內可採用任何合適數目之重複。此外，應瞭解到可在正常沉積循環之間的間隔(規則或以其他方式)***一或更多電漿處理循環。舉例而言，圖4顯示CFD製程時序圖400之實施例，其包含***於 二沉積循環之間的電漿處理階段。雖然圖4之實施例包含***於二沉積循環之間的電漿處理循環，但應瞭解到任何合適數目之沉積循環可位於一或更多電漿處理循環之前或之後。例如，在電漿處理係用以改變薄膜密度的情形中，可在每第十個沉積循環之後***電漿處理循環。在電漿處理係用以準備用於吸附及反應事件之表面的情形中，可將電漿處理循環合併在每一個CFD循環中(例如在每一個CFD沉積階段之後)。 Although the embodiment of Figure 3 includes an example of a CFD cycle including a plasma processing stage, it should be understood that any suitable number of repetitions can be employed within the scope of the invention. In addition, it should be understood that one or more plasma processing cycles can be inserted (regularly or otherwise) at intervals between normal deposition cycles. For example, FIG. 4 shows an embodiment of a CFD process timing diagram 400 that includes The plasma treatment stage between the two deposition cycles. Although the embodiment of Figure 4 includes a plasma processing cycle inserted between two deposition cycles, it should be understood that any suitable number of deposition cycles can be located before or after one or more plasma processing cycles. For example, in the case where the plasma treatment system is used to change the density of the film, a plasma treatment cycle can be inserted after every tenth deposition cycle. In the case where the plasma treatment system is used to prepare the surface for adsorption and reaction events, a plasma treatment cycle can be combined in each CFD cycle (eg, after each CFD deposition phase).

沉積薄膜之電漿處理可改變薄膜的一或更多物理特性。在一情形中，電漿處理可使新沉積薄膜緻密化。緻密化薄膜可比非緻密化薄膜較為抗蝕刻。例如，圖5顯示關於範例性CFD處理之二氧化矽薄膜相對於熱生長之二氧化矽薄膜之蝕刻速率的比較500之實施例。圖5之範例性薄膜實施例係藉由CFD製程502及504在從攝氏50度到400度的溫度範圍下沉積。作為參考，圖5顯示藉由電漿輔助CVD製程所沉積之未摻雜矽酸鹽玻璃(USG)與二氧化矽間隔層的相對蝕刻速率。由製程502(其每一沉積循環中包含1秒高頻氧電漿活化階段)產生之薄膜對於稀釋氫氟酸濕蝕刻(100：1H2O：HF)之抵抗性為製程504(其每一沉積循環中包含10秒高頻氧電漿活化階段)產生之薄膜的大約一半。因此，應瞭解到改變電漿活化階段之一或更多實施態樣及/或包含一或更多電漿處理循環可改變沉積薄膜的蝕刻速率。 Plasma treatment of deposited films can alter one or more physical properties of the film. In one case, the plasma treatment can densify the newly deposited film. Densified films are more resistant to etching than non-densified films. For example, Figure 5 shows an embodiment of a comparison 500 of etch rates for exemplary CFD treated ruthenium dioxide films relative to thermally grown ruthenium dioxide films. The exemplary film embodiment of FIG. 5 is deposited by CFD processes 502 and 504 at temperatures ranging from 50 degrees Celsius to 400 degrees Celsius. For reference, Figure 5 shows the relative etch rate of undoped tellurite glass (USG) deposited with a cerium oxide spacer by a plasma assisted CVD process. The film produced by process 502 (which contains a 1 second high frequency oxygen plasma activation phase in each deposition cycle) is resistant to dilute hydrofluoric acid wet etching (100:1H 2 O:HF) process 504 (each of which The deposition cycle contains approximately half of the film produced by the 10 second high frequency oxygen plasma activation phase. Thus, it will be appreciated that changing one or more embodiments of the plasma activation phase and/or including one or more plasma processing cycles can alter the etch rate of the deposited film.

在另一情形中，薄膜的電漿處理可改變薄膜的應力特性。例如，圖6顯示關於範例性CFD二氧化矽薄膜之濕蝕刻速率比率與薄膜應力之間相關性600之實施例。在圖6所示之實施例中，藉由例如延長電漿曝露時間而減小濕蝕刻速率比率可增大壓縮薄膜應力。 In another case, the plasma treatment of the film can alter the stress characteristics of the film. For example, Figure 6 shows an embodiment of a correlation 600 between wet etch rate ratios and film stress for an exemplary CFD cerium oxide film. In the embodiment illustrated in Figure 6, the compressive film stress can be increased by, for example, extending the plasma exposure time to reduce the wet etch rate ratio.

在另一情形中，沉積薄膜的電漿處理可提供相對於其他薄膜成分(例如在範例二氧化矽薄膜中的矽及/或氧)之微量薄膜污染物(例如在範例二氧化矽薄膜中的氫、氮、及/或碳)的瞬間差別移除。例如圖7顯示沉積溫度、電漿曝露時間、以及薄膜污染物濃度之間相關性700之實施例。在圖7所示之實施例中，在攝氏50度下沉積且具有10秒氧電漿活化階段之CFD二氧化矽薄膜704展現低於在相同溫度下沉積但具有1秒氧電漿活化階段之CFD二氧化矽薄膜702之氫及碳濃度。改變薄膜中污染物濃度可改變薄膜的電性及/或物理特性。舉例而言，調變碳及/或氫含量可調變薄膜介電常數及/ 或薄膜蝕刻速率。因此，應瞭解到改變電漿活化階段之一或更多實施態樣及/或包含一或更多電漿處理循環可提供用於改變薄膜成分的方法。 In another case, the plasma treatment of the deposited film can provide a trace amount of film contaminants relative to other film components (eg, germanium and/or oxygen in the exemplary ceria film) (eg, in an exemplary ceria film). Instantaneous differences in hydrogen, nitrogen, and/or carbon are removed. For example, Figure 7 shows an embodiment of a correlation 700 between deposition temperature, plasma exposure time, and film contaminant concentration. In the embodiment shown in FIG. 7, the CFD ceria film 704 deposited at 50 degrees Celsius and having a 10 second oxygen plasma activation stage exhibits a lower than the same temperature deposition but has a 1 second oxygen plasma activation stage. The hydrogen and carbon concentration of the CFD ceria film 702. Changing the concentration of contaminants in the film can alter the electrical and/or physical properties of the film. For example, modulating the carbon and/or hydrogen content of the variable film dielectric constant and / Or film etch rate. Thus, it will be appreciated that changing one or more embodiments of the plasma activation phase and/or including one or more plasma treatment cycles can provide a means for modifying the composition of the film.

雖然以上所討論的電漿處理與氧電漿處理有關，但應瞭解到在不離開本實施例的範圍之情況下可採用任何合適的電漿處理。例如，在一些實施例中，在合適的CFD製程中可採用替代胺取代NH3作為含氮反應物。雖然以替代胺(例如類似三級丁基胺之烷基胺)取代NH3對於保形SiN沉積可提供一些益處，但在一些情況下，所沉積之薄膜可包含源自烷基胺反應物之殘留碳(例如來自包含在每一三級丁基胺分子(NH2-(CH3)3)的三個甲基群之殘留碳)。此膜內碳可導致漏電，且可使得薄膜無法用在一些介電阻障層應用。 While the plasma treatment discussed above relates to oxygen plasma treatment, it should be understood that any suitable plasma treatment may be employed without departing from the scope of the present embodiments. For example, in some embodiments, a suitable process can be employed alternatively CFD substituted amine NH 3 as a nitrogen-containing reactant. While substituting NH3 with a substituted amine (e.g., an alkylamine similar to a tertiary butylamine) may provide some benefit to conformal SiN deposition, in some cases, the deposited film may comprise residues derived from alkylamine reactants. Carbon (e.g., residual carbon from three methyl groups contained in each of the tertiary butylamine molecules (NH 2 -(CH 3 ) 3 )). This intra-membrane carbon can cause leakage and can make the film unusable for some dielectric barrier applications.

因此，在一些實施例中，在SiN薄膜沉積期間激發氫電漿可減少在SiN薄膜中的殘留碳，其可相對改善薄膜的絕緣特性。在一些範例中，殘留碳之減少可容易地在FTIR光譜中觀察到。例如，SiN：C-H位準可從大約10原子%減少至大約1原子%。 Thus, in some embodiments, exciting the hydrogen plasma during deposition of the SiN film can reduce residual carbon in the SiN film, which can relatively improve the insulating properties of the film. In some examples, the reduction in residual carbon can be readily observed in the FTIR spectrum. For example, the SiN:C-H level can be reduced from about 10 atomic % to about 1 atomic %.

因此，在一些實施例中，可使用烷基胺或包含在含氮反應物及氫電漿處理的一或更多實例中之烷基胺混合物以CFD製程來沉積氮化矽薄膜。應瞭解到在不離開本發明的範圍之情況下可採用任何合適的氫電漿。因此，在一些實施例中，H2與例如He或Ar之氣體的混合物、或其他含H氣體、或由遠端電漿源產生之活化H原子可用以處理沉積薄膜。此外，在一些實施例中，可藉由改變一或更多數目之處理脈衝及其持續時間、處理電漿的強度、基板溫度、以及處理氣體成分來調整薄膜的碳含量至任何合適的濃度。 Thus, in some embodiments, a tantalum nitride film can be deposited in a CFD process using an alkylamine or an alkylamine mixture comprising one or more of the nitrogen-containing reactants and hydrogen plasma treatment. It will be appreciated that any suitable hydrogen plasma may be employed without departing from the scope of the invention. Thus, in some embodiments, H 2, for example, with a mixture of He or Ar gas, or other gases containing H, or activation of the H atoms produced by the remote plasma source can be used to deposit a thin film process. Moreover, in some embodiments, the carbon content of the film can be adjusted to any suitable concentration by varying one or more number of process pulses and their duration, the strength of the treated plasma, the substrate temperature, and the process gas composition.

雖然以上所討論的氫電漿處理與氮化矽薄膜有關，但應瞭解到合適的氫電漿處理之應用可用以調整其他包括(但不限於)SiOx、GeOx、及SiOxNy之CFD沉積薄膜的碳含量。 Although the hydrogen plasma treatment discussed above is related to tantalum nitride films, it should be understood that suitable hydrogen plasma processing applications can be used to adjust other carbons including, but not limited to, CFD deposited films of SiOx, GeOx, and SiOxNy. content.

一些於本文中揭露之實施例涉及氧化物CFD薄膜的紫外線處理(具有或不具有電漿處理)。該處理可減輕氧化物中的缺陷並改善如閘極介電層的CV特性之電性特性。採用可從如此處理受益之CFD氧化物的裝置及封裝應用包括：直通矽穿孔、採用閘極氧化物之邏輯技術、淺渠溝隔離(STI)、於STI光阻剝除之後形成細薄熱氧化物、於P井植入之前的犧牲氧化物(例如 ~60A)、後「井」熱氧化物生長、閘極/通道氧化物、DRAM PMD PECVD氧化物。 Some of the embodiments disclosed herein relate to ultraviolet treatment of oxide CFD films (with or without plasma treatment). This treatment mitigates defects in the oxide and improves electrical characteristics such as the CV characteristics of the gate dielectric layer. Devices and package applications that use CFD oxides that benefit from such processing include: through-via vias, logic techniques using gate oxides, shallow trench isolation (STI), and thin thermal oxidation after STI photoresist stripping Substance, sacrificial oxide before implantation of P well (eg ~60A), post "well" thermal oxide growth, gate/channel oxide, DRAM PMD PECVD oxide.

在一些情況下，已觀察到未經處理之CFD氧化物薄膜具有相對差的電性效能，據信是由於在如沉積薄膜中的固定電荷。例如，已發現一些薄膜具有明顯的晶圓內Vfb差異。如此問題已藉由在氫的存在下使用具有UV輻射及/或熱回火之後沉積處理而解決。據信此製程鈍化及/或減輕與位於(1)氧化物至矽介面、或(2)沉積之介電薄膜內、或(3)在空氣至氧化物表面(表面電荷)之固定電荷有關之缺陷。使用如此之處理，在UV硬化之後所沉積之氧化物的Vfb散布已從8.3V緊縮至約1.5V。 In some cases, it has been observed that untreated CFD oxide films have relatively poor electrical performance, believed to be due to fixed charges in, for example, deposited films. For example, some films have been found to have significant intra-wafer Vfb differences. Such a problem has been solved by using a deposition treatment with UV radiation and/or thermal tempering in the presence of hydrogen. It is believed that the process is passivated and/or mitigated by a fixed charge associated with (1) oxide to tantalum interface, or (2) deposited dielectric film, or (3) air to oxide surface (surface charge). defect. Using such treatment, the Vfb dispersion of the oxide deposited after UV hardening has been tightened from 8.3V to about 1.5V.

雖然這些實施例主要涉及改善氧化物薄膜，但所揭露之方法可廣泛地應用在介電層、金屬、金屬至介電層介面工程的生長。具體的介電層材料包含例如氧化矽(包括摻雜氧化矽)、碳化矽、氧碳化矽、氮化矽、氧氮化矽、以及可灰化硬遮罩材料。 While these embodiments are primarily directed to improving oxide films, the disclosed methods are widely applicable to dielectric layer, metal, metal to dielectric layer interface engineering. Specific dielectric layer materials include, for example, cerium oxide (including doped cerium oxide), cerium carbide, cerium oxycarbide, cerium nitride, cerium oxynitride, and an ashable hard mask material.

可用以增進介電特性之處理的範例包括如下： Examples of processes that can be used to enhance dielectric properties include the following:

(A)藉由以UV硬化且隨後氫回火之CFD而合成之介電薄膜的後沉積處理。在最簡單的實施例中，可單獨使用UV處理以減少固定電荷。 (A) Post-deposition treatment of a dielectric film synthesized by CFD which is cured by UV and then hydrogen tempered. In the simplest embodiment, UV treatment can be used alone to reduce the fixed charge.

(B)在CFD介電薄膜沉積之前的利用包含下列者之處理的基板預處理：在He、H2、Ar、N2、H2/N2形成氣體、NH3存在下之H2電漿、N2電漿、N2/H2電漿、NH3電漿、AR電漿、He電漿、He回火、H2回火、NH3回火、以及UV硬化。電漿處理可用包含(但不限於)微波、ICP遠端、直接、及其類似者之各種電漿產生器來實現。 (B) Pretreatment of the substrate prior to deposition of the CFD dielectric film using a process comprising: He, H 2 , Ar, N 2 , H 2 /N 2 forming gas, H 2 plasma in the presence of NH 3 , N 2 plasma, N 2 /H 2 plasma, NH 3 plasma, AR plasma, He plasma, He tempering, H 2 tempering, NH 3 tempering, and UV hardening. Plasma processing can be accomplished with various plasma generators including, but not limited to, microwaves, ICP remotes, direct, and the like.

(C)與包含以下處理之同時處理(沉積期間硬化)：在He、H2、Ar、N2、H2/N2形成氣體、NH3存在下之H2電漿、N2電漿、N2/H2電漿、NH3電漿、AR電漿、He電漿、He回火、H2回火、NH3回火、以及UV硬化。電漿處理可用包含(但不限於)微波、ICP遠端、直接、及其他本領域中具有通常技術者熟知之各種電漿產生器來實現。可應用之等向性及方向性處理包含(但不限於)遠端電漿、UV曝露、直接電漿、及微波電漿。一範例性方法包含在CFD循環的群組之間的薄膜間歇處理。CFD循環的一群組可從約1變化至10000個循環。典型的情形包含：(1)5個CFD氧化物生長循環、後接(2)用任何以 上所述之方法(例如He電漿、UV處理)之一或更多薄膜處理、後接(3)5個CFD氧化物生長循環。此方法可用以生長任何期望之厚度的薄膜。 (C) simultaneous treatment with the following treatments (hardening during deposition): H 2 plasma in the presence of He, H 2 , Ar, N 2 , H 2 /N 2 , NH 3 , N 2 plasma, N 2 /H 2 plasma, NH 3 plasma, AR plasma, He plasma, He tempering, H 2 tempering, NH 3 tempering, and UV hardening. The plasma treatment can be accomplished with, but is not limited to, microwaves, ICP remotes, direct, and other plasma generators well known in the art as is well known in the art. Applicable isotropic and directional processes include, but are not limited to, remote plasma, UV exposure, direct plasma, and microwave plasma. An exemplary method involves film intermittent processing between groups of CFD cycles. A group of CFD cycles can vary from about 1 to 10,000 cycles. Typical cases include: (1) 5 CFD oxide growth cycles followed by (2) treatment with one or more of the films described in any of the above methods (eg He plasma, UV treatment), followed by (3) 5 CFD oxide growth cycles. This method can be used to grow a film of any desired thickness.

(D)由以上所列之任何電漿所賦予為副產物之UV處理(例如氦電漿放射UV輻射)。 (D) UV treatment (eg, krypton plasma radiation UV radiation) imparted as a by-product by any of the plasmas listed above.

在CFD循環期間用於原位「硬化」程序之一範例涉及以下操作： An example of an in-situ "hardening" procedure during a CFD cycle involves the following operations:

(1)經由He電漿之UV處理 (1) UV treatment via He plasma

(2)BTBAS施用 (2) BTBAS administration

(3)清除 (3) Clear

(4)O2/Ar-RF電漿活化 (4) O 2 /Ar-RF plasma activation

(5)清除 (5) Clear

(6)重複步驟(1)-(5)以產生期望之厚度的薄膜。 (6) Repeat steps (1)-(5) to produce a film of the desired thickness.

UV硬化條件的範圍可用在任何所列出之上下文中。一般而言，於硬化期間基座溫度將維持在約250及500℃之間。對於許多裝置製作應用，上限溫度將限制在450℃或甚至400℃。硬化期間所採用之環境可為惰性或反應性。可於硬化期間存在之氣體的例子包含氦、氬、氮、形成氣體、以及氨。如此氣體之流速可為約2至20000 sccm，較佳地約4000至18000 sccm。UV燈的功率可例如為約2-10 kW，且較佳地介於約3.5及7 kW之間。曝露至來自此源之UV的適當持續時間為介於約20及200秒之間(例如約90秒)。最後，可將壓力保持在介於0 Torr及約40 Torr之間的位準。 The range of UV hardening conditions can be used in any of the listed contexts. In general, the susceptor temperature will remain between about 250 and 500 °C during hardening. For many device fabrication applications, the upper temperature limit will be limited to 450 ° C or even 400 ° C. The environment employed during hardening may be inert or reactive. Examples of gases that may be present during hardening include helium, argon, nitrogen, forming gases, and ammonia. The flow rate of such a gas may be from about 2 to 20,000 sccm, preferably from about 4,000 to 18,000 sccm. The power of the UV lamp can be, for example, about 2-10 kW, and preferably between about 3.5 and 7 kW. The appropriate duration of exposure to UV from this source is between about 20 and 200 seconds (e.g., about 90 seconds). Finally, the pressure can be maintained at a level between 0 Torr and about 40 Torr.

在一具體實施例中，使用以下條件來獲得CFD氧化物的有效處理： In a specific embodiment, the following conditions are used to obtain an effective treatment of the CFD oxide:

基座溫度=400℃ Base temperature = 400 ° C

環境=He Environment = He

壓力=40 Torr He Pressure = 40 Torr He

流速=10000 sccm Flow rate = 10000 sccm

在一些實施例中，於UV硬化操作之後執行氧化物之熱回火。在一範例 中，於該回火中使用以下條件： In some embodiments, thermal tempering of the oxide is performed after the UV hardening operation. In an example In the tempering, the following conditions are used:

基座溫度=400℃ Base temperature = 400 ° C

環境=H2+N2 Environment = H 2 + N 2

壓力=2.5 Torr Pressure = 2.5 Torr

流速=750 sccm H2；3000 sccm N2 Flow rate = 750 sccm H 2 ; 3000 sccm N 2

沉積薄膜的物理及電性特性亦可藉由調整其他如沉積溫度之製程參數加以改變。例如，圖7所繪示之實施例之相關性700亦顯示CFD薄膜沉積溫度與薄膜污染物濃度之間的範例性關係。當薄膜沉積溫度增高時，則薄膜污染物的併入減少。在另一範例中，圖5所示之實施例圖例說明範例性二氧化矽CFD薄膜之濕蝕刻速率比率隨著沉積溫度增高而減低，如同以上所述般。其他可調整以調諧薄膜特性之沉積參數包含RF功率、RF頻率、壓力、以及流速。此外，在一些實施例中，可藉由改變反應物選擇來改變薄膜特性。例如，可藉由使用四異氫酸酯矽烷(TICS)作為含矽反應物以及使用氧及/或一氧化二氮作為含氧反應物來減少二氧化矽薄膜的氫含量。 The physical and electrical properties of the deposited film can also be varied by adjusting other process parameters such as deposition temperature. For example, the correlation 700 of the embodiment depicted in FIG. 7 also shows an exemplary relationship between CFD film deposition temperature and film contaminant concentration. When the film deposition temperature is increased, the incorporation of film contaminants is reduced. In another example, the embodiment illustrated in FIG. 5 illustrates that the wet etch rate ratio of the exemplary ceria CFD film decreases as the deposition temperature increases, as described above. Other deposition parameters that can be adjusted to tune film characteristics include RF power, RF frequency, pressure, and flow rate. Moreover, in some embodiments, film properties can be altered by changing reactant selection. For example, the hydrogen content of the cerium oxide film can be reduced by using tetrahydrohydrogen phthalate (TICS) as the ruthenium-containing reactant and oxygen and/or nitrous oxide as the oxygen-containing reactant.

應瞭解到如以上所討論的那些物理及/或電性薄膜特性之變化可提供調整裝置效能和良率的機會、以及修改裝置製造製程整合之實施態樣的機會。作為一非限制性範例，調諧CFD二氧化矽薄膜之蝕刻速率特性的能力可使得薄膜成為蝕刻停止層、硬遮罩、及其他製程整合應用的候選者。因此，在本文中提供用於整合半導體裝置製造程序所有方面應用之CFD產生之薄膜的各種實施例。 It will be appreciated that variations in physical and/or electrical film properties as discussed above may provide opportunities to adjust device performance and yield, as well as opportunities to modify implementation aspects of device manufacturing process integration. As a non-limiting example, the ability to tune the etch rate characteristics of a CFD ceria film can make the film a candidate for etch stop layers, hard masks, and other process integration applications. Accordingly, various embodiments of CFD-produced films for integrating all aspects of semiconductor device fabrication processes are provided herein.

在一情形中，CFD製程可在非平面基板上沉積保形二氧化矽薄膜。舉例而言，CFD二氧化矽薄膜可用於結構之間隙填充，如淺渠溝隔離(STI)結構之渠溝填充。雖然以下敘述之各種實施例與間隙填充應用有關，但應瞭解到這僅為非限制性、示例性應用，並且利用其他合適薄膜材料之其他合適應用皆可在本發明的範圍內。CFD二氧化矽薄膜的其他應用包含(但不限於)層間介電(ILD)應用、金屬間介電(IMD)應用、前金屬介電(PMD)應用、用於直通矽穿孔(TSV)之介電襯墊應用、電阻式RAM(ReRAM)應用、及/或DRAM中堆疊式電容製作應用。 In one case, a CFD process can deposit a conformal ceria film on a non-planar substrate. For example, CFD yttria films can be used for gap filling of structures, such as trench trench fills in shallow trench isolation (STI) structures. While the various embodiments described below are related to gap fill applications, it should be understood that this is merely a non-limiting, exemplary application, and that other suitable applications utilizing other suitable film materials are within the scope of the present invention. Other applications for CFD yttria films include, but are not limited to, interlayer dielectric (ILD) applications, inter-metal dielectric (IMD) applications, pre-metal dielectric (PMD) applications, and through-through vias (TSV). Electrical pad applications, resistive RAM (ReRAM) applications, and/or stacked capacitor fabrication applications in DRAM.

可使用摻雜氧化矽作為硼、磷、或甚至砷摻雜物的擴散源。例如，可使用硼摻雜矽酸鹽玻璃(BSG)、磷摻雜矽酸鹽玻璃(PSG)、或甚至硼磷摻雜矽酸鹽玻璃(BPSG)。可採用摻雜之CFD層來提供例如三維電晶體結構(如多閘極鳍狀場效電晶體(FinFET)及三維之記憶體裝置)中的保形摻雜。習知的離子植入機無法容易地摻雜側壁，尤其是在高的高寬比結構中。CFD摻雜氧化 物作為擴散源具有各種優點。首先，其在低溫下提供高保形性。相較之下，低壓CVD產生之摻雜TEOS(四乙基正矽酸鹽)為人熟知但需要在高溫下沉積，而且次大氣壓CVD及PECVD摻雜氧化物薄膜可在低溫下實行但不具充分的保形性。摻雜的保形性係重要的，而薄膜本身的保形性亦然，因為薄膜通常為犧牲應用且隨後將必須移除。非保形薄膜通常在移除時面臨更多挑戰，即一些區域會被過度蝕刻。此外，CFD提供控制極佳之摻雜濃度。如所提及般，CFD製程可從幾層未摻雜氧化物後接單層摻雜來提供。可藉由用以沉積摻雜層之頻率以及摻雜循環的條件嚴格地控制摻雜的程度。在一些實施例中，摻雜循環係藉由例如使用具有明顯空間位阻(steric hindrance)之摻雜物源來控制。除了習知矽基微電子學外，CFD摻雜的其他應用包括基於III-V族半導體(如GaAs)和II-VI族半導體(如HgCdTe)之微電子學及光電子學、光伏電池、平面顯示器、以及電致變色技術。 Doped cerium oxide can be used as a diffusion source for boron, phosphorus, or even arsenic dopants. For example, boron doped tellurite glass (BSG), phosphorus doped tellurite glass (PSG), or even borophosphorus doped tellurite glass (BPSG) can be used. A doped CFD layer can be employed to provide conformal doping in, for example, a three-dimensional transistor structure, such as a multi-gate fin field effect transistor (FinFET) and a three-dimensional memory device. Conventional ion implanters do not readily dope sidewalls, especially in high aspect ratio structures. CFD doping oxidation The object has various advantages as a diffusion source. First, it provides high conformality at low temperatures. In contrast, low-pressure CVD-doped TEOS (tetraethyl-n-decanoate) is well known but needs to be deposited at high temperatures, and sub-atmospheric CVD and PECVD doped oxide films can be performed at low temperatures but not adequately. Conformality. The conformality of the doping is important, and the conformality of the film itself is also true, as the film is typically a sacrificial application and will have to be removed later. Non-conformal films often face more challenges when removed, ie some areas are over-etched. In addition, CFD provides excellent doping concentrations. As mentioned, the CFD process can be provided from several layers of undoped oxide followed by a single layer doping. The degree of doping can be strictly controlled by the conditions used to deposit the frequency of the doped layer and the doping cycle. In some embodiments, the doping cycle is controlled by, for example, using a dopant source having significant steric hindrance. In addition to conventional 矽-based microelectronics, other applications for CFD doping include microelectronics and optoelectronics based on III-V semiconductors (such as GaAs) and II-VI semiconductors (such as HgCdTe), photovoltaic cells, flat panel displays. And electrochromic technology.

一些間隙填充製程涉及在不同沉積工具上執行之二薄膜沉積步驟，於沉積步驟之間需要真空破壞及空氣曝露。圖8示意地顯示包含複數間隙802之範例性非平面基板800。如圖8所示，間隙802可具有不同的高寬比，其可定義為每一間隙802之間隙深度(H)與間隙寬度(W)的比率。舉例而言，整合半導體裝置的邏輯區域可具有對應於不同邏輯裝置結構之不同的間隙高寬比。 Some gap filling processes involve two thin film deposition steps performed on different deposition tools, requiring vacuum damage and air exposure between deposition steps. FIG. 8 schematically shows an exemplary non-planar substrate 800 including a plurality of gaps 802. As shown in FIG. 8, the gaps 802 can have different aspect ratios, which can be defined as the ratio of the gap depth (H) to the gap width (W) for each gap 802. For example, the logic regions of the integrated semiconductor device can have different gap aspect ratios corresponding to different logic device structures.

如圖8所示，非平面基板800係由細薄、保形薄膜804所覆蓋。雖然保形薄膜804已完全填充間隙802A，但間隙802B及802C仍留著開口。以保形薄膜封閉間隙802B及802C可導致製程時間的延長。因此，在一些方法中，可藉由如CVD及/或PECVD方法之更高沉積速率製程來異位沉積更厚的薄膜。然而，間隙填充薄膜之異位沉積可降低在生產線中的晶圓吞吐量。例如，在沉積工具之間的基板搬運及運送時間可於生產期間減少一些基板處理活動。此可減少生產線吞吐量，並且可能需要在生產線中安裝及維護額外處理工具。 As shown in FIG. 8, the non-planar substrate 800 is covered by a thin, conformal film 804. Although the conformal film 804 has completely filled the gap 802A, the gaps 802B and 802C still have openings. Closing gaps 802B and 802C with a conformal film can result in extended process times. Thus, in some methods, thicker films can be deposited ectopically by higher deposition rate processes such as CVD and/or PECVD. However, ectopic deposition of gap-filled films can reduce wafer throughput in the production line. For example, substrate handling and shipping time between deposition tools can reduce some substrate processing activity during production. This reduces line throughput and may require additional processing tools to be installed and maintained in the production line.

此外，雖然間隙802C可具有適合於氣相沉積製程的高寬比，但802B可具有由較高沉積速率製程可能導致之不完全填充並且可能形成鎖眼孔洞(keyhole void)之高寬比。例如，圖10顯示形成在基板1002中之範例性高高 寬比結構1000。如圖10所示，於沉積較厚之薄膜1006期間的麵包條效應已產生鎖眼孔洞1008。鎖眼孔洞可在後續的製程中被重新打開並以導電薄膜填充，其可導致裝置短路。 Moreover, while gap 802C may have an aspect ratio suitable for a vapor deposition process, 802B may have an aspect ratio that may result from incomplete filling by higher deposition rate processes and may form keyhole voids. For example, FIG. 10 shows an exemplary high level formed in the substrate 1002. The width ratio structure is 1000. As shown in FIG. 10, the dough strip effect 1008 has been created during the deposition of the thicker film 1006. The keyhole holes can be reopened in a subsequent process and filled with a conductive film that can cause a short circuit in the device.

應對如間隙802B之高高寬比間隙的一些方法包含提供避免產生如此間隙之裝置設計規則。然而，如此之設計規則可能需要額外的遮罩步驟、可使得裝置設計變困難、及/或可導致整合半導體裝置面積的增加，其可增加製造成本。因此，在一些實施例中，CFD製程可包含從CFD製程至CVD及/或PECVD製程之原位過渡。例如，圖9顯示已分為三階段之CFD製程時序圖900的實施例。CFD製程階段902描述一範例性CFD製程循環。為了清楚起見，儘管圖9所示之實施例僅顯示單一CFD製程循環，但應瞭解到CFD製程階段902中可包含任何合適數目之CFD製程循環及電漿處理循環。過渡階段904接在CFD製程階段902之後。如圖9之實施例所示，過渡階段904包含CFD製程及PECVD製程二者之實施態樣。具體而言，反應物B係在反應物B曝露階段904A結束後提供至處理站，使得在電漿活化階段904B期間反應物A和B皆存在於氣相之中。此可同時提供PECVD式氣相反應與CFD式表面反應。雖然過渡階段904僅包含反應物B曝露階段904A及電漿活化階段904B之一重複，但應瞭解到在過渡階段內可包含任何合適數目之重複。 Some methods of dealing with high aspect ratio gaps such as gap 802B include providing device design rules that avoid such gaps. However, such design rules may require additional masking steps, may make device design difficult, and/or may result in an increase in the area of the integrated semiconductor device, which may increase manufacturing costs. Thus, in some embodiments, the CFD process can include an in-situ transition from a CFD process to a CVD and/or PECVD process. For example, Figure 9 shows an embodiment of a three-stage CFD process timing diagram 900. CFD process stage 902 depicts an exemplary CFD process cycle. For the sake of clarity, although the embodiment shown in FIG. 9 shows only a single CFD process cycle, it should be understood that any suitable number of CFD process cycles and plasma processing cycles may be included in the CFD process stage 902. The transition phase 904 is followed by the CFD process phase 902. As shown in the embodiment of FIG. 9, the transition phase 904 includes aspects of both the CFD process and the PECVD process. Specifically, reactant B is provided to the processing station after the end of reactant B exposure stage 904A such that reactants A and B are present in the gas phase during the plasma activation phase 904B. This can provide both a PECVD type gas phase reaction and a CFD type surface reaction. While the transition phase 904 includes only one of the Reactant B exposure phase 904A and the plasma activation phase 904B, it should be understood that any suitable number of repeats may be included during the transition phase.

在一些實施例中，可控制電漿產生器以於電漿活化階段904B期間提供電漿能量之間歇脈衝。例如，可在包含(但不限於)介於10 Hz及150 Hz之間的頻率使電漿產生脈衝。與連續電漿相比，此可藉由減低離子轟擊的方向性來增進階梯覆蓋。又，此可減低離子轟擊對基板的損壞。例如，於連續電漿期間光阻基板會被離子轟擊侵蝕。使電漿能量產生脈衝可減低光阻侵蝕。 In some embodiments, the plasma generator can be controlled to provide intermittent pulses of plasma energy during the plasma activation phase 904B. For example, the plasma can be pulsed at a frequency including, but not limited to, between 10 Hz and 150 Hz. This improves step coverage by reducing the directionality of ion bombardment compared to continuous plasma. Moreover, this can reduce damage to the substrate by ion bombardment. For example, the photoresist substrate is eroded by ion bombardment during continuous plasma. Pulsed plasma energy reduces photoresist erosion.

在圖9所示之實施例中，電漿活化階段904B期間反應物B的流速低於反應物B曝露階段904A期間反應物B的流速。因此，於電漿活化階段904B期間反應物B可「細流」入處理站中。這可提供氣相PECVD反應從而增補CFD式表面反應。然而，應瞭解到在一些實施例中，於單一電漿活化階段期間或在過渡階段之過程中可改變反應物B的流速。例如，在包含反應物B 曝露及電漿活化的二個重複之過渡階段中，第一電漿活化階段期間反應物B的流速可低於第二電漿活化階段期間反應物B的流速。改變電漿活化階段904B期間反應物B的流速可提供從CFD製程階段902之階梯覆蓋特性到PECVD製程階段906之沉積速率特性的平穩過渡。 In the embodiment illustrated in Figure 9, the flow rate of reactant B during the plasma activation phase 904B is lower than the flow rate of reactant B during the reactant B exposure phase 904A. Thus, reactant B can "finely flow" into the processing station during the plasma activation phase 904B. This provides a gas phase PECVD reaction to supplement the CFD-type surface reaction. However, it will be appreciated that in some embodiments, the flow rate of reactant B can be varied during a single plasma activation phase or during a transition phase. For example, in the inclusion of reactant B In two repeated transition stages of exposure and plasma activation, the flow rate of reactant B during the first plasma activation phase may be lower than the flow rate of reactant B during the second plasma activation phase. Varying the flow rate of reactant B during the plasma activation phase 904B provides a smooth transition from the step coverage characteristics of the CFD process stage 902 to the deposition rate characteristics of the PECVD process stage 906.

在一些實施例中，CFD製程可包含用於選擇性移除沉積薄膜之凹入部分的原位蝕刻。表5提供包含用於間隙填充CFD製程之原位蝕刻的範例性二氧化矽沉積製程之非限制性參數範圍。 In some embodiments, the CFD process can include an in situ etch for selectively removing the recessed portions of the deposited film. Table 5 provides a non-limiting range of parameters for an exemplary ceria deposition process including in-situ etch for a gap-fill CFD process.

圖11顯示包含沉積階段1102、蝕刻階段1104、及後續沉積階段1106之CFD製程時序圖1100之實施例。在圖11所示之實施例的沉積階段1102，使薄膜沉積至基板之曝露表面上。例如，沉積階段1102可包含一或更多CFD製程沉積循環。 11 shows an embodiment of a CFD process timing diagram 1100 that includes a deposition phase 1102, an etch phase 1104, and a subsequent deposition phase 1106. In the deposition stage 1102 of the embodiment shown in Figure 11, a thin film is deposited onto the exposed surface of the substrate. For example, deposition stage 1102 can include one or more CFD process deposition cycles.

在圖11之實施例的蝕刻階段1104，將反應物A和B關閉並且導入蝕刻氣體至處理站。蝕刻氣體的一非限制性範例為三氟化氮(NF3)。在圖11所示之實施例中，蝕刻氣體係由蝕刻階段1104期間所激發之電漿活化。如處理站壓力、基板溫度、蝕刻氣體流速之各種製程參數可於蝕刻階段1104期 間加以調整，以便在非平面基板上選擇性移除沉積薄膜的凹入部分。在本發明的範圍內可採用任何合適的蝕刻製程。其它範例性蝕刻製程包含(但不限於)反應性離子蝕刻、非電漿氣相蝕刻、固相昇華、以及蝕刻物種之吸附與方向性活化(例如藉由離子轟擊)。 In the etch phase 1104 of the embodiment of Figure 11, reactants A and B are closed and an etch gas is introduced to the processing station. A non-limiting example of the etching gas is nitrogen trifluoride (NF 3). In the embodiment shown in FIG. 11, the etch gas system is activated by the plasma excited during the etch phase 1104. Various process parameters such as process station pressure, substrate temperature, and etch gas flow rate can be adjusted during the etch phase 1104 to selectively remove the recessed portions of the deposited film on the non-planar substrate. Any suitable etching process can be employed within the scope of the present invention. Other exemplary etching processes include, but are not limited to, reactive ion etching, non-plasma vapor phase etching, solid phase sublimation, and adsorption and directional activation of etched species (eg, by ion bombardment).

在一些實施例中，可在蝕刻薄膜之前和之後自處理站移除不相容氣相物種。例如，圖11之實施例於蝕刻階段1104期間在反應物A和B已關閉之後以及在蝕刻氣體已關閉之後包含惰性氣體的連續流量。 In some embodiments, the incompatible gas phase species can be removed from the processing station before and after etching the film. For example, the embodiment of Figure 11 contains a continuous flow of inert gas during the etch phase 1104 after reactants A and B have been turned off and after the etch gas has been turned off.

在蝕刻階段1104結束時，沉積階段1106開始，從而進一步填充非平面基板上的間隙。沉積階段1106可為任何合適的沉積製程。例如，沉積階段1106可包含一或更多的CFD製程、CVD製程、PECVD製程等等。雖然圖11之實施例顯示單一蝕刻階段1104，但應瞭解到於間隙填充製程期間可在多個任何合適形式的沉積階段之中間隔地***複數原位蝕刻製程。 At the end of the etch phase 1104, the deposition phase 1106 begins to further fill the gaps on the non-planar substrate. The deposition stage 1106 can be any suitable deposition process. For example, deposition stage 1106 can include one or more CFD processes, a CVD process, a PECVD process, and the like. Although the embodiment of FIG. 11 shows a single etch phase 1104, it will be appreciated that a plurality of in-situ etch processes may be interleaved during a gap fill process during a plurality of deposition cycles of any suitable form.

圖12A-C繪示非平面基板在以上所述之原位沉積及蝕刻製程之實施例的各個階段之範例性橫剖面圖。圖12A顯示包含間隙1202之範例性非平面基板1200的橫剖面圖。間隙1202係覆蓋以薄膜1204。薄膜1204幾乎與間隙1202保形，但薄膜1204包含間隙1202的頂部附近之凹入部1206。 12A-C illustrate exemplary cross-sectional views of various stages of an embodiment of a non-planar substrate in the in situ deposition and etching process described above. FIG. 12A shows a cross-sectional view of an exemplary non-planar substrate 1200 including a gap 1202. The gap 1202 is covered with a film 1204. The film 1204 is substantially conformal to the gap 1202, but the film 1204 includes a recess 1206 near the top of the gap 1202.

在圖12B所示之實施例中，薄膜1204的凹入部1206已被選擇性移除，並且薄膜1204的上部區域1204A較下部區域1204B更細薄。可藉由在活性蝕刻物種加上質量轉移限制及/或壽命限制來達成凹入部之選擇性移除及/或側壁角度調整。在一些實施例中，在間隙1202的頂部進行選擇性蝕刻亦可調整間隙1202的側壁角度，使得間隙1202在頂部處較在底部處為寬。這可更降低後續沉積階段中的麵包條效應。在圖12C所示之實施例中，在後續沉積階段之後間隙1202幾乎被填滿且並未展現孔洞。 In the embodiment illustrated in Figure 12B, the recessed portion 1206 of the film 1204 has been selectively removed, and the upper region 1204A of the film 1204 is thinner than the lower region 1204B. Selective removal of the recesses and/or sidewall angle adjustment can be achieved by adding mass transfer limitations and/or lifetime limits to the active etch species. In some embodiments, selective etching at the top of the gap 1202 may also adjust the sidewall angle of the gap 1202 such that the gap 1202 is wider at the top than at the bottom. This can further reduce the bread stick effect in the subsequent deposition stage. In the embodiment shown in Figure 12C, the gap 1202 is almost filled and does not exhibit holes after the subsequent deposition phase.

圖15顯示原位蝕刻製程之另一實施例，其繪示用於銅電極之直通矽穿孔(TSV)。一些範例性TSV具有大約105微米的深度和大約6微米的直徑，因而產生大約17.5：1高寬比，且可具有大約攝氏200度之熱預算上限。如圖15之實施例所示，直通矽穿孔2500係由介電隔離層2502覆蓋以使矽基板與金屬填充穿孔電性隔離。範例性介電隔離層材料包含(但不限於)氧化矽、氮化矽、低k介電材料。在一些實施例中，上述之範例性蝕刻製程可 使用合適的濺鍍氣體(如氬)以物理濺鍍來對凹入部加以增補。 Figure 15 shows another embodiment of an in-situ etch process depicting through-via vias (TSV) for copper electrodes. Some exemplary TSVs have a depth of about 105 microns and a diameter of about 6 microns, thus producing an aspect ratio of about 17.5:1, and can have an upper thermal budget limit of about 200 degrees Celsius. As shown in the embodiment of Figure 15, the through vias 2500 are covered by a dielectric isolation layer 2502 to electrically isolate the germanium substrate from the metal filled vias. Exemplary dielectric spacer materials include, but are not limited to, hafnium oxide, tantalum nitride, low-k dielectric materials. In some embodiments, the exemplary etching process described above can be The recess is supplemented by physical sputtering using a suitable sputtering gas such as argon.

關於CFD薄膜的其他範例性應用包含(但不限於)用於後端製程(back-end-of-line)互連隔離應用之保形低k薄膜(例如在一些非限制性範例中k大約為3.0或更低)、用於蝕刻停止層與間隔層應用之保形氮化矽薄膜、保形抗反射層、以及銅黏附與阻障層。可使用CFD來製作用於BEOL處理之低k介電層的許多不同合成物。範例包含氧化矽、氧摻雜碳化物、碳摻雜氧化物、氧氮化物、及其類似者。 Other exemplary applications for CFD films include, but are not limited to, conformal low-k films for back-end-of-line interconnect isolation applications (eg, in some non-limiting examples k is approximately 3.0 or lower), conformal tantalum nitride film for etch stop and spacer applications, conformal anti-reflective layer, and copper adhesion and barrier layers. CFD can be used to make many different compositions for the low-k dielectric layer for BEOL processing. Examples include yttria, oxygen doped carbides, carbon doped oxides, oxynitrides, and the like.

在另一範例中，在一整合製程情形中，可在光阻「芯」上方沉積二氧化矽間隔層。使用光阻芯而非替代芯材料(如碳化矽層)可排除整合製程中的圖案化步驟。該製程可涉及使用正常微影技術使光阻圖案化並隨後直接在該芯上方沉積細薄的CFD氧化物層。可隨後使用方向性乾蝕刻製程來移除在圖案化光阻頂部及底部之CFD氧化物薄膜，而僅留下沿著圖案化光阻之側壁(視為渠溝)的材料。在此階段，可使用簡單的灰化來移除CFD氧化物留下之曝露芯。曾經有過單一光阻線的地方，此時便有二CFD氧化物線。該製程以此方式使圖案密度加倍；因此其有時稱為「雙重」圖案化。可惜光阻芯的使用可限制間隔層沉積溫度低於攝氏70度，其可低於習知CVD、PECVD、及/或ALD製程之沉積溫度。因此在一些實施例中，可在低於攝氏70度之溫度下沉積低溫CFD二氧化矽薄膜。應瞭解到在本發明的範圍內存在有用於合適的CFD產生薄膜之其他潛在整合製程應用。此外，在各種實施例中，如上述所沉積氮化矽之氮化物可在半導體裝置製造的各個階段中用作保形擴散阻障層及/或蝕刻停止層。 In another example, a cerium oxide spacer layer can be deposited over the photoresist "core" in an integrated process. The use of a photoresist core instead of a replacement core material (such as a tantalum carbide layer) eliminates the patterning steps in the integration process. The process can involve patterning the photoresist using normal lithography techniques and then depositing a thin layer of CFD oxide directly over the core. A directional dry etch process can then be used to remove the CFD oxide film on top and bottom of the patterned photoresist leaving only the material along the sidewalls of the patterned photoresist (which are considered trenches). At this stage, simple ashing can be used to remove the exposed core left by the CFD oxide. Where there was a single photoresist line, there were two CFD oxide lines. This process doubles the pattern density in this way; therefore it is sometimes referred to as "dual" patterning. Unfortunately, the use of a photoresist core can limit the spacer layer deposition temperature to less than 70 degrees Celsius, which can be lower than the deposition temperatures of conventional CVD, PECVD, and/or ALD processes. Thus, in some embodiments, a low temperature CFD ceria film can be deposited at temperatures below 70 degrees Celsius. It will be appreciated that there are other potential integrated process applications for a suitable CFD producing film within the scope of the present invention. Moreover, in various embodiments, the nitride of tantalum nitride deposited as described above can be used as a conformal diffusion barrier layer and/or an etch stop layer in various stages of semiconductor device fabrication.

雖然已在沉積、處理、及/或蝕刻單一薄膜形式上指出以上所述之各種CFD沉積製程，但應瞭解到在本發明的範圍內一些CFD製程可包含複數薄膜形式之原位沉積。例如，可原位沉積薄膜形式之替代層。在第一情形中，可藉由原位沉積氮化矽/氧化矽間隔層堆疊來製作用於閘極裝置之雙重間隔層。此可減短循環時間及增加處理站吞吐量，並且可避免由潛在薄膜層不相容性所形成之層間缺陷。在第二情形中，可沉積用於微影圖案化應用之抗反射層作為具有可調光學特性之SiON或非晶矽與SiOC的堆疊。 While the various CFD deposition processes described above have been indicated in the deposition, processing, and/or etching of a single film form, it should be understood that some CFD processes may include in situ deposition in the form of a plurality of films within the scope of the present invention. For example, an alternative layer in the form of a film can be deposited in situ. In the first case, a dual spacer layer for the gate device can be fabricated by depositing a tantalum nitride/yttria spacer stack in situ. This can reduce cycle time and increase throughput at the processing station, and can avoid inter-layer defects caused by potential film layer incompatibility. In the second case, an anti-reflective layer for lithographic patterning applications can be deposited as a stack of SiON or amorphous germanium and SiOC with tunable optical properties.

在一些實施例中，藉由保形薄膜沉積製程來形成含摻雜物源層。該層 稱為「源」層係因為其提供摻雜物物種(例如硼、磷、鎵、及/或砷之摻雜物原子)的來源。摻雜CFD層作為用於摻雜裝置中的下方(或上方)結構之摻雜物源。在源層形成後(或其形成期間)，將摻雜物物種驅入或用其他方式併入製作中裝置的相鄰結構中。在一些實施例中，於形成保形摻雜物源薄膜期間或之後藉由回火操作將摻雜物物種驅入。CFD的高保形本質允許摻雜非習知裝置結構，包括需要以三維方式摻雜之結構。CFD摻雜物源層通常藉由本文中所述之一或更多製程形成，但包括併入摻雜物物種之額外製程操作。在一些實施例中，介電層作為摻雜物物種併入其中之基底源層。 In some embodiments, the dopant-containing source layer is formed by a conformal thin film deposition process. This layer This is referred to as the "source" layer because it provides a source of dopant species such as dopant atoms of boron, phosphorus, gallium, and/or arsenic. The doped CFD layer acts as a dopant source for the underlying (or upper) structure in the doping device. After the source layer is formed (or during its formation), the dopant species are driven into or otherwise incorporated into adjacent structures in the fabrication apparatus. In some embodiments, the dopant species are driven in by a tempering operation during or after formation of the conformal dopant source film. The high conformal nature of CFD allows the doping of non-conventional device structures, including structures that need to be doped in three dimensions. The CFD dopant source layer is typically formed by one or more of the processes described herein, but includes additional process operations incorporating dopant species. In some embodiments, the dielectric layer acts as a substrate source layer into which the dopant species are incorporated.

例如，可使用摻雜氧化矽作為硼、磷、砷等等之擴散源。例如，可使用硼摻雜矽酸鹽玻璃(BSG)、磷摻雜矽酸鹽玻璃(PSG)、或硼磷摻雜矽酸鹽玻璃(BPSG)。 For example, doped cerium oxide can be used as a diffusion source of boron, phosphorus, arsenic, or the like. For example, boron doped tellurite glass (BSG), phosphorus doped tellurite glass (PSG), or borophosphorus doped tellurite glass (BPSG) can be used.

摻雜CFD層可用以在例如多閘極鰭狀電晶體(FinFET)及三維記憶體裝置之三維電晶體結構中提供保形摻雜。一些三維結構的例子可見於J.Kavalieros等人於Symp.VLSI Tech Pg 50,2006所提出之「Tri-gate(Intel)」以及Yamashita等人(IBM Alliance)於VLSI 2011所提出之「FinFET」，其皆於此全部併入作為參考。習知的離子植入機無法容易地摻雜側壁，尤其在高的高寬比結構中。此外，在i3D結構的密集陣列中，可能在植入機中存在方向性離子束之陰影效應，從而引起傾斜植入角度之嚴重的劑量殘留問題。除了習知矽基微電子學外，CFD摻雜的其他應用還包括基於如GaAS之III-V族半導體以及如HgCdTe之II-VI族半導體的微電子學與光電子學、光伏電池、平面顯示器、以及電致變色技術。 The doped CFD layer can be used to provide conformal doping in, for example, a multi-gate fin transistor (FinFET) and a three-dimensional transistor structure of a three-dimensional memory device. Examples of some three-dimensional structures can be found in "Tri-gate (Intel)" proposed by J. Kavalieros et al. in Symp. VLSI Tech Pg 50, 2006, and "FinFET" proposed by Yamashita et al. (IBM Alliance) in VLSI 2011. They are all incorporated herein by reference. Conventional ion implanters do not readily dope sidewalls, especially in high aspect ratio structures. Furthermore, in dense arrays of i3D structures, there may be shadowing effects of directional ion beams in the implanter, causing severe dose sticking problems with oblique implant angles. In addition to conventional 矽-based microelectronics, other applications for CFD doping include microelectronics and optoelectronics based on GaAS-based III-V semiconductors and II-VI semiconductors such as HgCdTe, photovoltaic cells, flat panel displays, And electrochromic technology.

圖16顯示具有三維閘極結構之電晶體，其中源極和汲極形成為難以藉由習知離子植入技術來摻雜之細薄垂直結構。然而，當n或p型摻雜CFD氧化物之薄層形成於垂直結構上方時，則完成保形摻雜。已觀察到保形摻雜在三維裝置中由於串聯電阻的降低而增加10-25%之電流密度。見Yamashita等人於VLSI 2011提出之文獻。 Figure 16 shows a transistor having a three-dimensional gate structure in which the source and drain are formed into a thin vertical structure that is difficult to do by conventional ion implantation techniques. However, when a thin layer of n- or p-type doped CFD oxide is formed over the vertical structure, conformal doping is completed. It has been observed that conformal doping increases the current density by 10-25% due to the reduction in series resistance in a three-dimensional device. See the literature presented by Yamashita et al. in VLSI 2011.

CFD摻雜氧化物作為擴散源具有各種優點。首先，其於低溫下提供高保形性。因為摻雜薄膜可能為犧牲層，故非保形薄膜通常在移除時面臨更多挑戰，即一些區域會被過度蝕刻。如所說明般，CFD提供高保形薄膜。 此外，CFD提供控制極佳的摻雜濃度。CFD製程可提供一或更多未摻雜氧化物層後接如所需之單一摻雜層。可藉由用以沉積摻雜層之頻率以及摻雜循環的條件來嚴格地控制摻雜的程度。在一些實施例中，摻雜循環係藉由例如使用具有明顯空間位阻之摻雜物源來控制。 CFD doped oxides have various advantages as a diffusion source. First, it provides high conformality at low temperatures. Because the doped film may be a sacrificial layer, non-conformal films typically face more challenges when removed, ie some areas are over-etched. As illustrated, CFD provides a high conformal film. In addition, CFD provides excellent doping concentration control. The CFD process can provide one or more undoped oxide layers followed by a single doped layer as desired. The degree of doping can be strictly controlled by the conditions used to deposit the frequency of the doped layer and the doping cycle. In some embodiments, the doping cycle is controlled by, for example, using a dopant source having significant steric hindrance.

圖17以沿著x軸前進時間由左至右呈現基線CFD操作的順序。許多變化受到支持，並且此圖示僅為說明之目的而提出。在順序之初始(於操作A期間)，將氣相氧化劑導入反應腔室中，該腔室包含待沉積CFD薄膜於其上之基板。合適的氧化劑之範例包括元素氧(例如O2或O3)、一氧化二氮(N2O)、水、如異丙醇之烷基醇、一氧化碳、以及二氧化碳。氧化劑通常與例如氬或氮之惰性氣體一起提供。 Figure 17 shows the sequence of baseline CFD operations from left to right with advance time along the x-axis. Many variations are supported and this illustration is presented for illustrative purposes only. At the beginning of the sequence (during operation A), a vapor-phase oxidant is introduced into the reaction chamber containing the substrate onto which the CFD film is to be deposited. Suitable examples of the oxidizing agent comprises elemental oxygen (e.g. O 2 or O 3), nitrous oxide (N 2 O), water, alkyl alcohols such as isopropyl alcohol, carbon monoxide, and carbon dioxide. The oxidant is typically supplied with an inert gas such as argon or nitrogen.

接著，在操作B中，將介電質前驅物暫時導入反應腔室中。選取操作B的持續時間以允許足夠支持薄膜生長的一個循環之前驅物數量吸附至基板表面上。在一些實施例中，前驅物使基板表面飽和。將依其產生所期望成分之介電質的能力來選取前驅物。介電質成分的例子包含氧化矽(包括矽酸鹽玻璃)、氮化矽、氧氮化矽、以及氧碳化矽。合適前驅物的例子包含烷胺基矽烷(alkylamino silanes)(SiHx(NR2)4-x)(其中x=1-3，並且R包含如甲基、乙基、丙基、以及丁基各種同分異構配置之烷基)、以及鹵素矽烷(halosilanes)(SiHxY4-x)(其中x=1-3，並且Y包含Cl、Br、以及I)。更具體範例包含二烷胺基矽烷以及空間位阻烷基矽烷。在一具體範例中，BTBAS係用以產生氧化矽之前驅物。 Next, in operation B, the dielectric precursor is temporarily introduced into the reaction chamber. The duration of operation B is selected to allow adsorption of the number of precursors onto the substrate surface prior to one cycle sufficient to support film growth. In some embodiments, the precursor saturates the surface of the substrate. The precursor will be selected based on its ability to produce the dielectric of the desired composition. Examples of the dielectric component include cerium oxide (including silicate glass), cerium nitride, cerium oxynitride, and cerium oxycarbonate. Examples of suitable precursors include alkylamino silanes (SiH x (NR 2 ) 4-x ) (where x = 1-3, and R contains various groups such as methyl, ethyl, propyl, and butyl isomeric configuration of the same sub-group), halo and alkoxy silicon (halosilanes) (SiH x Y 4 -x) ( where x = 1-3, and Y comprises Cl, Br, and I). More specific examples include dialkylamino decanes and sterically hindered alkyl decanes. In a specific example, BTBAS is used to generate a cerium oxide precursor.

於操作B期間，使階段A期間導入腔室中之氧化劑持續流入。在一些實施例中，其以如操作A期間之相同速率及相同濃度持續流入。在操作B結束時，使進入腔室之介電質前驅物的流量停止，並且操作C如所述般開始。於操作C期間，使氧化劑和惰性氣體如操作A及B期間持續流入以清除在反應腔室中的剩餘介電質前驅物。 During operation B, the oxidant introduced into the chamber during phase A continues to flow. In some embodiments, it continues to flow in at the same rate and at the same concentration as during operation A. At the end of operation B, the flow of the dielectric precursor entering the chamber is stopped and operation C begins as described. During operation C, the oxidant and inert gases are continuously flowed during operations A and B to purge the remaining dielectric precursors in the reaction chamber.

於操作C期間清除完成之後，前驅物在基板表面上反應而形成介電薄膜的一部份(見操作D)。在各種實施例中，施加電漿以驅動吸附介電質前驅物之反應。在一些範例中，此反應為氧化反應。一些先前流入反應腔室中的氧化劑可與介電質前驅物一起吸附至表面上，從而提供用於電漿介導表 面反應之立即可用的氧化劑。 After the cleaning is completed during operation C, the precursor reacts on the surface of the substrate to form a portion of the dielectric film (see operation D). In various embodiments, a plasma is applied to drive the reaction of adsorbing a dielectric precursor. In some examples, the reaction is an oxidation reaction. Some of the oxidant previously flowing into the reaction chamber can be adsorbed onto the surface along with the dielectric precursor to provide a plasma mediated table The ready-to-use oxidant for the surface reaction.

操作A至D共同提供介電薄膜沉積製程之單一循環。應瞭解到於本文中所述之其他CFD實施例可用以代替此處所述之基本循環。在所描述之實施例中，在不導入任何摻雜物物種的情況下執行沉積循環(A至D)。在各種實施例中，由操作A至D所代表的循環在導入摻雜物物種之前連續地重複一或更多次。這在圖17的階段E中圖例說明。在一些範例中，在導入摻雜物之前重複操作A-D至少一次、或至少二次、或至少五次。 Operations A through D collectively provide a single cycle of the dielectric thin film deposition process. It should be understood that other CFD embodiments described herein may be used in place of the basic cycles described herein. In the described embodiment, the deposition cycle (A to D) is performed without introducing any dopant species. In various embodiments, the cycle represented by operations A through D is repeated one or more times continuously prior to introduction of the dopant species. This is illustrated in the diagram E of Figure 17. In some examples, operation A-D is repeated at least once, or at least twice, or at least five times prior to introduction of the dopant.

作為一範例，介電層以約0.5至1埃/循環的速率沉積。在一或更多循環(A-D的重複)之每一者自始至終使氧化劑持續流入反應腔室中。 As an example, the dielectric layer is deposited at a rate of about 0.5 to 1 angstrom per cycle. The oxidant is continuously flowed into the reaction chamber throughout each of one or more cycles (repetition of A-D).

在製程中的一些時間點，介電層沉積循環被摻雜物前驅物物種(例如乙硼烷)之導入所中斷。此圖例說明如圖式中的操作F。可提供於介電源薄膜中之摻雜物的範例包含如硼、鎵、磷、砷、以及其他摻雜物之III及IV價元素。除了乙硼烷之外，摻雜物前驅物之範例還包括磷化氫及其他氫化物源。亦可使用如烷基前驅物(例如三甲基鎵)、鹵素前驅物(例如氯化鎵)之非氫化物摻雜物。 At some point in the process, the dielectric layer deposition cycle is interrupted by the introduction of a dopant precursor species such as diborane. This illustration illustrates the operation F in the figure. Examples of dopants that can be provided in a dielectric film include III and IV valence elements such as boron, gallium, phosphorus, arsenic, and other dopants. In addition to diborane, examples of dopant precursors include phosphine and other hydride sources. Non-hydride dopants such as alkyl precursors (e.g., trimethylgallium), halogen precursors (e.g., gallium chloride) can also be used.

在一些變化形式中，將摻雜物沉積在與下方基板的界面處，後接以摻雜物脈衝散置在每x數目循環的CFD循環(如所述般)，並且選擇性地蓋上可為CFD氧化物薄膜之未摻雜保護「覆蓋」層。見圖18中所產生堆疊之範例。 In some variations, the dopant is deposited at the interface with the underlying substrate, followed by a dopant pulse interspersed in every x number of cycles of the CFD cycle (as described), and optionally capped It is an undoped "cover" layer of the CFD oxide film. See the example of the stack produced in Figure 18.

在一具體實施例中，將摻雜物前驅物物種與如惰性氣體(例如氬)之載體氣體以混合物的形式(但不與氧化劑或其他反應物混合)提供至反應腔室。因此，在此基線範例中，於操作F期間停止氧化劑的流量。在其他實施例中，將前驅物與還原劑或氧化劑一起導入。在一些實施例中，摻雜物對載體氣體的濃度介於約1：5及1：20之間。在一些實施例中，摻雜物沉積溫度介於約300及400℃之間。摻雜物曝露步驟的持續時間根據目標摻雜物濃度而變化。在一些實施例中，曝露步驟介於約2.5秒及7.5秒之間。在一具體實施例中，在3 Torr的壓力及約400℃下於10000 sccm的氬中流入1000 sccm的乙硼烷。 In a specific embodiment, a dopant precursor species is provided to the reaction chamber in the form of a mixture (but not mixed with an oxidant or other reactant) with a carrier gas such as an inert gas such as argon. Therefore, in this baseline example, the flow of oxidant is stopped during operation F. In other embodiments, the precursor is introduced with a reducing agent or oxidizing agent. In some embodiments, the concentration of dopant to carrier gas is between about 1:5 and 1:20. In some embodiments, the dopant deposition temperature is between about 300 and 400 °C. The duration of the dopant exposure step varies depending on the target dopant concentration. In some embodiments, the exposing step is between about 2.5 seconds and 7.5 seconds. In one embodiment, 1000 sccm of diborane is flowed into 10,000 sccm of argon at a pressure of 3 Torr and at about 400 °C.

在一些實施例中，藉由非表面限制機制使摻雜物前驅物聚集在基板表 面上。舉例而言，前驅物可藉由CVD式製程沉積而非ALD(表面吸附限制)製程。 In some embodiments, the dopant precursor is aggregated on the substrate surface by a non-surface confinement mechanism On the surface. For example, the precursor can be deposited by a CVD process rather than an ALD (surface adsorption limited) process.

在進一步處理介電薄膜之前，摻雜物前驅物選擇性地自反應腔室被清除。此外，如圖17所繪示，摻雜物前驅物之遞送後接可由電漿、升高之溫度等等中介之選擇性活化操作G。在乙硼烷作為摻雜物前驅物的範例中，活化操作轉換乙硼烷成元素硼。在操作G完成後，該製程以選擇性清除(未顯示)來接續。 The dopant precursor is selectively removed from the reaction chamber prior to further processing of the dielectric film. In addition, as illustrated in FIG. 17, the delivery of the dopant precursor is followed by a selective activation operation G that may be intervened by plasma, elevated temperature, and the like. In the example of diborane as a dopant precursor, the activation operation converts diborane to elemental boron. After operation G is completed, the process is selectively cleared (not shown) to continue.

在涉及CVD乙硼烷摻雜物的範例中，活化操作僅為溫度基礎分解以產生硼。此為易受溫度影響的製程。在較高溫度下，以每單位厚度相同的硼濃度為目標下可採用相對短的曝露時間。或者，在一些製程中(例如那些採用三甲基甲硼烷(TMB)的製程)，活化可涉及電漿或熱氧化步驟。至於一些其他前驅物，可適當採用「釘扎」(“pinning”)步驟以保留自由硼或其他摻雜物在適當的地方。此可使用「釘扎」電漿來完成。 In an example involving a CVD diborane dopant, the activation operation is only a temperature base decomposition to produce boron. This is a process that is susceptible to temperature. At higher temperatures, a relatively short exposure time can be employed with the same boron concentration per unit thickness. Alternatively, in some processes, such as those using trimethylborane (TMB), activation may involve a plasma or thermal oxidation step. As for some other precursors, a "pinning" step can be suitably employed to retain free boron or other dopants in place. This can be done using "pinning" plasma.

在一些實施例中，電漿活化涉及適合於使碳併入薄膜中之任何頻率的RF功率。在一些實施例中，RF電源供應可配置成彼此獨立地控制高頻及低頻RF電源。範例性低頻RF功率可包含(但不限於)介於約200 kHz及1000 kHz之間的頻率。範例性高頻RF功率可包含(但不限於)介於約10 MHz及80 MHz之間的頻率(例如13.56 MHz)。同樣地，RF電源供應與匹配網路可在任何合適的功率下操作以形成電漿。合適的功率之範例包含(但不限於)對於高頻電漿介於約100 W及3000 W之間的功率、以及對於低頻電漿介於約100 W及10000 W之間的功率(在每一晶圓基礎上)。RF電源供應可在任何合適的工作週期下操作。合適的工作週期之範例包含(但不限於)介於約5%及90%之間的工作週期。可接受的製程壓力通常介於約0.5-5 Torr之間，且較佳地約2-4 Torr之間。至於在曝露至摻雜物之前的一些(下方基板之)電漿處理，已發現在高達約10 Torr(或高達約9 Torr)之壓力下運作良好。 In some embodiments, plasma activation involves RF power at any frequency suitable for incorporation of carbon into the film. In some embodiments, the RF power supply can be configured to control the high frequency and low frequency RF power sources independently of each other. Exemplary low frequency RF power can include, but is not limited to, frequencies between about 200 kHz and 1000 kHz. Exemplary high frequency RF power can include, but is not limited to, frequencies between about 10 MHz and 80 MHz (eg, 13.56 MHz). Likewise, the RF power supply and matching network can operate at any suitable power to form a plasma. Examples of suitable power include, but are not limited to, power between about 100 W and 3000 W for high frequency plasma, and between about 100 W and 10000 W for low frequency plasma (in each On a wafer basis). The RF power supply can be operated at any suitable duty cycle. Examples of suitable duty cycles include, but are not limited to, a duty cycle between about 5% and 90%. Acceptable process pressures are typically between about 0.5 and 5 Torr, and preferably between about 2-4 Torr. As for some plasma treatment (under the substrate) prior to exposure to the dopant, it has been found to work well at pressures up to about 10 Torr (or up to about 9 Torr).

下表總結可用於各種BSG製程之電漿參數的範圍： The following table summarizes the range of plasma parameters that can be used for various BSG processes:

在所描述之基線製程中，介電層沉積及間歇性摻雜物遞送之循環(操作A至G)可如圖式之階段H中所示執行多次。製程順序重複次數的實際數目取決於所期望之薄膜的總厚度、以及每一循環所沉積之介電層的厚度、以及摻雜物併入薄膜中的數量。在一些實施例中，操作A-G至少重複二次、或至少三次、或至少五次、或至少約十次。 In the described baseline process, the cycles of dielectric layer deposition and intermittent dopant delivery (operations A through G) can be performed as many times as shown in stage H of the equation. The actual number of process sequence repetitions depends on the total thickness of the desired film, as well as the thickness of the dielectric layer deposited per cycle, and the amount of dopant incorporated into the film. In some embodiments, the operations A-G are repeated at least twice, or at least three times, or at least five times, or at least about ten times.

在介電薄膜完全沉積之後，其可用作附近半導體結構之摻雜物物種源。此可藉由如圖17之操作I所示將摻雜物自沉積薄膜驅入裝置結構中來完成。在各種實施例中，驅入係藉由如回火之熱介導擴散製程來完成。在一些情況下，尤其是那些採用極淺接面的情況下，可採用雷射尖峰回火。 After the dielectric film is completely deposited, it can be used as a source of dopant species for nearby semiconductor structures. This can be accomplished by driving dopants from the deposited film into the device structure as shown in operation I of FIG. In various embodiments, the drive-in is accomplished by a heat-mediated diffusion process such as tempering. In some cases, especially those with very shallow junctions, laser spike tempering can be used.

可實現在此基線製程上的許多變化。這些變化的其中一些以增加可用於擴散進入鄰近半導體結構中之摻雜物的數量作為其目標。其他變化係設計以控制藉以自源薄膜將摻雜物遞送入附近半導體結構中之速率。另外其他變化控制摻雜物物種擴散的方向。通常，理想上傾向摻雜物之擴散朝向裝置結構且遠離薄膜的反側。 Many variations on this baseline process can be achieved. Some of these variations are targeted by increasing the amount of dopant that can be used to diffuse into adjacent semiconductor structures. Other variations are designed to control the rate at which dopants are delivered from the source film into nearby semiconductor structures. Still other variations control the direction in which the dopant species diffuse. Generally, it is desirable to have the dopant diffuse toward the device structure and away from the opposite side of the film.

在一些實施例中，摻雜物藉以導入生長中介電薄膜之頻率係受到控制。更頻繁的摻雜物前驅物遞送循環導致在最後的介電薄膜中摻雜物之整體較大濃度。其亦導致遍及薄膜之摻雜物的相對均勻分佈。當***較少摻雜物前驅物遞送循環在沉積製程中時，則薄膜中高摻雜物濃度的區域比摻雜物遞送循環較頻繁時的情況分隔得更開。 In some embodiments, the frequency at which the dopant is introduced into the growth dielectric film is controlled. The more frequent dopant precursor delivery cycle results in a larger overall concentration of dopant in the final dielectric film. It also results in a relatively uniform distribution of dopants throughout the film. When a less dopant precursor delivery cycle is inserted during the deposition process, the region of high dopant concentration in the film is spaced apart more than when the dopant delivery cycle is more frequent.

在一實施例中，於介電層沉積的每一循環遞送摻雜物前驅物至生長中介電薄膜一次。在另一實施例中，於介電層沉積的每隔一循環期間遞送摻雜物前驅物一次。在其他實施例中，更低頻率之摻雜物前驅物遞送循環包含在製程中。舉例而言，可於介電層沉積的每第三、第四、或第五循環期間遞送摻雜物前驅物一次。在一些情況下，以每5-20個介電層沉積循環期間大約一次的頻率來遞送摻雜物前驅物。 In one embodiment, the dopant precursor is delivered to the growth dielectric film once per cycle of dielectric layer deposition. In another embodiment, the dopant precursor is delivered once every other cycle of dielectric layer deposition. In other embodiments, a lower frequency dopant precursor delivery cycle is included in the process. For example, the dopant precursor can be delivered once every third, fourth, or fifth cycle of dielectric layer deposition. In some cases, the dopant precursor is delivered at a frequency of about once every 5-20 dielectric layer deposition cycles.

應瞭解到摻雜物前驅物導入生長中薄膜的頻率在介電薄膜沉積的過程 中不必一致。考慮到這點，所產生之介電薄膜可具有分等級的摻雜物成分使得在沉積介電薄膜之厚度中摻雜物的平均濃度不均勻。在一實施例中，在鄰接待摻雜半導體裝置結構之介電薄膜的一側上摻雜物的濃度較大。當然，介電薄膜中摻雜物濃度梯度可藉由在整個介電層沉積製程的過程中謹慎地改變摻雜物遞送循環的頻率而修改成所期望者。 It should be understood that the frequency of introduction of the dopant precursor into the growing film during the deposition of the dielectric film There is no need to be consistent. In view of this, the resulting dielectric film can have a graded dopant composition such that the average concentration of dopants in the thickness of the deposited dielectric film is not uniform. In one embodiment, the concentration of dopants on the side of the dielectric film adjacent to the semiconductor device structure to be doped is relatively large. Of course, the dopant concentration gradient in the dielectric film can be modified to the desired by carefully varying the frequency of the dopant delivery cycle throughout the dielectric layer deposition process.

基線製程上的另一變化涉及在任何摻雜物前驅物遞送循環期間調整所遞送之摻雜物前驅物的數量。於任何特定的摻雜物遞送循環期間所遞送之摻雜物前驅物的數量將由遞送至反應腔室之摻雜物前驅物的濃度以及基板曝露至所遞送之摻雜物前驅物的持續時間來決定。 Another variation in the baseline process involves adjusting the amount of dopant precursor delivered during any dopant precursor delivery cycle. The amount of dopant precursor delivered during any particular dopant delivery cycle will be the concentration of dopant precursor delivered to the reaction chamber and the duration of exposure of the substrate to the delivered dopant precursor. Decide.

如以上所示，可經由類似CVD製程提供一些摻雜物前驅物至生長中薄膜上。在如此情況下，在任何特定循環中遞送至生長中薄膜之摻雜物前驅物的數量不受限於吸附或其他表面介導現象。因此，在任一摻雜物遞送循環所提供之摻雜物前驅物的數量可相對大且可控制。在任何摻雜物遞送循環期間遞送之摻雜物前驅物達到更大量的程度，則介電薄膜中摻雜物的整體濃度增加。此可補償在整個製程中具有相對不頻繁摻雜物前驅物遞送循環的效應。然而，必須瞭解到增加任何特定的摻雜物前驅物遞送循環期間所遞送摻雜物的數量可能導致薄膜中相對高之摻雜物的局部濃度。當然，如此之摻雜物濃度尖峰可藉由回火或其他在介電薄膜中摻雜物藉以擴散以使其濃度變得更均勻的操作使之柔和。 As indicated above, some dopant precursors can be provided to the growing film via a similar CVD process. In such cases, the amount of dopant precursor delivered to the growing film in any particular cycle is not limited to adsorption or other surface mediated phenomena. Thus, the amount of dopant precursor provided in any dopant delivery cycle can be relatively large and controllable. The dopant precursor delivered during any dopant delivery cycle reaches a greater extent, and the overall concentration of dopant in the dielectric film increases. This can compensate for the effects of relatively infrequent dopant precursor delivery cycles throughout the process. However, it must be understood that increasing the amount of dopant delivered during any particular dopant precursor delivery cycle may result in a local concentration of relatively high dopants in the film. Of course, such dopant concentration spikes can be softened by tempering or other operations in which the dopants in the dielectric film diffuse to make their concentration more uniform.

在硼作為摻雜物的情況下，典型的硼前驅物遞送循環期間所遞送之硼通量依據目標薄膜濃度可從約7.5 ML(百萬朗繆爾，Mega-Langmuirs)變化至30 ML(ML為通量/曝露之單位)。 In the case of boron as a dopant, the boron flux delivered during a typical boron precursor delivery cycle can vary from about 7.5 ML (Mega-Langmuirs) to 30 ML (ML) depending on the target film concentration. For flux/exposure units).

在一些實施例中，在每一前驅物遞送循環中所遞送之摻雜物前驅物的數量在全部介電薄膜的生長並非自始至終固定。因此，可修改每一循環所遞送之摻雜物前驅物的數量以便在介電薄膜中產生期望之摻雜物濃度梯度。例如，理想上可在那些發生在介電薄膜中相對靠近待摻雜半導體裝置特徵部的位置之摻雜物前驅物遞送循環中提供更大量的摻雜物前驅物。所產生之濃度梯度在鄰接待摻雜裝置結構之薄膜區域中具有較大的摻雜物濃度。 In some embodiments, the amount of dopant precursor delivered in each precursor delivery cycle is not fixed throughout the growth of the dielectric film. Thus, the amount of dopant precursor delivered per cycle can be modified to produce a desired dopant concentration gradient in the dielectric film. For example, it may be desirable to provide a greater amount of dopant precursor in a dopant precursor delivery cycle that occurs in a dielectric film that is relatively close to the location of the semiconductor device to be doped. The resulting concentration gradient has a larger dopant concentration in the region of the film adjacent to the structure of the device to be doped.

在一些實施例中，摻雜物前驅物係以吸附限制方式併入到基板表面上。在如此前驅物的情況下，經由類似ALD製程(相對於如以上所述類似CVD方式)進行摻雜物導入至薄膜中。藉由吸收介導過程而黏附至基板表面之摻雜物前驅物的範例包含三甲基硼烷、以及其他如三甲基鎵之烷基前驅物。藉由類似CVD製程而累積在基板表面上之摻雜物前驅物的範例包含乙硼烷、磷化氫、以及砷化氫。 In some embodiments, the dopant precursor is incorporated onto the surface of the substrate in an adsorption limited manner. In the case of such a precursor, dopants are introduced into the film via an ALD-like process (as opposed to a CVD process as described above). Examples of dopant precursors that adhere to the surface of the substrate by absorption mediated processes include trimethylborane, as well as other alkyl precursors such as trimethylgallium. Examples of dopant precursors accumulated on the surface of a substrate by a CVD-like process include diborane, phosphine, and arsine.

一般而言，介電薄膜中摻雜物的可濃度分佈可修改為適當者。在一實施例中，摻雜物濃度在鄰接待摻雜結構之薄膜的邊緣處突升至高位準。在一些實施例中，該濃度在整個薄膜厚度間歇地上升及下降。在一範例中，僅於下方基板與CFD介電層之間的界面處提供摻雜物(例如硼)。此摻雜物層有時稱為「尖峰層」(“spike layer”)。在一些情況下，使摻雜物曝露產生脈衝(使用例如CVD曝露至摻雜物前驅物)而非採用單一步驟，從而增加摻雜物併入之晶圓內一致性。在另一範例中，將CFD氧化物或其他介電質與摻雜物一起散佈(例如在摻雜BSG中的硼)。見圖18及19。散佈之摻雜介電質可在具有或不具有尖峰層的情況下提供。又另一範例中，未摻雜CFD氧化物或其他介電罩作為保護層。再次見圖18及19。 In general, the concentration distribution of dopants in the dielectric film can be modified as appropriate. In one embodiment, the dopant concentration is raised to a high level at the edge of the film adjacent the structure to be doped. In some embodiments, the concentration rises and falls intermittently throughout the thickness of the film. In one example, dopants (eg, boron) are provided only at the interface between the underlying substrate and the CFD dielectric layer. This dopant layer is sometimes referred to as a "spike layer". In some cases, the dopant exposure is pulsed (using, for example, CVD exposure to the dopant precursor) rather than using a single step, thereby increasing intra-wafer uniformity of dopant incorporation. In another example, a CFD oxide or other dielectric is interspersed with the dopant (eg, boron doped in the BSG). See Figures 18 and 19. The dispersed doped dielectric can be provided with or without a peak layer. In yet another example, an undoped CFD oxide or other dielectric cover acts as a protective layer. See Figures 18 and 19 again.

摻雜物物種存留於其中之介電薄膜可自我修改以影響摻雜物物種的擴散通過薄膜本身。例如，可控制薄膜密度及/或化學成份以便在摻雜物物種擴散上產生期望之影響。在一些方法中，整個介電層厚度具有相同密度或成份使得修改之摻雜物擴散特性在整個薄膜厚度始終不變。在其他方法中，修改薄膜特性以使摻雜物擴散在薄膜厚度範圍內變化。例如，發明人已發現可改變電漿氧化參數以使CFD氧化物較不密集，從而允許於回火期間較多摻雜物擴散橫越CFD氧化物。 The dielectric film in which the dopant species remain can be self-modifying to affect the diffusion of the dopant species through the film itself. For example, film density and/or chemical composition can be controlled to produce the desired effect on dopant species diffusion. In some methods, the entire dielectric layer thickness has the same density or composition such that the modified dopant diffusion characteristics are constant throughout the film thickness. In other methods, the film properties are modified to allow dopant diffusion to vary over the thickness of the film. For example, the inventors have discovered that the plasma oxidation parameters can be varied to make the CFD oxide less dense, allowing more dopant to diffuse across the CFD oxide during tempering.

在一些實施例中，修改介電薄膜的成分(或用以形成薄膜之處理氣體)來影響其中摻雜物擴散。已發現到例如於介電薄膜沉積循環期間在遞送至反應腔室之氧化劑處理氣體中的氮對氧比率影響摻雜物物種擴散通過介電薄膜的能力。舉例而言，較大量的氮存在於介電薄膜形成期間所使用之氧化劑氣體中導致介電薄膜具有對摻雜物擴散明顯的阻抗性。相較之下，相對較大量的氧存在該氣體中導致該薄膜具有對摻雜物擴散較小許多的阻抗 性。可藉由含氮化合物(例如N2O)或元素氮(N2)的方式來提供存在於處理氣體的氮。在各種實施例中，於介電薄膜沉積循環期間持續流入之氧化劑包含一氧化二氮。 In some embodiments, the composition of the dielectric film (or process gas used to form the film) is modified to affect dopant diffusion therein. It has been discovered, for example, that the nitrogen to oxygen ratio in the oxidant treatment gas delivered to the reaction chamber during the dielectric thin film deposition cycle affects the ability of the dopant species to diffuse through the dielectric film. For example, the presence of a relatively large amount of nitrogen in the oxidant gas used during the formation of the dielectric film results in the dielectric film having a significant resistance to dopant diffusion. In contrast, the presence of a relatively large amount of oxygen in the gas causes the film to have a much lesser resistance to dopant diffusion. By nitrogen-containing compound may be (e.g., N 2 O) or elemental nitrogen (N 2) provided by way of the nitrogen present in the process gas. In various embodiments, the oxidant that continues to flow during the dielectric film deposition cycle comprises nitrous oxide.

在一些實施例中，藉由在介電薄膜的初始生長階段期間最初使用高氧含量及相對低氮含量之氧化劑氣體來製作介電薄膜。稍後，在待摻雜之基板結構上形成部份薄膜之後，改變氧化劑氣體的成分使得其相對富含較多氮。舉例而言，於初始沉積循環期間，用於介電薄膜之氧化劑氣體可完全包含分子氧。在稍後的介電層沉積循環中，改變氧化劑氣體使得至少一部份的氧由一氧化二氮取代。假設目標為提高朝薄膜的底部方向擴散並阻止朝薄膜的頂部方向擴散(假設待摻雜之裝置結構位於介電薄膜下方)。發明人已發現若氮濃度位準大於約1E20 atoms/cc(由例如SIMS量測)，則對於硼擴散阻止作用顯著。相較之下，在約1E19 atoms/cc或更低的氮濃度位準時，實際上可忽略阻止作用。 In some embodiments, the dielectric film is fabricated by initially using a high oxygen content and a relatively low nitrogen content of oxidant gas during the initial growth phase of the dielectric film. Later, after a partial film is formed on the substrate structure to be doped, the composition of the oxidant gas is changed such that it is relatively rich in nitrogen. For example, the oxidant gas for the dielectric film may completely contain molecular oxygen during the initial deposition cycle. In a later dielectric layer deposition cycle, the oxidant gas is changed such that at least a portion of the oxygen is replaced by nitrous oxide. It is assumed that the goal is to increase diffusion toward the bottom of the film and prevent diffusion toward the top of the film (assuming that the device structure to be doped is below the dielectric film). The inventors have found that if the nitrogen concentration level is greater than about 1E20 atoms/cc (measured by, for example, SIMS), the boron diffusion blocking effect is significant. In contrast, at a nitrogen concentration level of about 1E19 atoms/cc or lower, the blocking effect is practically negligible.

從薄膜成分本身的觀點而言，薄膜中的氮含量可從接近待摻雜基板結構的薄膜部份中相對低位準變化至位於待摻雜結構對面的部份中相對較高位準。 From the viewpoint of the film composition itself, the nitrogen content in the film may vary from a relatively low level in the film portion close to the substrate structure to be doped to a relatively high level in the portion opposite the structure to be doped.

於介電薄膜形成期間採用之沉積溫度亦影響摻雜物原子在薄膜內部擴散的能力。一般而言，已發現到藉由CFD處理在相對低溫下沉積之介電層通常允許相對高摻雜物擴散速率。與相對高摻雜物擴散速率相關聯之相對低溫的範例為約300至400℃範圍中的溫度，或更具體地介於約350至400℃之間。當然，這些溫度範圍取決於介電質前驅物的選取以及其他沉積參數。雖然其可與一些前驅物一起採用，但其特別適合於使用BTBAS作為介電質前驅物。 The deposition temperature employed during the formation of the dielectric film also affects the ability of the dopant atoms to diffuse inside the film. In general, it has been discovered that dielectric layers deposited at relatively low temperatures by CFD processing generally allow for relatively high dopant diffusion rates. An example of a relatively low temperature associated with a relatively high dopant diffusion rate is a temperature in the range of about 300 to 400 °C, or more specifically between about 350 and 400 °C. Of course, these temperature ranges depend on the choice of dielectric precursor and other deposition parameters. Although it can be used with some precursors, it is particularly suitable for use with BTBAS as a dielectric precursor.

相較之下，在相對較高溫下沉積之介電層傾向於阻抗摻雜物物種的擴散。在使用BTBAS作為介電質前驅物的情況下，與相對低摻雜物擴散速率相關聯之相對高溫為約350至400℃的範圍中，或更具體地介於約300至380℃之間。當然，這些溫度可應用至其他前驅物。此外，雖然事實為更高溫度通常產生阻抗摻雜物擴散之更緻密薄膜，但亦可經由其他如電漿氧化期間之RF曝露時間及功率來控制擴散性及/或密度。可於CFD氧化物生長 期間採用之基線參數的範例包括(1)在約200-2500 Watts之高頻電漿(對於300 mm晶圓)，通常無低頻電漿、以及(2)在約0.2至1.5秒範圍中之電漿曝露時間。 In contrast, dielectric layers deposited at relatively high temperatures tend to diffuse the dopant species. Where BTBAS is used as the dielectric precursor, the relative high temperature associated with the relatively low dopant diffusion rate is in the range of about 350 to 400 °C, or more specifically between about 300 and 380 °C. Of course, these temperatures can be applied to other precursors. Moreover, while the fact that higher temperatures typically result in a denser film of impedance dopant diffusion, diffusion and/or density can also be controlled via other RF exposure times and power during plasma oxidation. Can grow in CFD oxide Examples of baseline parameters used during the period include (1) high frequency plasma at about 200-2500 Watts (for 300 mm wafers), usually no low frequency plasma, and (2) electricity in the range of about 0.2 to 1.5 seconds. Slurry exposure time.

在一些實施例中，採用相對低溫來沉積鄰接待摻雜之裝置結構的介電薄膜，並且採用較高溫度來沉積更遠離該裝置的介電薄膜部份。在一些實施例中，在全部介電薄膜的沉積期間採用之溫度係變動的，且同樣地，在沉積製程期間氧化劑氣體中氮對氧比率係變動的。以此方式，所產生之介電薄膜的摻雜物擴散特性可在薄膜厚度範圍內變化至一擴大程度。 In some embodiments, a relatively low temperature is used to deposit a dielectric film adjacent to the device structure to be doped, and a higher temperature is used to deposit a portion of the dielectric film further away from the device. In some embodiments, the temperature employed during deposition of all of the dielectric film varies, and as such, the ratio of nitrogen to oxygen in the oxidant gas varies during the deposition process. In this way, the dopant diffusion characteristics of the resulting dielectric film can vary to an extent within the thickness of the film.

在各種實施例中，沉積溫度係由加熱及/或冷卻於CFD期間夾持基板之基座或夾盤加以控制。適當基座之範例係敘述在申請於2009年5月5日之美國專利申請案第12/435890號(公開申請案第US-2009-0277472號)以及申請於2011年4月13日之美國專利申請案第13/086010號之中，其二者皆整體併入於此作為參考。 In various embodiments, the deposition temperature is controlled by a susceptor or chuck that holds the substrate during heating and/or cooling during CFD. An example of a suitable pedestal is described in U.S. Patent Application Serial No. 12/435,890, filed on May 5, 2009, the disclosure of which is hereby incorporated by In the application No. 13/086010, both of which are incorporated herein by reference in their entirety.

在一些實施例中，在介電薄膜或摻雜物前驅物沉積之前對待摻雜之基板表面上的裝置結構做預處理。在一範例中，預處理涉及曝露至電漿，如還原電漿。當例如待摻雜之基板特徵部包含矽時，如此之處理會是適當的。通常矽包含可對後續摻雜物擴散作為阻障之少量的原生氧化物。在一具體實施例中，以例如含氫電漿之還原電漿對基板表面做預處理，並接著在介電薄膜沉積的第一循環之前使該表面與呈氣相之摻雜物前驅物接觸。可在電漿預處理完成之後立即將該前驅物遞送至反應腔室。在一些範例中，摻雜物前驅物係乙硼烷。一般而言，可修改圖17所繪示之程序使得在第一介電層沉積循環之前將摻雜物或摻雜物前驅物遞送至基板表面。 In some embodiments, the device structure on the surface of the substrate to be doped is pretreated prior to deposition of the dielectric film or dopant precursor. In one example, the pretreatment involves exposure to a plasma, such as a reduced plasma. Such processing may be appropriate when, for example, the substrate features to be doped contain germanium. Typically, the ruthenium contains a small amount of native oxide that can diffuse the subsequent dopant as a barrier. In one embodiment, the surface of the substrate is pretreated with a reducing plasma such as a hydrogen-containing plasma, and then the surface is contacted with a dopant precursor in the vapor phase prior to the first cycle of dielectric film deposition. . The precursor can be delivered to the reaction chamber immediately after the plasma pretreatment is completed. In some examples, the dopant precursor is diborane. In general, the procedure illustrated in Figure 17 can be modified to deliver a dopant or dopant precursor to the substrate surface prior to the first dielectric layer deposition cycle.

在各種實施例中，於曝露至摻雜物前驅物前以電漿或其他活化處理對部份形成之介電薄膜本身做預處理。此藉由以下敘述用以提高晶圓內一致性：(a)在摻雜物前驅物曝露之前提供熱一致性、(b)活化介電層表面(例如藉由化學及/或物理粗糙化)以增加黏附至介電層表面之摻雜物前驅物。 In various embodiments, the partially formed dielectric film itself is pretreated by plasma or other activation treatment prior to exposure to the dopant precursor. This is used to improve intra-wafer uniformity by (a) providing thermal uniformity prior to exposure of the dopant precursor, and (b) activating the surface of the dielectric layer (eg, by chemical and/or physical roughening). To increase the dopant precursor adhered to the surface of the dielectric layer.

在一些其他實施例中，於薄膜沉積製程之摻雜物前驅物遞送及/或活化階段期間摻雜物物種的化學條件係受到控制。在一些實施例中，以將摻雜物「固定」在介電薄膜中並從而限制摻雜物擴散直到隨後由回火或其他如 此操作活化為止的方式來處理摻雜物前驅物。在一範例中，於介電薄膜沉積製程之摻雜物遞送階段期間藉由使其或其前驅物氧化而將一些摻雜物固定。在一具體範例中，將乙硼烷遞送至處於氧化環境之反應腔室以使所產生之含硼材料有效地固定在介電薄膜中。或者，藉由將前驅物遞送至處於惰性或還原環境之反應腔室而使摻雜物固定，並且之後在位於介電薄膜上時曝露至氧化環境。相較之下，在沒有後續氧化的情況下，以還原劑處理一些摻雜物前驅物可在介電薄膜中產生更易移動的摻雜物。 In some other embodiments, the chemical conditions of the dopant species are controlled during the dopant precursor delivery and/or activation phase of the thin film deposition process. In some embodiments, the dopant is "fixed" in the dielectric film and thereby limits dopant diffusion until subsequently by tempering or other The dopant precursor is processed in such a way that this operation is activated. In one example, some of the dopants are immobilized by oxidation of the precursor or its precursor during the dopant delivery phase of the dielectric thin film deposition process. In a specific example, diborane is delivered to a reaction chamber in an oxidizing environment to effectively immobilize the resulting boron-containing material in the dielectric film. Alternatively, the dopant is immobilized by delivering the precursor to a reaction chamber in an inert or reducing environment and then exposed to an oxidizing environment while on the dielectric film. In contrast, some dopant precursors treated with a reducing agent can produce more mobile dopants in the dielectric film without subsequent oxidation.

在源層形成之後(或於其形成期間)，將摻雜物物種驅入或用其他方式併入製作中裝置的相鄰結構中。在一些實施例中，於形成保形摻雜物源薄膜期間或之後藉由回火將摻雜物物種驅入。除了習知的熱回火之外，還可使用例如急驟回火及雷射尖峰回火。回火的時間和溫度取決於各種參數，包含：源層中摻雜物的濃度、數量、及種類；源層基材(例如氧化物玻璃)的成分與形態；摻雜物物種必須移動進入鄰接裝置結構中的距離；裝置結構中所期望之摻雜物的濃度；以及裝置結構的成分與形態。一些實施例中，在介於約900及1100℃之間的溫度下執行回火持續約2至30秒。 After formation of the source layer (or during its formation), the dopant species are driven into or otherwise incorporated into adjacent structures of the fabrication device. In some embodiments, the dopant species are driven in by tempering during or after formation of the conformal dopant source film. In addition to the conventional thermal tempering, for example, flash tempering and laser spike tempering can be used. The time and temperature of tempering depends on various parameters, including: the concentration, amount, and type of dopants in the source layer; the composition and morphology of the source layer substrate (eg, oxide glass); the dopant species must move into the abutment The distance in the device structure; the concentration of dopants desired in the device structure; and the composition and morphology of the device structure. In some embodiments, tempering is performed at a temperature between about 900 and 1100 °C for about 2 to 30 seconds.

可設計各種設備來沉積如此處所述之摻雜介電薄膜。一般而言，該設備將包含於摻雜薄膜之沉積期間用以夾持基板之處理腔室。該處理腔室將包含允許處理氣體進入之一或更多進氣口，該處理氣體包含介電質前驅物、氧化劑、載體氣體或惰性氣體、摻雜物物種、及其類似者。在各種實施例中，該設備將額外包含用於產生電漿的特徵，該電漿具有適合於產生介電層；使摻雜物併入介電層中；處理介電層以修改該層之電性、光學、機械、及/或化學特性；以及自薄膜將摻雜物驅入基板中之特性。通常，該設備將包含真空泵或用以連結至此泵之供應。再者，該設備將具有配置或設計成控制該設備以完成此處所述之摻雜介電層沉積操作的順序之一或複數控制器。該控制器可包含用以控制該設備之各種特徵的指令，該特徵包括用以遞送處理氣體及控制壓力的閥、用以產生電漿的電源供應、以及真空源。該指令可控制各種操作的時間及順序。在各種實施例中，該設備可具有如供應自加州聖荷西Novellus Systems之VectorTM系列沉積工具中所提供之特徵。用於沉積摻雜介電薄膜之合適設備的其他特徵將於本文中其他 地方加以敘述。 Various devices can be designed to deposit a doped dielectric film as described herein. In general, the apparatus will include a processing chamber for holding the substrate during deposition of the doped film. The processing chamber will contain one or more inlets that allow processing gas to enter, the processing gas comprising a dielectric precursor, an oxidant, a carrier gas or inert gas, a dopant species, and the like. In various embodiments, the apparatus will additionally include features for generating a plasma having a dielectric layer suitable for incorporation into the dielectric layer; processing the dielectric layer to modify the layer Electrical, optical, mechanical, and/or chemical properties; and properties that drive dopants into the substrate from the film. Typically, the device will contain a vacuum pump or a supply to connect to the pump. Again, the device will have one or a plurality of controllers configured or designed to control the device to perform the doped dielectric layer deposition operations described herein. The controller can include instructions to control various features of the device, including a valve to deliver process gas and control pressure, a power supply to generate plasma, and a vacuum source. This command controls the timing and sequence of various operations. In various embodiments, the apparatus may have a feature, such as available from Novellus Systems of San Jose, California Vector TM series provided by deposition tool. Other features of suitable equipment for depositing a doped dielectric film are described elsewhere herein.

摻雜CFD薄膜特性 Doped CFD film properties

作為摻雜物物種源之介電薄膜將具有各種特徵。在各種實施例中，薄膜厚度介於約20及200埃之間。在一些情況下，如用於三維電晶體結構之源極-汲極延伸區域的前端摻雜，則薄膜厚度介於約50及100埃之間。介電薄膜中摻雜物原子(或其他摻雜物物種)的平均濃度取決於各種因素，包括薄膜之每單位表面積摻雜物的總數量、及薄膜中摻雜物原子的擴散性、以及摻雜應用。在一些實施例中，薄膜中摻雜物的濃度介於約0.01及10重量百分率之間。在另外的實施例中，薄膜中摻雜物的濃度介於約0.1至1重量百分率之間。在更另外的實施例中，薄膜中摻雜物的濃度介於約0.5至4重量百分率之間。於此所述之技術允許在寬廣的範圍(例如介於約0.01及10重量百分率之間)中調整摻雜物濃度。例如，已教示在CFD介電薄膜中可將硼濃度輕易地調整在介於約0.1及4.3重量百分率之間。在一些實施例中，在硼介於約0.1及0.5 wt%的情況下生長5、7、10、以及12 nm CFD薄膜。 Dielectric films that are sources of dopant species will have a variety of features. In various embodiments, the film thickness is between about 20 and 200 angstroms. In some cases, such as for the front end doping of the source-drain extension region of a three-dimensional transistor structure, the film thickness is between about 50 and 100 angstroms. The average concentration of dopant atoms (or other dopant species) in the dielectric film depends on various factors, including the total amount of dopant per unit surface area of the film, and the diffusivity of the dopant atoms in the film, and the doping. Miscellaneous applications. In some embodiments, the concentration of dopant in the film is between about 0.01 and 10 weight percent. In other embodiments, the concentration of dopant in the film is between about 0.1 and 1 weight percent. In still other embodiments, the concentration of dopant in the film is between about 0.5 and 4 weight percent. The techniques described herein allow adjustment of the dopant concentration over a wide range, such as between about 0.01 and 10 weight percent. For example, it has been taught that the boron concentration can be readily adjusted between about 0.1 and 4.3 weight percent in a CFD dielectric film. In some embodiments, the 5, 7, 10, and 12 nm CFD films are grown with boron between about 0.1 and 0.5 wt%.

可以其他特性作為CFD摻雜介電薄膜之特徵。例如，CFD沉積薄膜的片電阻(Rs)可從約100變化至50000 ohms/方形。在一些情況下，在部份或全部摻雜物已從摻雜CFD層驅入後而獲得這些值。另外藉由從CFD薄膜驅入摻雜物所產生之接面深度(例如藉由SIMS量測)可適當調整至高達約1000埃的程度。當然，許多前端裝置而是需要較淺的接面深度(例如約5-50埃的範圍中)，其亦可使用CFD薄膜而獲得。可藉由許多因素來控制實際接面深度，例如界面摻雜物(例如硼)濃度、摻雜物從主體及界面進入基板(例如矽)的遷移率、以及用以驅入摻雜物之回火的溫度與持續時間。 Other characteristics may be featured as a CFD doped dielectric film. For example, the sheet resistance (Rs) of a CFD deposited film can vary from about 100 to 50,000 ohms per square. In some cases, these values are obtained after some or all of the dopant has been driven from the doped CFD layer. In addition, the junction depth produced by driving the dopant from the CFD film (e.g., by SIMS measurement) can be suitably adjusted to an extent of up to about 1000 angstroms. Of course, many front end devices require a shallow junction depth (e.g., in the range of about 5-50 angstroms), which can also be obtained using a CFD film. The actual junction depth can be controlled by a number of factors, such as the concentration of the interface dopant (e.g., boron), the mobility of the dopant from the body and interface into the substrate (e.g., germanium), and the drive back to the dopant. The temperature and duration of the fire.

CFD摻雜應用 CFD doping application

其上形成介電源層之基板表面可能需要高保形沉積。在一些範例中，介電源薄膜一致地覆蓋具有介於約1：0.5及1：12之間(更具體地介於約1：1及1：8之間)的高寬比之特徵部，並且具有不大於約60 nm(更具體地不大於約30 nm)的特徵部寬度。使用本文中所述介電源層類型之摻雜將在根據45 nm技術節點及更往後技術(包括22 nm技術節點、16 nm技術節點等等)所形成的裝置中找到特定應用。 The surface of the substrate on which the dielectric layer is formed may require high conformal deposition. In some examples, the dielectric film consistently covers features having an aspect ratio between about 1:0.5 and 1:12 (more specifically between about 1:1 and 1:8), and There is a feature width of no more than about 60 nm, and more specifically no more than about 30 nm. The use of the dielectric layer type doping described herein will find a particular application in devices formed from 45 nm technology nodes and later techniques (including 22 nm technology nodes, 16 nm technology nodes, etc.).

在可使用CFD源層摻雜的裝置結構之中為例如CMOS源極與汲極、源極-汲極延伸區域、記憶體裝置中的電容電極、閘極結構等等之習知摻雜結構。其他可以此方式摻雜之結構為例如在閘極結構中於源極/汲極延伸區域處之接面(如同那些以22奈米技術節點製作的一些裝置中所採用的一些三維閘極結構中之接面)的非平面或三維結構。一些三維結構可見於先前併入作為參考之J.Kavalieros等人於Symp.VLSI Tech Pg 50,2006所提出之「Tri-gate(Intel)」、以及Yamashita等人(IBM Alliance)於VLSI 2011所提出之「FinFET」、以及其中參考文獻。 Among the device structures that can be doped using a CFD source layer are conventional doped structures such as CMOS source and drain, source-drain extension regions, capacitive electrodes in memory devices, gate structures, and the like. Other structures that can be doped in this manner are, for example, junctions at the source/drain extension regions in the gate structure (as in some of the three-dimensional gate structures employed in some devices fabricated with 22 nm technology nodes). The non-planar or three-dimensional structure of the junction. Some of the three-dimensional structures can be found in "Tri-gate (Intel)" proposed by J. Kavalieros et al. in Symp. VLSI Tech Pg 50, 2006, and Yamashita et al. (IBM Alliance) in VLSI 2011. "FinFET", and references therein.

摻雜CFD薄膜具有各種其他應用，例如提供使用在積體電路製作中各個階段之可蝕刻層。在一些實施例中，可蝕刻層為具有可調式濕蝕刻速率之玻璃層，其中該蝕刻速率可由摻雜的程度加以調整。換言之，選取摻雜的程度以提供預定之蝕刻速率。在具體實施例中，可蝕刻層為包含如磷、硼、或其組合之摻雜物的矽酸鹽玻璃層。 Doped CFD films have a variety of other applications, such as providing etchable layers for use at various stages in the fabrication of integrated circuits. In some embodiments, the etchable layer is a glass layer having a tunable wet etch rate, wherein the etch rate can be adjusted by the degree of doping. In other words, the degree of doping is chosen to provide a predetermined etch rate. In a particular embodiment, the etchable layer is a tellurite glass layer comprising a dopant such as phosphorus, boron, or a combination thereof.

CFD摻雜範例 CFD doping example

CFD硼摻雜矽酸鹽玻璃(BSG)薄膜準備好並且在複雜的三維閘極結構上達到幾乎100%階梯覆蓋。預期磷摻雜矽酸鹽玻璃(PSG)有類似結果。在摻雜物之擴散下提供保形/同質的後續回火步驟期間可將硼或磷從如此薄膜驅入源極和汲極接面之橫向及垂直區域中。圖20顯示用以合成CFD BSG/PSG薄膜之典型沉積組塊。CFD氧化物生長循環包含(a)SiO2前驅物(BTBAS)的飽和劑量、(b)惰性清除以沖出殘餘前驅物物種、(c)氧化電漿步驟、以及(d)惰性氣體清除以移除反應副產物。此機制確保反應為自我限制並且促進在這些薄膜觀察到優越的保形性。若必要時，於CFD氧化物生長期間週期性***硼或磷曝露步驟，後接泵抽和清除序列，以及選擇性RF釘扎/硬化步驟(例如曝露至電漿)。此沉積組塊依目標BSG/PSG厚度需要重複多次。見圖20。 CFD boron-doped tellurite glass (BSG) films are prepared and achieve almost 100% step coverage on complex three-dimensional gate structures. Phosphorus doped tellurite glass (PSG) is expected to have similar results. Boron or phosphorus may be driven from such a film into the lateral and vertical regions of the source and drain junctions during the conformal/homogeneous subsequent tempering step provided by diffusion of the dopant. Figure 20 shows a typical deposition block used to synthesize a CFD BSG/PSG film. The CFD oxide growth cycle comprises (a) a saturated dose of SiO 2 precursor (BTBAS), (b) inert purge to flush out residual precursor species, (c) an oxidative plasma step, and (d) inert gas purge to shift In addition to reaction by-products. This mechanism ensures that the reaction is self-limiting and promotes superior conformality observed in these films. If necessary, periodically insert a boron or phosphorus exposure step during CFD oxide growth followed by a pumping and scavenging sequence, and a selective RF pinning/hardening step (eg, exposure to plasma). This deposition block needs to be repeated multiple times depending on the target BSG/PSG thickness. See Figure 20.

***硼或磷曝露的頻率調整在一特定溫度下摻雜物擴散距離，而曝露的期間長度控制總摻雜物劑量。這兩個強力的控制參數提供用以精準調整界面摻雜物濃度之多方面合成方案。 The frequency of insertion of boron or phosphorous exposure adjusts the dopant diffusion distance at a particular temperature, while the length of the exposure period controls the total dopant dose. These two powerful control parameters provide a multi-faceted synthetic solution to precisely adjust the interface dopant concentration.

在實驗中，CFD已證明在BSG薄膜中優越的生長特徵。該CFD BSG製程使用BTBAS作為矽源、N2O電漿用於氧化、以及氬之中5%乙硼烷(B2H6) 用於硼摻雜。氬和N2O的混合物用作清除氣體。獲得與未摻雜CFD氧化物上結果一致之~1埃/循環的生長速率，因而顯示包含硼曝露步驟不會對CFD生長造成不利影響。如藉由SEM照片所示般，250埃厚之CFD BSG薄膜在不同測試結構上展現近乎完美的保形性。這些薄膜的階梯覆蓋在密集和分離的結構(圖21)上估計為~100%。階梯覆蓋定義為特徵部之側壁上的薄膜厚度除以該相同特徵部之頂部上的薄膜厚度之商數。表6顯示來自初步研究的不同分歧，用以區分出硼曝露時間、硼***頻率、及生長溫度對薄膜中最後平均硼濃度的影響。25X CFD Ox表示每一硼***階段有25個CFD未摻雜氧化物循環。此樣本大約生長至500埃，因此整個序列重複約20次(假設CFD氧化物的生長速率為1埃/循環)。這些分歧的SIMS資料(如圖22所示)顯示平均硼濃度可調整在約0.5-3.5 wt%硼的範圍中，而使訂製摻雜選擇成為可能。 In experiments, CFD has demonstrated superior growth characteristics in BSG films. The CFD BSG process uses BTBAS as a helium source, N 2 O plasma for oxidation, and 5% diborane (B 2 H 6 ) in argon for boron doping. A mixture of argon and N 2 O is used as a purge gas. A growth rate of ~1 angstrom/cycle consistent with the results on the undoped CFD oxide was obtained, thus showing that the inclusion of the boron exposure step does not adversely affect CFD growth. As shown by the SEM photograph, the 250 angstrom thick CFD BSG film exhibited near perfect shape retention on different test structures. The step coverage of these films was estimated to be ~100% on dense and separate structures (Figure 21). The step coverage is defined as the lamella of the film thickness on the sidewalls of the feature divided by the film thickness on top of the same feature. Table 6 shows the different divergence from the preliminary study to distinguish the effect of boron exposure time, boron insertion frequency, and growth temperature on the final average boron concentration in the film. 25X CFD Ox means that there are 25 CFD undoped oxide cycles per boron insertion stage. This sample grew to approximately 500 angstroms, so the entire sequence was repeated approximately 20 times (assuming a CFD oxide growth rate of 1 angstrom/cycle). These divergent SIMS data (shown in Figure 22) show that the average boron concentration can be adjusted in the range of about 0.5-3.5 wt% boron, making custom doping options possible.

設備 device

應瞭解到在以上所述之一或更多實施例的情況下可採用任何合適的處理站。例如，圖13示意地顯示CFD處理站1300之實施例。為簡單起見，CFD處理站1300繪示為具有用以維持低壓環境之處理腔室本體1302之獨立處理站。然而，應瞭解到在共同的低壓處理工具環境中可包含複數CFD處理站1300。雖然圖13所示之實施例顯示一處理站，但應瞭解到在一些實施例中複數處理站可包含在一處理工具中。例如，圖14繪示一多站處理工具2400之實施例。此外，應瞭解到在一些實施例中可藉由一或更多電腦控制器程式性地調整CFD處理站1300之一或更多硬體參數，包含以下詳述之參數。 It will be appreciated that any suitable processing station may be employed in the case of one or more of the embodiments described above. For example, Figure 13 schematically shows an embodiment of a CFD processing station 1300. For simplicity, CFD processing station 1300 is depicted as an independent processing station having a processing chamber body 1302 for maintaining a low pressure environment. However, it should be appreciated that a plurality of CFD processing stations 1300 can be included in a common low pressure processing tool environment. Although the embodiment shown in Figure 13 shows a processing station, it should be appreciated that in some embodiments a plurality of processing stations may be included in a processing tool. For example, FIG. 14 illustrates an embodiment of a multi-station processing tool 2400. In addition, it should be appreciated that in some embodiments one or more hardware parameters of the CFD processing station 1300 can be programmatically adjusted by one or more computer controllers, including the parameters detailed below.

CFD處理站1300與用於遞送處理氣體至分佈噴淋頭1306之反應物遞送系統1301流體連通。反應物遞送系統1301包含用以混和及/或調節遞送至噴淋頭1306之處理氣體的混合容器1304。一或更多混合容器進氣閥1320可控制處理氣體至混合容器1304之導入。 The CFD processing station 1300 is in fluid communication with a reactant delivery system 1301 for delivering process gases to the distributed showerhead 1306. The reactant delivery system 1301 includes a mixing vessel 1304 to mix and/or condition the process gas delivered to the showerhead 1306. One or more mixing vessel intake valves 1320 can control the introduction of process gases to the mixing vessel 1304.

如BTBAS的一些反應物可在於處理站汽化並隨後遞送至處理站之前以液體形式儲存。例如，圖13之實施例包含用於汽化欲供應至混合容器1304之液態反應物的汽化點1303。在一些實施例中，汽化點1303可為加熱之汽化器。從如此汽化器產生的飽和反應物蒸汽可在下游遞送管道中凝結。使不相容氣體曝露至凝結的反應物可產生小顆粒。這些小顆粒可阻塞管道、妨礙閥操作、污染基板等等。應對這些問題的一些方法涉及清除及/或排空遞送管道以移除殘留反應物。然而，清除遞送管道可增加處理站循環時間，從而降低處理站吞吐量。因此，在一些實施例中可對汽化點1303下游之遞送管道進行熱追蹤。在一些範例中，亦可對混合容器1304進行熱追蹤。在一非限制性範例中，汽化點1303下游之管道具有在混合容器1304處從大約攝氏100度延伸至大約攝氏150度之遞增溫度曲線。 Some of the reactants, such as BTBAS, may be stored in liquid form prior to vaporization by the processing station and subsequent delivery to the processing station. For example, the embodiment of FIG. 13 includes a vaporization point 1303 for vaporizing a liquid reactant to be supplied to the mixing vessel 1304. In some embodiments, the vaporization point 1303 can be a heated vaporizer. The saturated reactant vapor produced from such a vaporizer can condense in the downstream delivery conduit. Exposure of the incompatible gas to the condensed reactants produces small particles. These small particles can block the pipe, hinder valve operation, contaminate the substrate, and the like. Some methods to address these issues involve removing and/or emptying the delivery tubing to remove residual reactants. However, clearing the delivery pipeline can increase processing station cycle time, thereby reducing processing station throughput. Thus, in some embodiments, the delivery conduit downstream of vaporization point 1303 can be thermally tracked. In some examples, the hybrid container 1304 can also be thermally tracked. In a non-limiting example, the conduit downstream of vaporization point 1303 has an incremental temperature profile that extends from about 100 degrees Celsius to about 150 degrees Celsius at mixing vessel 1304.

在一些實施例中，可在液體注入器使反應物液體汽化。例如，液體注入器可將液體反應物之脈衝注入在混合容器上游之載體氣體流中。在一個情形中，液體注入器可藉由將該液體從較高壓力急驟汽化至較低壓力來使反應物汽化。在另一情形中，液體注入器可使該液體霧化成隨後在加熱遞送管道中汽化之分散微滴。應瞭解到較小液滴可比較大液滴更快汽化，從而減小液體注入和完全汽化之間的延遲。更快的汽化可減短自汽化點1303下游管道的長度。在一個情形中，液體注入器可直接安裝至混合容器1304。在另一情形中，液體注入器可直接安裝至噴淋頭1306。 In some embodiments, the reactant liquid can be vaporized at the liquid injector. For example, a liquid injector can inject a pulse of liquid reactant into a carrier gas stream upstream of the mixing vessel. In one case, the liquid injector can vaporize the reactants by rapidly vaporizing the liquid from a higher pressure to a lower pressure. In another aspect, the liquid injector can atomize the liquid into discrete droplets that are subsequently vaporized in a heated delivery conduit. It will be appreciated that smaller droplets can vaporize faster than larger droplets, thereby reducing the delay between liquid injection and complete vaporization. Faster vaporization can reduce the length of the conduit downstream of the vaporization point 1303. In one case, the liquid injector can be mounted directly to the mixing vessel 1304. In another scenario, the liquid injector can be mounted directly to the showerhead 1306.

將噴淋頭1306及基座1308與RF電力供應1314及匹配網路1316電性連通以對電漿供電。在一些實施例中，可藉由控制處理站壓力、氣體濃度、RF源功率、RF源頻率、以及電漿功率脈衝計時之一者或多者來控制電漿能量。例如，RF電力供應1314及匹配網路1316可在任何合適功率下操作以形成具有期望之自由基物種成分的電漿。合適功率之範例包含(但不限於)對於300 mm晶圓介於100 W及5000 W之間的功率。同樣地，RF電力供應 1314可提供任何合適頻率的RF功率。在一些實施例中，RF電力供應1314可配置成高頻與低頻RF電源彼此獨立控制。範例性低頻RF頻率可包含(但不限於)介於50 kHz及500 kHz之間的頻率。範例性高頻RF頻率可包含(但不限於)介於1.8 MHz及2.45 GHz之間的頻率。應瞭解到可離散地或連續地調變任何合適的參數以提供用於表面反應之電漿能量。在一非限制性範例中，可使電漿功率間歇地產生脈衝以減輕相對於連續供電電漿對基板表面之離子轟擊。 The showerhead 1306 and the susceptor 1308 are in electrical communication with the RF power supply 1314 and the matching network 1316 to power the plasma. In some embodiments, the plasma energy can be controlled by controlling one or more of station pressure, gas concentration, RF source power, RF source frequency, and plasma power pulse timing. For example, RF power supply 1314 and matching network 1316 can operate at any suitable power to form a plasma having a desired radical species composition. Examples of suitable power include, but are not limited to, power between 100 W and 5000 W for a 300 mm wafer. Similarly, RF power supply The 1314 can provide RF power at any suitable frequency. In some embodiments, the RF power supply 1314 can be configured to control the high frequency and low frequency RF power sources independently of each other. Exemplary low frequency RF frequencies may include, but are not limited to, frequencies between 50 kHz and 500 kHz. Exemplary high frequency RF frequencies may include, but are not limited to, frequencies between 1.8 MHz and 2.45 GHz. It will be appreciated that any suitable parameter can be modulated discretely or continuously to provide plasma energy for surface reactions. In a non-limiting example, the plasma power can be pulsed intermittently to mitigate ion bombardment of the substrate surface relative to the continuous power supply plasma.

在一些實施例中，可藉由一或更多電漿監測器來原位監測電漿。在一情形中，可藉由一或更多電壓、電流感測器(例如VI探針)來監測電漿功率。在另一情形中，可藉由一或更多光學放射光譜感測器(OES)來量測電漿密度及/或處理氣體濃度。在一些實施例中，可基於從如此原位電漿監測器之量測來程式化地調整一或更多電漿參數。例如，可在回饋迴路中使用OES感測器以提供電漿功率之程式化控制。應瞭解到在一些實施例中，可使用其他監測器來監測電漿及其他製程特性。如此之監測器可包含(但不限於)遠紅外線(IR)監測器、聲學監測器、以及壓力轉換器。 In some embodiments, the plasma can be monitored in situ by one or more plasma monitors. In one case, the plasma power can be monitored by one or more voltage, current sensors (eg, VI probes). In another aspect, the plasma density and/or process gas concentration can be measured by one or more optical emission spectrum sensors (OES). In some embodiments, one or more plasma parameters can be programmatically adjusted based on measurements from such in-situ plasma monitors. For example, an OES sensor can be used in the feedback loop to provide stylized control of the plasma power. It should be appreciated that in some embodiments, other monitors can be used to monitor plasma and other process characteristics. Such monitors may include, but are not limited to, far infrared (IR) monitors, acoustic monitors, and pressure transducers.

在一些實施例中，可經由加熱器1310對基座1308進行溫度控制。此外，在一些實施例中，可藉由蝶形閥1318提供對CFD處理站1300之壓力控制。如圖13之實施例所示，蝶形閥1318調節由下游真空泵(未顯示)所提供之真空。然而，在一些實施例中，亦可藉由改變一或更多導入至CFD處理站1300之氣體的流速來調整處理站1300之壓力控制。 In some embodiments, the base 1308 can be temperature controlled via a heater 1310. Moreover, in some embodiments, pressure control of the CFD processing station 1300 can be provided by a butterfly valve 1318. As shown in the embodiment of Figure 13, butterfly valve 1318 regulates the vacuum provided by a downstream vacuum pump (not shown). However, in some embodiments, the pressure control of the processing station 1300 can also be adjusted by changing the flow rate of one or more gases introduced to the CFD processing station 1300.

如以上所述，一多站處理工具中可包含一或更多處理站。圖14顯示具有入站裝載鎖2402及出站裝載鎖2404(其任一者或二者可包含遠端電漿源)之多站處理工具2400之實施例的示意圖。一處於大氣壓力下之機械臂2406係配置以將來自經由箱體2408載入之卡匣的晶圓經由大氣口2410移動至入站裝載鎖2402中。藉由機械臂2406將晶圓置放在入站裝載鎖2402中的基座2412上、關閉大氣口2410、並且將裝載鎖抽空。在導入處理腔室2414之前可使晶圓曝露至裝載鎖中的遠端電漿處理，其中入站裝載鎖2402包含遠端電漿源。此外，亦可在入站裝載鎖2402中對晶圓加熱，同樣地例如移除水分及吸附氣體。接著，開啟通至處理腔室2414之腔室運送口2416，並 且另一機械臂(未顯示)將晶圓置放入反應器中之該反應器所示第一站的基座上以供處理。雖然圖14所示之實施例包含裝載鎖，但應瞭解到在一些實施例中可提供晶圓至處理站之直接進入。 As mentioned above, one or more processing stations may be included in a multi-station processing tool. 14 shows a schematic diagram of an embodiment of a multi-station processing tool 2400 having an inbound load lock 2402 and an outbound load lock 2404, either or both of which may include a remote plasma source. A robotic arm 2406 at atmospheric pressure is configured to move wafers from the cassette loaded via the housing 2408 into the inbound load lock 2402 via the air port 2410. The wafer is placed on the pedestal 2412 in the inbound load lock 2402 by the robot arm 2406, the atmosphere port 2410 is closed, and the load lock is evacuated. The wafer may be exposed to a remote plasma treatment in a load lock prior to introduction into the processing chamber 2414, wherein the inbound load lock 2402 includes a remote plasma source. In addition, the wafer may be heated in the inbound load lock 2402, such as to remove moisture and adsorb gas. Next, the chamber transfer port 2416 leading to the processing chamber 2414 is opened, and And another robotic arm (not shown) places the wafer on the susceptor of the first station shown in the reactor in the reactor for processing. Although the embodiment illustrated in Figure 14 includes a load lock, it will be appreciated that direct access of the wafer to the processing station may be provided in some embodiments.

所繪示之處理腔室2414包含四個處理站，在圖14所示之實施例中編號從1到4。每一站具有加熱基座(顯示在站1之2418處)、以及氣體管線入口。應瞭解到在一些實施例中，每一處理站可具有不同或多個目的。例如，在一些實施例中，處理站可於CFD及PECVD製程模式之間切換。此外或選擇性地，在一些實施例中，處理腔室2414可包含一或更多CFD及PECVD處理站之匹配對。雖然繪示之處理腔室2414包含四個站，但應瞭解到根據本發明之處理腔室可具有任何合適數目的站。例如，在一些實施例中處理腔室可具有五或更多站，而在其他實施例中處理腔室可具有三或更少站。 The illustrated processing chamber 2414 includes four processing stations, numbered from 1 to 4 in the embodiment shown in FIG. Each station has a heated pedestal (shown at 2418 of station 1) and a gas line inlet. It should be appreciated that in some embodiments, each processing station may have different or multiple purposes. For example, in some embodiments, the processing station can switch between CFD and PECVD process modes. Additionally or alternatively, in some embodiments, processing chamber 2414 can include a matching pair of one or more CFD and PECVD processing stations. Although the illustrated processing chamber 2414 includes four stations, it should be understood that the processing chamber in accordance with the present invention can have any suitable number of stations. For example, in some embodiments the processing chamber may have five or more stations, while in other embodiments the processing chamber may have three or fewer stations.

圖14亦繪示用於在處理腔室2414內運送晶圓之晶圓搬運系統2490的實施例。在一些實施例中，晶圓搬運系統2490可在各個處理站之間及/或處理站與裝載鎖之間運送晶圓。應瞭解到可採用任何合適的晶圓搬運系統。非限制性的範例包含晶圓傳送帶及晶圓搬運機械臂。圖14亦繪示用以控制處理工具2400之製程條件及硬體狀態之系統控制器2450的實施例。系統控制器2450可包含一或更多記憶體裝置2456、一或更多大量儲存裝置2454、以及一或更多處理器2452。處理器2452可包含CPU或電腦、類比及/或數位輸入/輸出連接、步進馬達控制器板等等。 FIG. 14 also illustrates an embodiment of a wafer handling system 2490 for transporting wafers within processing chamber 2414. In some embodiments, the wafer handling system 2490 can transport wafers between various processing stations and/or between processing stations and load locks. It should be understood that any suitable wafer handling system can be employed. Non-limiting examples include wafer conveyor belts and wafer handling robot arms. FIG. 14 also illustrates an embodiment of a system controller 2450 for controlling process conditions and hardware states of the processing tool 2400. System controller 2450 can include one or more memory devices 2456, one or more mass storage devices 2454, and one or more processors 2452. The processor 2452 can include a CPU or computer, analog and/or digital input/output connections, a stepper motor controller board, and the like.

在一些實施例中，系統控制器2450控制處理工具2400的所有活動。系統控制器2450執行儲存在大量儲存裝置2454中、載入至記憶體裝置2456、並於處理器2452上執行之系統控制軟體2458。系統控制軟體2458可包含用以控制由處理工具2400執行之特定製程的計時、氣體混合、腔室及/或站壓力、腔室及/或站溫度、晶圓溫度、目標功率位準、RF功率位準、基板基座、夾盤及/或晶座位置、以及其他參數之指令。系統控制軟體2458可以任何合適的方式來配置。例如，可寫入各種處理工具元件子程式或控制目標程式以控制實行各種處理工具製程必要之處理工具元件的操作。系統控制軟體2458可用任何合適的電腦可讀程式化語言予以編碼。 In some embodiments, system controller 2450 controls all activities of processing tool 2400. System controller 2450 executes system control software 2458 stored in mass storage device 2454, loaded into memory device 2456, and executed on processor 2452. The system control software 2458 can include timing, gas mixing, chamber and/or station pressure, chamber and/or station temperature, wafer temperature, target power level, RF power to control the particular process performed by the processing tool 2400. Commands for level, substrate pedestal, chuck and/or pedestal position, and other parameters. System control software 2458 can be configured in any suitable manner. For example, various processing tool component subroutines or control target programs can be written to control the operation of the processing tool components necessary to perform various processing tool processes. System Control Software 2458 can be encoded in any suitable computer readable stylized language.

在一些實施例中，系統控制軟體2458可包含用以控制以上所述之各種 參數的輸入/輸出控制(IOC)定序指令。例如，CFD製程的每一階段可包含供系統控制器2450執行之一或更多指令。用以設定CFD製程階段之製程條件的指令可包含在對應的CFD配方階段中。在一些實施例中，可依序安排CFD製程階段使得關於CFD製程的所有指令皆與該製程階段同時執行。 In some embodiments, system control software 2458 can include various controls for controlling the above Parameter input/output control (IOC) sequencing instructions. For example, each stage of the CFD process can include one or more instructions for system controller 2450 to execute. Instructions for setting the process conditions of the CFD process stage may be included in the corresponding CFD recipe stage. In some embodiments, the CFD process stage can be arranged in sequence such that all instructions regarding the CFD process are executed concurrently with the process stage.

在一些實施例中，可採用儲存在與系統控制器2450相關聯之大量儲存裝置2454及/或記憶體裝置2456上的其他電腦軟體及/或程式。用於此目的之程式或程式片段的範例包含基板定位程式、處理氣體控制程式、壓力控制程式、加熱器控制程式、以及電漿控制程式。 In some embodiments, other computer software and/or programs stored on a plurality of storage devices 2454 and/or memory devices 2456 associated with system controller 2450 may be employed. Examples of programs or program segments for this purpose include a substrate positioning program, a process gas control program, a pressure control program, a heater control program, and a plasma control program.

基板定位程式可包含用於裝載基板至基座2418上以及控制基板與處理工具2400其他部份之間的間隔之處理工具元件的程式碼。 The substrate positioning program can include code for processing tool elements for loading the substrate onto the pedestal 2418 and controlling the spacing between the substrate and other portions of the processing tool 2400.

處理氣體控制程式可包含用於控制氣體成分和流速、以及選擇性地用於在沉積之前使氣體流入一或更多處理站以使處理站中的壓力穩定之碼。壓力控制程式可包含藉由調節例如處理站之排氣系統中的節流閥、進入處理站之氣體流量等等以控制處理站中之壓力的編碼。 The process gas control program can include code for controlling the gas composition and flow rate, and selectively for allowing gas to flow into one or more processing stations prior to deposition to stabilize the pressure in the processing station. The pressure control program can include a code that controls the pressure in the processing station by adjusting, for example, a throttle valve in the exhaust system of the processing station, a gas flow into the processing station, and the like.

加熱器控制程式可包含用於控制通到用以加熱基板之加熱單元之電流的編碼。或者，加熱器控制程式可控制熱傳送氣體(如氦)至基板之遞送。 The heater control program can include a code for controlling the current to the heating unit used to heat the substrate. Alternatively, the heater control program can control the delivery of hot transfer gases, such as helium, to the substrate.

電漿控制程式可包含用於設定施加至一或更多處理站中之處理電極之RF功率位準的編碼。 The plasma control program can include a code for setting the RF power level applied to the processing electrodes in one or more processing stations.

在一些實施例中，可存在與系統控制器2450相關聯之使用者介面。使用者介面可包含顯示螢幕、設備及/或製程條件之圖形軟體顯示器、以及如指標裝置、鍵盤、觸控螢幕、麥克風等等之使用者輸入裝置。 In some embodiments, there may be a user interface associated with system controller 2450. The user interface can include a graphical software display that displays screens, devices, and/or process conditions, as well as user input devices such as indicator devices, keyboards, touch screens, microphones, and the like.

在一些實施例中，由系統控制器2450調整之參數可與製程條件有關。非限制性範例包含處理氣體成分及流速、溫度、壓力、電漿條件(如RF偏壓功率位準)、壓力、溫度等等。這些參數可以其可利用使用者介面輸入之配方的形式提供給使用者。 In some embodiments, the parameters adjusted by system controller 2450 can be related to process conditions. Non-limiting examples include process gas composition and flow rate, temperature, pressure, plasma conditions (eg, RF bias power level), pressure, temperature, and the like. These parameters can be provided to the user in the form of a recipe that can be entered using a user interface.

用來監測製程之信號可從各個處理工具感測器藉由系統控制器2450之類比及/或數位輸入連接來提供。用來控制製程之信號可輸出到處理工具2400之類比及數位輸出連接上。可受監測之處理工具感測器的非限制性範例包含質量流量控制器、壓力感測器(如壓力計)、熱電偶等等。適當程式化 回饋及控制演算法可與來自這些感測器的資料一起使用以維持製程條件。 Signals for monitoring the process may be provided from various processing tool sensors by analogy and/or digital input connections of system controller 2450. The signals used to control the process can be output to the analog and digital output connections of the processing tool 2400. Non-limiting examples of process tool sensors that can be monitored include mass flow controllers, pressure sensors (such as pressure gauges), thermocouples, and the like. Appropriate stylization Feedback and control algorithms can be used with data from these sensors to maintain process conditions.

系統控制器2450可提供用以實施以上所述之沉積製程的程式指令。程式指令可控制如DC功率位準、RF偏壓功率位準、壓力、溫度等等之各種製程參數。該指令可控制該參數以操作根據本文中所述之各種實施例之薄膜堆疊的原位沉積。 System controller 2450 can provide program instructions for implementing the deposition process described above. Program instructions control various process parameters such as DC power level, RF bias power level, pressure, temperature, and the like. The instructions can control the parameter to operate in situ deposition of a thin film stack in accordance with various embodiments described herein.

於上文中敘述之設備/製程可與例如用於製作或製造半導體裝置、顯示器、LED、光伏板、及其類似者之微影圖案化工具或製程結合使用。通常(儘管非必然)如此之工具/製程將在共同的製作設施中一起使用或實施。薄膜之微影圖案化通常包含以下操作(用一些合適的工具來實現每一操作)的部份或全部：(1)使用旋塗或噴塗工具在工作件(即基板)上塗佈光阻；(2)使用熱板或加熱爐或UV硬化工具使光阻硬化；(3)用例如晶圓步進機之工具使光阻曝露至可見或UV或x射線光；(4)使用如濕式工作檯之工具使光阻顯影以選擇性地移除光阻並從而將其圖案化；(5)藉由使用乾式或電漿輔助蝕刻工具將光阻圖案轉移至下方的薄膜或工作件中；以及(6)使用如RF或微波電漿光阻剝除器之工具來移除光阻。 The apparatus/processes described above can be used in conjunction with, for example, lithographic patterning tools or processes for fabricating or fabricating semiconductor devices, displays, LEDs, photovoltaic panels, and the like. Usually (although not necessarily) such tools/processes will be used or implemented together in a common fabrication facility. The lithographic patterning of a film typically involves some or all of the following operations (using some suitable tool to achieve each operation): (1) applying a photoresist to the workpiece (ie, the substrate) using a spin coating or spray tool; (2) hardening the photoresist using a hot plate or furnace or UV hardening tool; (3) exposing the photoresist to visible or UV or x-ray light using a tool such as a wafer stepper; (4) using a wet type The tool of the table develops the photoresist to selectively remove the photoresist and thereby pattern it; (5) transferring the photoresist pattern to the underlying film or workpiece by using a dry or plasma assisted etching tool; And (6) using a tool such as an RF or microwave plasma photoresist stripper to remove the photoresist.

應瞭解到於本文中敘述之配置及/或方法實質上為示範性的，而且這些具體實施例或範例不應視為限制性意義，因為許多變化均有可能。於本文中敘述之具體例行程序或方法可表示一或更多之任何數目的處理對策。因此，圖例說明之各種動作可按所示之順序、其他順序、並行、或一些省略的情況來執行。同樣地，可改變以上所述製程之順序。 It should be understood that the configurations and/or methods described herein are exemplary in nature and that such specific embodiments or examples are not to be considered as limiting, as many variations are possible. The specific routines or methods described herein may represent any number of processing strategies, one or more. Accordingly, the various acts illustrated in the figures may be performed in the sequence shown, in other sequences, in parallel, or in some omissions. Likewise, the order of the processes described above can be changed.

本發明之標的包含各種製程、系統與配置、以及於此揭露之其他特徵、功能、動作、及/或特性、以及與其相關之任何及所有均等者之所有新穎及非顯而易見之組合及次組合。 The subject matter of the present invention includes all novel and non-obvious combinations and sub-combinations of the various processes, systems and configurations, and other features, functions, and/or characteristics of the disclosure, and any and all equivalents thereof.

Claims (53)

一種在反應腔室中於基板表面上沉積薄膜之方法，該方法包含：(a)在允許第一反應物吸附至該基板表面上的條件下，將該第一反應物導入該反應腔室中；(b)在該第一反應物吸附在該基板表面上時，將第二反應物導入該反應腔室中；(c)使該基板表面曝露至電漿以驅動該基板表面上之該第一與第二反應物之間的反應，從而形成該薄膜的一部份；(d)重複(a)-(c)至少一次；(e)在允許含摻雜物材料接觸該薄膜之曝露表面的條件下，將未在(a)-(d)期間導入之該含摻雜物材料導入該反應腔室中；以及(f)自該含摻雜物材料將摻雜物導入該薄膜中。 A method of depositing a thin film on a surface of a substrate in a reaction chamber, the method comprising: (a) introducing the first reactant into the reaction chamber while allowing adsorption of the first reactant onto the surface of the substrate (b) introducing a second reactant into the reaction chamber when the first reactant is adsorbed on the surface of the substrate; (c) exposing the surface of the substrate to the plasma to drive the surface on the surface of the substrate a reaction between the first reactant and the second reactant to form a portion of the film; (d) repeating (a)-(c) at least once; (e) allowing the dopant-containing material to contact the exposed surface of the film The dopant-containing material introduced during (a)-(d) is introduced into the reaction chamber; and (f) the dopant is introduced into the film from the dopant-containing material. 如申請專利範圍第1項之在反應腔室中於基板表面上沉積薄膜之方法，更包含：(g)在(e)或(f)之後重複(a)-(c)。 The method of depositing a film on a surface of a substrate in a reaction chamber as claimed in claim 1 further comprises: (g) repeating (a)-(c) after (e) or (f). 如申請專利範圍第1項之在反應腔室中於基板表面上沉積薄膜之方法，更包含：(g)重複(a)-(e)。 The method of depositing a film on a surface of a substrate in a reaction chamber as in the first aspect of the patent application includes: (g) repeating (a)-(e). 如申請專利範圍第1項之在反應腔室中於基板表面上沉積薄膜之方法，其中於(a)-(c)期間沉積之該薄膜的厚度介於約0.5至1埃之間。 A method of depositing a film on a surface of a substrate in a reaction chamber as in claim 1, wherein the film deposited during (a)-(c) has a thickness of between about 0.5 and 1 angstrom. 如申請專利範圍第1項之在反應腔室中於基板表面上沉積薄膜之方法，更包含自該薄膜將該摻雜物驅入其上存留該薄膜之該基板表面的特徵部中。 The method of depositing a film on a surface of a substrate in a reaction chamber as in claim 1, further comprising driving the dopant from the film into a feature on a surface of the substrate on which the film is retained. 如申請專利範圍第5項之在反應腔室中於基板表面上沉積薄膜之方法，其中自該薄膜驅入該摻雜物包含回火該薄膜。 A method of depositing a film on a surface of a substrate in a reaction chamber as in claim 5, wherein driving the dopant from the film comprises tempering the film. 如申請專利範圍第5項之在反應腔室中於基板表面上沉積薄膜之方法，其中該薄膜存留在該基板表面之三維特徵部上，且其中自該薄膜驅入該摻雜物提供該摻雜物進入該特徵部之保形擴散。 A method of depositing a film on a surface of a substrate in a reaction chamber according to claim 5, wherein the film remains on a three-dimensional feature of the surface of the substrate, and wherein the dopant is driven from the film to provide the doping The debris enters the conformal diffusion of the feature. 如申請專利範圍第7項之在反應腔室中於基板表面上沉積薄膜之方法，其中該特徵部具有不大於約40奈米的寬度。 A method of depositing a film on a surface of a substrate in a reaction chamber as in claim 7 wherein the feature has a width of no greater than about 40 nanometers. 如申請專利範圍第1項之在反應腔室中於基板表面上沉積薄膜之方法，更包含在使該基板表面曝露至電漿之前自該反應腔室清除該第二反應物。 The method of depositing a film on a surface of a substrate in a reaction chamber as in claim 1 further comprises removing the second reactant from the reaction chamber before exposing the surface of the substrate to the plasma. 如申請專利範圍第9項之在反應腔室中於基板表面上沉積薄膜之方法，其中該清除包括使包含氧化劑之氣體流入該反應腔室中。 A method of depositing a film on a surface of a substrate in a reaction chamber, as in claim 9, wherein the removing comprises flowing a gas containing an oxidizing agent into the reaction chamber. 如申請專利範圍第1項之在反應腔室中於基板表面上沉積薄膜之方法，其中該第一與第二反應物以氣相共存於該反應腔室中，且其中該第一與第二反應物在該反應腔室中不明顯互相反應直到在(c)之中曝露至電漿為止。 A method of depositing a thin film on a surface of a substrate in a reaction chamber according to claim 1, wherein the first and second reactants coexist in the reaction chamber in a gas phase, and wherein the first and second The reactants do not significantly react with each other in the reaction chamber until they are exposed to the plasma in (c). 如申請專利範圍第1項之在反應腔室中於基板表面上沉積薄膜之方法，其中將該摻雜物導入該薄膜中包含使該含摻雜物材料曝露至電漿。 A method of depositing a thin film on a surface of a substrate in a reaction chamber as in claim 1, wherein introducing the dopant into the thin film comprises exposing the dopant-containing material to a plasma. 如申請專利範圍第1項之在反應腔室中於基板表面上沉積薄膜之方法，其中該第一反應物係氧化劑。 A method of depositing a film on a surface of a substrate in a reaction chamber as claimed in claim 1, wherein the first reactant is an oxidant. 如申請專利範圍第13項之在反應腔室中於基板表面上沉積薄膜之方法，其中該氧化劑係一氧化二氮。 A method of depositing a film on a surface of a substrate in a reaction chamber according to claim 13 wherein the oxidizing agent is nitrous oxide. 如申請專利範圍第1項之在反應腔室中於基板表面上沉積薄膜之方法，其中該第二反應物係選自由烷胺基矽烷(alkylamino silanes)(SiHx(NR2)4-x)(其中 x=1-3，並且R包含烷基)、以及鹵素矽烷(halosilanes)(SiHxY4-x)(其中x=1-3，並且Y包含Cl、Br、以及I)所組成的群組。 A method of depositing a film on a surface of a substrate in a reaction chamber according to claim 1, wherein the second reactant is selected from the group consisting of alkylamino silanes (SiH x (NR 2 ) 4-x ) (wherein x = 1-3, and R comprises an alkyl group), and halosilanes (SiH x Y 4-x ) (where x = 1-3, and Y comprises Cl, Br, and I) Group. 如申請專利範圍第1項之在反應腔室中於基板表面上沉積薄膜之方法，其中該第二反應物係BTBAS。 A method of depositing a film on a surface of a substrate in a reaction chamber according to claim 1, wherein the second reactant is BTBAS. 如申請專利範圍第1項之在反應腔室中於基板表面上沉積薄膜之方法，其中該含摻雜物材料係選自由磷化氫、砷化氫、烷基硼、烷基鎵、烷基磷、磷鹵化物、砷鹵化物、鎵鹵化物、硼鹵化物、烷基硼、以及乙硼烷所組成的群組。 A method of depositing a thin film on a surface of a substrate in a reaction chamber according to claim 1, wherein the dopant-containing material is selected from the group consisting of phosphine, arsine, alkyl boron, alkyl gallium, alkyl a group consisting of phosphorus, phosphorus halides, arsenic halides, gallium halides, boron halides, alkyl boron, and diborane. 如申請專利範圍第1項之在反應腔室中於基板表面上沉積薄膜之方法，其中該薄膜係介電薄膜。 A method of depositing a film on a surface of a substrate in a reaction chamber according to the first aspect of the patent application, wherein the film is a dielectric film. 如申請專利範圍第1項之在反應腔室中於基板表面上沉積薄膜之方法，其中總薄膜厚度介於約10-100埃之間。 A method of depositing a film on a surface of a substrate in a reaction chamber as in claim 1 wherein the total film thickness is between about 10 and 100 angstroms. 如申請專利範圍第1項之在反應腔室中於基板表面上沉積薄膜之方法，其中該薄膜中摻雜物的濃度介於約0.01及10重量百分率之間。 A method of depositing a film on a surface of a substrate in a reaction chamber as in claim 1, wherein the concentration of the dopant in the film is between about 0.01 and 10 weight percent. 如申請專利範圍第1項之在反應腔室中於基板表面上沉積薄膜之方法，更包含：將光阻塗佈在該基板表面；使該光阻曝露至光線；使該光阻圖案化並轉移該圖案至該基板表面；以及自該基板表面選擇性移除該光阻。 The method for depositing a film on a surface of a substrate in a reaction chamber according to the first aspect of the patent application, further comprising: coating a photoresist on the surface of the substrate; exposing the photoresist to light; patterning the photoresist Transferring the pattern to the surface of the substrate; and selectively removing the photoresist from the surface of the substrate. 如申請專利範圍第1項之在反應腔室中於基板表面上沉積薄膜之方法，其中在導入該含摻雜物材料之步驟(e)期間，該條件係使該含摻雜物材料 吸附於該薄膜之曝露表面上，而形成一吸附限制層；並且其中將摻雜物導入該薄膜中之步驟(f)包含使吸附之該含摻雜物材料反應，以形成含有摻雜物源之該薄膜的一層。 A method of depositing a thin film on a surface of a substrate in a reaction chamber according to the first aspect of the patent application, wherein the step of introducing the dopant-containing material during the step (e) is to cause the dopant-containing material Adsorbing on the exposed surface of the film to form an adsorption limiting layer; and wherein the step (f) of introducing the dopant into the film comprises reacting the adsorbed dopant-containing material to form a dopant-containing source a layer of the film. 如申請專利範圍第22項之在反應腔室中於基板表面上沉積薄膜之方法，其中在步驟(f)中使吸附之該含摻雜物材料反應包含使該含摻雜物材料暴露於電漿。 A method of depositing a thin film on a surface of a substrate in a reaction chamber as in claim 22, wherein reacting the adsorbed dopant-containing material in step (f) comprises exposing the dopant-containing material to electricity Pulp. 如申請專利範圍第22項之在反應腔室中於基板表面上沉積薄膜之方法，其中步驟(e)與步驟(f)包含原子層沉積。 A method of depositing a thin film on a surface of a substrate in a reaction chamber as in claim 22, wherein the steps (e) and (f) comprise atomic layer deposition. 如申請專利範圍第22項之在反應腔室中於基板表面上沉積薄膜之方法，更包含：(g)在步驟(e)或步驟(f)之後，形成一覆蓋層，該覆蓋層為保護性擴散阻障層。 The method for depositing a film on a surface of a substrate in a reaction chamber according to claim 22, further comprising: (g) forming a cover layer after the step (e) or the step (f), the cover layer is protected Sex diffusion barrier layer. 一種在反應腔室中於基板表面上沉積介電薄膜之方法，該方法包含：(a)在允許氧化劑吸附至該基板表面上的條件下，使該氧化劑流入該反應腔室中；(b)在該氧化劑持續流入該反應腔室時，將介電質前驅物導入該反應腔室中；(c)使該基板表面曝露至電漿以驅動該基板表面上之該介電質前驅物與該氧化劑之間的反應，從而形成該介電薄膜的一部份；(d)在允許含摻雜物材料接觸該介電薄膜之曝露表面的條件下，將未在(a)-(c)期間導入之該含摻雜物材料導入該反應腔室中；以及(e)使摻雜物自該含摻雜物材料結合至該介電薄膜中。 A method of depositing a dielectric film on a surface of a substrate in a reaction chamber, the method comprising: (a) flowing an oxidant into the reaction chamber while allowing an oxidant to adsorb onto the surface of the substrate; (b) Introducing a dielectric precursor into the reaction chamber as the oxidant continues to flow into the reaction chamber; (c) exposing the surface of the substrate to a plasma to drive the dielectric precursor on the surface of the substrate and a reaction between the oxidants to form a portion of the dielectric film; (d) under conditions that allow the dopant-containing material to contact the exposed surface of the dielectric film, not during (a)-(c) Introducing the dopant-containing material into the reaction chamber; and (e) incorporating dopants from the dopant-containing material into the dielectric film. 如申請專利範圍第26項之在反應腔室中於基板表面上沉積介電薄膜之方法，其中該介電質前驅物係BTBAS。 A method of depositing a dielectric film on a surface of a substrate in a reaction chamber according to claim 26, wherein the dielectric precursor is BTBAS. 如申請專利範圍第26項之在反應腔室中於基板表面上沉積介電薄膜之方法，更包含自該介電薄膜將該摻雜物驅入該基板中。 A method of depositing a dielectric film on a surface of a substrate in a reaction chamber as in claim 26, further comprising driving the dopant into the substrate from the dielectric film. 如申請專利範圍第26項之在反應腔室中於基板表面上沉積介電薄膜之方法，其中重複操作(a)-(c)。 A method of depositing a dielectric film on a surface of a substrate in a reaction chamber as in claim 26, wherein operations (a) - (c) are repeated. 如申請專利範圍第29項之在反應腔室中於基板表面上沉積介電薄膜之方法，其中當(a)最先執行時，該氧化劑包含氧對氮之第一比率，且其中當(a)重複時，該氧化劑包含氧對氮之第二比率，該第二比率小於該第一比率。 A method of depositing a dielectric film on a surface of a substrate in a reaction chamber as in claim 29, wherein when (a) is first performed, the oxidant comprises a first ratio of oxygen to nitrogen, and wherein (a) When repeated, the oxidant comprises a second ratio of oxygen to nitrogen, the second ratio being less than the first ratio. 如申請專利範圍第30項之在反應腔室中於基板表面上沉積介電薄膜之方法，其中當(a)最先執行時，該氧化劑包含元素氧，且其中當(a)重複時，該氧化劑包含一氧化二氮。 A method of depositing a dielectric film on a surface of a substrate in a reaction chamber as in claim 30, wherein when (a) is first performed, the oxidant comprises elemental oxygen, and wherein when (a) is repeated, The oxidant comprises nitrous oxide. 如申請專利範圍第29項之在反應腔室中於基板表面上沉積介電薄膜之方法，其中當(c)最先執行時，該基板係處於第一溫度下，且其中當(c)重複時，該基板係處於比該第一溫度高的第二溫度下。 A method of depositing a dielectric film on a surface of a substrate in a reaction chamber as in claim 29, wherein when (c) is first performed, the substrate is at a first temperature, and wherein (c) is repeated The substrate is at a second temperature that is higher than the first temperature. 如申請專利範圍第26項之在反應腔室中於基板表面上沉積介電薄膜之方法，更包含在(a)之前使該基板表面與該含摻雜物材料接觸。 A method of depositing a dielectric film on a surface of a substrate in a reaction chamber as in claim 26, further comprising contacting the surface of the substrate with the dopant-containing material prior to (a). 如申請專利範圍第26項之在反應腔室中於基板表面上沉積介電薄膜之方法，其中在導入該含摻雜物材料之步驟(d)期間，該條件係使該含摻雜物材料吸附於該介電薄膜之曝露表面上，而形成一吸附限制層；並且其中使摻雜物結合至該介電薄膜中之步驟(e)包含使吸附之該含摻雜物材料反應，以形成含有摻雜物源之該介電薄膜的一層。 A method of depositing a dielectric film on a surface of a substrate in a reaction chamber as in claim 26, wherein the step of introducing the dopant-containing material during the step (d) is to cause the dopant-containing material Adsorbing on the exposed surface of the dielectric film to form an adsorption limiting layer; and wherein the step (e) of bonding the dopant to the dielectric film comprises reacting the adsorbed dopant-containing material to form A layer of the dielectric film containing a dopant source. 如申請專利範圍第34項之在反應腔室中於基板表面上沉積介電薄膜之方法，其中在步驟(e)中使吸附之該含摻雜物材料反應包含使該含摻雜物材料暴露於電漿。 A method of depositing a dielectric film on a surface of a substrate in a reaction chamber according to claim 34, wherein reacting the adsorbed dopant-containing material in step (e) comprises exposing the dopant-containing material In plasma. 如申請專利範圍第34項之在反應腔室中於基板表面上沉積介電薄膜之方法，其中步驟(d)與步驟(e)包含原子層沉積。 A method of depositing a dielectric film on a surface of a substrate in a reaction chamber as in claim 34, wherein steps (d) and (e) comprise atomic layer deposition. 如申請專利範圍第34項之在反應腔室中於基板表面上沉積介電薄膜之方法，更包含：(f)在步驟(d)或步驟(e)之後，形成一覆蓋層，該覆蓋層為保護性擴散阻障層。 The method for depositing a dielectric film on a surface of a substrate in a reaction chamber according to claim 34, further comprising: (f) forming a cover layer after step (d) or step (e), the cover layer A protective diffusion barrier layer. 一種在反應腔室中於基板表面上沉積介電薄膜之方法，該方法包含：(a)在允許介電質前驅物吸附至該基板表面上的條件下，將該介電質前驅物導入該反應腔室中；(b)之後在該介電質前驅物保持吸附在該基板表面上時，自該反應腔室清除該介電質前驅物；(c)使該基板表面曝露至電漿以驅動該基板表面上之該介電質前驅物的反應，從而形成該介電薄膜的一部份；以及(d)在允許摻雜物前驅物接觸該介電薄膜之一部份的條件下，將未在(a)-(c)期間導入之該摻雜物前驅物導入該反應腔室中。 A method of depositing a dielectric film on a surface of a substrate in a reaction chamber, the method comprising: (a) introducing a dielectric precursor into the substrate while allowing a dielectric precursor to be adsorbed onto the surface of the substrate In the reaction chamber; (b) after the dielectric precursor remains adsorbed on the surface of the substrate, the dielectric precursor is removed from the reaction chamber; (c) the surface of the substrate is exposed to the plasma Driving a reaction of the dielectric precursor on the surface of the substrate to form a portion of the dielectric film; and (d) allowing the dopant precursor to contact a portion of the dielectric film, The dopant precursor that was not introduced during (a)-(c) was introduced into the reaction chamber. 如申請專利範圍第38項之在反應腔室中於基板表面上沉積介電薄膜之方法，更包含在(a)-(c)之前以及在(a)-(c)期間使氧化劑流入該反應腔室中。 A method of depositing a dielectric film on a surface of a substrate in a reaction chamber as in claim 38, further comprising flowing an oxidant into the reaction before (a)-(c) and during (a)-(c) In the chamber. 如申請專利範圍第38項之在反應腔室中於基板表面上沉積介電薄膜之方法，更包含：(e)使該摻雜物前驅物反應以導入摻雜物至該介電薄膜。 A method of depositing a dielectric film on a surface of a substrate in a reaction chamber as in claim 38, further comprising: (e) reacting the dopant precursor to introduce a dopant to the dielectric film. 如申請專利範圍第38項之在反應腔室中於基板表面上沉積介電薄膜之方 法，其中在導入該摻雜物前驅物之步驟(d)期間，該條件係使該摻雜物前驅物吸附於該介電薄膜之該部分上，而形成一吸附限制層；並且該方法更包含：(e)使吸附之該摻雜物前驅物反應，以形成含有摻雜物源之該介電薄膜的一層。 The method of depositing a dielectric film on the surface of the substrate in the reaction chamber as claimed in claim 38 a method, wherein during the step (d) of introducing the dopant precursor, the condition is such that the dopant precursor is adsorbed on the portion of the dielectric film to form an adsorption limiting layer; and the method is further The method comprises: (e) reacting the adsorbed dopant precursor to form a layer of the dielectric film containing a dopant source. 如申請專利範圍第41項之在反應腔室中於基板表面上沉積介電薄膜之方法，其中在步驟(e)中使吸附之該摻雜物前驅物反應包含使該摻雜物前驅物暴露於電漿。 A method of depositing a dielectric film on a surface of a substrate in a reaction chamber as in claim 41, wherein reacting the adsorbed dopant precursor in step (e) comprises exposing the dopant precursor In plasma. 如申請專利範圍第41項之在反應腔室中於基板表面上沉積介電薄膜之方法，其中步驟(d)與步驟(e)包含原子層沉積。 A method of depositing a dielectric film on a surface of a substrate in a reaction chamber as in claim 41, wherein step (d) and step (e) comprise atomic layer deposition. 如申請專利範圍第41項之在反應腔室中於基板表面上沉積介電薄膜之方法，更包含：(f)在步驟(d)或步驟(e)之後，形成一覆蓋層，該覆蓋層為保護性擴散阻障層。 The method for depositing a dielectric film on a surface of a substrate in a reaction chamber according to claim 41, further comprising: (f) forming a cover layer after step (d) or step (e), the cover layer A protective diffusion barrier layer. 一種在基板表面上沉積摻雜薄膜之設備，該設備包含：一反應腔室，包含該摻雜薄膜的沉積期間用以夾持該基板之裝置；一或更多處理氣體進氣口，耦接至該反應腔室；以及一控制器，設計或配置以造成該設備執行以下操作：(a)在允許第一反應物吸附至該基板表面上的條件下，將該第一反應物導入該反應腔室中；(b)在該第一反應物吸附在該基板表面上時，將第二反應物導入該反應腔室中；(c)使該基板表面曝露至電漿以驅動該基板表面上之該第一與第二反應物之間的反應，從而形成該摻雜薄膜的一部份； (d)重複(a)-(c)至少一次；(e)在允許含摻雜物材料接觸該摻雜薄膜之曝露表面的條件下，將未在(a)-(d)期間導入之該含摻雜物材料導入該反應腔室中；以及(f)自該含摻雜物材料將摻雜物導入該摻雜薄膜中。 An apparatus for depositing a doped film on a surface of a substrate, the apparatus comprising: a reaction chamber comprising means for holding the substrate during deposition of the doped film; one or more process gas inlets, coupled To the reaction chamber; and a controller, designed or configured to cause the apparatus to: (a) introduce the first reactant into the reaction while allowing the first reactant to adsorb onto the surface of the substrate (b) introducing a second reactant into the reaction chamber when the first reactant is adsorbed on the surface of the substrate; (c) exposing the surface of the substrate to the plasma to drive the surface of the substrate a reaction between the first and second reactants to form a portion of the doped film; (d) repeating (a)-(c) at least once; (e) introducing the dopant-free material into the exposed surface of the doped film, which is not introduced during (a)-(d) A dopant-containing material is introduced into the reaction chamber; and (f) a dopant is introduced into the doped film from the dopant-containing material. 如申請專利範圍第45項之在基板表面上沉積摻雜薄膜之設備，其中該控制器更設計或配置以造成該設備在(a)-(d)之前以及在(a)-(d)期間使氧化劑流入該反應腔室中。 An apparatus for depositing a doped film on a surface of a substrate as in claim 45, wherein the controller is more designed or configured to cause the device to be before (a)-(d) and during (a)-(d) The oxidant is flowed into the reaction chamber. 如申請專利範圍第45項之在基板表面上沉積摻雜薄膜之設備，其中該控制器更設計或配置以造成(g)在(e)或(f)之後重複(a)-(c)。 An apparatus for depositing a doped film on a surface of a substrate as in claim 45, wherein the controller is more designed or configured to cause (g) to repeat (a)-(c) after (e) or (f). 如申請專利範圍第45項之在基板表面上沉積摻雜薄膜之設備，其中該控制器更設計或配置以造成(g)自該摻雜薄膜將該摻雜物驅入其上存留該摻雜薄膜之該基板表面的特徵部中。 An apparatus for depositing a doped film on a surface of a substrate as in claim 45, wherein the controller is further designed or configured to cause (g) driving the dopant from the doped film to retain the doping thereon. The feature of the surface of the substrate of the film. 如申請專利範圍第48項之在基板表面上沉積摻雜薄膜之設備，其中自該摻雜薄膜驅入該摻雜物包含回火該摻雜薄膜。 An apparatus for depositing a doped film on a surface of a substrate as in claim 48, wherein driving the dopant from the doped film comprises tempering the doped film. 如申請專利範圍第45項之在基板表面上沉積摻雜薄膜之設備，其中該控制器更設計或配置以造成在使該基板表面曝露至電漿之前，自該反應腔室清除該第二反應物。 An apparatus for depositing a doped film on a surface of a substrate as in claim 45, wherein the controller is further designed or configured to cause the second reaction to be removed from the reaction chamber prior to exposing the surface of the substrate to the plasma Things. 如申請專利範圍第50項之在基板表面上沉積摻雜薄膜之設備，其中該清除包括使包含氧化劑之氣體流入該反應腔室中。 An apparatus for depositing a doped film on a surface of a substrate as in claim 50, wherein the removing comprises flowing a gas containing an oxidizing agent into the reaction chamber. 如申請專利範圍第45項之在基板表面上沉積摻雜薄膜之設備，其中該控制器更設計或配置以造成在(a)-(d)之一或更多重複之間的間隔執行(e)，且其中該間隔在沉積該摻雜薄膜的過程中改變。 An apparatus for depositing a doped film on a surface of a substrate as in claim 45, wherein the controller is more designed or configured to cause an interval between one or more of (a)-(d) to repeat (e And wherein the spacing changes during deposition of the doped film. 一種包含申請專利範圍第45項之設備以及步進機之系統。 A system comprising a device of claim 45 and a stepper.
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