TWI528458B - 半導體元件及其製備方法 - Google Patents
半導體元件及其製備方法 Download PDFInfo
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- TWI528458B TWI528458B TW101114809A TW101114809A TWI528458B TW I528458 B TWI528458 B TW I528458B TW 101114809 A TW101114809 A TW 101114809A TW 101114809 A TW101114809 A TW 101114809A TW I528458 B TWI528458 B TW I528458B
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- mesa structure
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- 239000004065 semiconductor Substances 0.000 title claims description 35
- 238000004519 manufacturing process Methods 0.000 title claims description 23
- 229910052751 metal Inorganic materials 0.000 claims description 66
- 239000002184 metal Substances 0.000 claims description 66
- 238000000034 method Methods 0.000 claims description 35
- 239000000758 substrate Substances 0.000 claims description 15
- 238000000151 deposition Methods 0.000 claims description 13
- 238000005530 etching Methods 0.000 claims description 13
- 230000004888 barrier function Effects 0.000 claims description 10
- 239000007943 implant Substances 0.000 claims description 9
- 238000002360 preparation method Methods 0.000 claims description 7
- 230000008021 deposition Effects 0.000 claims description 5
- 239000010953 base metal Substances 0.000 claims 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 35
- 229920005591 polysilicon Polymers 0.000 description 35
- 229920002120 photoresistant polymer Polymers 0.000 description 33
- 210000004027 cell Anatomy 0.000 description 24
- 150000004767 nitrides Chemical class 0.000 description 19
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 12
- 229910052732 germanium Inorganic materials 0.000 description 11
- 238000005253 cladding Methods 0.000 description 6
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 6
- 229910052721 tungsten Inorganic materials 0.000 description 6
- 239000010937 tungsten Substances 0.000 description 6
- 210000000746 body region Anatomy 0.000 description 5
- 239000002019 doping agent Substances 0.000 description 5
- 150000002500 ions Chemical class 0.000 description 5
- 230000015556 catabolic process Effects 0.000 description 4
- 239000010936 titanium Substances 0.000 description 4
- 238000001039 wet etching Methods 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 239000011248 coating agent Substances 0.000 description 3
- 238000000576 coating method Methods 0.000 description 3
- 238000001312 dry etching Methods 0.000 description 3
- SIWVEOZUMHYXCS-UHFFFAOYSA-N oxo(oxoyttriooxy)yttrium Chemical compound O=[Y]O[Y]=O SIWVEOZUMHYXCS-UHFFFAOYSA-N 0.000 description 3
- 238000003860 storage Methods 0.000 description 3
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- -1 boron ions Chemical class 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 239000010941 cobalt Substances 0.000 description 2
- 229910017052 cobalt Inorganic materials 0.000 description 2
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 238000005381 potential energy Methods 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 229910016570 AlCu Inorganic materials 0.000 description 1
- 229910052691 Erbium Inorganic materials 0.000 description 1
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 description 1
- HAYXDMNJJFVXCI-UHFFFAOYSA-N arsenic(5+) Chemical compound [As+5] HAYXDMNJJFVXCI-UHFFFAOYSA-N 0.000 description 1
- 210000000678 band cell Anatomy 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 229910052797 bismuth Inorganic materials 0.000 description 1
- JCXGWMGPZLAOME-UHFFFAOYSA-N bismuth atom Chemical compound [Bi] JCXGWMGPZLAOME-UHFFFAOYSA-N 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- KGBXLFKZBHKPEV-UHFFFAOYSA-N boric acid Chemical compound OB(O)O KGBXLFKZBHKPEV-UHFFFAOYSA-N 0.000 description 1
- 239000004327 boric acid Substances 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 239000005380 borophosphosilicate glass Substances 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- UYAHIZSMUZPPFV-UHFFFAOYSA-N erbium Chemical compound [Er] UYAHIZSMUZPPFV-UHFFFAOYSA-N 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000005121 nitriding Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000011084 recovery Methods 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- 229910052707 ruthenium Inorganic materials 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000004557 technical material Substances 0.000 description 1
- XSOKHXFFCGXDJZ-UHFFFAOYSA-N telluride(2-) Chemical compound [Te-2] XSOKHXFFCGXDJZ-UHFFFAOYSA-N 0.000 description 1
- 230000008719 thickening Effects 0.000 description 1
- RUDFQVOCFDJEEF-UHFFFAOYSA-N yttrium(III) oxide Inorganic materials [O-2].[O-2].[O-2].[Y+3].[Y+3] RUDFQVOCFDJEEF-UHFFFAOYSA-N 0.000 description 1
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- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
- H01L29/4238—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the surface lay-out
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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- H01L29/4933—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a silicide layer contacting the silicon layer, e.g. Polycide gate
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Description
本發明主要涉及半導體元件,更確切地說,是涉及在終端區內帶有集成蕭特基二極體的遮罩閘極溝槽金氧半導體的製備方法。
於2010年3月11日存檔的美國專利申請號為12/722,384,題為《帶有增強型源極吸引佈局的遮罩閘極溝槽MOS》的專利,提出了一種僅利用四個遮罩製備半導體元件的方法,特此引用其全文以作參考。該方法包括利用第一遮罩製備多個溝槽,在多個溝槽中製備第一導電區,利用第二遮罩製備中間電介質區以及終端保護區,至少在某些溝槽中製備第二導電區,利用第三遮罩形成到第二導電區的第一電性接點以及到第一導電區的第二電性接點,沉積金屬層,利用第四遮罩形成源極金屬區和閘極金屬區。
這種集成結構含有功率MOSFET元件,功率MOSFET中配置了體二極體。然而,典型的P-N面結型二極體在運行時具有不良特性。這些不良特性包括:巨大的正向傳導損耗、在正向配置狀態下本體-外延結之間的電荷儲存、當功率MOSFET從正向偏壓切換至反向偏壓時過量的儲存少子電荷導致巨大的恢復電流以及電壓過沖、以及在直流-直流轉換應用中開關節點電壓過沖/環繞。
另一方面,蕭特基二極體具有一些優於P-N結二極體的優良特性,尤其是配置在功率MOSFET中時。蕭特基二極體在正向傳導時正向壓降很低,會降低元件的功率耗散,從而使傳導損耗更低。由於蕭特基的傳導是通過多子進行的,因此在元件開關時不會發生少子電荷儲存效應。
正是在這一前提下,提出了本發明的各種實施例。
本發明的目的是提供一種在功率MOSFET內集成蕭特基二極體的方法,用於製備半導體元件,該方法在集成結構中引入了蕭特基二極體,但是其制備技術仍然沿用自對準接觸體系,並且同樣僅僅需要四個遮罩。該集成結構的製備成本更低,而且增強了元件的性能。
為了達到上述目的,本發明提供了一種用於製備半導體元件的方法,包括:a)利用第一遮罩,在基板上製備複數溝槽,所述複數溝槽包括位於主動區中的主動閘極溝槽,位於含有主動閘極溝槽的主動區之外的終端區中的閘極通道/終端溝槽以及屏蔽電極吸引溝槽,閘極通道/終端溝槽包括一個或多個溝槽,所述一個或多個溝槽限定了位於含有主動閘極溝槽的主動區之外的區域中的臺面結構;b)在限定臺面結構的一個或多個溝槽中,製備第一導電區;c)利用第二遮罩,在限定臺面結構的一個或多個溝槽中,製備一個中間電介質區以及一個終端保護區;d)在限定臺面結構的一個或多個溝槽中,製備第二導電區;
e)形成到第二導電區的第一電性接點,在位於終端區中的屏蔽電極吸引溝槽中,形成到第一導電區的第二電性接點,並且利用第三遮罩,在含有主動閘極溝槽的主動區外部的區域中,在終端溝槽之間形成的臺面結構內,製備一個或多個蕭特基二極體。
其中,該方法還包括:f)在元件上沉積一個金屬層;並且g)利用第四遮罩,用金屬層製備源極金屬區和閘極金屬區。
其中,該方法還包括在一個或多個終端溝槽中,製備非對稱的側壁。
其中,製備非對稱的側壁包括切口刻蝕至少部分被第二遮罩覆蓋的那部分氧化層。
其中,非對稱的側壁包括第一側壁和第二側壁,第一側壁具有比第二側壁更厚的氧化層,第一側壁更靠近蕭特基二極體。
其中,製備蕭特基二極體包括在終端溝槽之間形成的臺面結構的裸露表面上,沉積勢壘金屬。
其中,臺面結構的裸露表面是臺面結構中所形成的電位井的裸露表面。
其中,製備蕭特基二極體包括進行深孔穴植入,以便在蕭特基二極體有關的蕭特基結下方,形成摻雜遮罩區。
本發明還提供了一種半導體元件,包括:a)基板上的複數溝槽,其包括位於主動區中的一個或多個主動閘極溝槽,以及位於含有主動閘極溝槽的主動區外部的終端區中的一個或
多個閘極通道/終端溝槽以及遮罩閘極吸引溝槽,閘極通道/終端溝槽包括一個或多個溝槽,所述一個或多個溝槽限定了位於含有主動閘極溝槽的主動區之外的區域中的臺面結構;b)形成於所述複數溝槽中的第一導電區;c)形成於限定臺面結構的一個或多個溝槽的至少一部分中的一個中間電介質區以及一個終端保護區;d)形成於限定臺面結構的一個或多個溝槽的至少一部分中的第二導電區,其中,第二導電區通過中間電介質區,與第一導電區電絕緣;以及e)到第二導電區的第一電性接點,在位於終端區中的屏蔽電極吸引溝槽中,到第一導電區的第二電性接點,以及在臺面結構內,形成的一個或多個蕭特基二極體。
其中,該元件還包括連接到第一電性接點的閘極金屬區,以及連接到第二電性接點的源極金屬區,其中閘極金屬區域與源極金屬區電絕緣。
其中,所述蕭特基二極體包括位於臺面結構的裸露表面上的勢壘金屬。
其中,所述臺面結構的裸露表面是在臺面結構中所形成的電位井的裸露表面。
其中,所述蕭特基二極體包括深孔穴植入,以便在蕭特基二極體有關的蕭特基結下方,形成摻雜遮罩區。
其中,一個或多個蕭特基二極體位於主動元件的第一和第二鄰近組之間的封閉晶胞結構中。
其中,一個或多個蕭特基二極體形成在比主動元件的臺面結構更寬的蕭特基臺面結構上,一個或多個主動元件就形成在主動元件臺面結構上。
其中,一個或多個蕭特基二極體位於主動元件的第一和第二鄰近組之間的帶狀晶胞結構中。
其中,一個或多個蕭特基二極體形成在比主動元件的臺面結構更寬的蕭特基臺面結構上,一個或多個主動元件就形成在主動元件臺面結構上。
本發明提出了含有配置了蕭特基二極體的功率MOSFET元件的集成結構的技術方案;雖然在集成結構中引入了蕭特基二極體,但是其製備技術仍然沿用自對準接觸體系,並且同樣僅僅需要四個遮罩。該集成結構的製備成本更低,而且增強了元件的性能。
102、602‧‧‧基底
104、204‧‧‧主動閘極溝槽
106‧‧‧源極/本體接觸開口
108‧‧‧遮罩接頭
110‧‧‧終端/閘極通道溝槽
110、2210‧‧‧終端溝槽
112‧‧‧閘極吸引接觸開口
114‧‧‧閘極金屬區
116‧‧‧源極金屬
118‧‧‧遮罩吸引溝槽
120‧‧‧終端/閘極通道閘極通道延伸溝槽
122、906‧‧‧臺面結構
124‧‧‧蕭特基二極體接頭
145‧‧‧帶狀蕭特基二極體區
200‧‧‧溝槽遮罩
104、204‧‧‧主動閘極溝槽
208‧‧‧源極多晶矽吸引溝槽
210‧‧‧閘極通道/終端溝槽
300‧‧‧第二遮罩
302‧‧‧多晶矽覆蓋遮罩陰影
304‧‧‧第二遮罩非陰影區
306、308‧‧‧開口的邊緣靠近終端溝槽
400‧‧‧第三遮罩
402‧‧‧閘極多晶矽吸引接頭
404‧‧‧源極多晶矽吸引接頭
408‧‧‧蕭特基接頭
500‧‧‧金屬遮罩
502、504‧‧‧陰影區
102、602‧‧‧基底
604‧‧‧氧化矽層
606‧‧‧氮化層
702、902‧‧‧終端溝槽開口
704‧‧‧剩餘的PR層
802、902‧‧‧溝槽開口
906‧‧‧臺面結構
1000‧‧‧氮化物墊片
1102‧‧‧終端溝槽
1201、1701、1906‧‧‧氧化層
1301、1401‧‧‧多晶矽
1501‧‧‧等離子氧化物
1701‧‧‧氧化物薄膜
1801、2800、3304、1804、1804’、1806、3304‧‧‧PR覆層
1902‧‧‧終端溝槽
1904‧‧‧PR層邊緣
1906‧‧‧中間-多晶矽電介質(IPD)
2002、2004‧‧‧溝槽壁
2006‧‧‧結構溝槽
2110‧‧‧多晶矽層
2102‧‧‧閘極多晶矽
2200‧‧‧氮化物
2304‧‧‧本體區
2402‧‧‧源極區
2500‧‧‧氧化物
2900‧‧‧開口
3000‧‧‧電位井
3100‧‧‧摻雜遮罩區
3200‧‧‧勢壘金屬
3202‧‧‧鎢插頭
3300‧‧‧金屬
3302‧‧‧裸露區域
t1‧‧‧厚度
150、152、154、156、158、160、162、164‧‧‧流程步驟
第1a圖是依據本發明的實施例而製作的一種集成結構的俯視圖。
第1b圖是依據本發明的實施例,將蕭特基二極體配置在封閉晶胞佈局中的集成結構的俯視圖。
第1c圖是依據本發明的實施例,將蕭特基二極體配置在帶狀晶胞佈局中的集成結構的俯視圖。
第1d圖是第1a圖所示類型的集成結構的製備技術流程圖。
第2圖是在用於製備第1a圖所示類型的集成結構的製備技術中使用第一遮罩的示例。
第3圖是在用於製備1a圖所示類型的集成結構的製備技術中使用第二遮罩的示例。
第4圖是在用於製備1a圖所示類型的集成結構的製備技術中使用第三遮罩的示例。
第5圖是在用於製備第1a圖所示類型的集成結構的製備技術中使用第四遮罩的示例。
第6圖到第34圖所示的剖面圖,表示製備第1a圖所示類型的集成結構沿線SS’的步驟。
下文詳細介紹了本發明的一個或多個實施例以及附圖,並對本發明的原理進行解釋說明。雖然本發明與這些實施例有關,但是本發明並不局限於任意實施例。本發明的範圍僅由申請專利範圍限定,並且本發明含有各種可選、修正以及等效方案。下文中提出的各具體細節是為了全面解釋本發明。這些細節僅用於舉例說明,無需某些或全部具體細節,可以根據申請專利範圍來實現本發明。為了簡便,文中沒有詳細介紹關於本發明的技術領域中已知的技術材料,以免對本發明產生不必要的混淆。
本發明提出了含有配置了蕭特基二極體的功率金氧半場效電晶體(MOSFET)元件的集成結構的實施例。雖然在集成結構中引入了蕭特基二極體,但是其製備技術仍然沿用自對準接觸體系,並且同樣僅僅需要四個遮罩。該集成結構的製備成本更低,而且增強了MOSFET元件的性能。
第1a圖是依據我們當前發明的實施例,製作的一種集成結構的俯視圖。在本例中,集成結構內建於半導體基底102上。結構的主動區含有主動閘極溝槽104,閘極就在閘極溝槽中形成。主動區還包括源極/本體接觸開口106,在接觸開口中形成接頭,將源極區和本體區電性連接到源極金屬116。主動區還包括遮罩接頭108,該遮罩接頭108可能由類似多晶矽之類的傳導物質構成。屏蔽電極沉積在遮罩吸引溝槽118中,並且通過遮罩吸引接觸開口108電性連接到源極金屬116,源極金屬116依次電性連接到MOSFET元件的源極和本體區。主動區被終端/閘極通道溝槽110包圍著,其目的在於:作為終端溝槽,將高勢能區(例如汲極)和低勢能區(例如源極)分開;作為閘極通道,在主動閘極溝槽中形成帶有閘極電極的電性連接。終端/閘極通道溝槽110還包括構成閘極通道延伸溝槽120的部分。閘極通道延伸溝槽延伸到閘極金屬區114中,用作閘極通道溝槽,閘極吸引接觸開口112就沉積在閘極吸引溝槽中,用於將閘極通道電性連接到閘極金屬114。
上述可選件與美國專利申請號為12/722,384的專利中所述的集成結構的可選件完全相同。提出的方法含有附加的可選件。臺面結構122形成於兩個終端溝槽之間,一個或多個蕭特基二極體接頭124形成於臺面結構122中。引入這些蕭特基二極體為功率MOSFET元件帶來了上述良好的性能。
在本發明的具體實施例中,需要將蕭特基二極體或二極體組置於鄰近的主動元件晶胞或這種晶胞組之間。有許多不同可能的佈局,可以將蕭特基二極體置於主動晶胞之間。作為示例,但不作為局限,第1b圖表示第一種可能的蕭特基佈局,此處稱為“封閉晶胞”蕭特基佈局。在這類佈局中,蕭特基二極體區141位於主動元件晶胞的第一和第二組142A、142B之間。每組主動晶胞142A、142B都被對應的終端結
構143A、143B包圍。蕭特基二極體結構141形成在主動晶胞的第一和第二組的終端結構之間的空間中。每個蕭特基二極體結構都含有到源極金屬層(圖中沒有表示出)的垂直連接。蕭特基二極體結構141作為一系列蕭特基晶胞,沿附近的終端結構143A、143B的平行線分佈。兩個鄰近的主動晶胞組的終端結構通過橫向終端結構144連接起來,橫向終端結構144垂直於蕭特基二極體結構141。因此,每個蕭特基二極體晶胞結構都被終端結構包圍著。
第1c圖表示另一種可能的蕭特基佈局,此處稱為“帶狀晶胞”蕭特基佈局。在該佈局中,帶狀蕭特基二極體區145位於主動元件晶胞的第一和第二組142A、142B之間,142A、142B被對應的終端結構143A、143B包圍。帶狀蕭特基二極體結構145沿附近的終端結構143A、143B的平行線分佈。兩個鄰近的主動晶胞組的終端結構通過橫向終端結構144連接起來,橫向終端結構144在蕭特基二極體結構144的每個末端垂直於蕭特基二極體結構141。因此,蕭特基二極體晶胞結構144是連續的,並且都被終端結構包圍著。
第1d圖所示的流程圖表示集成結構的製備技術的實施例。流程150含有四個遮罩。步驟152,利用第一遮罩形成多個溝槽。
步驟154,在所述多個溝槽中形成第一組多晶矽區。步驟156,利用第二遮罩形成一個或多個中間-多晶矽電介質區,以及一個或多個終端保護區。步驟158,在一些溝槽中沉積多晶矽,形成第二組多晶矽區。步驟160,利用第三遮罩,製成到閘極多晶矽的第一電性接點開口,到源極多晶矽的第二電性接點開口,並且在終端溝槽之間的臺面結構中形成一個或多個蕭特基二極體,終端溝槽在含有主動閘極溝槽的主動區外部的區域中。步驟162,沉積一個金屬層。步驟164,利用第四遮罩,形成源極金屬區和閘極金屬區。
下文還將詳細介紹製備技術150。但是,為了簡便,將僅就在集成結構內製備蕭特基二極體進行討論。第2圖到第5圖表示製備技術中所用的四個遮罩的俯視圖,第6圖-第34圖,其係為製備第1a圖所示類型的集成結構的步驟且沿線SS’之剖面圖。SS’穿過蕭特基二極體延伸,兩個終端溝槽用於終端並包圍主動區,以及主動區中兩個源極/本體接頭的邊緣。
在下文的討論中,以N型MOSFET元件為例進行解釋說明。P型MOSFET元件也可利用類似的技術進行製備。在第6圖中,N型基底602(即N-外延層生長在N+矽晶圓上)用作MOSFET元件的汲極。在某些實施例中,外延層摻雜濃度為2×1016摻雜物/cm3,厚度為1.4μm。在其他實施例中,對於重摻雜的N++基底而言,使用雙外延層,包括一個摻雜濃度為2×1016摻雜物/cm3,厚度為1.4μm的外延層,以及一個摻雜濃度為1017摻雜物/cm3,厚度為2.4μm的緩衝層。
氧化矽層604通過沉積或熱氧化形成在基底602上。氮化層606沉積在氧化矽層上方。在某些實施例中,氧化矽層的厚度約為500至1500Å,氮化層的厚度約為1500Å。氧化層必須很厚,以便阻止蕭特基區在製備過程中隨後摻雜本體/源極。
然後,在氮化層上方使用光致抗蝕劑(PR)層,並利用第一遮罩製圖。第2圖表示第一遮罩示例的俯視圖,也稱為溝槽遮罩。溝槽遮罩含有開口,使MOSFET元件的溝槽和終端溝槽為刻蝕技術裸露出來。利用溝槽遮罩200繪製PR層的圖案。對應遮罩陰影區的PR區不會裸露出來,對應遮罩非陰影區的PR區裸露出來。在以下討論中,為了解釋說明,假設使用的是正性PR,則保留未裸露的區域,除去裸露區域。也可以使用負性PR,不過需要相應地修改遮罩。溝槽遮罩200限定主動
閘極溝槽204、源極多晶矽吸引溝槽208以及閘極通道/終端溝槽210。
在某些實施例中,主動閘極溝槽、源極多晶矽吸引溝槽以及閘極通道/終端溝槽的寬度分別約為0.45μm、1.0μm和2.0μm。可以使用低級遮罩,例如臨界尺寸為0.35μm的遮罩來製備MOSFET元件,從而降低所需遮罩的成本。
在第7圖中,剩餘的PR層704形成終端溝槽開口702。
隨後,通過硬遮罩(HM)刻蝕,除去氮化層和氧化矽層的裸露部分。刻蝕在矽表面停止。然後除去剩餘的PR層704。在第8圖中,在裸露區域中形成溝槽開口802。
在HM刻蝕之後進行溝槽刻蝕。在第9圖中,將終端溝槽開口902刻蝕得更深。在某些實施例中,溝槽的目標深度約為0.3μm至0.5μm。終端溝槽開口902之間的區域形成一個臺面結構906,蕭特基二極體就形成在臺面結構906上。對於具有在主晶片中的晶胞間距為1μm的帶狀晶胞的封閉晶胞蕭特基佈局設計而言,蕭特基臺面結構906要比承載主動元件的主動元件臺面結構更寬,這是由於較寬的蕭特基臺面結構906能承受較大的擊穿電壓。然而,當蕭特基臺面結構906的寬度過大時,將不再承受很大的擊穿電壓。作為示例,但不作為局限,1.2μm至1.4μm的蕭特基臺面結構寬度可以承受30V的擊穿電壓。對於在1μm間距的帶狀晶胞主晶片中的封閉晶胞蕭特基佈局設計而言,蕭特基臺面結構的寬度應為0.6μm至0.8μm。當蕭特基臺面結構的寬度小於0.6μm或大於0.8μm時,擊穿電壓會下降。蕭特基臺面結構的寬度取決於基底的摻雜濃度。與主動元件的臺面結構寬度有關的蕭特基臺面結構的寬度,是基底的外延摻雜濃度(例如生長在基底上的外延層的摻雜濃度)
在溝槽開口902中沉積或熱生長著一薄層氧化物,佈滿溝
槽底部和溝槽壁(圖中沒有表示出)。在某些實施例中,氧化層的厚度約為200Å。一旦形成了氧化物,就又沉積一層氮化物,並沿水平面回刻。在某些實施例中,氮化層的厚度約為2200Å。全面回刻之後,沿溝槽壁形成氮化物墊片1000,如第10圖所示。
接下來,除去溝槽開口底部的任意裸露的襯裏氧化層,通過全面的矽刻蝕進一步加深第11圖中的終端溝槽1102。所製成的溝槽深度約為1.5μm至2.5μm,溝槽壁的傾斜角約為87-88°。氮化物墊片1000使自對準刻蝕技術不需要額外的對準技術,例如額外的對準遮罩,從而實現了溝槽傾斜刻蝕。由於矽刻蝕負載因素的特性,較寬的溝槽開口製成的溝槽深度大於窄溝槽開口製成的溝槽深度。終端溝槽1102的深度約在1微米至2.5微米之間。通過250Å至500Å的圓孔(R/H)刻蝕,使溝槽的拐角更加圓滑,以避免尖銳的拐角所帶來的高電場。
在第12圖中,沉積或熱生長著一個或多個氧化層1201。
在某些實施例中,可以選擇生長一層500Å左右的犧牲性氧化層,並除去,以改善矽表面。生長一層250Å左右的氧化層,隨後生長一層900Å左右的高溫沉積氧化物(HTO)或熱氧化物。
沉積多晶矽1301如第13圖所示。在某些實施例中,多晶矽的厚度約為12000Å,大於最寬的溝槽寬度的一半。因此,側壁上的多晶矽層合併起來,並且完全填滿所有的溝槽。這層多晶矽有時也稱為源極多晶矽、遮罩多晶矽。
然後,如第14圖所示,利用乾刻蝕,回刻源極多晶矽。在本例中,終端溝槽中剩餘的多晶矽1401的厚度約為6000Å。
然後沉積高密度等離子(HDP)氧化物1501,並增稠。在某些實施例中,增稠大約在高溫1150℃下進行,持續大約30秒。溝槽
側壁上的氧化物在整個MOSFET元件上的厚度(在第15圖中標記為t1)基本一致。在某些實施例中,t1的範圍約從2000Å至4000Å左右,部分填充較寬的溝槽(例如終端溝槽)。因此,較寬的溝槽沒有被完全填滿,使閘極電極在接下來的步驟中,可以沉積在未被這種較寬溝槽中的HDP氧化物1501完全填充的空間中。
然後,進行氧化物化學機械拋光(CMP)。如第16圖所示,利用CMP技術拋光HDP氧化物1501,直到氧化物的頂面與氮化物表面606相平,以此作為刻蝕終點。
第17圖表示沉積一個額外的氧化層1701。在某些實施例中,額外氧化層1701的厚度約為1000Å至2000Å。額外氧化層1701的厚度控制在後續進行的第二遮罩下方的濕刻蝕的切角。氧化物薄膜1701也保護MOSFET元件非主動區中的氮化物606。受保護的氮化物606在稍後的處理技術中,有助於矽基底的無遮罩全面刻蝕。
然後,在該結構的表面上旋塗一層光致抗蝕劑,並使用第二遮罩。第3圖是第二遮罩300的俯視圖。上一個遮罩(溝槽遮罩)的輪廓如圖中虛線所示。第二遮罩300(也稱為多晶矽覆蓋遮罩)的輪廓如圖中虛線所示。使用多晶矽覆蓋遮罩300有助於形成中間-多晶矽區以及終端保護區。多晶矽覆蓋遮罩300的區域302(陰影區)中的PR沒有裸露,被保留下來,從而保護下方區域不受氧化物濕刻蝕的影響。遮罩300的區域,例如圖中304所指之區域(非陰影區)中的PR,裸露出來會被除去。沒有被PR保護的區域將被刻蝕。在開口(例如圖中304所指之區域)中形成主動MOSFET晶胞。正如下文將要詳細介紹的那樣,開口的邊緣靠近終端溝槽(例如圖中306所指之區域和圖中308所指之區域),有利於這些溝槽的非對稱刻蝕。
第18圖表示PR覆層的裸露部分除去後的圖案。PR覆層1801覆蓋了整個蕭特基臺面結構906,在圖中1804及1804’處填充終端溝槽,在圖中1806處延伸到主動區中。正如第19圖’所示,在PR覆層1801下面的部分氧化物將通過刻蝕除去。遮罩覆蓋以及濕或乾刻蝕切口共同決定了最終結構。因此,PR覆層1801在主動區中延伸的距離部分決定了將有多少氧化物被刻蝕除去。氧化物切口的深度約在0.6μm至1.5μm之間。PR覆層1801也保護蕭特基臺面結構906處的氧化物不被刻蝕。
隨後進行濕或乾刻蝕。最終結果如第19圖所示。區域中未被PR覆層1801覆蓋的氧化物被除去,使剩餘的氧化物保持在所需的高度。PR邊緣附近的氧化物也被除去。在第19圖中,終端溝槽1902中的一部分氧化物,位於PR下方以及PR邊緣附近,也被除去。刻蝕掉的氧化物的量可以通過調節PR層邊緣1904的位置來控制。將PR層邊緣1904向靠近主動區的地方延伸,會使更少的氧化物被刻蝕,將邊緣遠離主動區延伸則會有相反的效果。在不同的實施例中,刻蝕掉的氧化物的量有所不同。在本例中,刻蝕掉足夠的氧化物,使溝槽壁內襯的剩餘氧化物在垂直方向上的厚度大致相同。多晶矽1401上方的氧化層1906稱為中間-多晶矽電介質(IPD),其範圍約在幾百隻幾千埃之間。
然後,除去PR,沉積或熱生長一層閘極氧化物。在某些實施例中,增加的氧化層厚度約為450Å。因此,在第20圖中,溝槽壁2002和2004佈滿了氧化物。結構溝槽2006具有不對稱的側壁,側壁2004的氧化物比側壁2002的氧化層更厚。
再一次進行多晶矽沉積和回刻。在第21圖中,在不同的溝槽中沉積大約8000Å至12000Å左右的多晶矽。回刻沉積的多晶矽,
形成閘極多晶矽2102。在本例中,多晶矽表面比氮化物墊片1000底部參考平面大約低500Å至1000Å。沉積一層鈦或鈷的金屬層,並退火。
在金屬與多晶矽相接觸的地方,形成多晶矽層2110。氧化物或氮化物上方的鈦或鈷金屬不會形成矽化物,將被除去。
在第22圖中,終端溝槽中裸露的氮化物墊片通過濕刻蝕技術除去。然而,位於蕭特基臺面結構上的氮化物2200不受濕刻蝕的影響。
在第23圖中,進行本體植入。用摻雜物離子以一定的角度轟擊MOSFET元件。在未被氮化物保護的主動區中,植入形成本體區(例如圖中2304處)。在某些實施例中,利用劑量能級約為1013/cm3,植入能量從60KeV至180KeV左右的硼離子,形成N-通道MOSFET元件。
也可以使用其他類型的離子。例如,用磷離子製備P-通道MOSFET元件。
在第24圖中,用零傾斜角進行源極植入。再次用摻雜物離子轟擊MOSFET元件。在某些實施例中,利用劑量能級為4×1015,植入能量從40KeV至80KeV左右的砷離子。在本體區(例如圖中2304處)中形成源極區(例如圖中2402處)。
植入MOSFET元件的本體和源極不需要額外的遮罩。在蕭特基臺面結構處,氧化物-氮化物-氧化物勢壘阻擋植入離子,防止形成源極和本體區,從而在該區域中繼續植入蕭特基二極體。
在第25圖中,沉積5000Å至8000Å左右的氧化物2500,填充溝槽開口,閉鎖閘極多晶矽2102和多晶矽1401。在某些實施例中,利用化學氣相沉積(CVD)技術,沉積厚度約為5000Å的低溫氧化物(LTO)以及含有硼酸的矽玻璃(BPSG)。
在第26圖中,通過乾刻蝕技術回刻氧化物,向下刻蝕氧化
物,並在主動晶胞矽表面上的終點刻蝕停止。在這個過程中,除去在蕭特基臺面結構處的氮化層上方的氧化層。
進行矽全面刻蝕,刻蝕後如第27圖所示。矽刻蝕的深度取決於第9圖中的溝槽902的初始溝槽刻蝕深度,大約從0.6μm至0.8μm。刻蝕裸露的矽區域,但被氧化物和/或氮化物保護的區域不會被刻蝕。由於刻蝕過程不需要額外的遮罩,因此稱為自對準的接觸技術。
使用另一層PR以及第三遮罩。第4圖表示第三遮罩400的一個示例。第三遮罩400也稱為多晶矽吸引遮罩或接觸遮罩。在本例中,遮罩覆蓋的可選件包括閘極多晶矽吸引接頭(例如圖中402處)、源極多晶矽吸引接頭(例如圖中404處)以及蕭特基接頭(例如圖中408處)。
在第28圖中,除去裸露的PR覆層2800後形成接觸圖案。
接觸開口形成在蕭特基接頭上方,如第28圖所示。
接下來,通過濕或乾刻蝕,除去接觸開口中所形成的裸露的氮化層。此外,接觸開口中裸露的氧化層也被除去,以便形成蕭特基二極體。第29圖表示除去裸露的氮化層和氧化層之後的蕭特基接觸開口2900。
蕭特基二極體可以形成在蕭特基臺面結構的表面上,或者還可選擇形成在蕭特基臺面結構906中的電位井中。第30圖表示在蕭特基臺面結構906的表面上進行矽刻蝕的可選步驟,以製成電位井3000,蕭特基二極體就形成在電位井3000中。必須指出的是,無需該步驟,蕭特基二極體就可以形成在集成結構內。
在製備蕭特基二極體之前,要在蕭特基接觸開口處進行深孔穴植入,使摻雜遮罩區3100形成在電位井3000下方,如第31圖所
示。可以調節摻雜離子的能量和劑量,確保摻雜遮罩區3100形成在電位井3000的裸露表面下方。作為示例,但不作為局限,摻雜遮罩區可以是p-型。摻雜遮罩區3100用於在MOSFET元件開關時抑制反向漏電流。
然後,除去PR。如第32圖所示,沉積勢壘金屬3200(例如Ti和TiN)。在電位井3000的裸露表面上形成蕭特基結。勢壘金屬3200構成蕭特基二極體的陽極,基底602構成蕭特基二極體的陰極。所使用的Ti和TiN的厚度根據MOSFET元件的不同而不同。然後,在勢壘金屬上方沉積鎢。在某些實施例中,沉積大約4000Å至6000Å的鎢。
將沉積的鎢回刻到氧化物表面,形成單獨的鎢插頭3202。鎢插頭3202作為導體,用於接下來沉積源極金屬層和閘極金屬層。
利用第四遮罩製備源極金屬區和閘極金屬區,並且在適當的位置接觸。第5圖表示第四遮罩500的一個示例,該遮罩也稱為金屬遮罩500。陰影區502和504分別對應源極金屬和閘極金屬。非陰影部分對應刻蝕掉的金屬部分,以分離源極金屬區和閘極金屬區。
在第33圖中,沉積金屬層3300。在某些實施例中,利用AlCu製備大約3μm至8μm厚的金屬層。然後,沉積PR覆層3304,並利用金屬遮罩裸露出來。刻蝕掉裸露區域(例如圖中3302處)中的金屬3300。
除去剩餘的PR層,並使金屬3300退火。在某些實施例中,金屬退火是在450℃下進行30分鐘。第34圖表示蕭特基二極體位於兩個終端溝槽之間的最終結構的剖面圖。
儘管上述內容已經對本發明的較佳實施例進行了完整說明,但是仍然可能存在各種可選、修正和等價方案。因此,本發明的範圍不應局限於上述說明,相反地,本發明的範圍應由所附的申請專利範
圍及其全部等效內容決定。任何可選件(無論首選與否),都可與其他任何可選件(無論首選與否)組合。在以下權利要求中,除非特別聲明,否則不定冠詞“一個”或“一種”都指下文內容中的一個或多個專案的數量。任何沒有用“意思是”明確指出限定功能的特定的權利要求,都不應認為局限於意思功能。
150、152、154、156、158、160、162、164‧‧‧流程步驟
Claims (24)
- 一種半導體元件之製備方法,其包含:利用一第一遮罩,在一基板上製備複數個第一溝槽,該些第一溝槽包含位於一主動區中的一主動閘極溝槽,位於含有該主動閘極溝槽的該主動區之外的一終端區中的至少一閘極通道或一終端溝槽以及一屏蔽電極吸引溝槽,該至少一閘極通道或該終端溝槽包含至少一第二溝槽,該至少一第二溝槽限定了位於含有該主動閘極溝槽的該主動區之外的區域中的一臺面結構;在限定該臺面結構的該至少一第二溝槽中,製備一第一導電區;利用一第二遮罩,在限定該臺面結構的該至少一第二溝槽中,製備一中間電介質區以及一終端保護區;在限定該臺面結構的該至少一第二溝槽中,製備一第二導電區;形成到該第二導電區的一第一電性接點,在位於該終端區中的該屏蔽電極吸引溝槽中,形成到該第一導電區的一第二電性接點,並且利用一第三遮罩,在含有該主動閘極溝槽的該主動區外部的區域中,在該終端溝槽之間形成的該臺面結構內,製備至少一蕭特基二極體;以及在至少一終端溝槽中,製備一非對稱的側壁;其中,製備該非對稱的側壁包含切口刻蝕至少部分被該第二遮罩覆蓋的那部分氧化層。
- 如申請專利範圍第1項所述之半導體元件之製備方法,其中更包含下列步驟: 在該半導體元件上沉積一個金屬層;以及利用一第四遮罩,用該金屬層製備一源極金屬區和一閘極金屬區。
- 如申請專利範圍第1項所述之半導體元件之製備方法,其中該非對稱的側壁包括一第一側壁和一第二側壁,該第一側壁具有比該第二側壁更厚的氧化層,該第一側壁更靠近該至少一蕭特基二極體。
- 如申請專利範圍第1項所述之半導體元件之製備方法,其中製備該至少一蕭特基二極體包括在該至少一終端溝槽之間形成的該臺面結構的一裸露表面上,沉積勢壘金屬。
- 如申請專利範圍第4項所述之半導體元件之製備方法,其中,該臺面結構的該裸露表面是該臺面結構中所形成的一電位井的該裸露表面。
- 一種半導體元件之製備方法,其包含:利用一第一遮罩,在一基板上製備複數個第一溝槽,該些第一溝槽包含位於一主動區中的一主動閘極溝槽,位於含有該主動閘極溝槽的該主動區之外的一終端區中的至少一閘極通道或一終端溝槽以及一屏蔽電極吸引溝槽,該至少一閘極通道或該終端溝槽包含至少一第二溝槽,該至少一第二溝槽限定了位於含有該主動閘極溝槽的該主動區之外的區域中的一臺面結構;在限定該臺面結構的該至少一第二溝槽中,製備一第一導電區; 利用一第二遮罩,在限定該臺面結構的該至少一第二溝槽中,製備一中間電介質區以及一終端保護區;在限定該臺面結構的該至少一第二溝槽中,製備一第二導電區;以及形成到該第二導電區的一第一電性接點,在位於該終端區中的該屏蔽電極吸引溝槽中,形成到該第一導電區的一第二電性接點,並且利用一第三遮罩,在含有該主動閘極溝槽的該主動區外部的區域中,在該終端溝槽之間形成的該臺面結構內,製備至少一蕭特基二極體;其中製備該蕭特基二極體包括進行一深孔穴植入,以便在該至少一蕭特基二極體有關的一蕭特基結下方,形成一摻雜遮罩區。
- 如申請專利範圍第6項所述之半導體元件之製備方法,其中更包含下列步驟:在該半導體元件上沉積一個金屬層;以及利用一第四遮罩,用該金屬層製備一源極金屬區和一閘極金屬區。
- 如申請專利範圍第6項所述之半導體元件之製備方法,其中更包含下列步驟:在至少一終端溝槽中,製備一非對稱的側壁。
- 如申請專利範圍第8項所述之半導體元件之製備方法,其中製備該非對稱的側壁包含切口刻蝕至少部分被該第二遮罩覆蓋的那部分氧化層。
- 如申請專利範圍第9項所述之半導體元件之製備方法,其 中該非對稱的側壁包括一第一側壁和一第二側壁,該第一側壁具有比該第二側壁更厚的氧化層,該第一側壁更靠近該蕭特基二極體。
- 如申請專利範圍第6項所述之半導體元件之製備方法,其中製備該蕭特基二極體包括在該至少一終端溝槽之間形成的該臺面結構的一裸露表面上,沉積勢壘金屬。
- 如申請專利範圍第11項所述之半導體元件之製備方法,其中,該臺面結構的該裸露表面是該臺面結構中所形成的一電位井的該裸露表面。
- 一種半導體元件,包括:一基板上的複數個第一溝槽,其包括位於一主動區中的至少一主動閘極溝槽,以及位於含有該主動閘極溝槽的該主動區外部的一終端區中的至少一閘極通道或至少一終端溝槽以及一遮罩閘極吸引溝槽,該至少一閘極通道或終端溝槽包括至少一第二溝槽,該至少一第二溝槽限定了位於含有該主動閘極溝槽的該主動區之外的區域中的該臺面結構;形成於該至少一第二溝槽中的一第一導電區;形成於限定該臺面結構的該至少一第二溝槽的至少一部分中的一中間電介質區以及一終端保護區;形成於限定該臺面結構的該至少一第二溝槽的至少一部分中的一第二導電區,其中,該第二導電區通過該中間電介質區,與該第一導電區電絕緣;以及到該第二導電區的一第一電性接點,在位於該終端區中的一屏蔽電極吸引溝槽中,到該第一導電區的該第二電性 接點,以及在該臺面結構內,形成的該至少一蕭特基二極體;其中,該至少一蕭特基二極體位於主動元件的一第一鄰近組和一第二鄰近組之間的一封閉晶胞結構中。
- 如申請專利範圍第13項所述之半導體元件,其中該半導體元件還包括連接到該第一電性接點的一閘極金屬區,以及連接到該第二電性接點的一源極金屬區,其中該閘極金屬區域與該源極金屬區電絕緣。
- 如申請專利範圍第13項所述之半導體元件,其中,該至少一蕭特基二極體包括位於該臺面結構的一裸露表面上的一勢壘金屬。
- 如申請專利範圍第15項所述之半導體元件,其中該臺面結構的該裸露表面是在該臺面結構中所形成的一電位井的該裸露表面。
- 如申請專利範圍第13項所述之半導體元件,其中該至少一蕭特基二極體包括深孔穴植入,以便在該至少一蕭特基二極體有關的一蕭特基結下方,形成一摻雜遮罩區。
- 如申請專利範圍第13項所述之半導體元件,其中該至少一蕭特基二極體形成在比該主動元件的該臺面結構更寬的該蕭特基蕭特基之該臺面結構上,至少一該主動元件就形成在該主動元件該臺面結構上。
- 一種半導體元件,包括:一基板上的複數個第一溝槽,其包括位於一主動區中的至少一主動閘極溝槽,以及位於含有該主動閘極溝槽的該 主動區外部的一終端區中的至少一閘極通道或至少一終端溝槽以及一遮罩閘極吸引溝槽,該閘極通道或終端溝槽包括至少一第二溝槽,該至少一第二溝槽限定了位於含有該主動閘極溝槽的該主動區之外的區域中的該臺面結構;形成於該至少一第二溝槽中的一第一導電區;形成於限定該臺面結構的該至少一第二溝槽的至少一部分中的一中間電介質區以及一終端保護區;形成於限定該臺面結構的該至少一第二溝槽的至少一部分中的一第二導電區,其中,該第二導電區通過該中間電介質區,與該第一導電區電絕緣;以及到該第二導電區的一第一電性接點,在位於該終端區中的一屏蔽電極吸引溝槽中,到該第一導電區的該第二電性接點,以及在該臺面結構內,形成的至少一蕭特基二極體;其中,該至少一蕭特基二極體位於該主動元件的一第一鄰近組和一第二鄰近組之間的一帶狀晶胞結構中。
- 如申請專利範圍第19項所述之半導體元件,其中該半導體元件還包括連接到該第一電性接點的一閘極金屬區,以及連接到該第二電性接點的一源極金屬區,其中該閘極金屬區域與該源極金屬區電絕緣。
- 如申請專利範圍第19項所述之半導體元件,其中,該蕭特基二極體包括位於該臺面結構的一裸露表面上的一勢壘金屬。
- 如申請專利範圍第21項所述之半導體元件,其中該臺面結 構的該裸露表面是在該臺面結構中所形成的一電位井的該裸露表面。
- 如申請專利範圍第19項所述之半導體元件,其中該至少一蕭特基二極體包括深孔穴植入,以便在該至少一蕭特基二極體有關的該蕭特基結下方,形成一摻雜遮罩區。
- 如申請專利範圍第19項所述之半導體元件,其中該至少一蕭特基二極體形成在比該主動元件的該臺面結構更寬的該蕭特基二極體之該臺面結構上,至少一該主動元件就形成在該主動元件該臺面結構上。
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Families Citing this family (33)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8431457B2 (en) * | 2010-03-11 | 2013-04-30 | Alpha And Omega Semiconductor Incorporated | Method for fabricating a shielded gate trench MOS with improved source pickup layout |
US8580667B2 (en) * | 2010-12-14 | 2013-11-12 | Alpha And Omega Semiconductor Incorporated | Self aligned trench MOSFET with integrated diode |
JP5738653B2 (ja) * | 2011-03-31 | 2015-06-24 | セミコンダクター・コンポーネンツ・インダストリーズ・リミテッド・ライアビリティ・カンパニー | 絶縁ゲート型半導体装置 |
US8502302B2 (en) * | 2011-05-02 | 2013-08-06 | Alpha And Omega Semiconductor Incorporated | Integrating Schottky diode into power MOSFET |
WO2012158977A2 (en) | 2011-05-18 | 2012-11-22 | Vishay-Siliconix | Semiconductor device |
US8610235B2 (en) * | 2011-09-22 | 2013-12-17 | Alpha And Omega Semiconductor Incorporated | Trench MOSFET with integrated Schottky barrier diode |
CN103021867B (zh) * | 2012-12-21 | 2016-11-16 | 上海华虹宏力半导体制造有限公司 | 沟槽型金属-氧化物-半导体势垒肖特基器件的形成方法 |
CN103151270A (zh) * | 2013-02-26 | 2013-06-12 | 上海宏力半导体制造有限公司 | 沟槽式金属氧化物半导体肖特基势垒器件制造方法 |
US9230957B2 (en) | 2013-03-11 | 2016-01-05 | Alpha And Omega Semiconductor Incorporated | Integrated snubber in a single poly MOSFET |
CN103346087B (zh) * | 2013-06-03 | 2017-02-08 | 上海华虹宏力半导体制造有限公司 | 沟槽式金属氧化物半导体肖特基势垒器件的制造方法 |
JP6135364B2 (ja) * | 2013-07-26 | 2017-05-31 | 住友電気工業株式会社 | 炭化珪素半導体装置およびその製造方法 |
KR102046663B1 (ko) * | 2013-11-04 | 2019-11-20 | 매그나칩 반도체 유한회사 | 반도체 소자 및 그 제조방법 |
US9773902B2 (en) * | 2013-11-25 | 2017-09-26 | Vanguard International Semiconductor Corporation | Trench-gate semiconductor device and method for forming the same |
CN104674162B (zh) | 2015-01-29 | 2018-06-12 | 京东方科技集团股份有限公司 | 一种掩膜板、oled器件封装方法及oled器件 |
US9583482B2 (en) * | 2015-02-11 | 2017-02-28 | Monolith Semiconductor Inc. | High voltage semiconductor devices and methods of making the devices |
DE102016101545B4 (de) | 2016-01-28 | 2020-10-08 | Infineon Technologies Dresden Gmbh | Verfahren zum herstellen einer halbleitervorrichtung mit silicidschichten und eine halbleitervorrichtung |
US10056461B2 (en) | 2016-09-30 | 2018-08-21 | Alpha And Omega Semiconductor Incorporated | Composite masking self-aligned trench MOSFET |
CN108257869A (zh) * | 2016-12-28 | 2018-07-06 | 中航(重庆)微电子有限公司 | 屏蔽栅沟槽mosfet的制备方法 |
US10211333B2 (en) | 2017-04-26 | 2019-02-19 | Alpha And Omega Semiconductor (Cayman) Ltd. | Scalable SGT structure with improved FOM |
US10325908B2 (en) | 2017-04-26 | 2019-06-18 | Alpha And Omega Semiconductor Incorporated | Compact source ballast trench MOSFET and method of manufacturing |
US10818788B2 (en) | 2017-12-15 | 2020-10-27 | Alpha And Omega Semiconductor (Cayman) Ltd. | Schottky diode integrated into superjunction power MOSFETs |
US10714580B2 (en) | 2018-02-07 | 2020-07-14 | Alpha And Omega Semiconductor (Cayman) Ltd. | Source ballasting for p-channel trench MOSFET |
CN108417487A (zh) * | 2018-02-07 | 2018-08-17 | 上海华虹宏力半导体制造有限公司 | 沟槽型屏蔽栅功率器件的工艺方法 |
US10600905B1 (en) * | 2018-09-11 | 2020-03-24 | Semiconductor Components Industries, Llc | Trench MOSFET contacts |
CN109904152A (zh) * | 2019-01-24 | 2019-06-18 | 江苏东海半导体科技有限公司 | 集成肖特基二极管的沟槽mosfet的制备方法 |
US11588037B2 (en) * | 2019-03-01 | 2023-02-21 | Intel Corporation | Planar transistors with wrap-around gates and wrap-around source and drain contacts |
CN111048408B (zh) * | 2020-01-03 | 2022-05-31 | 苏州锴威特半导体股份有限公司 | 一种集成肖特基二极管的短沟道碳化硅mosfet器件及其制造方法 |
CN112614883A (zh) * | 2020-12-16 | 2021-04-06 | 西安电子科技大学 | 基于横向肖特基隧穿发射结的半导体垂直igbt及制备方法 |
CN113299767B (zh) * | 2021-05-21 | 2022-04-08 | 江苏东海半导体股份有限公司 | 一种沟槽型肖特基器件及其制造方法 |
CN113270321A (zh) * | 2021-07-01 | 2021-08-17 | 安建科技(深圳)有限公司 | 一种高密度屏蔽栅沟槽型场效应管器件的制造方法 |
CN113823698B (zh) * | 2021-08-30 | 2024-04-16 | 瑶芯微电子科技(上海)有限公司 | 一种SiC肖特基功率二极管及其制备方法 |
US20230084411A1 (en) * | 2021-09-14 | 2023-03-16 | Analog Power Conversion LLC | Schottky diode integrated with a semiconductor device |
CN114334621B (zh) * | 2022-01-04 | 2023-08-11 | 广东芯粤能半导体有限公司 | 半导体结构、半导体器件及其制备方法 |
Family Cites Families (56)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB2151844A (en) * | 1983-12-20 | 1985-07-24 | Philips Electronic Associated | Semiconductor devices |
US6509233B2 (en) | 2000-10-13 | 2003-01-21 | Siliconix Incorporated | Method of making trench-gated MOSFET having cesium gate oxide layer |
US7045859B2 (en) * | 2001-09-05 | 2006-05-16 | International Rectifier Corporation | Trench fet with self aligned source and contact |
US6838722B2 (en) | 2002-03-22 | 2005-01-04 | Siliconix Incorporated | Structures of and methods of fabricating trench-gated MIS devices |
US6987305B2 (en) * | 2003-08-04 | 2006-01-17 | International Rectifier Corporation | Integrated FET and schottky device |
US7049652B2 (en) * | 2003-12-10 | 2006-05-23 | Sandisk Corporation | Pillar cell flash memory technology |
US7667264B2 (en) | 2004-09-27 | 2010-02-23 | Alpha And Omega Semiconductor Limited | Shallow source MOSFET |
US7371641B2 (en) * | 2004-10-29 | 2008-05-13 | International Rectifier Corporation | Method of making a trench MOSFET with deposited oxide |
US20060108635A1 (en) | 2004-11-23 | 2006-05-25 | Alpha Omega Semiconductor Limited | Trenched MOSFETS with part of the device formed on a (110) crystal plane |
US7671439B2 (en) | 2005-02-11 | 2010-03-02 | Alpha & Omega Semiconductor, Ltd. | Junction barrier Schottky (JBS) with floating islands |
US7436022B2 (en) | 2005-02-11 | 2008-10-14 | Alpha & Omega Semiconductors, Ltd. | Enhancing Schottky breakdown voltage (BV) without affecting an integrated MOSFET-Schottky device layout |
US7952139B2 (en) * | 2005-02-11 | 2011-05-31 | Alpha & Omega Semiconductor Ltd. | Enhancing Schottky breakdown voltage (BV) without affecting an integrated MOSFET-Schottky device layout |
US7737522B2 (en) | 2005-02-11 | 2010-06-15 | Alpha & Omega Semiconductor, Ltd. | Trench junction barrier controlled Schottky device with top and bottom doped regions for enhancing forward current in a vertical direction |
US7285822B2 (en) | 2005-02-11 | 2007-10-23 | Alpha & Omega Semiconductor, Inc. | Power MOS device |
US7948029B2 (en) | 2005-02-11 | 2011-05-24 | Alpha And Omega Semiconductor Incorporated | MOS device with varying trench depth |
US7453119B2 (en) | 2005-02-11 | 2008-11-18 | Alphs & Omega Semiconductor, Ltd. | Shielded gate trench (SGT) MOSFET cells implemented with a schottky source contact |
US7786531B2 (en) | 2005-03-18 | 2010-08-31 | Alpha & Omega Semiconductor Ltd. | MOSFET with a second poly and an inter-poly dielectric layer over gate for synchronous rectification |
CN101185169B (zh) * | 2005-04-06 | 2010-08-18 | 飞兆半导体公司 | 沟栅场效应晶体管及其形成方法 |
US7659570B2 (en) | 2005-05-09 | 2010-02-09 | Alpha & Omega Semiconductor Ltd. | Power MOSFET device structure for high frequency applications |
JP2008546189A (ja) * | 2005-05-26 | 2008-12-18 | フェアチャイルド・セミコンダクター・コーポレーション | トレンチゲート電界効果トランジスタ及びその製造方法 |
US7449354B2 (en) * | 2006-01-05 | 2008-11-11 | Fairchild Semiconductor Corporation | Trench-gated FET for power device with active gate trenches and gate runner trench utilizing one-mask etch |
US8193580B2 (en) | 2009-08-14 | 2012-06-05 | Alpha And Omega Semiconductor, Inc. | Shielded gate trench MOSFET device and fabrication |
US8236651B2 (en) | 2009-08-14 | 2012-08-07 | Alpha And Omega Semiconductor Incorporated | Shielded gate trench MOSFET device and fabrication |
US7633119B2 (en) | 2006-02-17 | 2009-12-15 | Alpha & Omega Semiconductor, Ltd | Shielded gate trench (SGT) MOSFET devices and manufacturing processes |
US7446374B2 (en) * | 2006-03-24 | 2008-11-04 | Fairchild Semiconductor Corporation | High density trench FET with integrated Schottky diode and method of manufacture |
US7504676B2 (en) | 2006-05-31 | 2009-03-17 | Alpha & Omega Semiconductor, Ltd. | Planar split-gate high-performance MOSFET structure and manufacturing method |
US7750447B2 (en) | 2007-06-11 | 2010-07-06 | Alpha & Omega Semiconductor, Ltd | High voltage and high power boost converter with co-packaged Schottky diode |
US7564099B2 (en) * | 2007-03-12 | 2009-07-21 | International Rectifier Corporation | Monolithic MOSFET and Schottky diode device |
US8035159B2 (en) | 2007-04-30 | 2011-10-11 | Alpha & Omega Semiconductor, Ltd. | Device structure and manufacturing method using HDP deposited source-body implant block |
US7994005B2 (en) | 2007-11-01 | 2011-08-09 | Alpha & Omega Semiconductor, Ltd | High-mobility trench MOSFETs |
US7825431B2 (en) | 2007-12-31 | 2010-11-02 | Alpha & Omega Semicondictor, Ltd. | Reduced mask configuration for power MOSFETs with electrostatic discharge (ESD) circuit protection |
US20090242973A1 (en) | 2008-03-31 | 2009-10-01 | Alpha & Omega Semiconductor, Ltd. | Source and body contact structure for trench-dmos devices using polysilicon |
US7799646B2 (en) | 2008-04-07 | 2010-09-21 | Alpha & Omega Semiconductor, Ltd | Integration of a sense FET into a discrete power MOSFET |
US7939882B2 (en) | 2008-04-07 | 2011-05-10 | Alpha And Omega Semiconductor Incorporated | Integration of sense FET into discrete power MOSFET |
US7626231B1 (en) * | 2008-06-23 | 2009-12-01 | Force Mos Technology Co., Ltd. | Integrated trench MOSFET and junction barrier schottky rectifier with trench contact structures |
US7867852B2 (en) | 2008-08-08 | 2011-01-11 | Alpha And Omega Semiconductor Incorporated | Super-self-aligned trench-dmos structure and method |
US8174067B2 (en) * | 2008-12-08 | 2012-05-08 | Fairchild Semiconductor Corporation | Trench-based power semiconductor devices with increased breakdown voltage characteristics |
US8362552B2 (en) | 2008-12-23 | 2013-01-29 | Alpha And Omega Semiconductor Incorporated | MOSFET device with reduced breakdown voltage |
US7851856B2 (en) | 2008-12-29 | 2010-12-14 | Alpha & Omega Semiconductor, Ltd | True CSP power MOSFET based on bottom-source LDMOS |
US7767526B1 (en) | 2009-01-29 | 2010-08-03 | Alpha & Omega Semiconductor Incorporated | High density trench MOSFET with single mask pre-defined gate and contact trenches |
US7829947B2 (en) | 2009-03-17 | 2010-11-09 | Alpha & Omega Semiconductor Incorporated | Bottom-drain LDMOS power MOSFET structure having a top drain strap |
US8252647B2 (en) | 2009-08-31 | 2012-08-28 | Alpha & Omega Semiconductor Incorporated | Fabrication of trench DMOS device having thick bottom shielding oxide |
US8829614B2 (en) | 2009-08-31 | 2014-09-09 | Alpha And Omega Semiconductor Incorporated | Integrated Schottky diode in high voltage semiconductor device |
US8187939B2 (en) | 2009-09-23 | 2012-05-29 | Alpha & Omega Semiconductor Incorporated | Direct contact in trench with three-mask shield gate process |
US8324053B2 (en) | 2009-09-30 | 2012-12-04 | Alpha And Omega Semiconductor, Inc. | High voltage MOSFET diode reverse recovery by minimizing P-body charges |
US8138605B2 (en) | 2009-10-26 | 2012-03-20 | Alpha & Omega Semiconductor, Inc. | Multiple layer barrier metal for device component formed in contact trench |
US8466510B2 (en) | 2009-10-30 | 2013-06-18 | Alpha And Omega Semiconductor Incorporated | Staggered column superjunction |
US8519476B2 (en) | 2009-12-21 | 2013-08-27 | Alpha And Omega Semiconductor Incorporated | Method of forming a self-aligned charge balanced power DMOS |
US8431457B2 (en) | 2010-03-11 | 2013-04-30 | Alpha And Omega Semiconductor Incorporated | Method for fabricating a shielded gate trench MOS with improved source pickup layout |
US8394702B2 (en) | 2010-03-24 | 2013-03-12 | Alpha And Omega Semiconductor Incorporated | Method for making dual gate oxide trench MOSFET with channel stop using three or four masks process |
US8367501B2 (en) | 2010-03-24 | 2013-02-05 | Alpha & Omega Semiconductor, Inc. | Oxide terminated trench MOSFET with three or four masks |
US8252648B2 (en) | 2010-06-29 | 2012-08-28 | Alpha & Omega Semiconductor, Inc. | Power MOSFET device with self-aligned integrated Schottky and its manufacturing method |
US8580667B2 (en) | 2010-12-14 | 2013-11-12 | Alpha And Omega Semiconductor Incorporated | Self aligned trench MOSFET with integrated diode |
US8476676B2 (en) | 2011-01-20 | 2013-07-02 | Alpha And Omega Semiconductor Incorporated | Trench poly ESD formation for trench MOS and SGT |
US8431470B2 (en) | 2011-04-04 | 2013-04-30 | Alpha And Omega Semiconductor Incorporated | Approach to integrate Schottky in MOSFET |
US8502302B2 (en) * | 2011-05-02 | 2013-08-06 | Alpha And Omega Semiconductor Incorporated | Integrating Schottky diode into power MOSFET |
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2011
- 2011-05-02 US US13/098,852 patent/US8502302B2/en active Active
-
2012
- 2012-04-23 CN CN201210138850.9A patent/CN102768994B/zh active Active
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CN102768994A (zh) | 2012-11-07 |
US8502302B2 (en) | 2013-08-06 |
US8785270B2 (en) | 2014-07-22 |
US9356132B2 (en) | 2016-05-31 |
US20130309823A1 (en) | 2013-11-21 |
CN102768994B (zh) | 2015-03-25 |
US20160005853A1 (en) | 2016-01-07 |
TW201246390A (en) | 2012-11-16 |
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