JP2016502270A - 改善されたトレンチ保護を有するトレンチベースデバイス - Google Patents
改善されたトレンチ保護を有するトレンチベースデバイス Download PDFInfo
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- 239000000758 substrate Substances 0.000 claims abstract description 35
- 239000004065 semiconductor Substances 0.000 claims abstract description 33
- 239000002184 metal Substances 0.000 claims abstract description 27
- 229910052751 metal Inorganic materials 0.000 claims abstract description 27
- 239000004020 conductor Substances 0.000 claims abstract description 12
- 238000000034 method Methods 0.000 claims description 24
- 239000002019 doping agent Substances 0.000 claims description 13
- 238000005530 etching Methods 0.000 claims description 3
- 238000004519 manufacturing process Methods 0.000 claims description 3
- 230000005684 electric field Effects 0.000 description 18
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 6
- 229920005591 polysilicon Polymers 0.000 description 6
- 229910021332 silicide Inorganic materials 0.000 description 6
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 6
- 230000004888 barrier function Effects 0.000 description 5
- 230000015556 catabolic process Effects 0.000 description 5
- 238000002513 implantation Methods 0.000 description 4
- 238000002347 injection Methods 0.000 description 4
- 239000007924 injection Substances 0.000 description 4
- 230000003647 oxidation Effects 0.000 description 4
- 238000007254 oxidation reaction Methods 0.000 description 4
- 229910021417 amorphous silicon Inorganic materials 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- 230000008021 deposition Effects 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000000969 carrier Substances 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 230000007774 longterm Effects 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 230000000116 mitigating effect Effects 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 230000036470 plasma concentration Effects 0.000 description 1
- 238000011084 recovery Methods 0.000 description 1
- 238000001953 recrystallisation Methods 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 230000005641 tunneling Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/872—Schottky diodes
- H01L29/8725—Schottky diodes of the trench MOS barrier type [TMBS]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
- H01L29/0623—Buried supplementary region, e.g. buried guard ring
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
- H01L29/6606—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/6609—Diodes
- H01L29/66143—Schottky diodes
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- General Physics & Mathematics (AREA)
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Abstract
Description
(1)p−濃度:1×1013cm−3〜5×1018cm−3
(2)p−深さ:0.05μm〜10μm
(3)トレンチ深さ:0.5μm〜10.0μm
(4)トレンチ幅:0.5μm〜5.0μm
(5)メサ幅(すなわち、隣接するトレンチの間の間隔):0.3μm〜30.0μm
(6)N−ドリフト領域長さ:5μm〜200μm
(7)N−ドリフト領域濃度:5×1012cm−3〜5×1017cm−3
Claims (16)
- 半導体デバイスであって:
第1導電型を有する半導体基板と;
前記第1導電型を有する前記基板上に形成され、前記基板よりも低濃度でドープされた第1層と;
前記第1層内に形成された、少なくとも1つのトレンチと;
前記少なくとも1つのトレンチの底面及び側壁を被覆する誘電層と;
前記少なくとも1つのトレンチを充填する導電性材料と;
第2導電型を有する、前記第1層内に形成された低濃度でドープした領域であって、前記低濃度でドープした領域は、前記トレンチの前記底面の下に配置される、低濃度でドープした領域と;
前記第1層及び前記導電性材料の上に配置された金属層と;
前記金属層上に形成された第1電極、及び前記基板の裏側に形成された第2電極とを含む、半導体デバイス。 - 前記低濃度でドープした領域は、前記トレンチの前記底部から延びる、請求項1に記載の半導体デバイス。
- 前記低濃度でドープした領域が、前記トレンチの前記底部を包囲し、前記トレンチの前記底部と隣接する前記側壁の一部と接触する、請求項2に記載の半導体デバイス。
- 前記第1層及び前記金属層が、その間にショットキー接触を形成する、請求項1に記載の半導体デバイス。
- 前記基板上に形成され、第2導電型を有する第2層を更に含み、前記第2層は前記トレンチの少なくとも一方の側に隣接するように位置し、前記金属層と前記第2層との間にショットキー接触が形成されるように、低濃度でドープされている、請求項1に記載の半導体デバイス。
- 前記第2層が、前記第1層内に形成されている、請求項5に記載の半導体デバイス。
- 前記第2層が、前記トレンチの両側に隣接している、請求項6に記載の半導体デバイス。
- 前記第2層が、前記金属層と前記第2層との間にオーミック接触を形成するために必要とされるよりも低いドープ濃度を有する、請求項5に記載の半導体デバイス。
- 半導体デバイスを製造する方法であって:
第1導電型を有する半導体基板をもたらす工程と;
前記基板上に第1層を形成する工程であって、前記第1層は前記第1導電型を有し、前記基板より低濃度でドープされている、工程と;
前記第1層中に少なくとも1つのトレンチを形成する工程と;
前記少なくとも1つのトレンチの底面及び側壁を、誘電層で被覆する工程と;
前記トレンチの前記底面の前記誘電層をエッチバックする工程と;
第2導電型のドーパントを、前記トレンチの前記底面を通じて、前記第1層に注入する工程と;
前記少なくとも1つのトレンチを、導電性材料で充填する工程と;
前記第1層、及び前記導電性材料の上に金属層を形成する工程と;
前記金属層上に第1電極を、前記基板の裏側に第2電極を形成する工程とを含む、方法。 - 少なくとも前記誘電層をマスクとして使用して、前記第2導電型の前記ドーパントを前記第1層内に注入する工程を更に含む、請求項9に記載の方法。
- 前記第1層及び前記金属層が、その間にショットキー接触を形成する、請求項9に記載の方法。
- 前記基板上に、第2導電型を有する第2層を形成する工程を更に含み、前記第2層は前記トレンチの少なくとも一方の側に隣接するように位置し、前記金属層と前記第2層との間にショットキー接触が形成されるように、低濃度でドープされている、請求項9に記載の方法。
- 半導体デバイスであって:
第1導電型を有する半導体基板と;
前記第1導電型を有する前記基板上に形成され、前記基板よりも低濃度でドープされた第1層と;
前記第1層内に形成された、少なくとも1つのトレンチと;
前記少なくとも1つのトレンチの底面及び側壁を被覆する誘電層と;
前記少なくとも1つのトレンチを充填する導電性材料と;
第2導電型を有する、前記第1層内に形成された低濃度でドープした領域であって、前記低濃度でドープした領域は、前記トレンチの前記底面の下に配置される、低濃度でドープした領域と;
接合層であって、前記第1層、及び前記導電性材料の上に配置され、前記接合層と前記第1層との間に接合が画定される、接合層とを含む、半導体デバイス。 - 前記接合は、ショットキー接合である、請求項13に記載の半導体デバイス。
- 前記低濃度でドープした領域は、前記トレンチの前記底部から延びる、請求項13に記載の半導体デバイス。
- 前記低濃度でドープした領域が、前記トレンチの前記底部を包囲し、前記トレンチの前記底部と隣接する前記側壁の一部と接触する、請求項14に記載の半導体デバイス。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
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US13/678,571 | 2012-11-16 | ||
US13/678,571 US9018698B2 (en) | 2012-11-16 | 2012-11-16 | Trench-based device with improved trench protection |
PCT/US2012/071616 WO2014077861A1 (en) | 2012-11-16 | 2012-12-26 | Trench-based device with improved trench protection |
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JP2016502270A true JP2016502270A (ja) | 2016-01-21 |
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JP2015543023A Pending JP2016502270A (ja) | 2012-11-16 | 2012-12-26 | 改善されたトレンチ保護を有するトレンチベースデバイス |
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Country | Link |
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US (1) | US9018698B2 (ja) |
EP (1) | EP2920816B1 (ja) |
JP (1) | JP2016502270A (ja) |
KR (2) | KR20150084854A (ja) |
CN (1) | CN104981909A (ja) |
TW (1) | TWI517415B (ja) |
WO (1) | WO2014077861A1 (ja) |
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KR102249592B1 (ko) * | 2015-12-02 | 2021-05-07 | 현대자동차 주식회사 | 쇼트키 배리어 다이오드 및 그 제조 방법 |
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JPWO2020203650A1 (ja) * | 2019-03-29 | 2020-10-08 | ||
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2012
- 2012-11-16 US US13/678,571 patent/US9018698B2/en active Active
- 2012-12-26 JP JP2015543023A patent/JP2016502270A/ja active Pending
- 2012-12-26 KR KR1020157012794A patent/KR20150084854A/ko active Search and Examination
- 2012-12-26 WO PCT/US2012/071616 patent/WO2014077861A1/en active Application Filing
- 2012-12-26 CN CN201280077111.1A patent/CN104981909A/zh active Pending
- 2012-12-26 EP EP12888321.2A patent/EP2920816B1/en active Active
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Patent Citations (3)
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JP2003506903A (ja) * | 1999-08-10 | 2003-02-18 | イノベイティブ・テクノロジー・ライセンシング・エルエルシー | ハイパワー整流器 |
US20120181652A1 (en) * | 2009-08-05 | 2012-07-19 | Ning Qu | Semiconductor system and method for manufacturing same |
WO2012054682A2 (en) * | 2010-10-21 | 2012-04-26 | Vishay General Semiconductor Llc | Improved schottky rectifier |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
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JP2021120989A (ja) * | 2020-01-30 | 2021-08-19 | 株式会社豊田中央研究所 | ダイオード |
JP7479157B2 (ja) | 2020-01-30 | 2024-05-08 | 株式会社豊田中央研究所 | ダイオード |
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KR20190136095A (ko) | 2019-12-09 |
EP2920816B1 (en) | 2020-03-11 |
EP2920816A4 (en) | 2016-11-30 |
KR20150084854A (ko) | 2015-07-22 |
US9018698B2 (en) | 2015-04-28 |
TW201421705A (zh) | 2014-06-01 |
TWI517415B (zh) | 2016-01-11 |
CN104981909A (zh) | 2015-10-14 |
US20140138764A1 (en) | 2014-05-22 |
EP2920816A1 (en) | 2015-09-23 |
WO2014077861A1 (en) | 2014-05-22 |
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