TWI528377B

TWI528377B - Memory circuit and the refresh method thereof

Info

Publication number: TWI528377B
Application number: TW103124883A
Authority: TW
Inventors: 張昆輝
Original assignee: 華邦電子股份有限公司
Priority date: 2014-07-21
Filing date: 2014-07-21
Publication date: 2016-04-01
Also published as: TW201604890A

Description

記憶體電路及其刷新方法 Memory circuit and refresh method thereof

本發明係有關於記憶體電路，特別是有關於記憶體電路之刷新方法以及應用此刷新方法之記憶體電路。 The present invention relates to a memory circuit, and more particularly to a method of refreshing a memory circuit and a memory circuit to which the refresh method is applied.

由於半導體製程微縮，記憶體產品中字元線與字元線間的互相干擾日益嚴重。在記憶體產品中，當某一記憶區塊中的複數字元線在經過連續存取之後，與該複數字元線相鄰的複數字元線會因此被干擾而造成該等相鄰字元線中的資料遺失(cell leak)。有鑑於此，本發明提出一種記憶體電路及其刷新方法來解決上述問題。 Due to the shrinking of the semiconductor process, mutual interference between word lines and word lines in memory products is increasingly serious. In a memory product, when a complex digital element line in a memory block is continuously accessed, a complex digital element line adjacent to the complex digital element line is thereby disturbed to cause the adjacent character element. The data in the line is missing. In view of this, the present invention proposes a memory circuit and a refresh method thereof to solve the above problems.

本發明之一實施例提供一種記憶體電路。該記憶體電路包括一記憶體陣列以及一記憶體控制器。該記憶體陣列具有複數記憶體區塊，其中每一該記憶體區塊對應設置複數字元線。該記憶體控制器輸出一存取指令以定址該等字元線而存取該記憶體陣列。該記憶體控制器每當輸出一刷新指令，則在一刷新週期中循序地對每一該等記憶體區塊進行刷新操作。其中於該刷新週期，該記憶體控制器於至少一第一時間點，中斷該刷新操作而對該等記憶體區塊中之一第一記憶體區塊進行一強制刷新操作，之後再回復該刷新操作；或是其中該記憶體控制器每隔一特定時間，從該等記憶體區塊中找出於該特定時間內被存取次數最多之一第二記憶體區塊，以進行該強制刷新操作。 One embodiment of the present invention provides a memory circuit. The memory circuit includes a memory array and a memory controller. The memory array has a plurality of memory blocks, wherein each of the memory blocks corresponds to a complex digital element line. The memory controller outputs an access command to address the word lines to access the memory array. Each time the memory controller outputs a refresh command, each of the memory blocks is sequentially refreshed in a refresh cycle. During the refresh cycle, the memory controller interrupts the refresh operation at at least a first time point to perform a forced refresh operation on one of the first memory blocks in the memory blocks, and then restores the a refresh operation; or wherein the memory controller finds the specific time from the memory blocks at a specific time The second memory block is accessed the most in the interval to perform the forced refresh operation.

本發明之一實施例一種記憶體電路刷新方法。該記憶體電路刷新方法用以刷新一記憶體陣列中之複數記憶體區塊。該記憶體電路刷新方法包括輸出一存取指令以定址該等字元線而存取該記憶體陣列；每當該記憶體控制器輸出一刷新指令，則在一刷新週期中循序地對每一該等記憶體區塊進行刷新操作；以及於該刷新週期，該記憶體控制器於至少一第一時間點，中斷該刷新操作而對該等記憶體區塊中之一第一記憶體區塊進行一強制刷新操作，之後再回復該刷新操作；或是在每隔一特定時間，該記憶體控制器從該等記憶體區塊中找出於該特定時間內被存取次數最多之一第二記憶體區塊，以進行該強制刷新操作。 One embodiment of the present invention is a memory circuit refresh method. The memory circuit refresh method is used to refresh a plurality of memory blocks in a memory array. The memory circuit refresh method includes outputting an access command to address the word lines to access the memory array; each time the memory controller outputs a refresh command, each of the refresh cycles sequentially The memory block performs a refresh operation; and during the refresh cycle, the memory controller interrupts the refresh operation and at least one of the first memory blocks in the memory block at at least a first time point Performing a forced refresh operation, and then replying to the refresh operation; or at every certain time, the memory controller finds from the memory blocks that the number of accesses is the highest in the specific time. Two memory blocks to perform the forced refresh operation.

10‧‧‧記憶體電路 10‧‧‧ memory circuit

100‧‧‧記憶體控制器 100‧‧‧ memory controller

101‧‧‧指令解碼器 101‧‧‧ instruction decoder

102‧‧‧刷新位址解碼器 102‧‧‧Refresh address decoder

110‧‧‧偵測器 110‧‧‧Detector

111-11n‧‧‧存取計數器 111-11n‧‧‧ access counter

120‧‧‧記憶體陣列 120‧‧‧Memory array

121-12n‧‧‧記憶體區塊 121-12n‧‧‧ memory block

第1圖係依據本發明之一第一實施例實現之一記憶體電路10之區塊圖。 1 is a block diagram of a memory circuit 10 implemented in accordance with a first embodiment of the present invention.

第2圖係以流程圖說明第二和第三實施例之記憶體電路刷新方法。 Fig. 2 is a flow chart showing a memory circuit refreshing method of the second and third embodiments.

第3圖係以流程圖說明第四實施例之記憶體電路刷新方法。 Fig. 3 is a flow chart showing a memory circuit refreshing method of the fourth embodiment.

本發明所附圖示之實施例或例子將如以下說明。本發明之範疇並非以此為限。習知技藝者應能知悉在不脫離本發明的精神和架構的前提下，當可作些許更動、替換和置換。在本發明之實施例中，元件符號可能被重複地使用，本發明之數種實施例可能共用相同的元件符號，但為一實施例所使用的特徵元件不必然為另一實施例所使用。 Embodiments or examples of the accompanying drawings of the present invention will be described below. The scope of the invention is not limited thereto. Those skilled in the art should be able to know that they are not out of this Under the premise of the spirit and structure of the invention, some changes, substitutions and replacements can be made. In the embodiments of the present invention, the component symbols may be used repeatedly, and the several embodiments of the present invention may share the same component symbols, but the feature elements used in one embodiment are not necessarily used in another embodiment.

第1圖係依據本發明之一第一實施例實現之一記憶體電路10之區塊圖。在第一實施例中，記憶體電路10包括一記憶體控制器100、一偵測器110以及一記憶體陣列120。記憶體控制器100包括一指令解碼器101、一刷新位址解碼器102以及複數存取計數器111~11n，其中指令解碼器101分別耦接刷新位址解碼器102以及複數存取計數器111~11n。記憶體控制器100接收一指令輸入，輸出一存取指令、一刷新指令或是一中斷刷新指令至記憶體陣列120。偵測器110耦接記憶體控制器100以及記憶體陣列120。指令解碼器101接收上述指令輸入，輸出上述存取指令至記憶體陣列120，以及輸出刷新資訊或強制中斷資訊至刷新位址解碼器102。刷新位址解碼器102依據刷新資訊輸出上述刷新指令至記憶體陣列120，或是依據強制中斷資訊輸出上述中斷刷新指令至記憶體陣列120。記憶體陣列120包括複數記憶體區塊121~12n。每一複數記憶體區塊121~12n皆對應設置相同數量之複數字元線。存取計數器111用以在一既定時間內計數對應之記憶體區塊121被存取的次數。同理，複數存取計數器122~12n亦分別用以在該既定時間內計數對應之複數記憶體區塊122~12n被存取的次數。在第一實施例中，該既定時間等於該刷新週期。因此，每一複數存取計數器111~11n計數每一複數記憶體區塊121~12n在該刷新週期內被存取的次數。 1 is a block diagram of a memory circuit 10 implemented in accordance with a first embodiment of the present invention. In the first embodiment, the memory circuit 10 includes a memory controller 100, a detector 110, and a memory array 120. The memory controller 100 includes an instruction decoder 101, a refresh address decoder 102, and complex access counters 111-11n, wherein the instruction decoder 101 is coupled to the refresh address decoder 102 and the complex access counters 111~11n, respectively. . The memory controller 100 receives an instruction input and outputs an access command, a refresh command or an interrupt refresh command to the memory array 120. The detector 110 is coupled to the memory controller 100 and the memory array 120. The instruction decoder 101 receives the above instruction input, outputs the access instruction to the memory array 120, and outputs refresh information or forced interrupt information to the refresh address decoder 102. The refresh address decoder 102 outputs the refresh command to the memory array 120 according to the refresh information, or outputs the interrupt refresh command to the memory array 120 according to the forced interrupt information. The memory array 120 includes a plurality of memory blocks 121-12n. Each of the plurality of memory blocks 121~12n is correspondingly provided with the same number of complex digital elements. The access counter 111 is configured to count the number of times the corresponding memory block 121 is accessed within a predetermined time. Similarly, the complex access counters 122~12n are also used to count the number of times the corresponding complex memory blocks 122~12n are accessed within the predetermined time. In the first embodiment, the predetermined time is equal to the refresh period. Therefore, each complex access counter 111~11n counts each complex memory block 121~12n to be stored in the refresh cycle. The number of times taken.

在第一實施例中，指令解碼器101接收該指令輸入，並判斷該指令輸入是否為一存取指令，例如一ACT命令。若該指令輸入為一存取指令，則指令解碼器101輸出該存取指令以定址該複數字元線而存取記憶體陣列120。刷新位址解碼器102接收來自指令解碼器101的刷新資訊，並依據刷新資訊輸出該刷新指令至記憶體陣列120。記憶體控制器100再依據該刷新指令在一刷新週期中對記憶體陣列120之每一複數記憶體區塊121~12n進行刷新操作。此外，值得注意的是在記憶體陣列120對某一記憶體區塊(例如，記憶體區塊125)執行完刷新操作之後，指令解碼器101就會重置某一記憶體區塊對應之存取計數器(例如，存取計數器115)中的一計數值，其中該計數值為記憶體區塊125被存取的次數(例如，記憶體區塊125接收ACT命令的次數)。 In the first embodiment, the instruction decoder 101 receives the instruction input and determines whether the instruction input is an access instruction, such as an ACT command. If the instruction input is an access instruction, the instruction decoder 101 outputs the access instruction to address the complex digital line to access the memory array 120. The refresh address decoder 102 receives the refresh information from the instruction decoder 101 and outputs the refresh command to the memory array 120 in accordance with the refresh information. The memory controller 100 further performs a refresh operation on each of the plurality of memory blocks 121 to 12n of the memory array 120 in a refresh cycle according to the refresh command. In addition, it is worth noting that after the memory array 120 performs a refresh operation on a memory block (for example, the memory block 125), the instruction decoder 101 resets the memory corresponding to a certain memory block. A count value in a counter (e.g., access counter 115) is taken, wherein the count value is the number of times the memory block 125 is accessed (e.g., the number of times the memory block 125 receives the ACT command).

本發明之一第二實施例舉例說明本發明之記憶體電路10如何刷新記憶體陣列120。本發明之第二實施例沿用第一實施例所述之記憶體電路10。為求方便理解，在第二實施例中，記憶體陣列120具有8個記憶體區塊121~128(n=8)。每一記憶體區塊121~128皆設置有8K條字元線。因此，記憶體陣列120總共設置有64K條字元線。在第二實施例中，指令解碼器101選定要執行強制刷新操作一第一記憶體區塊，其中該第一記憶體區塊可由記憶體控制器100指定得到；或是，記憶體電路10上之偵測器110會偵測複數記憶體區塊121~12n得到目前資料保存功能最差的記憶體區塊(即衰弱記憶體區塊)，並告知指令解碼器101將其做為該第一記憶體區塊；或是，在製造記憶體陣列120時，燒保險絨絲決定該第一記憶體區塊。 A second embodiment of the present invention illustrates how the memory circuit 10 of the present invention refreshes the memory array 120. The second embodiment of the present invention follows the memory circuit 10 of the first embodiment. For ease of understanding, in the second embodiment, the memory array 120 has eight memory blocks 121-128 (n=8). Each memory block 121~128 is provided with 8K word lines. Therefore, the memory array 120 is provided with a total of 64K word lines. In the second embodiment, the instruction decoder 101 selects a first memory block to perform a forced refresh operation, wherein the first memory block can be specified by the memory controller 100; or, on the memory circuit 10 The detector 110 detects the complex memory blocks 121~12n to obtain the memory block with the worst data storage function (ie, the weak memory block), and informs the finger The decoder 101 is caused to be the first memory block; or, when the memory array 120 is manufactured, the burned fuse determines the first memory block.

在第二實施例中，指令解碼器101選定記憶體區塊122做為該第一記憶體區塊，但本發明並不以此為限。接著，指令解碼器101發出刷新資訊至刷新位址解碼器102。刷新資訊包括記憶體區塊122的區塊資訊以及執行強制刷新操作的至少一第一時間點。在第二實施例中，指令解碼器101選定記憶體陣列120對記憶體區塊124執行完刷新操作的時間點做為該第一時間點。刷新位址解碼器102接收來自指令解碼器101的刷新資訊，並依據刷新資訊輸出一刷新指令至記憶體陣列120。該刷新指令包括要被執行刷新操作的該等字元線的記憶體位址順序。因此，記憶體陣列120得以依據該刷新指令中的記憶體位址順序在一刷新週期中對每一複數記憶體區塊121~128進行刷新操作。 In the second embodiment, the instruction decoder 101 selects the memory block 122 as the first memory block, but the invention is not limited thereto. Next, the instruction decoder 101 issues a refresh message to the refresh address decoder 102. The refresh information includes block information of the memory block 122 and at least a first time point at which the forced refresh operation is performed. In the second embodiment, the instruction decoder 101 selects the time point at which the memory array 120 performs the refresh operation on the memory block 124 as the first time point. The refresh address decoder 102 receives the refresh information from the instruction decoder 101 and outputs a refresh command to the memory array 120 in accordance with the refresh information. The refresh instruction includes a memory address sequence of the word lines to be subjected to the refresh operation. Therefore, the memory array 120 can perform a refresh operation on each of the plurality of memory blocks 121-128 in a refresh cycle in accordance with the memory address order in the refresh command.

當記憶體陣列120開始執行該刷新指令，記憶體陣列120先從記憶體區塊121的第一條字元線刷新至最後一條字元線，並依此循序地對記憶體區塊121~124進行刷新操作。當記憶體陣列120刷新完記憶體區塊124的最後一條字元線時(即到達上述第一時間點時)，記憶體陣列120中斷原先的刷新操作，並開始對第一記憶體區塊122進行一強制刷新操作。在記憶體陣列120強制刷新完第一記憶體區塊122的最後一條字元線之後，記憶體陣列120再回頭循序地對記憶體區塊125~128進行刷新操作。藉由上述方法，第一記憶體區塊122在一刷新週期中的刷新頻率會是其他記憶體區塊121和123~128的兩倍。 When the memory array 120 starts to execute the refresh command, the memory array 120 first refreshes from the first word line of the memory block 121 to the last word line, and sequentially pairs the memory blocks 121-124. Perform a refresh operation. When the memory array 120 refreshes the last word line of the memory block 124 (ie, when the first time point is reached), the memory array 120 interrupts the original refresh operation and starts to the first memory block 122. Perform a forced refresh operation. After the memory array 120 forcibly refreshes the last word line of the first memory block 122, the memory array 120 performs a refresh operation on the memory blocks 125-128 in a sequential manner. By the above method, the refresh frequency of the first memory block 122 in one refresh cycle will be two of the other memory blocks 121 and 123-128. Times.

在第二實施例中，指令解碼器101更可選定在對記憶體陣列120之記憶體區塊128執行完刷新操作的時間點做為一第二時間點以再強制更新記憶體區塊122。如此一來，第一記憶體區塊122在該刷新週期中，會在該第一和第二時間點被強制更新，故第一記憶體區塊122的刷新頻率會是其他記憶體區塊121和123~128的三倍。藉由第二實施例所述之刷新方法，記憶體電路10即可加強維護特定記憶體區塊的儲存資料。 In the second embodiment, the instruction decoder 101 is further selected to perform a refresh operation on the memory block 128 of the memory array 120 as a second time point to force the memory block 122 to be re-updated. In this way, the first memory block 122 is forced to be updated at the first and second time points during the refresh cycle, so the refresh frequency of the first memory block 122 may be other memory blocks 121. And three times the 123~128. With the refresh method described in the second embodiment, the memory circuit 10 can enhance the maintenance of the stored data of a particular memory block.

本發明之一第三實施例舉例說明本發明之記憶體電路10如何刷新記憶體陣列120。本發明之第三實施例沿用第一實施例所述之記憶體電路10以及第二實施例所述記憶體陣列120的配置方式。在第三實施例中，複數存取計數器121~118刷新分別計數對應之複數記憶體區塊121~128被存取的次數。與第二實施例不同的是，指令解碼器101選定最大計數值(即存取次數最多)之存取計數器所對應之記憶體區塊做為執行強制刷新操作的一第一記憶體區塊。此外，當記憶體控制器100刷新完記憶體陣列120之某一記憶體區塊時，指令解碼器101會重置其對應存取計數器的計數值。舉例來說，當記憶體控制器100刷新完記憶體區塊127時，指令解碼器101會重置存取計數器117的計數值。藉由第三實施例之刷新方法，記憶體電路10即可加強維護存取次數頻繁之記憶體區塊的儲存資料。 A third embodiment of the present invention illustrates how the memory circuit 10 of the present invention refreshes the memory array 120. The third embodiment of the present invention follows the arrangement of the memory circuit 10 of the first embodiment and the memory array 120 of the second embodiment. In the third embodiment, the complex access counters 121-118 refresh the number of times the corresponding complex memory blocks 121-128 are accessed. Different from the second embodiment, the instruction decoder 101 selects the memory block corresponding to the access counter of the maximum count value (ie, the maximum number of accesses) as a first memory block for performing the forced refresh operation. In addition, when the memory controller 100 refreshes a certain memory block of the memory array 120, the instruction decoder 101 resets the count value of its corresponding access counter. For example, when the memory controller 100 refreshes the memory block 127, the instruction decoder 101 resets the count value of the access counter 117. With the refresh method of the third embodiment, the memory circuit 10 can enhance the storage of the memory block that maintains frequent access times.

本發明之一第四實施例舉例說明本發明之記憶體電路10如何刷新記憶體陣列120。本發明之第四實施例沿用上述第一至第三實施例所述記憶體電路10的配置方式。在第四實施例中，指令解碼器101每隔一特定時間檢查複數存取計數器121~128的計數值，並發出一強制中斷資訊至刷新位址解碼器102。強制中斷資訊包括被存取次數最多之一第二記憶體區塊的區塊資訊。在第四實施例中，上述被存取次數最多之第二記憶體區塊係記憶體區塊126。指令解碼器101在發出強制中斷資訊之後，會重置被存取次數最多之記憶體區塊對應之存取計數器(即存取計數器116)。刷新位址解碼器102依據強制中斷資訊發出一強制刷新指令至記憶體陣列120。此時，若記憶體控制器100與正對記憶體陣列120進行刷新的話，則會先停止正在進行的刷新操作，並對記憶體區塊126進行一強制刷新操作。在記憶體陣列120強制刷新完第一記憶體區塊126的最後一條字元線之後，記憶體陣列120再回頭進行原先的刷新操作。 A fourth embodiment of the present invention illustrates how the memory circuit 10 of the present invention refreshes the memory array 120. The fourth embodiment of the present invention follows the configuration of the memory circuit 10 described in the above first to third embodiments. In the fourth real In the embodiment, the instruction decoder 101 checks the count values of the complex access counters 121-128 at a specific time and issues a forced interrupt message to the refresh address decoder 102. The forced interrupt information includes block information of the second memory block that is accessed the most. In the fourth embodiment, the second memory block that has been accessed the most is the memory block 126. After issuing the forced interrupt information, the instruction decoder 101 resets the access counter (ie, the access counter 116) corresponding to the memory block that has been accessed the most. The refresh address decoder 102 issues a forced refresh command to the memory array 120 in accordance with the forced interrupt information. At this time, if the memory controller 100 and the facing memory array 120 are refreshed, the ongoing refresh operation is stopped first, and a forced refresh operation is performed on the memory block 126. After the memory array 120 forcibly refreshes the last word line of the first memory block 126, the memory array 120 returns to the original refresh operation.

在第四實施例中，指令解碼器101選定小於該刷新週期的一段時間做為上述特定時間，例如，選擇該刷新週期的四分之一做為上述特定時間。如此一來，記憶體電路10即可加強維護在短時間內存取次數頻繁之記憶體區塊的儲存資料。此外，指令解碼器101更可選擇在被存取次數最多之記憶體區塊的計數值超過某一既定值時，才發出該強制中斷資訊至刷新位址解碼器102。藉此避免記憶體陣列120在上述特定時間內未進行存取卻進行該強制刷新操作的情形。 In the fourth embodiment, the instruction decoder 101 selects a period of time smaller than the refresh period as the above-described specific time, for example, selecting one quarter of the refresh period as the above-described specific time. In this way, the memory circuit 10 can enhance the storage of the memory blocks that are frequently accessed in a short period of time. In addition, the instruction decoder 101 may further select the forced interrupt information to the refresh address decoder 102 when the count value of the memory block having the most access times exceeds a predetermined value. Thereby, the situation in which the memory array 120 does not perform access during the specific time period described above is performed to perform the forced refresh operation.

第2圖係以流程圖說明第二和第三實施例之記憶體電路刷新方法。在步驟S201中，記憶體控制器100循序地對記憶體區塊121~12n進行刷新操作，其中每當記憶體控制器100對一記憶體區塊執行完刷新操作(即刷新完一記憶體區塊之最後一條字元線)，即進入步驟S202。在步驟S202中，記憶體控制器100判斷是否到達一特定時間點(即前述第一或第二時間點)。若是進入步驟S203；反之回到步驟S201以繼續原先的刷新操作。在步驟S203中，記憶體控制器100對一第一記憶體區塊進行一強制刷新操作，之後回到步驟S201以繼續原先的刷新操作。 Fig. 2 is a flow chart showing a memory circuit refreshing method of the second and third embodiments. In step S201, the memory controller 100 sequentially performs a refresh operation on the memory blocks 121~12n, wherein each time the memory controller 100 performs a refresh operation on a memory block (ie, refreshes a memory area). Piece The last word line), then proceeds to step S202. In step S202, the memory controller 100 determines whether a specific time point (i.e., the aforementioned first or second time point) is reached. If yes, go to step S203; otherwise, go back to step S201 to continue the original refresh operation. In step S203, the memory controller 100 performs a forced refresh operation on a first memory block, and then returns to step S201 to continue the original refresh operation.

第3圖係以流程圖說明第四實施例之記憶體電路刷新方法。在步驟S301中，指令解碼器101每隔一特定時間檢查複數存取計數器121~128的計數值以找出被存取次數最多之一第二記憶體區塊，並發出一強制中斷資訊至刷新位址解碼器102。在步驟S302中，刷新位址解碼器102依據強制中斷資訊發出一強制刷新指令至記憶體陣列120。在步驟S303中，記憶體陣列120先停止正在進行的刷新操作，並對上述第二記憶體區塊進行一強制刷新操作。在步驟S304中，記憶體陣列120在強制刷新完上述第二記憶體區塊的最後一條字元線之後，即回覆原先進行的刷新操作。 Fig. 3 is a flow chart showing a memory circuit refreshing method of the fourth embodiment. In step S301, the instruction decoder 101 checks the count values of the complex access counters 121-128 every other specific time to find the second memory block that has been accessed the most, and issues a forced interrupt information to the refresh. Address decoder 102. In step S302, the refresh address decoder 102 issues a forced refresh command to the memory array 120 in accordance with the forced interrupt information. In step S303, the memory array 120 first stops the ongoing refresh operation and performs a forced refresh operation on the second memory block. In step S304, after forcibly refreshing the last word line of the second memory block, the memory array 120 replies to the original refresh operation.

本發明雖以較佳實施例揭露如上，使得本領域具有通常知識者能夠更清楚地理解本發明的內容。然而，本領域具有通常知識者應理解到他們可輕易地以本發明做為基礎，設計或修改流程以及操作不同的記憶體電路刷新方法進行相同的目的和/或達到這裡介紹的實施例的相同優點。因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。 The present invention has been described above in terms of preferred embodiments, so that those skilled in the art can understand the present invention more clearly. However, those of ordinary skill in the art will appreciate that they can be readily based on the present invention, designing or modifying processes and operating different memory circuit refresh methods for the same purpose and/or achieving the same as the embodiments described herein. advantage. Therefore, the scope of the invention is defined by the scope of the appended claims.

10‧‧‧記憶體電路 10‧‧‧ memory circuit

100‧‧‧記憶體控制器 100‧‧‧ memory controller

101‧‧‧指令解碼器 101‧‧‧ instruction decoder

102‧‧‧刷新位址解碼器 102‧‧‧Refresh address decoder

110‧‧‧偵測器 110‧‧‧Detector

111-11n‧‧‧存取計數器 111-11n‧‧‧ access counter

120‧‧‧記憶體陣列 120‧‧‧Memory array

121-12n‧‧‧記憶體區塊 121-12n‧‧‧ memory block

Claims

一種記憶體電路，包括：一記憶體陣列，具有複數記憶體區塊，其中每一該記憶體區塊對應設置複數字元線；以及一記憶體控制器，輸出一存取指令以定址該等字元線而存取該記憶體陣列；該記憶體控制器每當輸出一刷新指令，則在一刷新週期中循序地對每一該等記憶體區塊進行刷新操作；其中於該刷新週期，該記憶體控制器於至少一第一時間點，中斷該刷新操作而對該等記憶體區塊中之一第一記憶體區塊進行一強制刷新操作，之後再回復該刷新操作；或是其中該記憶體控制器每隔一特定時間，從該等記憶體區塊中找出於該特定時間內被存取次數最多之一第二記憶體區塊，以進行該強制刷新操作。 A memory circuit includes: a memory array having a plurality of memory blocks, wherein each of the memory blocks is correspondingly provided with a complex digital line; and a memory controller outputting an access command to address the addresses And accessing the memory array by the word line; each time the memory controller outputs a refresh command, sequentially refreshing each of the memory blocks in a refresh cycle; wherein, in the refresh cycle, The memory controller interrupts the refresh operation at at least a first time point to perform a forced refresh operation on one of the first memory blocks in the memory block, and then resumes the refresh operation; or The memory controller finds, from the memory blocks, one of the second memory blocks that are accessed the most in the specific time at a specific time to perform the forced refresh operation.

如申請專利範圍第1項所述記憶體電路，更包括複數存取計數器對應於該等記憶體區塊而設置，用以計數每一該等記憶體區塊於一既定時間內被存取的次數。 The memory circuit of claim 1, further comprising a plurality of access counters corresponding to the memory blocks for counting that each of the memory blocks is accessed within a predetermined time. frequency.

如申請專利範圍第2項所述記憶體電路，其中，該第一記憶體區塊係為該等記憶體區塊於該既定時間內被存取次數最多者。 The memory circuit of claim 2, wherein the first memory block is the one that is accessed the most time in the predetermined time.

如申請專利範圍第2項所述記憶體電路，其中該既定時間等於該刷新週期。 The memory circuit of claim 2, wherein the predetermined time is equal to the refresh period.

如申請專利範圍第1項所述記憶體電路，其中該第一時間點為該刷新操作完成一特定數目之該等記憶體區塊的刷新操作的時點。 The memory circuit of claim 1, wherein the first time point is that the refresh operation completes a specific number of refresh operations of the memory blocks. The time of the work.

如申請專利範圍第5項所述記憶體電路，其中該特定數目係該等記憶體區塊數目之一半。 The memory circuit of claim 5, wherein the specific number is one-half the number of the memory blocks.

如申請專利範圍第5項所述記憶體電路，其中該第一記憶體區塊係藉由記憶體控制器指定得到、或是該記憶體電路偵測到之一衰弱記憶體區塊。 The memory circuit of claim 5, wherein the first memory block is specified by a memory controller or the memory circuit detects one of the weak memory blocks.

一種記憶體電路刷新方法，用以刷新一記憶體陣列中之複數記憶體區塊，該記憶體電路刷新方法包括：輸出一存取指令以定址該等字元線而存取該記憶體陣列；每當該記憶體控制器輸出一刷新指令，則在一刷新週期中循序地對每一該等記憶體區塊進行刷新操作；以及於該刷新週期，該記憶體控制器於至少一第一時間點，中斷該刷新操作而對該等記憶體區塊中之一第一記憶體區塊進行一強制刷新操作，之後再回復該刷新操作；或是在每隔一特定時間，該記憶體控制器從該等記憶體區塊中找出於該特定時間內被存取次數最多之一第二記憶體區塊，以進行該強制刷新操作。 A memory circuit refreshing method for refreshing a plurality of memory blocks in a memory array, the memory circuit refreshing method comprising: outputting an access instruction to address the word lines to access the memory array; Each time the memory controller outputs a refresh command, sequentially refreshing each of the memory blocks in a refresh cycle; and during the refresh cycle, the memory controller is at least a first time Pointing, interrupting the refresh operation to perform a forced refresh operation on one of the first memory blocks in the memory block, and then replying to the refresh operation; or at every other specific time, the memory controller A second memory block that is accessed the most in the specific time period is found from the memory blocks to perform the forced refresh operation.

如專利申請範圍第8項所述之記憶體電路刷新方法，更包括計數每一該等記憶體區塊於一既定時間內被存取的次數。 The memory circuit refreshing method of claim 8, further comprising counting the number of times each of the memory blocks is accessed within a predetermined time.

如專利申請範圍第9項所述之記憶體電路刷新方法，其中，該第一記憶體區塊係為該等記憶體區塊於該既定時間內被存取次數最多者。 The memory circuit refreshing method of claim 9, wherein the first memory block is the one with the most access times of the memory blocks in the predetermined time.

如申請專利範圍第8項所述之記憶體電路刷新方法，其中該既定時間等於該刷新週期。 The method for refreshing a memory circuit according to claim 8, wherein the method The established time is equal to the refresh period.

如專利申請範圍第8項所述之記憶體電路刷新方法，其中該第一時間點為該刷新操作完成一特定數目之該等記憶體區塊的刷新操作的時點。 The memory circuit refreshing method of claim 8, wherein the first time point is a time point at which the refresh operation completes a specific number of refresh operations of the memory blocks.

如專利申請範圍第12項所述之記憶體電路刷新方法，其中該特定數目係該等記憶體區塊數目之一半。 The memory circuit refresh method of claim 12, wherein the specific number is one-half the number of the memory blocks.

如專利申請範圍第12項所述之記憶體電路刷新方法，其中該第一記憶體區塊係藉由記憶體控制器指定得到、或是該記憶體電路偵測到之一衰弱記憶體區塊。 The memory circuit refreshing method of claim 12, wherein the first memory block is specified by a memory controller, or the memory circuit detects one of the weak memory blocks. .