TWI527375B - Voltage selection circuits - Google Patents
Voltage selection circuits Download PDFInfo
- Publication number
- TWI527375B TWI527375B TW102110604A TW102110604A TWI527375B TW I527375 B TWI527375 B TW I527375B TW 102110604 A TW102110604 A TW 102110604A TW 102110604 A TW102110604 A TW 102110604A TW I527375 B TWI527375 B TW I527375B
- Authority
- TW
- Taiwan
- Prior art keywords
- voltage
- circuit
- common mode
- clock signal
- diode
- Prior art date
Links
Landscapes
- Logic Circuits (AREA)
Description
本發明係有關於一種電晶體之基體電壓選擇電路，特別係有關於低電壓差動訊號(low-voltage differential signaling)之電晶體的基體電壓選擇電路。 The present invention relates to a substrate voltage selection circuit for a transistor, and more particularly to a substrate voltage selection circuit for a low-voltage differential signaling transistor.
隨著半導體製程技術的演進，電晶體的尺寸越縮越小，使得操作電壓也隨之減小。但是，固有的系統規格(例如，低電壓差動訊號)因為靈敏度以及其他系統的考量，並沒有隨著操作電壓的降低而調整，造成訊號之電壓高於系統之操作電壓。此現象於P型電晶體上尤其明顯，當源極或汲極端的電壓較基體端之操作電壓高一臨限電壓而造成PN接面的導通時，極有可能發生閂鎖現象(latch-up)而燒毀電晶體。 As semiconductor process technology evolves, the size of the transistor shrinks smaller, resulting in a reduction in operating voltage. However, inherent system specifications (eg, low voltage differential signals) are not adjusted with operating voltage reduction because of sensitivity and other system considerations, causing the voltage of the signal to be higher than the operating voltage of the system. This phenomenon is especially noticeable on P-type transistors. When the voltage at the source or the 汲 terminal is higher than the operating voltage of the substrate terminal and the PN junction is turned on, the latch-up phenomenon is very likely to occur (latch-up). ) and burned the transistor.
第1圖係顯示根據本發明之一實施例所示之傳統低電壓差動訊號電路之電路圖。如第1圖所示，低電壓差動訊號電路100包括閂鎖電路110、第一P型電晶體120以及第二P型電晶體130，其中閂鎖電路110具有第一反相器111以及第二反相器1112，並透過經由外部時脈訊號CK控制之N型電晶體113耦接至地，且閂鎖電路110耦接至供應電壓VDD。此外，第一P型電晶體120之汲極端耦接至低電壓差動訊號負極端DN，第二P型電晶體130之汲極端 耦接至低電壓差動訊號正極端DP，第一P型電晶體120以及第二P型電晶體130之基體端皆耦接至源極端，且第一P型電晶體120以及第二P型電晶體130皆經由外部時脈訊號CK控制分別將低電壓差動訊號負極端DN以及低電壓差動訊號正極端DP提供到分別耦接至第一P型電晶體120以及第二P型電晶體130之源極端的反相輸出端DOUTB以及輸出端DOUT。 1 is a circuit diagram showing a conventional low voltage differential signal circuit shown in accordance with an embodiment of the present invention. As shown in FIG. 1, the low voltage differential signal circuit 100 includes a latch circuit 110, a first P-type transistor 120, and a second P-type transistor 130, wherein the latch circuit 110 has a first inverter 111 and a The two inverters 1112 are coupled to the ground through an N-type transistor 113 controlled via an external clock signal CK, and the latch circuit 110 is coupled to the supply voltage VDD. In addition, the first terminal of the first P-type transistor 120 is coupled to the negative terminal DN of the low voltage differential signal, and the terminal of the second P-type transistor 130 is extreme. The first P-type transistor 120 and the second P-type transistor 130 are coupled to the source terminal, and the first P-type transistor 120 and the second P-type are coupled to the low-voltage differential signal positive terminal DP. The transistor 130 is respectively controlled to provide the low voltage differential signal negative terminal DN and the low voltage differential signal positive terminal DP to the first P-type transistor 120 and the second P-type transistor respectively via the external clock signal CK. The source of the source of the 130 is the inverting output terminal DOUTB and the output terminal DOUT.
當低電壓差動訊號電路100不動作時，假設輸出端DOUT之電壓位準為0V，則反相輸出端DOUTB之電壓位準為供應電壓VDD。而低電壓差動訊號正極端DP之訊號將透過第二P型電晶體130之寄生二極體之導通而漏電至輸出端DOUT，隨著供應電壓VDD不斷降低，該漏電顯的日益嚴重。因此，亟需一基體電壓選擇電路來解決此一問題。 When the low voltage differential signal circuit 100 does not operate, if the voltage level of the output terminal DOUT is 0V, the voltage level of the inverting output terminal DOUTB is the supply voltage VDD. The signal of the positive terminal DP of the low voltage differential signal will leak to the output terminal DOUT through the conduction of the parasitic diode of the second P-type transistor 130. As the supply voltage VDD continues to decrease, the leakage becomes increasingly serious. Therefore, a matrix voltage selection circuit is needed to solve this problem.
有鑑於此，本發明提出一種一種電壓選擇電路，適用於一高速低電壓差動訊號電路，包括：一第一電晶體，具有一第一第一端，一第一第二端，一第一控制端以及一第一基體端；一第二電晶體，具有一第二第一端，一第二第二端，一第二控制端以及一第二基體端，其中上述第一基體端以及上述第二基體端耦接至一節點，其中上述第一第一端與上述第二第一端接收一組低電壓差動訊號，上述第一控制端與上述第二控制端接收一內部時脈訊號；一閂鎖電路，閂鎖上述第一第二端與上述第二第二端之訊號位準；一分壓電路，接收上述低電壓差動訊號，上述低電壓差動訊號經由上述分壓電路之一第一輸入端以及一第二輸入端 接收，並於上述分壓電路之一共模端取出一共模電壓；一第一二極體，包括一第一正極端以及一第一負極端，其中上述第一正極端耦接至上述共模電壓，上述第一負極端耦接至上述節點；以及一第二二極體，包括一第二正極端以及一第二負極端，其中上述第二正極端耦接至上述供應電壓，上述第二負極端耦接至上述節點。 In view of the above, the present invention provides a voltage selection circuit suitable for a high-speed low-voltage differential signal circuit, comprising: a first transistor having a first first end, a first second end, and a first a control terminal and a first base end; a second transistor having a second first end, a second second end, a second control end and a second base end, wherein the first base end and the The second base end is coupled to a node, wherein the first first end and the second first end receive a set of low voltage differential signals, and the first control end and the second control end receive an internal clock signal a latch circuit for latching the signal levels of the first second end and the second second end; a voltage dividing circuit receiving the low voltage differential signal, wherein the low voltage differential signal is divided by the voltage One of the first input of the circuit and a second input Receiving, and extracting a common mode voltage at one common mode end of the voltage dividing circuit; a first diode body including a first positive terminal and a first negative terminal, wherein the first positive terminal is coupled to the common mode a voltage, the first negative terminal is coupled to the node; and a second diode includes a second positive terminal and a second negative terminal, wherein the second positive terminal is coupled to the supply voltage, and the second The negative terminal is coupled to the above node.
當上述共模電壓高於上述供應電壓時，上述第一二極體將上述共模電壓提供至上述節點，上述第二二極體阻斷提供至上述供應電壓之上述共模電壓；或者當上述共模電壓低於上述供應電壓時，上述第二二極體將上述供應電壓提供至上述節點，上述第一二極體阻斷提供至上述共模電壓之上述供應電壓。 And when the common mode voltage is higher than the supply voltage, the first diode supplies the common mode voltage to the node, and the second diode blocks the common mode voltage supplied to the supply voltage; or when When the common mode voltage is lower than the supply voltage, the second diode supplies the supply voltage to the node, and the first diode blocks the supply voltage supplied to the common mode voltage.
上述電壓選擇電路更包括一位準移位電路，接收上述共模電壓且耦接於上述外部時脈訊號以及上述內部時脈訊號之間，上述位準移位電路將一外部時脈訊號轉換成上述內部時脈訊號，其中上述外部時脈訊號之高邏輯位準為上述供應電壓，經上述位準移位電路轉換後之上述內部時脈訊號之高邏輯位準為上述共模電壓。 The voltage selection circuit further includes a quasi-shift circuit that receives the common mode voltage and is coupled between the external clock signal and the internal clock signal, and the level shift circuit converts an external clock signal into The internal clock signal, wherein the high logic level of the external clock signal is the supply voltage, and the high logic level of the internal clock signal converted by the level shift circuit is the common mode voltage.
上述電壓選擇電路更包括一第三二極體，上述第三二極體具有一第三正極端以及一第三負極端，上述第三正極端耦接至上述外部時脈訊號，上述第三負極端耦接至上述內部時脈訊號，其中當上述供應電壓大於上述共模電壓時，上述外部時脈訊號經由上述第三二極體耦接至上述內部時脈電壓。 The voltage selection circuit further includes a third diode, the third diode has a third positive terminal and a third negative terminal, and the third positive terminal is coupled to the external clock signal, and the third negative The external clock signal is coupled to the internal clock signal, wherein the external clock signal is coupled to the internal clock voltage via the third diode when the supply voltage is greater than the common mode voltage.
上述電壓選擇電路更包括一升壓電路，具有一輸入端以及一輸出端，上述輸入端耦接至上述外部時脈訊號，上述輸 出端耦接至上述節點。 The voltage selection circuit further includes a booster circuit having an input end and an output end, wherein the input end is coupled to the external clock signal, and the input is The output is coupled to the above node.
當上述共模電壓與上述供應電壓相近時，啟動上述升壓電路利用上述外部時脈訊號使得上述節點之電壓高於上述共模電壓以及上述供應電壓。 When the common mode voltage is close to the supply voltage, the boosting circuit is activated to use the external clock signal to make the voltage of the node higher than the common mode voltage and the supply voltage.
100、200、300‧‧‧低電壓差動訊號電路 100, 200, 300‧‧‧ low voltage differential signal circuit
110、210、310‧‧‧閂鎖電路 110, 210, 310‧‧‧Latch circuit
111、211、311‧‧‧第一反相器 111, 211, 311‧‧‧ first inverter
112、212、312‧‧‧第二反相器 112, 212, 312‧‧‧ second inverter
113、213、313‧‧‧N型電晶體 113, 213, 313‧‧‧N type transistor
120、220、320‧‧‧第一P型電晶體 120, 220, 320‧‧‧ First P-type transistor
130、230、330‧‧‧第二P型電晶體 130, 230, 330‧‧‧ second P-type transistor
240、340‧‧‧第一二極體 240, 340‧‧‧ first diode
250、350‧‧‧第二二極體 250, 350‧‧‧ second diode
260、360‧‧‧第一電阻 260, 360‧‧‧ first resistance
270、370‧‧‧第二電阻 270, 370‧‧‧ second resistor
280、380‧‧‧位準移位電路 280, 380‧‧ ‧ level shift circuit
390‧‧‧第三二極體 390‧‧‧third diode
400‧‧‧升壓電路 400‧‧‧Boost circuit
410‧‧‧電容 410‧‧‧ Capacitance
420‧‧‧反相器 420‧‧‧Inverter
421‧‧‧P型電晶體 421‧‧‧P type transistor
422‧‧‧N型電晶體 422‧‧‧N type transistor
Buck‧‧‧基體端 Buck‧‧‧ base end
CK‧‧‧外部時脈訊號 CK‧‧‧ external clock signal
CKint‧‧‧內部時脈訊號 CKint‧‧‧ internal clock signal
DN‧‧‧低電壓差動訊號負極端 DN‧‧‧ low voltage differential signal negative terminal
DP‧‧‧低電壓差動訊號正極端 DP‧‧‧ low voltage differential signal positive terminal
DOUT‧‧‧輸出端 DOUT‧‧‧ output
DOUTB‧‧‧反相輸出端 DOUTB‧‧‧inverting output
CM‧‧‧共模端 CM‧‧‧Common end
VCM‧‧‧共模電壓 VCM‧‧‧ Common mode voltage
VDD‧‧‧供應電壓 VDD‧‧‧ supply voltage
REF‧‧‧參考端 REF‧‧‧ reference end
第1圖係顯示根據本發明之一實施例所示之傳統低電壓差動訊號電路之電路圖。 1 is a circuit diagram showing a conventional low voltage differential signal circuit shown in accordance with an embodiment of the present invention.
第2圖係根據本發明之一實施例所示之低電壓差動訊號電路之方塊圖。 Figure 2 is a block diagram of a low voltage differential signal circuit in accordance with one embodiment of the present invention.
第3圖係顯示根據本發明之一實施例所述之低電壓差動訊號電路之方塊圖。 Figure 3 is a block diagram showing a low voltage differential signal circuit in accordance with an embodiment of the present invention.
第4圖係顯示根據本發明之一實施例所述之升壓電路之電路圖。 Figure 4 is a circuit diagram showing a booster circuit in accordance with an embodiment of the present invention.
為使本發明之上述目的、特徵和優點能更明顯易懂，下文特例舉一較佳實施例，並配合所附圖式，來作詳細說明如下：以下將介紹係根據本發明所述之較佳實施例。必須要說明的是，本發明提供了許多可應用之發明概念，在此所揭露之特定實施例，僅是用於說明達成與運用本發明之特定方式，而不可用以侷限本發明之範圍。 The above described objects, features, and advantages of the present invention will become more apparent from the description of the appended claims appended claims A good example. It is to be understood that the invention is not limited to the scope of the invention.
第2圖係根據本發明之一實施例所示之低電壓差動訊號電路之方塊圖。如第2圖所示，低電壓差動訊號電路200包括閂鎖電路210、N型電晶體213、第一P型電晶體220、第二P型電晶體230、第一二極體240、第二二極體250、第一電阻260、第二電阻270以及位準移位電路280。根據本發明之一實施例，閂鎖電路210具有第一反相器211以及第二反相器212，用以將輸出端DOUT以及反相輸出端DOUTB鎖定於一者為最高邏輯位準且另一者為最低邏輯位準。閂鎖電路210、第一P型電晶體220、第二P型電晶體230以及N型電晶體213之連接方式與第1圖所示相同。第一電阻260以及第二電阻270之一端分別耦接至低電壓差動訊號負極端DN以及低電壓差動訊號正極端DP，並於第一電阻260以及第二電阻270間之共模端CM取出共模電壓VCM。 Figure 2 is a block diagram of a low voltage differential signal circuit in accordance with one embodiment of the present invention. As shown in FIG. 2, the low voltage differential signal circuit 200 includes a latch circuit 210, an N-type transistor 213, a first P-type transistor 220, a second P-type transistor 230, a first diode 240, and a first The diode 220, the first resistor 260, the second resistor 270, and the level shift circuit 280. According to an embodiment of the invention, the latch circuit 210 has a first inverter 211 and a second inverter 212 for locking the output terminal DOUT and the inverting output terminal DOUTB to one of the highest logic levels and another One is the lowest logic level. The connection manner of the latch circuit 210, the first P-type transistor 220, the second P-type transistor 230, and the N-type transistor 213 is the same as that shown in FIG. One end of the first resistor 260 and the second resistor 270 are respectively coupled to the low voltage differential signal negative terminal DN and the low voltage differential signal positive terminal DP, and the common mode terminal CM between the first resistor 260 and the second resistor 270 Take out the common mode voltage VCM.
第一二極體240之正極端耦接至共模端CM，第一二極體240之負極端耦接至第一P型電晶體220以及第二P型電晶體230之基體端Buck。同樣地，第二二極體250之正極端耦接至供應電壓VDD，第二二極體250之負極端耦接至第一P型電晶體220以及第二P型電晶體230之基體端Buck。因此，第一二極體240以及第二二極體250之用途為選擇共模電壓VCM以及供應電壓VDD之較高者，將較高之電壓提供至基體端Buck，並且如第1圖所示之漏電路徑不復存在。 The positive terminal of the first diode 240 is coupled to the common mode terminal CM, and the negative terminal of the first diode 240 is coupled to the first P-type transistor 220 and the base terminal Buck of the second P-type transistor 230. Similarly, the positive terminal of the second diode 250 is coupled to the supply voltage VDD, and the negative terminal of the second diode 250 is coupled to the first P-type transistor 220 and the base terminal of the second P-type transistor 230. . Therefore, the first diode 240 and the second diode 250 are used to select the higher common mode voltage VCM and the supply voltage VDD, and provide a higher voltage to the base end Buck, and as shown in FIG. The leakage path no longer exists.
根據本發明之另一實施例，第一二極體240以及第二二極體250可利用P型電晶體之PN接面完成，也就是P型電晶體之閘極與源極以及基體相連接，而汲極與基體間的PN接面即可作為二極體使用。根據本發明之一較佳實施例，二極體亦可利用蕭特 基二極體(schottky diode)具有較低的順向電壓(forward voltage)之特性，而得到較佳之效能。 According to another embodiment of the present invention, the first diode 240 and the second diode 250 can be completed by using a PN junction of the P-type transistor, that is, the gate of the P-type transistor is connected to the source and the substrate. The PN junction between the drain and the substrate can be used as a diode. According to a preferred embodiment of the invention, the diode can also utilize Schott The schottky diode has a lower forward voltage characteristic for better performance.
根據本發明之一實施例，供應電壓VDD之範圍為1.05V至1.35V。根據本發明之另一實施例，共模電壓VCM之範圍為0.8V至1.6V。如第2圖所示，當供應電壓VDD為最低電壓1.05V而共模電壓VCM為1.6V時，第一二極體240導通將共模端CM之共模電壓VCM提供至基體端Buck，而低電壓差動訊號也不再透過第一P型電晶體220以及第二P型電晶體230之寄生二極體分別漏電至反相輸出端VOUTB以及輸出端VOUT。 According to an embodiment of the invention, the supply voltage VDD ranges from 1.05V to 1.35V. According to another embodiment of the invention, the common mode voltage VCM ranges from 0.8V to 1.6V. As shown in FIG. 2, when the supply voltage VDD is the lowest voltage of 1.05 V and the common mode voltage VCM is 1.6 V, the first diode 240 is turned on to supply the common mode voltage VCM of the common mode terminal CM to the base terminal Buck, and The low voltage differential signal also no longer leaks through the first P-type transistor 220 and the parasitic diode of the second P-type transistor 230 to the inverting output terminal VOUTB and the output terminal VOUT, respectively.
根據本發明之一實施例，當供應電壓VDD為最低電壓1.05V而共模電壓VCM為1.6V時，若要斷路第一P型電晶體220以及第二P型電晶體230必須透過最高電壓位準為供應電壓VDD之外部時脈訊號CK將第一P型電晶體220以及第二P型電晶體230之閘極電壓拉至供應電壓VDD之位準。由於低電壓差動訊號負極端DN以及低電壓差動訊號正極端DP之共模電壓VCM為1.6V，第一P型電晶體220以及第二P型電晶體230之汲極至閘極電壓差至少皆有0.4V之壓差，造成第一P型電晶體220以及第二P型電晶體230之通道無法完全斷路。因此，根據本發明之一實施例所述之低電壓差動訊號電路200更包括位準移位電路280，用以將最高電壓位準為供應電壓VDD=1.2V之外部時脈訊號CK，轉換成最高電壓位準為共模電壓VCM=1.6V之內部時脈訊號CKint。如此一來，可使得第一P型電晶體220以及第二P型電晶體230之汲極至閘極電壓差為0V而完全斷路。 According to an embodiment of the present invention, when the supply voltage VDD is the lowest voltage of 1.05 V and the common mode voltage VCM is 1.6 V, the first P-type transistor 220 and the second P-type transistor 230 must be disconnected to pass the highest voltage level. The external clock signal CK, which is the supply voltage VDD, pulls the gate voltages of the first P-type transistor 220 and the second P-type transistor 230 to the level of the supply voltage VDD. Since the common mode voltage VCM of the low voltage differential signal negative terminal DN and the low voltage differential signal positive terminal DP is 1.6V, the drain-to-gate voltage difference between the first P-type transistor 220 and the second P-type transistor 230 At least a voltage difference of 0.4V causes the channels of the first P-type transistor 220 and the second P-type transistor 230 to be completely disconnected. Therefore, the low voltage differential signal circuit 200 according to an embodiment of the present invention further includes a level shifting circuit 280 for converting the highest voltage level to the external clock signal CK of the supply voltage VDD=1.2V. The highest voltage level is the internal clock signal CKint of the common mode voltage VCM=1.6V. In this way, the first P-type transistor 220 and the second P-type transistor 230 can be completely disconnected from the drain-to-gate voltage difference of 0V.
第3圖係顯示根據本發明之一實施例所述之低電壓 差動訊號電路之方塊圖。低電壓差動訊號電路300包括閂鎖電路310、N型電晶體313、第一P型電晶體320、第二P型電晶體330、第一二極體340、第二二極體350、第一電阻360、第二電阻370、位準移位電路380、第三二極體390以及升壓電路400。根據本發明之一實施例，閂鎖電路310係接收供應電壓VDD之供應，且透過N型電晶體313而耦接至接地端，其中閂鎖電路310包括第一反相器311以及第二反相器312，用以將輸出端DOUT以及反相輸出端DOUTB鎖定於一者為最高邏輯位準且另一者為最低邏輯位準。第一P型電晶體320以及第二P型電晶體330用以分別將低電壓差動訊號負極端DN以及低電壓差動訊號正極端DP提供至反相輸出端DOUTB以及輸出端DOUT，且經由外部時脈訊號CK之控制第一P型電晶體320以及第二P型電晶體330導通或斷路。 Figure 3 is a diagram showing a low voltage according to an embodiment of the present invention. Block diagram of the differential signal circuit. The low voltage differential signal circuit 300 includes a latch circuit 310, an N-type transistor 313, a first P-type transistor 320, a second P-type transistor 330, a first diode 340, a second diode 350, and a first A resistor 360, a second resistor 370, a level shifting circuit 380, a third diode 390, and a boosting circuit 400. According to an embodiment of the invention, the latch circuit 310 receives the supply of the supply voltage VDD and is coupled to the ground through the N-type transistor 313, wherein the latch circuit 310 includes the first inverter 311 and the second reverse The phase converter 312 is configured to lock the output terminal DOUT and the inverting output terminal DOUTB to one of the highest logic level and the other to the lowest logic level. The first P-type transistor 320 and the second P-type transistor 330 are respectively provided to the low-voltage differential signal negative terminal DN and the low-voltage differential signal positive terminal DP to the inverting output terminal DOUTB and the output terminal DOUT, respectively, via The external clock signal CK controls the first P-type transistor 320 and the second P-type transistor 330 to be turned on or off.
第一電阻360以及第二電阻370用以在第一電阻360以及第二電阻370之間的共模端CM，取出低電壓差動訊號負極端DN以及低電壓差動訊號正極端DP之共模電壓VCM。第一二極體340以及第二二極體350用以選擇供應電壓VDD以及共模電壓VCM之最高者，提供至第一P型電晶體320以及第二P型電晶體330之基體端Buck。位準移位電路用以將最高邏輯位準為供應電壓VDD之外部時脈訊號CK轉換至最高邏輯位準為共模電壓VCM之內部時脈訊號CKint。 The first resistor 360 and the second resistor 370 are used to extract the common mode of the low voltage differential signal negative terminal DN and the low voltage differential signal positive terminal DP at the common mode terminal CM between the first resistor 360 and the second resistor 370. Voltage VCM. The first diode 340 and the second diode 350 are used to select the highest of the supply voltage VDD and the common mode voltage VCM, and are supplied to the base terminal Buck of the first P-type transistor 320 and the second P-type transistor 330. The level shifting circuit is configured to convert the external clock signal CK with the highest logic level to the supply voltage VDD to the internal clock signal CKint of the highest logic level of the common mode voltage VCM.
根據本發明之另一實施例，供應電壓VDD為1.35V且共模電壓VCM為0.8V。此時，第二二極體350將較高的供應電壓VDD=1.35V提供至第一P型電晶體320以及第二P型電晶體330之基體端Buck。因此，外部時脈訊號CK之最高邏輯位準即為1.35V， 若是使用位準移位電路380轉換成最高邏輯位準為共模電壓VCM之內部時脈訊號CKint，將造成第一P型電晶體320以及第二P型電晶體330源極至閘極之電壓差為0.45V，使得第一P型電晶體320以及第二P型電晶體330無法完全斷路。 According to another embodiment of the invention, the supply voltage VDD is 1.35V and the common mode voltage VCM is 0.8V. At this time, the second diode 350 supplies a higher supply voltage VDD=1.35 V to the base terminal Buck of the first P-type transistor 320 and the second P-type transistor 330. Therefore, the highest logic level of the external clock signal CK is 1.35V. If the internal clock signal CKint of the common logic voltage VCM is converted to the highest logic level using the level shift circuit 380, the voltage of the first P-type transistor 320 and the second P-type transistor 330 from the source to the gate will be caused. The difference is 0.45 V, so that the first P-type transistor 320 and the second P-type transistor 330 cannot be completely broken.
有鑑於此，低電壓差動訊號電路300更包括第三二極體390，位準移位電路380與第三二極體390將自動選擇供應電壓VDD以及共模電壓VCM較高者作為內部時脈訊號CKint之最高邏輯位準。亦即，當供應電壓VDD為1.35V共模電壓VCM為0.8V時，第三二極體390導通將原本外部時脈訊號CK之高邏輯位準(供應電壓VDD)提供至內部時脈訊號CKint，使得第一P型電晶體320以及第二P型電晶體330得以完全斷路。因此，低電壓差動訊號電路300可根據共模電壓VCM與供應電壓VDD之不同，而選擇最佳的操作方式。 In view of this, the low voltage differential signal circuit 300 further includes a third diode 390, and the level shifting circuit 380 and the third diode 390 will automatically select the supply voltage VDD and the common mode voltage VCM as the internal time. The highest logic level of the pulse signal CKint. That is, when the supply voltage VDD is 1.35V and the common mode voltage VCM is 0.8V, the third diode 390 is turned on to supply the high logic level (supply voltage VDD) of the external external clock signal CK to the internal clock signal CKint. The first P-type transistor 320 and the second P-type transistor 330 are completely disconnected. Therefore, the low voltage differential signal circuit 300 can select the optimal operation mode according to the difference between the common mode voltage VCM and the supply voltage VDD.
根據本發明之一實施例，低電壓差動訊號電路300更包括一升壓電路400。當內部時脈訊號CKint為低邏輯位準時第一P型電晶體320以及第二P型電晶體330導通，為了保證第一P型電晶體320以及第二P型電晶體330正常動作，升壓電路400用以將基體端Buck之電壓值提高。 According to an embodiment of the invention, the low voltage differential signal circuit 300 further includes a booster circuit 400. When the internal clock signal CKint is at a low logic level, the first P-type transistor 320 and the second P-type transistor 330 are turned on, in order to ensure that the first P-type transistor 320 and the second P-type transistor 330 operate normally, boosting The circuit 400 is used to increase the voltage value of the base terminal Buck.
第4圖係顯示根據本發明之一實施例所述之升壓電路之電路圖。根據本發明之一實施例，如第4圖所示，升壓電路400包括一電容410以及一反相器420。反相器420包括一P型電晶體421以及一N型電晶體422，其中外部時脈訊號CK耦接至P型電晶體421以及N型電晶體422之閘極端，外部時脈訊號CK為高邏輯位準時斷路P型電晶體421導通N型電晶體422，為低邏輯位準時導通P型電 晶體421斷路N型電晶體422。 Figure 4 is a circuit diagram showing a booster circuit in accordance with an embodiment of the present invention. According to an embodiment of the present invention, as shown in FIG. 4, the boosting circuit 400 includes a capacitor 410 and an inverter 420. The inverter 420 includes a P-type transistor 421 and an N-type transistor 422. The external clock signal CK is coupled to the gate terminals of the P-type transistor 421 and the N-type transistor 422, and the external clock signal CK is high. The logic bit on time breaks the P-type transistor 421 to turn on the N-type transistor 422, and turns on the P-type when the logic level is low. The crystal 421 is broken by the N-type transistor 422.
根據第3圖之實施例，外部時脈訊號CK輸出高邏輯位準時將反相器420之N型電晶體422導通，電容410之參考端REF接地，使得電容410儲存基體端Buck之電壓值。根據第3圖之實施例，此時基體端Buck之基體電壓Vbuck為供應電壓VDD減去第二二極體350之壓降VD(亦即Vbuck=VDD-VD)。 According to the embodiment of FIG. 3, when the external clock signal CK outputs a high logic level, the N-type transistor 422 of the inverter 420 is turned on, and the reference terminal REF of the capacitor 410 is grounded, so that the capacitor 410 stores the voltage value of the base terminal Buck. According to the embodiment of FIG. 3, the base voltage Vbuck of the base terminal Buck is the supply voltage VDD minus the voltage drop VD of the second diode 350 (ie, Vbuck=VDD-VD).
當外部時脈訊號CK輸出低邏輯位準而將反相器420之P型電晶體421導通且斷路N型電晶體422時，反相器420之P型電晶體421將供應電壓VDD提供至參考端REF，使得基體端Buck之電壓Vbuck被抬升一個供應電壓VDD之電壓差(亦即Vbuck=VDD-VD+VDD)。 When the external clock signal CK outputs a low logic level and the P-type transistor 421 of the inverter 420 is turned on and the N-type transistor 422 is turned off, the P-type transistor 421 of the inverter 420 supplies the supply voltage VDD to the reference. The terminal REF is such that the voltage Vbuck of the base terminal Buck is raised by a voltage difference of a supply voltage VDD (ie, Vbuck = VDD - VD + VDD).
以上敘述許多實施例的特徵，使所屬技術領域中具有通常知識者能夠清楚理解本說明書的形態。所屬技術領域中具有通常知識者能夠理解其可利用本發明揭示內容為基礎以設計或更動其他製程及結構而完成相同於上述實施例的目的及/或達到相同於上述實施例的優點。所屬技術領域中具有通常知識者亦能夠理解不脫離本發明之精神和範圍的等效構造可在不脫離本發明之精神和範圍內作任意之更動、替代與潤飾。 The features of many embodiments are described above to enable those of ordinary skill in the art to clearly understand the form of the specification. Those having ordinary skill in the art will appreciate that the objectives of the above-described embodiments and/or advantages consistent with the above-described embodiments can be accomplished by designing or modifying other processes and structures based on the present disclosure. It is also to be understood by those skilled in the art that <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt;
310‧‧‧閂鎖電路 310‧‧‧Latch circuit
311‧‧‧第一反相器 311‧‧‧First Inverter
312‧‧‧第二反相器 312‧‧‧Second inverter
313‧‧‧N型電晶體 313‧‧‧N type transistor
320‧‧‧第一P型電晶體 320‧‧‧First P-type transistor
330‧‧‧第二P型電晶體 330‧‧‧Second P-type transistor
300‧‧‧低電壓差動訊號電路 300‧‧‧Low voltage differential signal circuit
340‧‧‧第一二極體 340‧‧‧First Diode
350‧‧‧第二二極體 350‧‧‧Secondary
360‧‧‧第一電阻 360‧‧‧First resistance
370‧‧‧第二電阻 370‧‧‧second resistance
380‧‧‧位準移位電路 380‧‧‧bit shift circuit
390‧‧‧第三二極體 390‧‧‧third diode
400‧‧‧升壓電路 400‧‧‧Boost circuit
Buck‧‧‧基體端 Buck‧‧‧ base end
CK‧‧‧外部時脈訊號 CK‧‧‧ external clock signal
CKint‧‧‧內部時脈訊號 CKint‧‧‧ internal clock signal
DN‧‧‧低電壓差動訊號負極端 DN‧‧‧ low voltage differential signal negative terminal
DP‧‧‧低電壓差動訊號正極端 DP‧‧‧ low voltage differential signal positive terminal
DOUT‧‧‧輸出端 DOUT‧‧‧ output
DOUTB‧‧‧反相輸出端 DOUTB‧‧‧inverting output
CM‧‧‧共模端 CM‧‧‧Common end
VDD‧‧‧供應電壓 VDD‧‧‧ supply voltage
Claims (8)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW102110604A TWI527375B (en) | 2013-03-26 | 2013-03-26 | Voltage selection circuits |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW102110604A TWI527375B (en) | 2013-03-26 | 2013-03-26 | Voltage selection circuits |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| TW201438400A TW201438400A (en) | 2014-10-01 |
| TWI527375B true TWI527375B (en) | 2016-03-21 |
Family
ID=52113525
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW102110604A TWI527375B (en) | 2013-03-26 | 2013-03-26 | Voltage selection circuits |
Country Status (1)
| Country | Link |
|---|---|
| TW (1) | TWI527375B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113972907A (en) | 2020-07-24 | 2022-01-25 | 雅特力科技(重庆)有限公司 | Voltage divider circuit for battery voltage and electronic device having the same |
-
2013
- 2013-03-26 TW TW102110604A patent/TWI527375B/en active
Also Published As
| Publication number | Publication date |
|---|---|
| TW201438400A (en) | 2014-10-01 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9197199B2 (en) | Level shifter for high density integrated circuits | |
| TWI433442B (en) | Buck converter | |
| US20170126230A1 (en) | Input/output circuit | |
| JP5430507B2 (en) | Voltage level shifter | |
| US20150288365A1 (en) | Level shifter | |
| CN103856205B (en) | Level shifting circuit, for driving the drive circuit of high tension apparatus and corresponding method | |
| US20150263731A1 (en) | Level shift circuit | |
| US9787176B2 (en) | Charge pump | |
| US20140197881A1 (en) | Charge pump and method of biasing deep n-well in charge pump | |
| KR20160103901A (en) | Input/output circuit | |
| CN105099173A (en) | Charge pump | |
| US10685727B2 (en) | Level shifter | |
| CN111245428A (en) | High-voltage PMOS (P-channel metal oxide semiconductor) driving circuit | |
| US10116299B2 (en) | Power-on reset circuit | |
| US20130222036A1 (en) | Voltage level converting circuit | |
| CN109417606B (en) | Level converter capable of outputting positive and negative voltages | |
| KR102322658B1 (en) | Level shift circuit | |
| TWI527375B (en) | Voltage selection circuits | |
| TWI390846B (en) | Input cell, output cell and input/output device | |
| US10277117B2 (en) | Device with a voltage multiplier | |
| TWI739695B (en) | Level shifter | |
| US7965123B2 (en) | High boosting-ratio/low-switching-delay level shifter | |
| US20130181764A1 (en) | Semiconductor integrated circuit | |
| US20150236688A1 (en) | Power-on reset circuit | |
| CN220492976U (en) | Bidirectional level conversion circuit, domain controller and vehicle |