TWI520282B - 用於半導體裝置之互連結構及相關之製造方法 - Google Patents

用於半導體裝置之互連結構及相關之製造方法 Download PDF

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TWI520282B
TWI520282B TW099108290A TW99108290A TWI520282B TW I520282 B TWI520282 B TW I520282B TW 099108290 A TW099108290 A TW 099108290A TW 99108290 A TW99108290 A TW 99108290A TW I520282 B TWI520282 B TW I520282B
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conductive
interconnect
layer
semiconductor device
interconnect structure
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TW099108290A
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TW201044522A (en
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柯拉葛 齊爾德
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格羅方德半導體公司
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Description

用於半導體裝置之互連結構及相關之製造方法
本發明主題之實施方式大致上係關於適合用於半導體裝置之互連結構。更具體而言，本發明主題之實施方式係關於用於半導體裝置互連結構之彈性應力吸收器。
先前技術包括用於將半導體晶片連接至電路板、其他裝置、基板等多種技術及互連結構。例如，經常使用焊珠(solder bead)將倒裝晶片(flip chip)連接至外部電路。該等焊珠通常設置於倒裝晶片之導電凹槽或端點且經回焊以形成用於連接至外部裝置(如電路板)之珠粒。該等焊珠通常由鉛或鉛合金形成。最近，以銀取代鉛以減少廢棄晶片對環境所產生的任何影響。
用於形成焊料連接之另一製程為生成柱狀互連件且在該柱狀互連件頂面形成焊珠。該柱狀互連件通常設置於半導體裝置之接觸墊上且向上延伸。可製作具有非常小節距之柱狀互連件的陣列以適應高密度應用。之後，該陣列之焊珠可使用回焊技術與外部電路耦接。
當使用柱狀互連件時，外部電路所施加的任何力會傳導至該柱狀互連件。該柱狀互連件轉而將該力傳導至於該柱狀互連件與該裝置之間之耦接處之半導體裝置。與直接設置於晶片之焊珠(使用傳統技術)相比，柱狀互連件具有更窄的基底，從而使施加於該半導體裝置上的應力更大。所造成之應變可能會以各種非所欲之方式顯現出來，如某些材料之裂化或剝離。
本發明提供具有裝置基板之半導體裝置。該半導體裝置包括形成為疊置於該裝置基板上之導電墊；形成為疊置於該導電墊上且密封一空腔之導電平臺，其中，該導電平臺具有從該導電墊延伸離開之邊緣部分及在該邊緣部分上面之頂蓋部分；以及設置於該空腔中之緩衝材料。
本發明亦提供具有裝置基板之半導體裝置結構。該半導體裝置結構包括形成為疊置於該裝置基板上之導電接觸墊、設置於該接觸墊上並經調適成回應於力而彈性變形之彈性塊、實質上圍繞該彈性塊且與該彈性塊耦接以及與該接觸墊電耦接之導電平臺、設置於該平臺上面而與該平臺電耦接且延伸至一末端之導電柱狀互連件、以及形成於該末端上之焊珠。
本發明亦提供形成用於裝置基板之接觸平臺之方法。該方法包括提供具有導電接觸元件、在該導電接觸元件上面之鈍化層、以及延伸穿過該鈍化層且終止於該導電接觸元件之凹槽之半導體裝置結構；以彈性材料至少部分地填充該凹槽以獲得經填充之凹槽；從該經填充之凹槽選擇性地去除一部分彈性材料以形成位於該凹槽中之彈性墊，該彈性墊疊置於該導電接觸元件上且與該鈍化層分隔開；以及於該凹槽中形成導電平臺以使該導電平臺至少部分圍繞該彈性墊。
此發明內容係用於簡要說明概念之選集，該等概念將於下文中進一步詳細說明。此發明內容非意欲指出所主張之發明主題的關鍵特徵或基本特徵，亦非意欲用作確定所主張之發明主題的範圍之輔助。
以下詳細說明僅於本質上說明而非意欲限制該主題之實施方式或該等實施方式之應用及使用。本文中所述之術語“例示性”意指“用作實例、例子或例證”。作為例示性之任意實施不必然被解讀為更優於或更有利於其他實施之實施。再者，本文非意欲限於任何揭示於上文之技術領域、先前技術、發明內容或下文之實施方式之明示或暗示理論。
“耦接(couple)”－－以下說明係指元件或節點或特徵被“耦接”在一起。除非明白地另行說明，本文所述之“耦接”意指一個元件/節點/特徵直接或間接地連接至(或直接或間接連通於)另一個元件/節點/特徵，且不必然與直接機械連接相連接。應理解耦接的元件/節點/特徵互相施加影響。因此，雖然第1圖圖解揭示了元件的一種例示性方案(scheme)，但是所揭示主題之實施方式中可存在其他的元件、裝置、特徵或組件。
“調整(adjust)”－－某些元件、組件及/或特徵被描述為可調整的或已調整的。除非明白地另行說明，本文所敘述之“調整”意指定位、改進、改變或設置元件或組件或元件或組件之一部分以適應環境及實施方式。於某些情況下，若對於實施方式所處環境為合適或有需要，則調整後元件或組件或元件或組件之一部分之位置、狀態及/或狀況可維持不變化。於某些情況下，若合適或有需要，則該元件或組件可更改、改變或改進為新位置、狀態及/或狀況。
“抑制”－－本文所述之抑制係用於描述減小效應或最小化效應。當揭示一組件或特徵被描述為抑制活動、移動或狀況時，該組件或特徵可完全防止結果或後果或將來的狀態。另外，“抑制”亦可指反之則可能會發生的後果、性能及/或效應之降低或減少。藉此，當揭示一組件、元件或特徵被指為可抑制結果或狀態時，其不一定完全阻止或消除該結果或狀態。
此外，某些用於以下說明中之術語亦僅作為參考，因此非意欲限制本發明。例如，“上部”、“下部”、“上方”及“下方”等術語係指附圖中之方向，而附圖中之參考架構係一致但為隨意者。該等術語可包括上述特別提到的詞語、該等詞語之衍生物以及相似舶來詞。類似地，除非文中另行說明，涉及結構之術語“第一”、“第二”及其他該等數字並非表示次序或順序。
為了簡潔起見，關於半導體裝置製造之傳統技術可能不於此詳細說明。再者，本文所述之多種工作及製程步驟可併入於具有本文未詳細揭示之其他步驟或功能之更複雜的步驟或製程。特別地，製造半導體系電晶體之多個步驟已廣泛習知，因此，為了簡潔起見，多個傳統步驟僅簡單說明或將全部省略而不提供習知製程細節。
本文所揭示之技術及工藝可用以製造用於任何數量的半導體系裝置(如電晶體裝置、二極體、開關、傳輸線等)之互連件。另外，發明主題係關於控制塌陷晶片連接(controlled collapse chip connection)，其經常使用於倒裝晶片，且包括於下述之半導體裝置結構之說明中。
對於使用柱狀互連件技術之半導體裝置而言，與緩衝墊或彈性墊類似之彈性應力吸收器可位於該柱狀互連件下方以減少傳送至該半導體裝置之環繞區域之應力。該彈性應力吸收器較宜包括至少一個導電部分，藉此實現該半導體裝置與該柱狀互連件之間的電連接。於較佳實施方式中，彈性部分係併入至互連結構；該彈性部分在遭受應力時可發生彈性形變。因此，該柱狀互連件所接收之力及應力在傳送至該半導體裝置之前會被吸收。
第1圖係具有複數個互連結構60之半導體裝置50之透視圖。互連結構60可用於將半導體裝置50與其他組件或外部電路耦接。互連結構60可提供耦接點，該耦接點不僅機械地將組件耦接在一起，亦提供導電通道，透過該導電通道，半導體裝置50之特徵可藉由如外部電路板操作。其他裝置亦可與半導體裝置50耦接。
雖然基於例示之目的顯示一定數量的互連結構60，惟不同實施例的確切數量可不同。另外，熟知本領域之技術人員將認識到額外的互連結構60可存在於半導體裝置50之多種實施例中。再者，當對實施例適合時，不同集中度、排列、群組及形狀可用於互連結構60。
第2圖係一個互連結構100之詳細示意圖。互連結構100除了別的元件還包括導電柱狀互連件180及在柱狀互連件180頂面之焊珠190。柱狀互連件180較佳於導電平臺160與互連結構100耦接。其他層、特徵及/或組件可形成在柱狀互連件180及/或焊珠190周圍，但為了簡潔而予以省略。另外，如上所述，其他互連結構可存在於單個半導體裝置上。
第3圖係沿著第2圖之線3-3所取得的互連結構100之橫截面示意圖。互連結構100較佳包括，但不限於：裝置基板102、導電接觸元件或接觸墊110、第一層絕緣材料(如氮化物層)120、第二層絕緣材料(如氧化物層)130、彈性塊140、黏合層150、導電平臺160、柱狀互連件180及焊珠190。導電平臺160可包括邊緣部分162及頂蓋部分170。
本文所述之裝置基板102表示半導體裝置50之一部分，該半導體裝置50包括功能裝置特徵、導電線路、互連栓、電路元件等。換言之，裝置基板102包括任意操作特徵及元件，以及相關之電連接及導電線路。例如，裝置基板102可包括不同材料的任何數量的層，如半導體材料層、介電質材料層、導電金屬層等。該等不同材料層可用以形成主動裝置(如電晶體)、電接觸、夾層連接及其他通常會發現於半導體裝置之特徵。為了說明之簡要，不於圖中繪示裝置基板102之詳細特徵(每個裝置的特徵互相不同)。
裝置基板102可包括半導體材料，該半導體材料可使用廣泛習知之技術及製程步驟(如關於摻雜、光微影法及圖案化、蝕刻、材料生長、材料沉積、表面平坦化等之技術及步驟)處理，此處將不詳細說明。裝置基板102可使用絕緣體覆矽上(SOI)基板來實現，其中，半導體材料設置於絕緣體材料層上，該絕緣體材料轉而由載體晶片(未顯示)支持。於替代實施例中，裝置基板102可使用塊體矽基板代替SOI基板來實現。
雖然可使用任意適當的半導體材料，但是本實施例中，裝置基板102中之半導體材料係包括矽材料，其中，本文所述之術語“矽材料”包括普通單晶矽及通常用於半導體工業之相對純的矽材料，以及與其他元素(如鍺、碳等)混合之矽。另外，裝置基板102可包括鍺、砷化鎵等。
導電墊110可形成為覆蓋於裝置基板102上。實際上，導電墊110相當於互連結構100的一個電節點、端口(port)或連接點，且導電墊110表示用於互連結構100之電界面。例如，導電墊110可為形成於裝置基板102上之電晶體裝置之源極、閘極或汲極所用之接觸區域。導電墊110可使用任意所欲之技術及/或製程形成。較佳地，導電墊110包括導電金屬材料，如純銅或銅合金。然而，可視實施例之需要而使用其他導電材料，如鋁及鋁合金、銀及銀合金等。雖然導電墊110係顯示為沿著裝置基板102延伸一定長度，但導電墊110之確切尺寸可視實施例之不同而改變。再者，可將多於一個之柱狀互連件180與單個導電墊110耦接。
氮化物層120及氧化物層130位於導電墊110上方且圍繞邊緣部分162。氮化物層120可由任意適當的氮化物化合物(包括矽氮化物)形成。如下文更詳細之說明，氮化物層120定義至少凹槽(如含有導電平臺160之凹槽132)之一部分。氮化物層120可沿著導電墊110以所欲之程度延伸，以與互連結構100之其他特徵適當地作用。氮化物層120可具有約4000至5000埃(Angstrom)之厚度。於某些實施例中，氮化物層120視需要可更薄或更厚。
氧化物層130至少部分覆蓋於氮化物層120上，且其形狀與氮化物層120之形狀一致。因此，氧化物層130較佳為與氮化物層120類似地定義相同凹槽132之至少一部分。氧化物層130可由任意適當的材料形成，如氧化矽或低k材料。氧化物層130可具有約4000至5000埃之厚度，惟於某些實施例中，氧化物層130視需要可更薄或更厚。
氮化物層120及氧化物層130可作為電絕緣體。另外，雖然揭示了兩個鈍化層，但更多或更少的鈍化層可存在於不同實施例中選擇用於該實施例之互連結構100中。因此，某些實施方式可具有單個鈍化層，而其他實施方式可具有兩個或更多個鈍化層。
彈性部分或彈性塊140可形成為覆蓋導電墊110。如圖所示，彈性塊140位於導電平臺160下方之空腔中。於某些實施例中，彈性塊140直接形成於導電墊110上且與導電墊110相鄰接。較佳地，彈性塊140由具有線形彈性應力/應變機械特性之材料構成。因此，可適當地設計或組構彈性塊140以使其在非負載狀態下保持不變形之形狀(如矩形塊)。然而，當力施加於彈性塊140時，彈性塊140可回應於該力而發生彈性變形，當去除力時，彈性塊140恢復至其未變形之形狀。因此，彈性塊140就像彈簧或緩衝墊，可透過彈性形變吸收應力。因此，彈性塊140可稱為緩衝塊、緩衝材料、應力吸收組件等等。
因此，彈性塊140較佳由顯現該等機械特性以及易於成形之材料形成。該等類型的材料之其中一種為聚醯亞胺，較佳為易於製造之光敏聚醯亞胺。再者，彈性塊140可視需要實現為具有由不同材料形成的複數個不同層、部分或區域之複合結構。彈性塊140係繪示為直方角柱，惟不需為特定尺度或比例。因此，可視需要使用其他尺寸及尺度。較佳地，彈性塊140具有實質上四邊形之形狀。
彈性塊140可具有厚度(即高度，從導電墊110上方測量之延伸度)。較佳地，彈性塊140之最大高度比氮化物層120與氧化物層130之總厚度小一適當的間隙，以讓具有所欲厚度之頂蓋部分170可形成。因此，彈性塊140較佳具有小於圍繞之氮化物層120與氧化物層130之總高度之高度。於某些實施例中，彈性塊140具有約600至1000埃之範圍內的厚度。另外，彈性塊140較佳與氮化物層120及氧化物層130隔開。於某些實施例中，此間隔可為約400至800奈米之範圍內。
黏合層150可有助於將導電平臺160黏合至彈性塊140及導電墊110，如下文更詳細之說明。因此，黏合層150位於導電平臺160與彈性塊140之間以及導電平臺160與導電墊110之間。如第3圖所示，黏合層150較佳為形成於氮化物層120及氧化物層130之凹槽中，且覆蓋彈性塊140以及位於導電平臺160之邊緣部分162下方之導電墊110部分。因此，彈性塊140之上表面及側表面可由黏合層150覆蓋。
黏合層150可包括鉻或鉻合金，或其他促進彈性塊140與用於導電墊110之材料之間之黏合並能允許導電於其間之材料(如銅及/或銅合金)。黏合層150可藉由濺鍍製程形成，以沉積於互連結構100上。黏合層150可具有實質上均勻之厚度，如20至40埃之間，但是該厚度在不同的實施例中可不同。
導電平臺160較佳為形成於導電墊110及彈性塊140上方。導電平臺160包括邊緣部分162及頂蓋部分170。邊緣部分162較佳為圍繞彈性塊140之彈性塊140之整個高度。頂蓋部分170較佳為覆蓋邊緣部分162及彈性塊140，並密封彈性塊140所在之空腔。如第3圖所示，凹槽132相當於由頂蓋部分170、邊緣部分162及導電墊110所定義之空間。於某些實施例中，邊緣部分162可延伸至導電平臺160之最大高度，而頂蓋部分170僅為直接在彈性塊140頂面之部分。因此，在不同的實施例中，導電平臺160之各部分不同，但仍具有相同功能以及實質上相同的特徵。導電墊110透過該黏合層與導電平臺160電耦接。
邊緣部分162較佳為形成於彈性塊140及氮化物層120及氧化物層130之間之空間中。如圖所示，邊緣部分162可形成於黏合層150之頂面。於將黏合層150自導電墊110之表面去除之其他實施例中，邊緣部分162可直接形成於導電墊110之表面上。黏合層150仍可形成彈性塊140之側壁與邊緣部分162之間之表面。邊緣部分162較宜向上延伸以與頂蓋部分170耦接。
頂蓋部分170可形成於彈性塊140之頂面上，且如上所述，於某些實施例中，頂蓋部分170亦形成於邊緣部分162之頂面上。頂蓋部分170較佳為被調適成覆蓋彈性塊140之實質上平坦之組件，且與導電墊110實質上平行地延伸。頂蓋部分170之厚度在不同實施例中可不同。邊緣部分162與頂蓋部分170之於導電墊110上方之組合高度較佳為實質上等於氮化物層120及氧化物層130之高度。因此，彈性塊140、黏合層150及導電平臺160之組合較佳為填滿顯示於氮化物層120及氧化物層130中之凹槽。
頂蓋部分170具有外邊緣及內邊緣。該外邊緣或外邊界為頂蓋部分170之最大延伸限度。頂蓋部分170橫跨彈性塊140而由邊緣部分162支撐。因此，該內邊緣為由彈性塊140之外邊緣所界定之邊界，且在該內邊界或內邊緣內，頂蓋部分170係透過黏合層150由彈性塊140支撐。
邊緣部分162及頂蓋部分170較佳由高導電金屬材料構成，如銅、鋁、銀、金或其合金。邊緣部分162及頂蓋部分170可整體形成一個連續的或整體的元件，或可形成兩個連接或耦接在一起的不同元件。
柱狀互連件180可形成於導電平臺160之頂面上。如圖所示，柱狀互連件180較佳具有實質上圓柱形之形狀。柱狀互連件180可直接形成於頂蓋部分170上、或在柱狀互連件180與頂蓋部分170之間形成一個或多個另外的導電層。較佳地，柱狀互連件180由高導電金屬材料形成，如銅、鋁或其合金。實際上，柱狀互連件180、導電平臺160及導電墊110皆可由相同材料形成。
另外參照第4圖，可以看到柱狀互連件180及頂蓋部分170之頂視圖，其中頂蓋部分170之內邊緣172以虛線標出。可以看出，柱狀互連件180在其基底具有外徑、外邊緣184或外邊界，其中該基底與導電平臺160耦接。柱狀互連件180之外邊緣184可當成柱狀互連件180與頂蓋部分170之間之接觸面積之底面積(footprint)。較佳地，柱狀互連件180之外邊緣184係被定義或界定為全部位於頂蓋部分170之內邊緣172內。因此，柱狀互連件180較佳為在全部於彈性塊140上之區域與頂蓋部分170耦接。因此，於較佳實施例中，柱狀互連件180之接觸表面沒有任一部分設置成覆蓋於邊緣部分162上。其他實施例可具有其他組構。
柱狀互連件180可由其他材料圍繞，如其他鈍化或導電層及/或墊(視所實施的裝置或電路之需要)。柱狀互連件180可在其相對於導電墊110之頂部具有末端182。視所使用的連接技術之需要，末端182可為光滑者或具有紋理。焊珠190可形成於末端182上或柱狀互連件180之頂部。焊珠190可由鉛、銀、錫或任意其他所欲之材料構成。
來自互連結構100與外部電路之間之連接之應力、或來自熱膨脹差之應力可於焊珠190處被接收且傳送通過柱狀互連件180。傳送通過柱狀互連件180之應力或力轉而施加於導電平臺160上或由導電平臺160所接收或經歷。因為導電平臺160與彈性塊140耦接，扭力及壓縮應力等應力可傳送至彈性塊140。彈性塊140可回應於所接收之應力而發生彈性變形，藉此吸收所接收之應力且抑制貫穿互連結構100之傳送。因此，可其他特徵與接收自外部組件以及熱膨脹之應力隔離以保護該等特徵。
第5圖至第15圖係顯示用於半導體裝置之例示性互連結構之形成之橫截面示意圖。上述互連結構100可根據下述製程製造。應理解不同實施例之形成可包括任意數量的其他或替代步驟，此處將不再贅述該等步驟。另外，用於標示第5圖至第15圖之某些特徵之數字與上述特徵之數字相同，惟在適當時增加300之數目。如下所述，亦可具有其他的特徵及/或變形。
第5圖為處於在前端處理之後及形成互連結構之前之狀態之半導體裝置。第5圖為顯示形成裝置基板402、導電墊410、氮化物層420及氧化物層430之後之整體製造製程之中間狀態。裝置基板402可包括不同材料之任何數量的層(如半導體層、電介質層、導電金屬層等)及併入特徵(如主動裝置(如電晶體)、電接觸、夾層連接以及其他通常用於半導體裝置之特徵)。另外，雖然揭示了具體的化合物，如氧化物、氮化物，但亦可使用其他材料，如低k及超低k電介質材料。氮化物420及氧化物430層可用作某些製程之終止指示器或終止層(如下所述)。
當獲得第5圖所示之結構之後，可選擇性地去除材料以形成凹槽432，如第6圖所示。使用廣泛習知之製程技術選擇性地自氮化物420及氧化物430層去除材料。例如，適當的圖案化蝕刻遮罩可形成於430之上表面上，且該蝕刻遮罩可用於選擇性地蝕刻氧化物層430及氮化物層420以定義凹槽432。較佳地，材料之去除係向下延伸至導電墊410。實際上，裝置基板402可能需要複數個(如數十個、數百個、數千個或更多個)互連結構。因此，雖然第6圖僅顯示用於一互連結構之一個凹槽432，但是為了對應複數個互連結構，實際中的實施例可於氮化物層420及氧化物層430蝕刻凹槽陣列。因此，此處及下文所述之用於製造彈性塊及導電平臺之製程步驟可用於製造任意數量的半導體裝置結構。
形成凹槽432之後，能以彈性材料500至少部分地填充凹槽432(如第7圖所示)。如上所述，彈性材料500可為光敏聚醯亞胺，其適合對應後續製程步驟。
於某些實施例中，彈性材料500藉由適當的沉積技術形成，如塗覆技術(如旋塗)。較佳地，保形地沉積彈性材料500以使其完全填滿凹槽432。因此，在沉積步驟過程中，可將一些量之彈性材料500沉積於氧化物430層上方。第7圖說明了此過量的材料501(稱為“過量層”)如何覆蓋於氧化物層130上。至少部分填充凹槽432之彈性材料500的沉積係導致經填充之凹槽532。
該實施例繼續進行一個或多個光微影步驟。關於這點，第8圖揭示了光微影曝光步驟，在該步驟中彈性材料500(其為光敏材料)曝露至具有預定圖案之輻射(如光)。例如在其上定義有適當的光遮罩之圖案化玻璃層510的選擇性曝光裝置可設置在彈性材料500上。如圖所示，電磁波譜之適當的部分之光512(不必為可見光)可通過圖案化玻璃層510指向互連結構。
經調整之光514將會依照設置於圖案化玻璃層510上的圖案之設計而穿過圖案化玻璃層510。經調整之光514可選擇性通過或視需要過濾特定波長而具有改變自光512之特性。眾所周知，經調整之光514可調整被曝光之敏彈性材料之特性。例示性實施例使用兩個光微影步驟以選擇性去除彈性材料500之一部分。如第8圖所示，在第一步驟中，經調整之光514被傳送至彈性材料500於填充凹槽532之部分。如第9圖所示，被曝光的彈性材料500再以適當的顯影劑化學作用顯影，以除去一些位於填充凹槽532之彈性材料500。需注意第9圖所繪示之凹槽632表示因初始顯影步驟而去除之彈性材料的部分。
之後，剩餘彈性材料500可經受第二曝光及顯影步驟。如第9圖所示，通過第二圖案化玻璃層560之第二曝光可獲得經調整之光562，而經調整之光562係沿著填充凹槽532之邊緣被提供至彈性材料500。在以經調整之光562使彈性材料500曝光之後，將該曝光之材料顯影以形成第10圖所示之彈性塊540。
應理解雖然該例示性實施例繪示了在沿著凹槽732之邊緣去除彈性材料500之前去除於凹槽632之彈性材料500之寬層，但是可以相反順序實施操作以實現第10圖所示之相同結果。另外，雖然繪示及說明了雙曝光光微影製程，但亦可使用以循序漸進之選擇性照射及/或控制之濃度以選擇性去除彈性材料500之單個光微影製程。再者，在某些實施例中，雙曝光光微影製程可包括在兩個照射步驟之後之僅單個之顯影步驟。用於選擇性去除彈性材料500之確切技術在不同實施例中可不同，但較佳為導致形成與氮化物120及氧化物130層隔開之彈性塊440(如第10圖所示)。
在形成彈性塊之後，該實施例之方法接著附加黏合層450(如第11圖所示)。黏合層450可使用任意所欲之技術沉積，包括CVD或PVD(包括濺鍍法)。較佳地，黏合層450圍繞彈性塊440。如上所述，黏合層450亦可形成於於凹槽732中之導電墊410之頂面上。亦可產生黏合層材料之一些過量層451。沿著導電墊410形成之黏合層450之部分可選擇性地被去除。
如第12圖所示，在形成黏合層450之後，導電材料530可形成於彈性塊440上方。導電材料530通常為金屬材料。於較佳實施例中，導電材料530包括銅或其合金。或者，導電材料530可包括，但不限於鋁或其合金。
導電材料530可藉由適當的沉積技術形成，如CVD或PVD技術。較佳地，保形地沉積彈性材料500以使其完全填滿凹槽632、732，而同時圍繞彈性塊440及在彈性塊440上。導電材料530之某些過量層531可形成於彈性材料500之過量層501及黏合層450之過量層451上。黏合層450較佳促進及有助於彈性塊440與導電材料530之間之耦接。
在沉積導電材料530之後，可將多餘材料自互連結構400去除(如第13圖所示)。更具體地，彈性材料之過量層部分501、黏合層之過量層451及導電材料之過量層531可藉由研磨過量層501、531從氧化層430上去除。關於這點，可使用氧化層430作為終止層、終止標記、終端層或端點指標而藉由化學機械研磨/平坦化(CMP)去除覆蓋層部分。在CMP製程之後，剩餘導電材料530包括邊緣部分462及頂蓋部分470，其共同形成導電平臺460。導電平臺460具有上表面472。較佳地，導電平臺460之高度與周圍之氮化物420及氧化物430層之高度匹配。
如第14圖所示，在去除製程之後，可在導電平臺460上形成導電柱狀互連件480。柱狀互連件480較佳設置於頂蓋部分470之上表面472上。柱狀互連件480可用任何適合之方式形成，包含已知之沉積技術及選擇性移除技術。柱狀互連件480可根據傳統裝置製造及半導體封裝技術製造，此處將不再詳細說明該等傳統技術。較佳地，柱狀互連件480與導電平臺460耦接。另外，如圖所示，柱狀互連件480較宜疊置於彈性塊440上，且未延伸成疊置於邊緣部分462上。
如第15圖所示，在生成柱狀互連件之後，焊珠490可形成於柱狀互連件480上。焊珠490可使用任意所欲之技術形成，以將其定位於柱狀互連件480之末端482上。焊珠490可以多種技術(包括回焊製程)成形，以有助於其與外部組件及/或電路之連接性。
雖然前面已詳細說明至少一個例示性實施例，但應了解存在大量的變形例。亦應了解此處所述之例示性實施例非意欲以任何方式限制所主張的發明主題之範圍、應用或組構。相反，前述詳細說明將為熟知本領域之技術人員提供方便的用於實施說明之實施例之路線圖。應理解在不背離申請專利範圍所定義之範圍之條件下可進行元件之功能及設置之多種改變，該等改變包括在申請該專利時所習知的等同物及可預見的等同物。
50．．．半導體裝置
60、100、400．．．互連結構
102、402．．．裝置基板
110．．．接觸墊
120、420．．．氮化物層
130、430．．．氧化物層
132、432、532、632、732．．．凹槽
140、440．．．彈性塊
150、450．．．黏合層
160、460．．．導電平臺
162、462．．．邊緣部分
170、470．．．頂蓋部分
172．．．內邊緣
180、480．．．導電柱狀互連件
182、482．．．末端
184．．．外邊緣
190、490．．．焊珠
410．．．導電墊
451．．．過量層
472．．．上表面
500．．．彈性材料
501、531．．．過量層
510．．．圖案化玻璃層
512．．．光
514、562．．．經調整之光
530．．．導電材料
560．．．第二圖案化玻璃層
可藉由參照詳細說明及申請專利範圍並結合下列附圖更完整的理解本發明主題，其中，相似的參考數字在整個附圖中係指相似的元件。
第1圖係具有應力吸收互連結構之群組之半導體裝置之實施方式之透視圖；
第2圖係具有彈性應力吸收器之互連結構之透視圖；
第3圖係第2圖之互連結構之橫截面示意圖；
第4圖係第2圖之互連結構之頂視圖；
第5圖至第14圖係顯示包括彈性應力吸收器之例示性互連結構之形成的橫截面示意圖；以及
第15圖係在形成該彈性應力吸收器後之該互連結構之橫截面示意圖。
100．．．互連結構
102．．．裝置基板
110．．．接觸墊
120．．．氮化物層
130．．．氧化物層
132．．．凹槽
140．．．彈性塊
150．．．黏合層
160．．．導電平臺
162．．．邊緣部分
170．．．頂蓋部分
180．．．導電柱狀互連件
182．．．末端
190．．．焊珠

Claims (4)

  1. 一種半導體裝置(50)，其包括裝置基板(102)及互連結構(60)，該互連結構(60)包括：形成為疊置於該裝置基板(102)上之導電墊(110)；形成為疊置於該導電墊(110)上且密封一空腔之導電平臺(160)，其中，該導電平臺(160)具有從該導電墊(110)延伸離開之邊緣部分(162)及在該邊緣部分(162)之上面之頂蓋部分(170)；設置於該空腔中之緩衝材料(140)；以及設置於該導電墊(110)與該邊緣部分(162)之間、以及該緩衝材料(140)與該頂蓋部分(170)之間之黏合層(150)。
  2. 如申請專利範圍第1項之半導體裝置(50)，其中，該黏合層(150)進一步設置於該緩衝材料(140)與該邊緣部分(162)之間。
  3. 如申請專利範圍第1項之半導體裝置(50)，其進一步包括形成為至少部分疊置於該導電平臺(160)上且與該導電平臺(160)電耦接之導電柱狀互連件(180)。
  4. 如申請專利範圍第3項之半導體裝置(50)，其中，該導電柱狀互連件(180)具有橫截面邊緣(184)，該橫截面邊緣(184)全部疊置於該緩衝材料(140)上。
TW099108290A 2009-03-27 2010-03-22 用於半導體裝置之互連結構及相關之製造方法 TWI520282B (zh)

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Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5126231B2 (ja) * 2007-08-10 2013-01-23 富士通セミコンダクター株式会社 半導体素子の選別取得方法、半導体装置の製造方法及び半導体装置
US8895358B2 (en) * 2009-09-11 2014-11-25 Stats Chippac, Ltd. Semiconductor device and method of forming cavity in PCB containing encapsulant or dummy die having CTE similar to CTE of large array WLCSP
US9013037B2 (en) * 2011-09-14 2015-04-21 Stmicroelectronics Pte Ltd. Semiconductor package with improved pillar bump process and structure
US8916481B2 (en) 2011-11-02 2014-12-23 Stmicroelectronics Pte Ltd. Embedded wafer level package for 3D and package-on-package applications, and method of manufacture
US8779601B2 (en) 2011-11-02 2014-07-15 Stmicroelectronics Pte Ltd Embedded wafer level package for 3D and package-on-package applications, and method of manufacture
US10332805B2 (en) 2017-10-30 2019-06-25 Avago Technologies International Sales Pte. Limited Semiconductor structure with strain reduction

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4400865A (en) * 1980-07-08 1983-08-30 International Business Machines Corporation Self-aligned metal process for integrated circuit metallization
JPH05275489A (ja) 1992-03-26 1993-10-22 Hitachi Ltd 電極間の接続構造
US5334804A (en) * 1992-11-17 1994-08-02 Fujitsu Limited Wire interconnect structures for connecting an integrated circuit to a substrate
US5615824A (en) * 1994-06-07 1997-04-01 Tessera, Inc. Soldering with resilient contacts
US6727579B1 (en) * 1994-11-16 2004-04-27 Formfactor, Inc. Electrical contact structures formed by configuring a flexible wire to have a springable shape and overcoating the wire with at least one layer of a resilient conductive material, methods of mounting the contact structures to electronic components, and applications for employing the contact structures
JPH1012621A (ja) 1996-06-26 1998-01-16 Casio Comput Co Ltd 突起電極の構造及びその形成方法
EP1271640A3 (en) 1996-07-12 2003-07-16 Fujitsu Limited Mold for manufacturing semiconductor device
US6222280B1 (en) * 1999-03-22 2001-04-24 Micron Technology, Inc. Test interconnect for semiconductor components having bumped and planar contacts
JP2000299338A (ja) 1999-04-14 2000-10-24 Sony Corp 突起電極を有するベアチップｉｃ及び突起電極の形成方法
SG115455A1 (en) * 2002-03-04 2005-10-28 Micron Technology Inc Methods for assembly and packaging of flip chip configured dice with interposer
US20050095835A1 (en) * 2003-09-26 2005-05-05 Tessera, Inc. Structure and method of making capped chips having vertical interconnects
US7294929B2 (en) * 2003-12-30 2007-11-13 Texas Instruments Incorporated Solder ball pad structure
US20080108221A1 (en) * 2003-12-31 2008-05-08 Microfabrica Inc. Microprobe Tips and Methods for Making
US7187078B2 (en) * 2004-09-13 2007-03-06 Taiwan Semiconductor Manufacturing Co. Ltd. Bump structure
JP2006278417A (ja) 2005-03-28 2006-10-12 Fujikura Ltd 半導体装置及び半導体装置の製造方法
TWI320588B (en) * 2006-12-27 2010-02-11 Siliconware Precision Industries Co Ltd Semiconductor device having conductive bumps and fabrication methodthereof
TW200836275A (en) * 2007-02-16 2008-09-01 Chipmos Technologies Inc Packaging conductive structure and method for manufacturing the same
US7994638B2 (en) * 2007-05-11 2011-08-09 Panasonic Corporation Semiconductor chip and semiconductor device

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