TWI515844B - 具一高功率晶片和一低功率晶片的低互連寄生現象的系統 - Google Patents

具一高功率晶片和一低功率晶片的低互連寄生現象的系統 Download PDF

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TWI515844B
TWI515844B TW101132727A TW101132727A TWI515844B TW I515844 B TWI515844 B TW I515844B TW 101132727 A TW101132727 A TW 101132727A TW 101132727 A TW101132727 A TW 101132727A TW I515844 B TWI515844 B TW I515844B
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Taiwan
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wafer
low power
package substrate
high power
power wafer
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TW101132727A
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TW201322384A (zh
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亞伯拉罕Ｆ 伊
喬 格列柯
翟軍
約瑟夫 米納卡佩利
約翰Ｙ 陳
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輝達公司
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Publication of TW201322384A publication Critical patent/TW201322384A/zh
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    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
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  • Condensed Matter Physics & Semiconductors (AREA)
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  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Description

具一高功率晶片和一低功率晶片的低互連寄生現象的 系統
本發明之具體實施例概略關於積體電路晶片封裝，尤指一種具一高功率晶片和一低功率晶片的系統。
在積體電路(IC，Integrated Circuit)晶片的封裝當中，在包含於一封裝中的晶片與其它元件的熱管理與該等元件的效能之間概略會有所折衷。特別是藉由將一IC封裝的記憶體晶片、被動元件和其它低功率組件儘可能地定位在接近於一IC封裝中的中央處理單元(CPU，Central Processor Unit)和其它高功率元件，在該IC封裝中的元件之間的通訊可以加速，並可降低封裝寄生現象。但是，由較高功率晶片所產生的熱量已知會負面地影響放置在鄰近的記憶體晶片和其它元件。因此，當加入到一單一IC封裝當中時，對於熱性質而言並不適合將記憶體晶片和被動元件直接堆疊在一CPU或其它高功率晶片之上或之下；這種組態需要限制該高功率晶片的功率或限制風險損害到及/或影響到該等記憶體晶片的效能。藉由將這些晶片設置在該IC封裝中該等高功率晶片旁邊來在一單一IC封裝中包括較低功率的晶片亦非必要，因為這種水平分佈的組態會造成該IC封裝具有並不實際的大底面積，以及於該等低功率晶片和該等高功率晶片之間具有一較長的互連路徑。如前所述，本技術中需要一種IC封裝，其中一高功率晶片和一低功率晶片可設置成彼此靠近來防止該低功率晶片過熱。
本發明一具體實施例提出一種IC系統，其中低功率晶片(例如記憶體晶片)被定位在靠近一或多個較高功率的晶片(例如邏輯晶片)，而不會受到過熱的影響。該IC系統包括嵌入在 一封裝基板中的一低功率晶片及設置在該封裝基板上的一高功率邏輯晶片來形成一堆疊。因為該封裝基板的某些部份將該嵌入的低功率晶片與該高功率晶片隔熱，該低功率晶片能夠放置在靠近該高功率晶片而不會過熱。
本發明一項好處為記憶體晶片和其它低功率元件可放置成很靠近在相同IC系統中的高功率元件，而不會由於該等高功率元件而過熱。這樣的緊密鄰近性較佳地是可縮短該等高和低功率元件之間的互連路徑長度，其可改善元件效能，並降低該IC系統中的互連寄生現象。
第一圖係根據本發明一具體實施例之一種積體電路(IC)系統100的橫截面示意圖。IC系統100包括多個IC晶片及/或其它分散的微電子組件，且設置成電性與機械性地連接該等晶片和組件至一印刷電路板190。IC系統100包括一高功率晶片101和一低功率晶片102的一垂直組合，即一堆疊組態，其中低功率晶片102與高功率晶片101隔熱，因此不會受到高功率晶片101之顯著影響。
IC系統100包括高功率晶片101、低功率晶片102、一封裝基板110及複數條封裝導線180。高功率晶片101安裝在封裝基板110的一側上，而低功率晶片102被嵌入在封裝基板110中，所以低功率晶片102與高功率晶片101有隔熱。
由於封裝基板110的某些部份做為一隔熱層，低功率晶片102可被放置成重疊高功率晶片101的一顯著部份，而不會受到高功率晶片101所產生的熱量之負面影響。封裝導線180提供IC系統100和一印刷電路板(PCB，Printed Circuit Board)190之間的電性連接，且可為任何本技術中已知的任何技術上可行的晶片封裝電性連接，包括有球格柵封裝陣列(BGA，Ball-grid Array)、針柵陣列(PGA，Pin-grid Array)及類似者。
高功率晶片101為一種高功率晶片，例如一中央處理單元(CPU，Central Processing Unit)、一圖形處理單元(GPU，Graphics Processing Unit)、應用處理器或其它邏輯元件或任何的IC晶片，其於作業期間會產生足夠的熱量而負面地影響位在IC系統100中的低功率晶片102或被動元件的效能。此處所定義之「高功率晶片」為任何一種IC晶片，其於正常作業期間產生至少10W或更高的熱量。高功率晶片101為一未包封的晶粒，其並未包含在一晶片載體或封裝當中。高功率晶片101固定在封裝基板110的一表面118上，且電性連接至封裝基板110的表面118上的電性連接。高功率晶片101與封裝基板110之間的該等電性連接可使用本技術中已知的任何技術上可行的方式來構成，包括設置在高功率晶片101的表面115上的微型凸塊105之焊接到形成在封裝基板110的表面118上的接合墊113。
另外，這種電性連接藉由機械性地將高功率晶片101上的一PGA壓入到形成在封裝基板110中的通孔或插槽當中所構成。在第一圖所示的具體實施例中，高功率晶片101設置有微型凸塊105，其電性與機械性地將高功率晶片101耦合至封裝基板110。其可使用底填106(垂直交叉線)、超模壓或任何技術上可行的封裝技術來保護高功率晶片101至封裝基板110的該等電性連接。
如所示，高功率晶片101的側部115係固定成抵住封裝基板110，而高功率晶片101的一相反側部116面向遠離於封裝基板110，並可用於附接一散熱器或其它冷卻機構於其上。在第一圖所示的具體實施例中，高功率晶片101熱性耦合至一冷卻機構130，其中包括一散熱裝置131來增進IC系統100的熱傳遞。
低功率晶片102為一種低功率IC晶片，其於作業期間不會產生足夠的熱量而負面地影響鄰接的IC晶片或元件之效 能。如此處所定義的一「低功率晶片」為任何的IC晶片，其於正常作業期間產生等級大約為1W的熱量，即不超過大約5W。低功率晶片102可為位在IC系統100中的被動元件、一記憶體裝置(例如隨機存取記憶體(RAM，Random Access Memory)、快閃記憶體等)、一輸入/輸出(I/O，Input/Output)晶片或任何其它在正常作業中不會產生5W以上的晶片。低功率晶片102可為一未包封、或「外露矽」(bare silicon)記憶體晶片，或在一較佳具體實施例中為一完整封裝的一經包封與經測試的記憶體晶片。在後者的案例中，包含低功率晶片102的該封裝為一「低剖面」(low-profile)封裝，其係足夠地薄而可嵌入在封裝基板110中。低功率晶片102在一堆疊組態中係固定成相對於高功率晶片101，且經由形成在封裝基板110中的導電跡線114電性連接至PCB 190和高功率晶片101。
低功率晶片102與封裝基板110之間的該電性連接可使用本技術中已知的任何技術上可行的方式來構成。在第一圖所示的具體實施例中，在封裝基板110中的這種低功率晶片102和導電跡線114之間的電性連接使用填入銅的介層窗123所構成，其係於由一核心119建構封裝基板110的製程期間所形成。
在一些具體實施例中，低功率晶片102包括穿通矽介層窗(TSVs，Through-silicon Vias)125來促成低功率晶片102、高功率晶片101和PCB 190之間的電性連接。特別是，TSVs 125有效地提供低功率晶片102面對PCB 190的該表面與低功率晶片102面對高功率晶片101的該表面之間極短的電性連接。
此係因為設置在低功率晶片102上的該等電性連接，例如接合墊及類似者，其基本上係製造在低功率晶片102的單一側上，而低功率晶片102需要構成電性連接至位在兩側上的組件，即連接至封裝基板110和連接至PCB 190。
因此，透過TSVs 125，低功率晶片102可被嵌入在IC系統100中，如第一圖所示，且電性連接可直接地同時構成至封 裝基板110上的PCB 190及導電跡線114，因而在低功率晶片102和高功率晶片101之間形成極短路徑長度的互連。TSVs 125為「微型介層窗」(micro vias)，其形成穿過低功率晶片102，並與一導電材料(例如焊料)構成凸塊，用於經由導電跡線114直接與低功率晶片102形成電性連接。
封裝基板110提供IC系統100有結構剛性以及用於在高功率晶片101、低功率晶片102和印刷電路板190之間導引輸入及輸出信號和電力的一電性介面。封裝基板110為一堅硬及隔熱的基板，在其上固定高功率晶片101，而其內側嵌入低功率晶片102。在一些具體實施例中，封裝基板110為一疊層基板，且由建構在核心119之頂面與底面上的一絕緣層117或積層的堆疊所構成。如所示，互連層111和介層窗112係形成在該等絕緣積層層之間，以產生低功率晶片102和PCB 190之間，及低功率晶片102和高功率晶片101之間的導電跡線114。於形成互連層111和介層窗112之前，在核心119中形成一孔，且低功率晶片102被放置在其中。然後介層窗123和封裝基板110的外層(即互連層111和絕緣層117)即形成環繞低功率晶片102。
在本技術中已普遍熟知有一些適當的材料可用於製造在本發明之具體實施例中所使用的積層基板，其可具有所要求的機械強度、電氣特性及所需要的低導熱性。這種材料包括FR-2和FR-4，其為三菱瓦斯化學株式會社(Mitsubishi Gas and Chemical)所提供的傳統環氧式積層和樹脂式雙馬來醯亞胺-三氮雜苯(BT，Bismaleimide-Triazine)。
FR-2為一種合成樹脂黏合紙，其導熱性大約在0.2 W/(K-m)的範圍內。FR-4為一種編織玻璃纖維布，其具有一環氧樹脂黏結劑，其導熱性大約在0.35 W/(K-m)的範圍內。BT/環氧積層基板之導熱性也大約在0.35 W/(K-m)的範圍 內。其亦可使用導熱性低於大約0.5 W/(K-m)的其它適當的堅硬、電性絕緣與隔熱的材料，其仍屬於本發明的範疇。
除了做為IC系統100的結構性基底之外，封裝基板110亦經由導電跡線114導引電力信號、接地信號及輸入/輸出(I/O，Input/Output)信號進入與離開於高功率晶片101、低功率晶片102和PCB 190之間。因此，封裝基板110設置有金屬導體來執行此導引功能，即互連層111和介層窗112。在一些具體實施例中，互連層111由接合至封裝基板110的一或多個積層之銅箔蝕刻有跡線，而介層窗112利用金及/或一無電鍍鎳層來電鍍或加工。
因為封裝基板110的某些部份設置在高功率晶片101和低功率晶片102之間，低功率晶片102可放置成部份地或完全地重疊高功率晶片101，而不會過熱。將低功率晶片102放置成部份地或完全地重疊高功率晶片101造成高功率晶片101和低功率晶片102之較佳的電性效能，因為電路之間互連之較短連接造成較快的信號傳遞，並可降低雜訊、干擾及其它的寄生現象。在電子電路設計中，寄生現象為由於該電路之該等多種組件與配線結構之電性互動所造成之非期望的電性效應，包括有電阻性、電容性及電感性。在IC封裝的領域中，寄生現象由於一晶片和外部組件之互連所造成，例如IC接合墊、接合線、封裝導線、導電跡線等等。藉由將高功率晶片101和低功率晶片102堆疊在如第一圖所示的一重疊組態中，高功率晶片101和低功率晶片102之間的互連長度可最小化，並可大為降低這種寄生現象。另外，IC系統100的整體「底面積」藉由如所示地堆疊高功率晶片101和低功率晶片102而最小化，所以IC系統100較佳地是小於一IC封裝，其中高功率晶片101和低功率晶片102係並排地放置在一封裝基板的相同側上。
在第一圖所示的具體實施例中，高功率晶片101和低功率晶片102係放置成高功率晶片101完全重疊低功率晶片102， 藉此形成一晶片的堆疊。在其它具體實施例中，當低功率晶片102僅部份地重疊高功率晶片101時，即可實現將低功率晶片102和高功率晶片101放置成緊密靠近的好處。第二圖係根據本發明一具體實施例具有多個低功率晶片102部份地重疊高功率晶片101的一種IC系統200的橫截面示意圖。如所示，在IC系統200中，每一低功率晶片102偏離高功率晶片101的中心，並重疊高功率晶片101的一邊緣211。因為每一低功率晶片102設置成靠近高功率晶片101，且僅有與其相隔的封裝基板110，低功率晶片102和高功率晶片101之間互連的路徑長度非常短。特別是，互連可直接行進穿過低功率晶片102的TSVs 125及封裝基板110的導電跡線114。可注意到在習用的PoP晶片載體中，將一或多個低功率晶片102放置成實質地重疊於一高功率邏輯元件，例如CPU或GPU，其通常就熱性而言並不可行，因為該邏輯元件的高功率和顯著的熱量產生會負面地影響到低功率晶片102的效能與可靠度。
在一具體實施例中，低功率晶片102由一間隙250隔開，或偏離於高功率晶片101，所以電性互連260可由PCB 190直接行進至高功率晶片101，並穿過封裝基板110。可使用電性互連260來提供電力及/或接地信號至高功率晶片101。在另一具體實施例中，I/O信號線270設置在間隙250中，並將低功率晶片102連接至高功率晶片101，其可在低功率晶片102中取代TSVs 125的使用，或額外地使用。
根據一些具體實施例，一種IC系統包括兩個或更多的高功率邏輯晶片。第三圖係根據本發明一具體實施例之具有多個高功率晶片301、302的一種IC系統300的橫截面示意圖。IC系統300在組織及作業上實質類似於IC系統100，除了IC系統300包括兩個高功率邏輯晶片301、302及一***物350。高功率晶片301、302之每一者可為一邏輯元件，例如一CPU或一GPU，其於作業期間會產生足夠的熱量而負面地影響IC 系統300中鄰近的低功率晶片102A、102B及/或被動元件之效能。由於高功率邏輯晶片301、302之每一者的顯著熱傳遞需要，高功率邏輯晶片301、302並未堆疊。而是，高功率邏輯晶片301、302係放置成一並排的組態，藉此能夠將冷卻機構130直接置於其上，如所示。在一些具體實施例中，低功率晶片102A設置成配合高功率邏輯晶片301使用，而低功率晶片102B設置成配合高功率邏輯晶片302使用。在一些具體實施例中，IC系統300除了高功率晶片301、302之外，可包括設置在***物350上的一或多個額外的IC晶片。例如，這些額外的IC晶片可包括一或多個全球定位系統(GPS，Global Positioning System)晶片、射頻(RF，Radio Frequency)收發器晶片、Wi-Fi晶片及類似者。
高功率邏輯晶片301、302耦合至***物350，其為一種中間層或結構來提供高功率邏輯晶片301、302、低功率晶片102A、102B及PCB 190之間的電性互連。在一些具體實施例中，***物350由一矽或玻璃基板形成，且設置有多層的金屬互連和介層窗來提供該等電性連接。在一些具體實施例中，***物350包括穿通矽介層窗351，其在結構上類似於第一圖中所述之低功率記憶體晶片102中的TSVs 125。穿通矽介層窗351可提供高功率晶片101和封裝基板110之間極短的電性連接。***物350可以利用C4焊料凸塊352、沉積的微型凸塊或焊接至封裝基板110上接合墊113的焊球來電性及機械性地耦合至封裝基板110。
在第三圖所示的具體實施例中，***物350提供高功率邏輯晶片301、302和低功率晶片102A、102B之間的額外隔熱。因此，使用***物350可促成高功率邏輯晶片301和302之間信號的高速傳遞，並增進低功率晶片102A、102B與高功率邏輯晶片301、302之間的隔熱。
根據一些具體實施例，一IC系統包括一熱量分佈層，其嵌入在一封裝基板中，並設置成鄰接於該IC系統中的一低功率晶片，以增加來自該低功率晶片的熱量傳遞。第四圖係根據本發明一具體實施例具有嵌入在一封裝基板中的一熱量分佈層401的一種IC系統400的橫截面示意圖。如所示，熱量分佈層401形成為一層封裝基板410，且放置成接觸於低功率晶片102。熱量分佈層401，亦可稱之為一「導熱管」(heat pipe)，其可包括具有高導熱性的材料，例如銅或鋁。熱量分佈層401設置成將由低功率晶片102產生的熱能量傳導離開低功率晶片102，藉此於IC系統400的作業期間降低低功率晶片102的過熱風險。
在一些具體實施例中，熱量分佈層401由一或多層的金屬箔所形成，其厚度可由本技術專業人士根據IC系統400的底面積及低功率晶片102和高功率晶片101之熱量產生即可立即決定。在一些具體實施例中，熱量分佈層401包括通孔405來允許互連行進於低功率晶片102和高功率晶片101之間，而不會接觸熱量分佈層401。在一些具體實施例中，一或多個低功率晶片102可設置成靠近IC系統400的一邊緣，以增進自低功率晶片102之熱量移除。
在本發明另外一具體實施例中，一IC系統包括多個記憶體晶片的一堆疊，其放置成實質地重疊一高功率邏輯晶片，藉此當該IC系統包括多個記憶體晶片時可以降低該IC系統的底面積。第五圖係根據本發明一具體實施例將高功率晶片101設置在封裝基板110的一側上而兩個低功率晶片102配置在一堆疊組態中且嵌入封裝基板110中的一種IC系統500的橫截面示意圖。因為低功率晶片102堆疊成如圖所示，多個低功率晶片102可被包括在IC系統500中，而不會增加IC系統500的底面積。
在這種具體實施例中，一或多個熱量分佈層401可被放置成接觸一或多個低功率晶片102。在一些具體實施例中，熱量分佈層401可設置成鄰接於且接觸於每一低功率晶片102及/或在低功率晶片102之間。
在一些具體實施例中，熱量分佈層401於建構封裝基板110的製程期間形成為沉積或另行附接於核心119之該等疊層之一。熱量分佈層401包括通孔405，其可允許互連行進於低功率晶片102和封裝基板110之間。
如以上配合第一圖所述，TSVs 125在低功率晶片102和高功率晶片101之間提供具有極短路徑長度的互連，藉此最小化IC系統500中的互連寄生現象和最大化信號傳遞。另外，低功率晶片102不會在IC系統500中受到過熱的影響，首先係因為封裝基板110提供了低功率晶片102與高功率晶片101之間實質的隔熱，其次係因為熱量分佈層401增加來自低功率晶片102的熱傳遞以移除由低功率晶片102產生的熱量。
總而言之，本發明之具體實施例提出一種IC系統，其中低功率晶片係位在鄰近於相同IC系統中的一或多個高功率晶片，而不會受到過熱的影響。此外，這樣的緊密鄰近性較佳地是可縮短該等高和低功率元件之間的互連路徑長度，其可改善元件效能，並降低該IC系統中的互連寄生現象。
前述係關於本發明之具體實施例，本發明之其它及進一步的具體實施例皆可進行，而並不背離其基本範疇，且其範疇由以下的申請專利範圍所決定。
100‧‧‧積體電路系統
101‧‧‧高功率晶片
102,102A,102B‧‧‧低功率晶片
105‧‧‧微型凸塊
106‧‧‧底填
110‧‧‧封裝基板
111‧‧‧互連層
112‧‧‧介層窗
113‧‧‧接合墊
114‧‧‧導電跡線
115‧‧‧表面，側部
116‧‧‧側部
117‧‧‧絕緣層
118‧‧‧表面
119‧‧‧核心
123‧‧‧介層窗
125‧‧‧穿通矽介層窗
130‧‧‧冷卻機構
131‧‧‧散熱裝置
180‧‧‧封裝導線
190‧‧‧印刷電路板
200‧‧‧積體電路系統
211‧‧‧邊緣
250‧‧‧間隙
260‧‧‧電性互連
270‧‧‧輸入/輸出信號線
300‧‧‧積體電路系統
301,302‧‧‧高功率邏輯晶片
350‧‧‧***物
351‧‧‧穿通矽介層窗
352‧‧‧焊料凸塊
400‧‧‧積體電路系統
401‧‧‧熱量分佈層
405‧‧‧通孔
410‧‧‧封裝基板
500‧‧‧積體電路系統
所以，可以詳細瞭解本發明上述特徵之方式當中，本發明之一更為特定的說明簡述如上，其可藉由參照具體實施例來進行，其中一些例示於所附圖式中。但是應要注意到，該等所附 圖式僅例示本發明的典型具體實施例，因此其並非要做為本發明之範疇的限制，其可允許其它同等有效的具體實施例。
第一圖係根據本發明一具體實施例之一種積體電路(IC)系統的橫截面示意圖；第二圖係根據本發明一具體實施例中將多個低功率晶片部份重疊於一高功率晶片的一種IC系統的橫截面示意圖；第三圖係根據本發明一具體實施例之具有多個高功率晶片的一種IC封裝的橫截面示意圖；第四圖係根據本發明一具體實施例具有設置成鄰接低功率晶片的一熱量分佈層的一種IC封裝的橫截面示意圖；以及第五圖係根據本發明一具體實施例將一高功率晶片設置在一封裝基板的一側上而兩個低功率晶片配置在一堆疊組態中且嵌入在該封裝基板中的一種IC封裝的橫截面示意圖。
為了清楚起見，在任何用到之處相同的參考編號皆用於代表不同圖式之間共通的相同元件。可考慮到一具體實施例之特徵可被併入其它具體實施例中，而並不另行列舉。
102A、102B‧‧‧低功率晶片
110‧‧‧封裝基板
125‧‧‧穿通矽介層窗
130‧‧‧冷卻機構
180‧‧‧封裝導線
190‧‧‧印刷電路板
300‧‧‧積體電路系統
301、302‧‧‧高功率邏輯晶片
350‧‧‧***物
351‧‧‧穿通矽介層窗
352‧‧‧焊料凸塊

Claims (9)

  1. 一種具至少一高功率晶片和至少一低功率晶片的系統，該系統包含：一第一高功率晶片，其設置在一晶片封裝基板的一第一側上；一第一低功率晶片，其嵌入在該晶片封裝基板中，並電性連接至該第一高功率晶片；以及一包括一或多層的金屬箔並嵌入在該晶片封裝基板中且鄰接於該第一低功率晶片的熱量分佈層，其中該熱量分佈層從該晶片封裝基板的一第一邊緣延伸至該晶片封裝基板的一第二邊緣，並且其深度大體上沒有改變；其中該高功率晶片產生至少10W的熱量，且該低功率晶片產生少於5W的熱量。
  2. 如申請專利範圍第1項之系統，其中該第一低功率晶片藉由形成在該第一低功率晶片中的一穿通矽介層窗來電性連接至該第一高功率晶片。
  3. 如申請專利範圍第1項之系統，進一步包含一第二高功率晶片，其設置在該晶片封裝基板中鄰接於該第一高功率晶片的該第一側上。
  4. 如申請專利範圍第1項之系統，其中該晶片封裝基板包含具有導熱性低於大約0.5W/(℃-m)的一隔熱材料。
  5. 一種具至少一高功率晶片和至少一低功率晶片的系統，該系統包含：一***物，其具有一第一側耦合至一晶片封裝基板的一第一側；多個晶片，其設置在該***物的一第二側上，其中該***物的該第二側並未耦合至該晶片封裝基板；一第一低功率晶片，其嵌入在該晶片封裝基板中；以及一包括一或多層的金屬箔並嵌入在該晶片封裝基板中 且鄰接於該第一低功率晶片的熱量分佈層，其中該熱量分佈層從該晶片封裝基板的一第一邊緣延伸至該晶片封裝基板的一第二邊緣，並且其深度大體上沒有改變。
  6. 如申請專利範圍第5項之系統，其中該等多個晶片包括一全球定位系統(GPS，Global Positioning System)晶片、一射頻(RF，Radio Frequency)收發器晶片或一Wi-Fi晶片。
  7. 如申請專利範圍第5項之系統，進一步包含一散熱器，其設置在設置於該***物上的該等多個晶片中至少一晶片之上。
  8. 如申請專利範圍第7項之系統，其中該等多個晶片包含一中央處理單元(CPU，Central Processing Unit)和一圖形處理單元(GPU，Graphics Processing Unit)。
  9. 如申請專利範圍第8項之系統，其中一通道設置在該第一低功率晶片和該第二低功率晶片之間，且(a)由該系統外部的一來源至該等晶片之一晶片的一電力連接，以及(b)該第一低功率晶片或該第二低功率晶片之任一晶片和該等晶片中一晶片之間的一電性互連當中至少一者係設置在該通道中。
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