TWI512917B - Process of forming an anti-oxidant metal layer on an electronic device - Google Patents
Process of forming an anti-oxidant metal layer on an electronic device Download PDFInfo
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- TWI512917B TWI512917B TW100100074A TW100100074A TWI512917B TW I512917 B TWI512917 B TW I512917B TW 100100074 A TW100100074 A TW 100100074A TW 100100074 A TW100100074 A TW 100100074A TW I512917 B TWI512917 B TW I512917B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
Description
本發明係有關於一種在載板上之導接件之側面形成抗氧化金屬層之製程，特別係有關於一種防止在載板上之導接件氧化之製程。 The present invention relates to a process for forming an oxidation resistant metal layer on the side of a via member on a carrier, and more particularly to a process for preventing oxidation of a via on a carrier.
請參閱第1圖，在習知凸塊製程中，係會在一基板100上形成複數個凸塊110，各該凸塊110係具有一頂面111及一側面112，並且在該些凸塊110之該頂面111上形成一接合層120，其中該些凸塊110係為銅凸塊，該接合層120係為鎳-金層，當該些凸塊110之該側面112接觸水氣後，係會使該些凸塊110係會產生膨脹，因而造成微間距之相鄰凸塊110接觸而造成短路，且由於該些凸塊110之該頂面111形成有該接合層120，因此使得該些凸塊110之該頂面111之材質與該側面112的材質不同而造成腐蝕效應，此外在該基板100薄化製程中，係會造成該基板100產生翹曲，而影響後續測試及切割等製程。 Referring to FIG. 1 , in the conventional bump process, a plurality of bumps 110 are formed on a substrate 100 , and each of the bumps 110 has a top surface 111 and a side surface 112 , and the bumps are A bonding layer 120 is formed on the top surface 111 of the 110, wherein the bumps 110 are copper bumps, and the bonding layer 120 is a nickel-gold layer. When the side surface 112 of the bumps 110 is in contact with moisture, The bumps 110 are caused to expand, thereby causing the micro-spaced adjacent bumps 110 to contact to cause a short circuit, and since the top surface 111 of the bumps 110 is formed with the bonding layer 120, The material of the top surface 111 of the bumps 110 is different from the material of the side surface 112 to cause a corrosive effect. In addition, in the thinning process of the substrate 100, the substrate 100 is warped, which affects subsequent testing and cutting. Wait for the process.
本發明之主要目的係在於提供一種在載板上導接件之側面形成抗氧化金屬層之製程，其步驟包含提供一載體，該載體係具有複數個銲墊及一保護層；形成一導接金屬層於該載體上；形成一第一光阻層於該導接金屬層上；圖案化該第一光阻層，以使該第一光阻層形成有複數個開口及複數個第一溝槽；在各該開口及各該第一溝槽中形成一導接件，各該導接件係具有一頂面及一側面 ；移除該第一光阻層，以顯露出各該導接件之該頂面及該側面；形成一第二光阻層於該導接金屬層上，該第二光阻層係覆蓋各該導接件；圖案化該第二光阻層，以使該第二光阻層形成有複數個開口及複數個第二溝槽，各該開口及各該第二溝槽係顯露出各該導接件之該頂面及該側面以及該導接金屬層；在各該開口及各該第二溝槽形成一抗氧化金屬層，該抗氧化金屬層係包覆各該導接件之該頂面及該側面及被各該開口及各該第二溝槽顯露該導接金屬層；移除該第二光阻層，以顯露出該抗氧化金屬層及該導接金屬層；最後移除各該導接件及該抗氧化金屬層下以外之該導接金屬層。本發明可藉由在形成該第一光阻層後，圖案化該第一光阻層，並在該第一光阻層之該些開口或該些溝槽中形成該些導接件(如凸塊、重分配線路、重分配接墊等)，之後，再以該第二光阻層覆蓋各該導接件，並圖案化該第二光阻層，以顯露出該些導接件之該頂面及該側面，並在該些導接件之該頂面及該側面形成該抗氧化金屬層，以使該些導接件具有抗氧化之功效，以避免該些導接件因氧化而體積膨脹，造成短路，且在該些導接件之該頂面及該側面同時形成該抗氧化金屬層，係可避免因該些導接件之該頂面或該側面所包覆材質不同而造成腐蝕效應，此外，在該些導接件之該頂面及該側面同時形成該抗氧化金屬層係可在薄化該載板(如晶圓)時，避免該載板產生翹曲，而影響後續測試及切割等製程。 The main object of the present invention is to provide a process for forming an anti-oxidation metal layer on the side of a conductive member on a carrier, the step of which comprises providing a carrier having a plurality of pads and a protective layer; forming a conductive connection a metal layer on the carrier; forming a first photoresist layer on the conductive metal layer; patterning the first photoresist layer such that the first photoresist layer is formed with a plurality of openings and a plurality of first trenches a guiding member is formed in each of the openings and each of the first grooves, each of the guiding members having a top surface and a side surface Removing the first photoresist layer to expose the top surface and the side surface of each of the conductive members; forming a second photoresist layer on the conductive metal layer, the second photoresist layer covering each The second photoresist layer is patterned to form the plurality of openings and the plurality of second trenches, each of the openings and each of the second trenches exposing each of the plurality of openings The top surface and the side surface of the guiding member and the guiding metal layer; forming an anti-oxidation metal layer in each of the openings and each of the second trenches, the anti-oxidation metal layer covering the respective guiding members The top surface and the side surface are exposed by the openings and the second trenches; the second photoresist layer is removed to expose the oxidation resistant metal layer and the conductive metal layer; The conductive metal layer is removed except for each of the conductive members and the anti-oxidation metal layer. After the first photoresist layer is formed, the first photoresist layer is patterned, and the vias are formed in the openings or trenches of the first photoresist layer (eg, a bump, a redistribution line, a redistribution pad, etc.), and then covering each of the vias with the second photoresist layer, and patterning the second photoresist layer to reveal the vias The top surface and the side surface, and the anti-oxidation metal layer are formed on the top surface and the side surface of the guiding members, so that the guiding members have anti-oxidation effect to prevent the guiding members from being oxidized The volume is expanded to cause a short circuit, and the anti-oxidation metal layer is simultaneously formed on the top surface and the side surface of the conductive members, so that the top surface or the side surface of the conductive members may be prevented from being coated with different materials. And causing a corrosive effect. In addition, simultaneously forming the anti-oxidation metal layer on the top surface and the side surface of the conductive members can prevent the carrier from warping when the carrier (such as a wafer) is thinned. It affects the subsequent testing and cutting processes.
請參閱第2A至2K圖，其係為一種在載板上導接件之 側面形成抗氧化金屬層之製程示意圖，首先，請參閱第2A圖，提供一載體10，該載體係具有複數個銲墊11、複數個線路12及一保護層13，該保護層13具有複數個開口13a，該保護層13係覆蓋該些線路12，且該些開口13a係顯露出該些銲墊11，在本實施例中，該載體10係為晶圓，該保護層13的材質可選自於無機化合物(如氧矽化合物、氮矽化合物或磷矽玻璃)或有機化合物(如是聚醯亞胺)。接著，請參閱第2B圖，形成一導接金屬層20於該載體10上，該導接金屬層20係覆蓋該些銲墊11及該保護層13，且該導接金屬層20係與該些銲墊11電性連接，該導接金屬層20係可以濺鍍方法形成於該載體10上，該導接金屬層20可包含有一鈦層21及一銅層22，該鈦層21係位於該載體10與該銅層22之間。之後，請參閱第2C圖，形成一第一光阻層30於該導接金屬層20上，該第一光阻層30係覆蓋該導接金屬層20，該第一光阻層30係可選自於正型光阻。接著，請參閱第2D圖，進行圖案化該第一光阻層30步驟，其係藉由一光罩(圖未繪出)並經曝光及顯影等製程，以使該第一光阻層30形成有複數個第一開口31、複數個第二開口32及複數個第一溝槽33，其中該些第一開口31係位於該些銲墊11上方，且該些第一開口31、該些第二開口32及該些第一溝槽33係顯露出該導接金屬層20。之後，請參閱第2E圖，在該第一光阻層30之各該第一開口31、各該第二開口32及各該第一溝槽33中形成一導接件40，在本實施例中各該導接件40的材質係為銅，各該導接件40係電性連接該導接金屬層20，在本實施例中，形成於各該第一開口31中之該導接件40係為凸塊 40a，形成於各該第二開口32中之各該導接件40係為重分佈導接墊40b，形成於各該第一溝槽33中之之各該導接件40係為重分佈線路40c，各該導接件係具有一頂面41及一側面42，各該導接件40(凸塊40a、重分佈導接墊40b及重分佈線路40c)係可以電鍍方法形成於各該第一開口31、各該第二開口32及各該第一溝槽33。接著，請參閱第2F圖，進行移除該第一光阻層30之步驟，以顯露出各該導接件40(凸塊40a、重分佈導接墊40b及重分佈線路40c)之該頂面41及該側面42。之後，請參閱第2G1及2G2圖，形成一第二光阻層50於該導接金屬層20上，請參閱第2G1圖，該第二光阻層50之形成方法係可為旋轉塗佈(SPIN COATING)，該第二光阻層50係覆蓋各該導接件40，或者，請參閱第2G2圖，該第二光阻層50之形成方法係可為噴霧披覆(SPRAY COATING)，該第二光阻層50係覆蓋各該導接件40，該第二光阻層50係可選自於正型光阻。接著，請參閱第2H1及2H2圖，進行圖案化該第二光阻層50步驟，請參閱第2H1圖，其係藉由一光罩(圖未繪出)並經曝光及顯影等製程，以使該第二光阻層50形成有複數個第三開口51、複數個第四開口52及複數個第二溝槽53，其中該些第三開口51係位於該些銲墊11上方，且各該第三開口51、各該第四開口52及各該第二溝槽53係顯露出各該導接件40之該頂面41及該側面42，此外，各該第三開口51、各該第四開口52及各該第二溝槽53亦顯露出在各該第三開口51、各該第四開口52及各該第二溝槽53中之該導接金屬層20，在本實例該各該第三開口51係顯露出各該凸塊40a之頂面及側面，各該第四開口52係 顯露出各該重分佈導接墊40b之頂面及側面，各該第二溝槽53係顯露出各該重分佈線路40c之頂面及側面，或者，請參閱第2H2圖，各該第三開口51、各該第四開口52及各該第二溝槽53係顯露出各該導接件40之該頂面41及該側面42，且各該第三開口51、各該第四開口52及各該第二溝槽53亦顯露出在各該第三開口51、各該第四開口52及各該第二溝槽53中之該導接金屬層20。接著，請參閱第2I1及2I2圖，在該第二光阻層50之各該第三開口51、各該第四開口52及各該第二溝槽53中形成一抗氧化金屬層60，該抗氧化金屬層60係包覆各該導接件40之該頂面41及該側面42，在本實施例中，該抗氧化金屬層60亦覆蓋被各該第三開口51、各該第四開口52及各該第二溝槽53顯露之該導接金屬層20，使得該抗氧化金屬層60與在該抗氧化金屬層60下之該導接金屬層20係具有一接合界面A，該抗氧化金屬層60係可以電鍍方法形成於各該導接件40之該頂面41及該側面42，在本實施例中，該抗氧化金屬層60係包含有一鎳層61及一金層62，該鎳層61係位於各該導接件40與該金層62之間。之後，請參閱第2J圖，進行移除該第二光阻層步驟，以顯露出該抗氧化金屬層60及該導接金屬層20。最後，請參閱第2K圖，以各該導接件40及該抗氧化金屬層60為罩幕，移除各該導接件40及該抗氧化金屬層60下以外之該導接金屬層20，以使該些銲墊11上之該導接金屬層20形成為一凸塊下金屬層20A，在本實施例中係以蝕刻方法移除該導接金屬層20。 Please refer to Figures 2A to 2K, which are a kind of guides on the carrier board. A schematic diagram of a process for forming an anti-oxidation metal layer on the side. First, referring to FIG. 2A, a carrier 10 is provided. The carrier has a plurality of pads 11, a plurality of wires 12, and a protective layer 13. The protective layer 13 has a plurality of layers. The opening 13a covers the plurality of wires 12, and the openings 13a expose the pads 11. In the embodiment, the carrier 10 is a wafer, and the protective layer 13 is made of a material. From inorganic compounds (such as oxonium compounds, hydrazine compounds or phosphonium glass) or organic compounds (such as polyimine). Next, referring to FIG. 2B, a conductive metal layer 20 is formed on the carrier 10. The conductive metal layer 20 covers the pads 11 and the protective layer 13, and the conductive metal layer 20 is attached thereto. The conductive pads 11 are electrically connected to each other. The conductive metal layer 20 can be formed on the carrier 10 by a sputtering method. The conductive metal layer 20 can include a titanium layer 21 and a copper layer 22, and the titanium layer 21 is located. The carrier 10 is interposed between the copper layer 22. Then, referring to FIG. 2C, a first photoresist layer 30 is formed on the conductive metal layer 20, and the first photoresist layer 30 covers the conductive metal layer 20, and the first photoresist layer 30 is Selected from a positive photoresist. Next, referring to FIG. 2D, the step of patterning the first photoresist layer 30 is performed by a photomask (not shown) and subjected to exposure and development processes to make the first photoresist layer 30. Forming a plurality of first openings 31, a plurality of second openings 32, and a plurality of first trenches 33, wherein the first openings 31 are located above the pads 11, and the first openings 31, the The second opening 32 and the first trenches 33 expose the conductive metal layer 20. Then, referring to FIG. 2E, a guiding member 40 is formed in each of the first opening 31, each of the second openings 32, and each of the first trenches 33 of the first photoresist layer 30, in this embodiment. Each of the guiding members 40 is made of copper, and each of the guiding members 40 is electrically connected to the guiding metal layer 20. In the embodiment, the guiding members are formed in each of the first openings 31. 40 series is a bump 40a, each of the guiding members 40 formed in each of the second openings 32 is a redistribution guiding pad 40b, and each of the guiding members 40 formed in each of the first grooves 33 is a redistribution line 40c. Each of the guiding members has a top surface 41 and a side surface 42. Each of the guiding members 40 (the bump 40a, the redistribution guiding pad 40b and the redistribution line 40c) can be formed by plating in each of the first openings. 31. Each of the second openings 32 and each of the first trenches 33. Next, referring to FIG. 2F, the step of removing the first photoresist layer 30 is performed to expose the top of each of the guiding members 40 (the bump 40a, the redistribution pad 40b, and the redistribution line 40c). Face 41 and the side 42. Then, referring to the 2G1 and 2G2, a second photoresist layer 50 is formed on the conductive metal layer 20. Referring to FIG. 2G1, the second photoresist layer 50 can be formed by spin coating ( SPIN COATING), the second photoresist layer 50 covers each of the guiding members 40. Alternatively, please refer to FIG. 2G2. The second photoresist layer 50 can be formed by SPRAY COATING. The second photoresist layer 50 covers each of the guiding members 40, and the second photoresist layer 50 is selected from a positive photoresist. Next, please refer to FIGS. 2H1 and 2H2, and perform the step of patterning the second photoresist layer 50. Please refer to FIG. 2H1, which is processed by a photomask (not shown) and exposed and developed. The second photoresist layer 50 is formed with a plurality of third openings 51 , a plurality of fourth openings 52 , and a plurality of second trenches 53 , wherein the third openings 51 are located above the pads 11 and each The third opening 51, each of the fourth openings 52 and each of the second grooves 53 expose the top surface 41 and the side surface 42 of each of the guiding members 40. Further, each of the third openings 51 and each of the third openings 51 The fourth opening 52 and each of the second trenches 53 are also exposed to the conductive metal layer 20 in each of the third openings 51, the fourth openings 52, and the second trenches 53. Each of the third openings 51 exposes a top surface and a side surface of each of the bumps 40a, and each of the fourth openings 52 The top surface and the side surface of each of the redistribution pad 40b are exposed, and each of the second trenches 53 exposes a top surface and a side surface of each of the redistribution lines 40c, or please refer to FIG. 2H2, each of which is third The opening 51, each of the fourth openings 52 and each of the second grooves 53 expose the top surface 41 and the side surface 42 of each of the guiding members 40, and each of the third openings 51 and the fourth openings 52 The second trenches 53 are also exposed to the conductive metal layer 20 in each of the third openings 51, the fourth openings 52, and the second trenches 53. Next, referring to FIGS. 2I1 and 2I2, an anti-oxidation metal layer 60 is formed in each of the third openings 51, the fourth openings 52, and the second trenches 53 of the second photoresist layer 50. The oxidation resistant metal layer 60 covers the top surface 41 and the side surface 42 of each of the guiding members 40. In this embodiment, the oxidation resistant metal layer 60 also covers each of the third openings 51 and the fourth portion. The conductive metal layer 20 is exposed by the opening 52 and each of the second trenches 53 such that the metal oxide layer 60 and the conductive metal layer 20 under the oxidation resistant metal layer 60 have a bonding interface A. The anti-oxidation metal layer 60 can be formed on the top surface 41 and the side surface 42 of each of the guiding members 40. In the embodiment, the oxidation resistant metal layer 60 includes a nickel layer 61 and a gold layer 62. The nickel layer 61 is located between each of the guiding members 40 and the gold layer 62. Thereafter, referring to FIG. 2J, the step of removing the second photoresist layer is performed to expose the oxidation resistant metal layer 60 and the conductive metal layer 20. Finally, referring to FIG. 2K, each of the guiding member 40 and the oxidation resistant metal layer 60 is used as a mask to remove the guiding metal layer 20 except the guiding member 40 and the anti-oxidation metal layer 60. The conductive metal layer 20 on the pads 11 is formed as an under bump metal layer 20A. In the embodiment, the conductive metal layer 20 is removed by etching.
本發明係在該載體10上之該些導接件40之該頂面41及該側面42形成該抗氧化金屬60，以使該些導接件40具 有抗氧化之功效，其係可避免該些導接件40因氧化而體積膨脹，而造成相鄰的導接件40接觸形成短路，且在該些導接件40之該頂面41及該側面42同時形成該抗氧化金屬層60，係可避免如習知技術所揭露僅於該些導接件之該頂面形成導接層而造成，該些導接件之頂部與側部材質不同，因氧化還原電位差造成電池腐蝕效應，此外，本發明在該些導接件40之該頂面41及該側面42同時形成該抗氧化金屬層60係可在薄化該載體10(如晶圓)時，避免該載體10產生翹曲，而影響後續測試及切割等製程。 The top surface 41 and the side surface 42 of the guiding members 40 on the carrier 10 form the oxidation resistant metal 60, so that the guiding members 40 have It has an anti-oxidation effect, which can avoid the volume expansion of the connecting members 40 due to oxidation, and cause the adjacent connecting members 40 to contact to form a short circuit, and the top surface 41 of the guiding members 40 and the The side surface 42 simultaneously forms the anti-oxidation metal layer 60, which can avoid the formation of the conductive layer only on the top surface of the guiding members as disclosed in the prior art. The top and side materials of the guiding members are different. The corrosion-inhibiting effect of the battery is caused by the difference of the oxidation-reduction potential. In addition, the top surface 41 of the conductive member 40 and the side surface 42 simultaneously form the anti-oxidation metal layer 60 to thin the carrier 10 (such as a wafer). When the carrier 10 is prevented from warping, the subsequent testing and cutting processes are affected.
此外在形成該抗氧化金屬層60之步驟中，由於該抗氧化金屬層60係包覆該各該導接件40之該頂面41、該側面42及覆蓋該抗氧化金屬層60下之該導接金屬層20，因此使得該抗氧化金屬層60與該抗氧化金屬層60下之該導接金屬層20具有該接合界面A，而該接合界面A係使得水氣無法滲透入各該導接件40，以避免各該導接件40與該抗氧化金屬層60間產生氧化。 In addition, in the step of forming the anti-oxidation metal layer 60, the anti-oxidation metal layer 60 covers the top surface 41 of the respective guiding members 40, the side surface 42 and the underlying layer of the anti-oxidation metal layer 60. Conducting the metal layer 20, thereby causing the oxidation resistant metal layer 60 and the conductive metal layer 20 under the oxidation resistant metal layer 60 to have the bonding interface A, and the bonding interface A is such that moisture cannot penetrate into each of the guiding layers The connector 40 prevents oxidation between the respective contact members 40 and the oxidation resistant metal layer 60.
本發明之保護範圍當視後附之申請專利範圍所界定者為準，任何熟知此項技藝者，在不脫離本發明之精神和範圍內所作之任何變化與修改，均屬於本發明之保護範圍。 The scope of the present invention is defined by the scope of the appended claims, and any changes and modifications made by those skilled in the art without departing from the spirit and scope of the invention are within the scope of the present invention. .
10‧‧‧載體 10‧‧‧ Carrier
11‧‧‧銲墊 11‧‧‧ solder pads
12‧‧‧線路 12‧‧‧ lines
13‧‧‧保護層 13‧‧‧Protective layer
13a‧‧‧開口 13a‧‧‧ Opening
20‧‧‧導接金屬層 20‧‧‧Guided metal layer
20A‧‧‧凸塊下金屬層 20A‧‧‧ under bump metal layer
21‧‧‧鈦層 21‧‧‧Titanium
22‧‧‧銅層 22‧‧‧ copper layer
30‧‧‧第一光阻層 30‧‧‧First photoresist layer
31‧‧‧第一開口 31‧‧‧ first opening
32‧‧‧第二開口 32‧‧‧second opening
33‧‧‧第一溝槽 33‧‧‧First trench
40‧‧‧導接件 40‧‧‧Connector
40a‧‧‧凸塊 40a‧‧‧Bumps
40b‧‧‧重分佈導接墊 40b‧‧‧Redistribution pad
40c‧‧‧重分佈線路 40c‧‧‧Redistributed lines
41‧‧‧頂面 41‧‧‧ top surface
42‧‧‧側面 42‧‧‧ side
50‧‧‧第二光阻層 50‧‧‧second photoresist layer
51‧‧‧第三開口 51‧‧‧ third opening
52‧‧‧第四開口 52‧‧‧fourth opening
53‧‧‧第三溝槽 53‧‧‧ third trench
60‧‧‧抗氧化金屬層 60‧‧‧Antioxidant metal layer
61‧‧‧鎳層 61‧‧‧ Nickel layer
62‧‧‧金層 62‧‧‧ gold layer
100‧‧‧基板 100‧‧‧Substrate
110‧‧‧凸塊 110‧‧‧Bumps
111‧‧‧頂面 111‧‧‧ top surface
112‧‧‧側面 112‧‧‧ side
120‧‧‧接合層 120‧‧‧ joint layer
A‧‧‧接合界面 A‧‧‧ joint interface
第1圖：習知在一基板上形成複數個凸塊之示意圖。 Figure 1: A schematic view of forming a plurality of bumps on a substrate.
第2A圖：依據本發明之一較佳實施例，提供一載體之示意圖。 Figure 2A is a schematic illustration of a carrier in accordance with a preferred embodiment of the present invention.
第2B圖：依據本發明之一較佳實施例，形成一導接金屬層於該載體之示意圖。 2B is a schematic view showing the formation of a conductive metal layer on the carrier in accordance with a preferred embodiment of the present invention.
第2C圖：依據本發明之一較佳實施例，形成一第一光阻層於導接金屬層上之示意圖。 2C is a schematic view showing the formation of a first photoresist layer on a conductive metal layer in accordance with a preferred embodiment of the present invention.
第2D圖：依據本發明之一較佳實施例，進行圖案化第一光阻層之示意圖。 2D is a schematic view of a patterned first photoresist layer in accordance with a preferred embodiment of the present invention.
第2E圖：依據本發明之一較佳實施例，在第一光阻層之第一開口、第二開口及第一溝槽中形成導接件之示意圖。 2E is a schematic view showing a conductive member formed in a first opening, a second opening, and a first trench of the first photoresist layer according to a preferred embodiment of the present invention.
第2F圖：依據本發明之一較佳實施例，移除第一光阻層之示意圖。 Figure 2F is a schematic illustration of the removal of a first photoresist layer in accordance with a preferred embodiment of the present invention.
第2G1圖：依據本發明之一較佳實施例，形成一第二光阻層於該導接金屬層上之示意圖。 2G1 is a schematic view showing a second photoresist layer formed on the conductive metal layer in accordance with a preferred embodiment of the present invention.
第2G2圖：依據本發明之另一較佳實施例，形成一第二光阻層於該導接金屬層上之示意圖。 FIG. 2G2 is a schematic view showing a second photoresist layer formed on the conductive metal layer according to another preferred embodiment of the present invention.
第2H1圖：依據本發明之一較佳實施例，進行圖案化該第二光阻層之示意圖。 2H1: A schematic diagram of patterning the second photoresist layer in accordance with a preferred embodiment of the present invention.
第2H2圖：依據本發明之另一較佳實施例，進行圖案化該第二光阻層之示意圖。 2H2: A schematic diagram of patterning the second photoresist layer in accordance with another preferred embodiment of the present invention.
第2I1圖：依據本發明之一較佳實施例，在第二光阻層之第三開口、第四開口及第二溝槽中形成一抗氧化金屬層之示意圖。 2I1 is a schematic view showing an anti-oxidation metal layer formed in the third opening, the fourth opening and the second trench of the second photoresist layer according to a preferred embodiment of the present invention.
第2I2圖：依據本發明之另一較佳實施例，在第二光阻層之第三開口、第四開口及第二溝槽中形成一抗氧化金屬層之示意圖。 2I2: According to another preferred embodiment of the present invention, a schematic diagram of an anti-oxidation metal layer is formed in the third opening, the fourth opening and the second trench of the second photoresist layer.
第2J圖：依據本發明之一較佳實施例，移除第二光阻層之示意圖。 2J is a schematic view of a second photoresist layer removed in accordance with a preferred embodiment of the present invention.
第2K圖：依據本發明之一較佳實施例，移除導接件及抗 氧化金屬層下以外之導接金屬層之示意圖。 Figure 2K: Removal of the guide member and the anti-resistance according to a preferred embodiment of the present invention Schematic diagram of a conductive metal layer other than under the oxidized metal layer.
10‧‧‧載體 10‧‧‧ Carrier
11‧‧‧銲墊 11‧‧‧ solder pads
12‧‧‧線路 12‧‧‧ lines
13‧‧‧保護層 13‧‧‧Protective layer
13a‧‧‧開口 13a‧‧‧ Opening
20‧‧‧導接金屬層 20‧‧‧Guided metal layer
20A‧‧‧凸塊下金屬層 20A‧‧‧ under bump metal layer
21‧‧‧鈦層 21‧‧‧Titanium
22‧‧‧銅層 22‧‧‧ copper layer
40‧‧‧導接件 40‧‧‧Connector
40a‧‧‧凸塊 40a‧‧‧Bumps
40b‧‧‧重分佈導接墊 40b‧‧‧Redistribution pad
40c‧‧‧重分佈線路 40c‧‧‧Redistributed lines
41‧‧‧頂面 41‧‧‧ top surface
42‧‧‧側面 42‧‧‧ side
60‧‧‧抗氧化金屬層 60‧‧‧Antioxidant metal layer
61‧‧‧鎳層 61‧‧‧ Nickel layer
62‧‧‧金層 62‧‧‧ gold layer
Claims (13)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW100100074A TWI512917B (en) | 2011-01-03 | 2011-01-03 | Process of forming an anti-oxidant metal layer on an electronic device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW100100074A TWI512917B (en) | 2011-01-03 | 2011-01-03 | Process of forming an anti-oxidant metal layer on an electronic device |
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| Publication Number | Publication Date |
|---|---|
| TW201230264A TW201230264A (en) | 2012-07-16 |
| TWI512917B true TWI512917B (en) | 2015-12-11 |
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| TW100100074A TWI512917B (en) | 2011-01-03 | 2011-01-03 | Process of forming an anti-oxidant metal layer on an electronic device |
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| CN110854066A (en) * | 2019-11-28 | 2020-02-28 | 无锡微视传感科技有限公司 | Semiconductor electroplating method |
Citations (5)
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|---|---|---|---|---|
| US6495442B1 (en) * | 2000-10-18 | 2002-12-17 | Magic Corporation | Post passivation interconnection schemes on top of the IC chips |
| US6673698B1 (en) * | 2002-01-19 | 2004-01-06 | Megic Corporation | Thin film semiconductor package utilizing a glass substrate with composite polymer/metal interconnect layers |
| US6784087B2 (en) * | 2002-01-07 | 2004-08-31 | Megic Corporation | Method of fabricating cylindrical bonding structure |
| US6818545B2 (en) * | 2001-03-05 | 2004-11-16 | Megic Corporation | Low fabrication cost, fine pitch and high reliability solder bump |
| US20060292851A1 (en) * | 2005-06-24 | 2006-12-28 | Mou-Shiung Lin | Circuitry component and method for forming the same |
-
2011
- 2011-01-03 TW TW100100074A patent/TWI512917B/en active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6495442B1 (en) * | 2000-10-18 | 2002-12-17 | Magic Corporation | Post passivation interconnection schemes on top of the IC chips |
| US6818545B2 (en) * | 2001-03-05 | 2004-11-16 | Megic Corporation | Low fabrication cost, fine pitch and high reliability solder bump |
| US6784087B2 (en) * | 2002-01-07 | 2004-08-31 | Megic Corporation | Method of fabricating cylindrical bonding structure |
| US6673698B1 (en) * | 2002-01-19 | 2004-01-06 | Megic Corporation | Thin film semiconductor package utilizing a glass substrate with composite polymer/metal interconnect layers |
| US20060292851A1 (en) * | 2005-06-24 | 2006-12-28 | Mou-Shiung Lin | Circuitry component and method for forming the same |
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| TW201230264A (en) | 2012-07-16 |
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