TWI510798B - Universal test platform and test method thereof - Google Patents
Universal test platform and test method thereof Download PDFInfo
- Publication number
- TWI510798B TWI510798B TW104105859A TW104105859A TWI510798B TW I510798 B TWI510798 B TW I510798B TW 104105859 A TW104105859 A TW 104105859A TW 104105859 A TW104105859 A TW 104105859A TW I510798 B TWI510798 B TW I510798B
- Authority
- TW
- Taiwan
- Prior art keywords
- port
- gate array
- logic gate
- board
- test
- Prior art date
Links
Landscapes
- Tests Of Electronic Circuits (AREA)
- Test And Diagnosis Of Digital Computers (AREA)
- For Increasing The Reliability Of Semiconductor Memories (AREA)
Description
本發明是有關於一種測試平台及其測試方法，且特別是有關於一種通用型測試平台及其測試方法。The invention relates to a test platform and a test method thereof, and in particular to a universal test platform and a test method thereof.
目前晶片廠商在對某一類晶片進行出廠前測試時，可以通過搭建專門的測試電路來實現，但是對於在研發工作中同時需要使用多塊晶片的測試者來說，逐一搭建專門的測試電路進行晶片檢測的方法過於繁瑣，效率很低，因此急需一種操作簡便、能夠提高晶片的測試效率的測試裝置。At present, wafer manufacturers can implement special test circuits by performing pre-shipment tests on certain types of wafers. However, for testers who need to use multiple wafers in research and development, build dedicated test circuits for wafers. The detection method is too cumbersome and inefficient, so there is an urgent need for a test device that is easy to operate and can improve the test efficiency of the wafer.
本發明提供一種通用型測試平台及其測試方法，可用於測試不同型號的控制器，有助於提高控制器的測試效率。The invention provides a universal test platform and a test method thereof, which can be used for testing different types of controllers, and helps to improve the test efficiency of the controller.
本發明提出一種通用型測試平台，包括主機、控制板、現場可編輯邏輯閘陣列板、多個第二連接埠、多個插座板以及多個NAND快閃記憶體。控制板電性連接至主機，且具有控制器以 及至少一多倍資料速率同步動態隨機存取記憶體以及多個第一連接埠。現場可編輯邏輯閘陣列板具有處理單元。這些第二連接埠成對設置於現場可編輯邏輯閘陣列板的相對兩側，且位於現場可編輯邏輯閘陣列板的其中一側的各個第二連接埠電性連接至對應的第一連接埠。各個插座板具有兩第三連接埠，並透過對應的前述兩第三連接埠電性連接至位於現場可編輯邏輯閘陣列板的另一側的任兩相鄰的第二連接埠。這些NAND快閃記憶體分別插接至這些插座板。The invention provides a universal test platform, which comprises a host, a control board, a field editable logic gate array board, a plurality of second ports, a plurality of socket boards and a plurality of NAND flash memories. The control board is electrically connected to the host and has a controller And at least one multiple data rate synchronous dynamic random access memory and a plurality of first ports. The field editable logic gate array board has a processing unit. The second ports are disposed in pairs on opposite sides of the field editable logic gate array board, and each of the second ports located on one side of the field editable logic gate array board is electrically connected to the corresponding first port. . Each of the socket boards has two third ports, and is electrically connected to any two adjacent second ports located on the other side of the field editable logic gate array board through the corresponding two third ports. These NAND flash memories are respectively plugged into these socket boards.
在本發明的一實施例中，上述的控制板還具有第一連接器，主機透過第一連接器電性連接至控制板。In an embodiment of the invention, the control board further has a first connector, and the host is electrically connected to the control board through the first connector.
在本發明的一實施例中，上述的第一連接埠包括多個第一測試連接埠以及第一訊號擷取連接埠。第二連接埠包括多個第二測試連接埠以及兩第二訊號擷取連接埠。第一測試連接埠與位於現場可編輯邏輯閘陣列板的其中一側的第二測試連接埠對應設置，且第一訊號擷取連接埠與位於現場可編輯邏輯閘陣列板的其中一側的第二訊號擷取連接埠對應設置。In an embodiment of the invention, the first connection port includes a plurality of first test ports and a first signal port. The second port includes a plurality of second test ports and two second signal ports. The first test port is disposed corresponding to the second test port located on one side of the field editable logic gate array board, and the first signal picking port is connected to one side of the field editable logic gate array board The second signal captures the corresponding settings.
在本發明的一實施例中，上述的第一訊號擷取連接埠與至少一多倍資料速率同步動態隨機存取記憶體電性連接。In an embodiment of the invention, the first signal extraction port is electrically connected to the at least one multiple data rate synchronous dynamic random access memory.
在本發明的一實施例中，上述的第一連接埠還包括一第監控連接埠，第二連接埠還包括兩第二監控連接埠。第一監控連接埠與位於現場可編輯邏輯閘陣列板的其中一側的第二監控連接埠對應設置。In an embodiment of the invention, the first port further includes a first monitoring port, and the second port further includes two second monitoring ports. The first monitoring port is configured corresponding to a second monitoring port located on one side of the field editable logic gate array board.
在本發明的一實施例中，上述的通用型測試平台更包括監控模組，電性連接至位於現場可編輯邏輯閘陣列板的另一側的第二監控連接埠，並透過位於現場可編輯邏輯閘陣列板的其中一側的第二監控連接埠以及第一監控連接埠而與控制板電性連接。In an embodiment of the invention, the universal test platform further includes a monitoring module electrically connected to the second monitoring port located on the other side of the field editable logic gate array board, and is editable by being located in the field. A second monitoring port on one side of the logic gate array board and a first monitoring port are electrically connected to the control board.
本發明提出一種通用型測試平台的測試方法，包括以下步驟。提供多個插座板。將多個NAND快閃記憶體電性連接至這些插座板。電性連接這些插座板與現場可編輯邏輯閘陣列板。電性連接現場可編輯邏輯閘陣列板與控制板。電性連接控制板與主機。利用主機發出指示訊號至控制板。透過控制板上的控制器將指示訊號轉換為控制訊號。將控制訊號寫入現場可編輯邏輯閘陣列板的處理單元，並透過處理單元將控制訊號分送至各個插座板，以測試各個插座板上的這些NAND快閃記憶體。The invention provides a test method for a universal test platform, which comprises the following steps. Multiple socket boards are available. A plurality of NAND flash memories are electrically connected to the socket boards. These socket boards are electrically connected to the field editable logic gate array board. Electrically connect the field to edit the logic gate array board and control board. Electrically connect the control panel to the host. Use the host to send an indication signal to the control panel. The indication signal is converted to a control signal through a controller on the control panel. The control signals are written to the processing unit of the field editable logic gate array board, and the control signals are distributed to the respective socket boards through the processing unit to test the NAND flash memories on the respective socket boards.
本發明提出一種通用型測試平台的測試方法，更包括以下步驟。電性連接監控模組與現場可編輯邏輯閘陣列板，並利用處理單元對控制訊號進行分析，且將控制訊號的分析結果顯示於監控模組。The invention provides a test method for a universal test platform, which further comprises the following steps. The electrical connection monitoring module and the field editable logic gate array board are used, and the processing signal is analyzed by the processing unit, and the analysis result of the control signal is displayed on the monitoring module.
本發明提出一種通用型測試平台的測試方法，更包括以下步驟。使各個插座板上的NAND快閃記憶體的測試結果顯示於監控模組，以與顯示於監控模組的控制訊號的分析結果進行比對。The invention provides a test method for a universal test platform, which further comprises the following steps. The test results of the NAND flash memory on each socket board are displayed on the monitoring module for comparison with the analysis results of the control signals displayed on the monitoring module.
基於上述，本發明的模組化的通用型測試平台及其測試方法可令測試者將待測試的控制器電性連接至控制板上，且將待測試的NAND快閃記憶體電性連接至於插座板上，並透過現場可 編輯邏輯閘陣列板電性連接控制板與插座板，以對多個插座板上的多個待測試的NAND快閃記憶體分別進行測試。相較於習知的測試裝置需針對不同型號的控制器逐一設計對應的線路配置，且將控制器與NAND快閃記憶體設置於同一塊電路板的技術架構而言，本實施例的模組化的通用型測試平台及其測試方法可有效提高控制器的測試效率，並大幅降低測試成本。Based on the above, the modular universal test platform and the test method thereof of the present invention enable the tester to electrically connect the controller to be tested to the control board, and electrically connect the NAND flash memory to be tested to On the socket board and through the field The logic gate array board is electrically connected to the control board and the socket board to test a plurality of NAND flash memories to be tested on the plurality of socket boards. Compared with the conventional test device, the corresponding circuit configuration is designed one by one for different types of controllers, and the technical architecture of the controller and the NAND flash memory are disposed on the same circuit board, the module of this embodiment The universal test platform and its test method can effectively improve the test efficiency of the controller and greatly reduce the test cost.
為讓本發明的上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。The above described features and advantages of the invention will be apparent from the following description.
10、20‧‧‧排線10, 20‧‧‧ cable
100‧‧‧通用型測試平台100‧‧‧Universal test platform
110‧‧‧主機110‧‧‧Host
120‧‧‧控制板120‧‧‧Control panel
121‧‧‧控制器121‧‧‧ Controller
122‧‧‧多倍資料速率同步動態隨機存取記憶體122‧‧‧Multiple data rate synchronous dynamic random access memory
123‧‧‧第一連接埠123‧‧‧First connection埠
123a‧‧‧第一測試連接埠123a‧‧‧First Test Connection埠
123b‧‧‧第一訊號擷取連接埠123b‧‧‧First signal capture port
123c‧‧‧第一監控連接埠123c‧‧‧First Monitoring Connection埠
124‧‧‧第一連接器124‧‧‧First connector
130‧‧‧現場可編輯邏輯閘陣列板130‧‧‧Field editable logic gate array board
131‧‧‧處理單元131‧‧‧Processing unit
140、141‧‧‧第二連接埠140, 141‧‧‧Second connection埠
140a、141a‧‧‧第二測試連接埠140a, 141a‧‧‧Second test connection埠
140b、141b‧‧‧第二訊號擷取連接埠140b, 141b‧‧‧second signal capture port埠
140c、141c‧‧‧第二監控連接埠140c, 141c‧‧‧Second monitoring connection埠
150‧‧‧插座板150‧‧‧Socket board
151‧‧‧第三連接埠151‧‧‧ Third connection埠
152‧‧‧插接區152‧‧‧Docking area
160‧‧‧NAND快閃記憶體160‧‧‧NAND flash memory
170‧‧‧監控模組170‧‧‧Monitoring module
S1~S10‧‧‧步驟S1~S10‧‧‧Steps
圖1是本發明一實施例的測試平台的方塊圖。1 is a block diagram of a test platform in accordance with an embodiment of the present invention.
圖2是圖1的測試平台的部分結構側視圖。2 is a side elevational view of a portion of the test platform of FIG. 1.
圖3是圖2的控制板的俯視圖。3 is a top plan view of the control board of FIG. 2.
圖4是圖2的現場可編輯邏輯閘陣列板的俯視圖。4 is a top plan view of the field editable logic gate array panel of FIG. 2.
圖5是圖2的插座板的俯視圖。Figure 5 is a top plan view of the socket plate of Figure 2;
圖6是圖1的測試平台的測試方法的流程圖。6 is a flow chart of a test method of the test platform of FIG. 1.
圖1是本發明一實施例的測試平台的方塊圖。圖2是圖1的測試平台的部分結構側視圖。圖3是圖2的控制板的俯視圖，為求清楚表示與便於說明，圖2示意地繪示出電性連接至現場可 編輯邏輯閘陣列板130的其中一個插座板150，並以虛線標示出被第二監控連接埠141c所遮擋的第二訊號擷取連接埠141b。請參考圖1至圖3，在本實施例中，通用型測試平台100包括主機110、控制板120、現場可編輯邏輯閘陣列板130、多個第二連接埠140與141、多個插座板150以及多個NAND快閃記憶體160，其中主機110可以是桌上型電腦或筆記型電腦，並可透過排線10連接到控制板120的第一連接器124，例如SATA或PCIe匯流排界面。1 is a block diagram of a test platform in accordance with an embodiment of the present invention. 2 is a side elevational view of a portion of the test platform of FIG. 1. Figure 3 is a plan view of the control board of Figure 2, for clarity and convenience of illustration, Figure 2 schematically shows the electrical connection to the site One of the socket boards 150 of the logic gate array board 130 is edited, and the second signal extraction port 141b blocked by the second monitoring port 141c is indicated by a broken line. Referring to FIG. 1 to FIG. 3, in the embodiment, the universal test platform 100 includes a host 110, a control board 120, a field editable logic gate array board 130, a plurality of second ports 140 and 141, and a plurality of socket boards. 150 and a plurality of NAND flash memories 160, wherein the host 110 can be a desktop computer or a notebook computer, and can be connected to the first connector 124 of the control board 120 through the cable 10, such as a SATA or PCIe bus interface. .
詳細而言，控制板120可具有控制器121、兩個多倍資料速率同步動態隨機存取記憶體(DDRx SDRAM)122以及多個第一連接埠123，其中控制器121例如是SSD控制器，且分別與多倍資料速率同步動態隨機存取記憶體122、第一連接埠123以及第一連接器124電性連接。因此，主機110可經由第一連接器124電性連接至控制器121，以與控制器121進行NAND快閃記憶體160的控制與存取。另一方面，多倍資料速率同步動態隨機存取記憶體122例如是雙倍資料速率同步動態隨機存取記憶體、三倍資料速率同步動態隨機存取記憶體、四倍資料速率同步動態隨機存取記憶體或更高倍數之資料速率同步動態隨機存取記憶體，本發明對此不加以限制。In detail, the control board 120 may have a controller 121, two multiple data rate synchronous dynamic random access memory (DDRx SDRAM) 122, and a plurality of first ports 123, wherein the controller 121 is, for example, an SSD controller. And electrically connected to the multiple data rate synchronous dynamic random access memory 122, the first connection port 123, and the first connector 124, respectively. Therefore, the host 110 can be electrically connected to the controller 121 via the first connector 124 to perform control and access of the NAND flash memory 160 with the controller 121. On the other hand, the multiple data rate synchronous dynamic random access memory 122 is, for example, double data rate synchronous dynamic random access memory, triple data rate synchronous dynamic random access memory, quadruple data rate synchronous dynamic random access memory. The data rate synchronization memory dynamic random access memory is taken from a memory or a higher multiple, which is not limited in the present invention.
圖4是圖2的現場可編輯邏輯閘陣列板的俯視圖。請參考圖2至圖4，現場可編輯邏輯閘陣列板130可作為控制板120與這些插座板150的連接媒介，其中成對設置於現場可編輯邏輯閘陣列板130的相對兩側的這些第二連接埠140與141即作為其 主要的連接介面。詳細而言，第一連接埠123可包括多個第一測試連接埠123a以及第一訊號擷取連接埠123b，而第二連接埠140可包括多個第二測試連接埠140a以及第二訊號擷取連接埠140b，其中第一測試連接埠123a與第二測試連接埠140a對應設置，且第一訊號擷取連接埠123b與第二訊號擷取連接埠140b對應設置。4 is a top plan view of the field editable logic gate array panel of FIG. 2. Referring to FIG. 2 to FIG. 4, the field editable logic gate array board 130 can serve as a connection medium between the control board 120 and the socket boards 150, and these pairs are disposed in pairs on opposite sides of the field editable logic gate array board 130. Two ports 140 and 141 are used as their The main connection interface. In detail, the first port 123 may include a plurality of first test ports 123a and a first signal port 123b, and the second port 140 may include a plurality of second test ports 140a and a second signal The connection port 140b is configured, wherein the first test port 123a is disposed corresponding to the second test port 140a, and the first signal port connection 123b is disposed corresponding to the second signal port connection 140b.
相似地，第二連接埠141亦可包括多個第二測試連接埠141a以及第二訊號擷取連接埠141b，其中第二測試連接埠140a與141a成對設置於現場可編輯邏輯閘陣列板130的相對兩側，且第二訊號擷取連接埠140b與141b成對設置於現場可編輯邏輯閘陣列板130的相對兩側。此處，現場可編輯邏輯閘陣列板130中面向控制板120的這一側的各個第二測試連接埠140a會插接至對應的第一測試連接埠123a，而各個第二訊號擷取連接埠140b會插接至對應的第一訊號擷取連接埠123b，以電性連接現場可編輯邏輯閘陣列板130與控制板120。在未繪示的實施例中，亦可透過排線或其他適當的連接線來連接各個第二測試連接埠140a與對應的第一測試連接埠123a以及連接各個第二訊號擷取連接埠140b與對應的第一訊號擷取連接埠123b，本發明對此並不加以限制。Similarly, the second port 141 can also include a plurality of second test ports 141a and a second signal port 141b, wherein the second test ports 140a and 141a are disposed in pairs on the field editable logic gate array plate 130. On opposite sides of the field, the second signal extraction ports 140b and 141b are disposed in pairs on opposite sides of the field editable logic gate array board 130. Here, each of the second test ports 140a of the field editable logic gate array board 130 facing the side of the control board 120 is plugged into the corresponding first test port 123a, and each second signal port is connected. The 140b is plugged into the corresponding first signal capture port 123b to electrically connect the field editable logic gate array board 130 and the control board 120. In an embodiment not shown, each of the second test ports 140a and the corresponding first test port 123a and the second signal port 140b can be connected to each other through a cable or other suitable connecting line. The corresponding first signal capture port 123b, which is not limited by the present invention.
圖5是圖2的插座板的俯視圖。請參考圖1、圖2與圖5，各個插座板150可具有兩個第三連接埠151以及多個插接區(或稱插座)152，其中這些NAND快閃記憶體160分別插接至這些插接區152，且各個插座板150上的NAND快閃記憶體160皆位於第三連接埠151的同一側。由於NAND快閃記憶體160例如是可插 拔地組裝於插座板150上的插接區(或稱插座)152，因此在NAND快閃記憶體160受測結束後，其可輕易地自插接區(或稱插座)152拔除，無需解焊也不會有膠體殘留的問題產生，故可防止損傷NAND快閃記憶體160的結構。具體來說，各個插座板150是透過對應的兩個第三連接埠151插接至現場可編輯邏輯閘陣列板130中背向控制板120的這一側的任兩相鄰的第二測試連接埠141a，以使控制器121可透過第一測試連接埠123a、第二測試連接埠140a與141a以及第三連接埠151電性連接至各個插座板150上的NAND快閃記憶體160。並且，控制器121所發出的控制訊號可經由第一測試連接埠123a與第二測試連接埠140a傳送至現場可編輯邏輯閘陣列板130上的處理單元131，以進行訊號分析。Figure 5 is a top plan view of the socket plate of Figure 2; Referring to FIG. 1, FIG. 2 and FIG. 5, each socket board 150 may have two third ports 151 and a plurality of plug-in areas (or sockets) 152, wherein the NAND flash memories 160 are respectively connected to these The NAND flash memory 160 on each of the socket boards 150 is located on the same side of the third port 151. Since the NAND flash memory 160 is, for example, pluggable The plug-in area (or socket) 152 is assembled on the socket board 150. Therefore, after the NAND flash memory 160 is tested, it can be easily removed from the docking area (or socket) 152 without solution. There is no problem of colloidal residue in the soldering, so that the structure of the NAND flash memory 160 can be prevented from being damaged. Specifically, each of the socket boards 150 is plugged into the two adjacent second test connections on the side of the field editable logic gate array board 130 that faces away from the control board 120 through the corresponding two third ports 151. The 141a is configured to enable the controller 121 to be electrically connected to the NAND flash memory 160 on each of the socket boards 150 through the first test port 123a, the second test ports 140a and 141a, and the third port 151. Moreover, the control signal sent by the controller 121 can be transmitted to the processing unit 131 on the field editable logic gate array board 130 via the first test port 123a and the second test port 140a for signal analysis.
另一方面，第一訊號擷取連接埠123b會與各個多倍資料速率同步動態隨機存取記憶體122電性連接，藉以擷取各個多倍資料速率同步動態隨機存取記憶體122的時脈訊號。在本實施例中，第一連接埠123還包括第一監控連接埠123c，第二連接埠140還包括對應於第一監控連接埠123c而設置的第二監控連接埠140c，相似地，第二連接埠141還包括對應於第二監控連接埠140c而設置的第二監控連接埠141c。由於第一監控連接埠123c與現場可編輯邏輯閘陣列板130中面向監控板120的第二監控連接埠140c對應設置，因此在將第二監控連接埠140c插接至第一監控連接埠123c後，第一監控連接埠123c可透過第二監控連接埠140c而電性連接至第二監控連接埠141c，並透過第二監控連接埠141c 電性連接至監控模組170。此處，第二監控連接埠141c與監控模組170之間的電性連接例如是透過排線20以達成。換句話說，控制器121傳送至現場可編輯邏輯閘陣列板130上的處理單元131的控制訊號經分析後，可將其分析結果經由第二監控連接埠141c傳送至監控模組170並顯示於其上。此外，控制器121所發出的控制訊號亦會轉寫至處理單元131，再經由處理單元131快速地透過第二測試連接埠141a分送至各個插座板150(如圖1與圖2所示)，以對各個插座板150上的NAND快閃記憶體160進行測試。對NAND快閃記憶體160進行測試後的測試結果會先回傳至現場可編輯邏輯閘陣列板130，再經由第二監控連接埠141c傳送至監控模組170並顯示於其上。因此，測試者可在監控模組170同時觀察到控制器121所發出的控制訊號的分析結果以及NAND快閃記憶體160的測試結果，以便於進行比對並分析靭體設計的準確性，或者是在必要時進行除錯的動作。On the other hand, the first signal capture port 123b is electrically connected to each of the multiple data rate synchronous DRAMs 122, so as to capture the clocks of the multiple data rate synchronous DRAMs 122. Signal. In this embodiment, the first port 123 further includes a first monitoring port 123c, and the second port 140 further includes a second monitoring port 140c corresponding to the first monitoring port 123c. Similarly, the second port The port 141 also includes a second monitoring port 141c that is provided corresponding to the second monitoring port 140c. Since the first monitoring port 123c is correspondingly disposed with the second monitoring port 140c facing the monitoring board 120 in the field editable logic gate array board 130, after the second monitoring port 140c is plugged to the first monitoring port 123c The first monitoring port 123c can be electrically connected to the second monitoring port 141c through the second monitoring port 140c and through the second monitoring port 141c. Electrically connected to the monitoring module 170. Here, the electrical connection between the second monitoring port 141c and the monitoring module 170 is achieved, for example, through the cable 20. In other words, after the control signal transmitted from the controller 121 to the processing unit 131 on the field editable logic gate array board 130 is analyzed, the analysis result can be transmitted to the monitoring module 170 via the second monitoring port 141c and displayed on the control signal. On it. In addition, the control signals sent by the controller 121 are also transferred to the processing unit 131, and then quickly distributed to the respective socket boards 150 via the second test connection port 141a via the processing unit 131 (as shown in FIG. 1 and FIG. 2). The NAND flash memory 160 on each of the socket boards 150 is tested. The test result after testing the NAND flash memory 160 is first transmitted back to the field editable logic gate array board 130, and then transmitted to the monitoring module 170 via the second monitoring port 141c and displayed thereon. Therefore, the tester can simultaneously observe the analysis result of the control signal sent by the controller 121 and the test result of the NAND flash memory 160 in the monitoring module 170, so as to compare and analyze the accuracy of the firmware design, or It is an action to debug when necessary.
簡言之，模組化的通用型測試平台100的設計，可令測試者將待測試的控制器121電性連接至控制板120上，且將待測試的NAND快閃記憶體160電性連接至於插座板150上，並透過現場可編輯邏輯閘陣列板130電性連接控制板120與插座板150，以對多個插座板150上的多個待測試的NAND快閃記憶體160分別進行測試。相較於習知的測試裝置需針對不同型號的控制器逐一設計對應的線路配置，且將控制器與NAND快閃記憶體設置於同一塊電路板的技術架構而言，本實施例的模組化的通用型測試 平台100可有效提高控制器121的測試效率，並大幅降低測試成本。In short, the modular general-purpose test platform 100 is designed to electrically connect the controller 121 to be tested to the control board 120, and electrically connect the NAND flash memory 160 to be tested. As for the socket board 150, the control board 120 and the socket board 150 are electrically connected through the field editable logic gate array board 130 to test a plurality of NAND flash memory 160 to be tested on the plurality of socket boards 150 respectively. . Compared with the conventional test device, the corresponding circuit configuration is designed one by one for different types of controllers, and the technical architecture of the controller and the NAND flash memory are disposed on the same circuit board, the module of this embodiment Universal test The platform 100 can effectively improve the test efficiency of the controller 121 and greatly reduce the test cost.
圖6是圖1的測試平台的測試方法的流程圖。請參考圖6並配合上述圖式，通用型測試平台100的測試方法需先進行步驟S1與S2，提供插座板150，並將多個NAND快閃記憶體160分別電性連接至插座板150。接著，進行步驟S3，電性連接插座板150與現場可編輯邏輯閘陣列板130。接著，進行步驟S4，電性連接現場可編輯邏輯閘陣列板130與控制板120。接著，進行步驟S5，電性連接控制板120與主機110。接著，進行步驟S6，電性連接監控模組170與現場可編輯邏輯閘陣列板130。接著，進行步驟S7，利用主機110發出指示訊號至控制板120的控制器121，並透過控制器121將指示訊號轉換為控制訊號。接著，進行步驟S8，將控制訊號寫入現場可編輯邏輯閘陣列板130的處理單元131，並透過處理單元131將控制訊號分送至各個插座板150，以測試各個插座板150上的NAND快閃記憶體160。在進行步驟S8的同時，進行步驟S9，利用處理單元131對控制訊號進行分析，並將控制訊號的分析結果顯示於監控模組170。最後，在步驟S10中，使各個插座板150上的NAND快閃記憶體160的測試結果顯示於監控模組170，以與顯示於監控模組170的控制訊號的分析結果進行比對。6 is a flow chart of a test method of the test platform of FIG. 1. Referring to FIG. 6 and the above diagram, the test method of the universal test platform 100 needs to perform steps S1 and S2 first, provide the socket board 150, and electrically connect the plurality of NAND flash memories 160 to the socket board 150, respectively. Next, proceeding to step S3, the socket board 150 and the field editable logic gate array board 130 are electrically connected. Then, step S4 is performed to electrically connect the field editable logic gate array board 130 and the control board 120. Then, in step S5, the control board 120 and the host 110 are electrically connected. Then, in step S6, the monitoring module 170 and the field editable logic gate array board 130 are electrically connected. Next, in step S7, the host 110 sends an instruction signal to the controller 121 of the control board 120, and the controller 121 converts the indication signal into a control signal. Then, in step S8, the control signal is written into the processing unit 131 of the field editable logic gate array board 130, and the control signal is distributed to the respective socket boards 150 through the processing unit 131 to test the NAND fast on each socket board 150. Flash memory 160. At the same time as step S8, step S9 is performed, the control signal is analyzed by the processing unit 131, and the analysis result of the control signal is displayed on the monitoring module 170. Finally, in step S10, the test results of the NAND flash memory 160 on each of the socket boards 150 are displayed on the monitoring module 170 for comparison with the analysis results of the control signals displayed on the monitoring module 170.
綜上所述，本發明的模組化的通用型測試平台及其測試方法可令測試者將待測試的控制器電性連接至控制板上，且將待 測試的NAND快閃記憶體電性連接至於插座板上，並透過現場可編輯邏輯閘陣列板電性連接控制板與插座板，以對多個插座板上的多個待測試的NAND快閃記憶體分別進行測試。相較於習知的測試裝置需針對不同型號的控制器逐一設計對應的線路配置，且將控制器與NAND快閃記憶體設置於同一塊電路板的技術架構而言，本實施例的模組化的通用型測試平台及其測試方法可有效提高控制器的測試效率，並大幅降低測試成本。In summary, the modular universal test platform and the test method thereof of the present invention enable the tester to electrically connect the controller to be tested to the control board, and will be The tested NAND flash memory is electrically connected to the socket board, and is electrically connected to the control board and the socket board through the field editable logic gate array board, so as to scan a plurality of NAND flash memories to be tested on the plurality of socket boards. The body is tested separately. Compared with the conventional test device, the corresponding circuit configuration is designed one by one for different types of controllers, and the technical architecture of the controller and the NAND flash memory are disposed on the same circuit board, the module of this embodiment The universal test platform and its test method can effectively improve the test efficiency of the controller and greatly reduce the test cost.
雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明的精神和範圍內，當可作些許的更動與潤飾，故本發明的保護範圍當視後附的申請專利範圍所界定者為準。Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.
10、20‧‧‧排線10, 20‧‧‧ cable
100‧‧‧通用型測試平台100‧‧‧Universal test platform
110‧‧‧主機110‧‧‧Host
120‧‧‧控制板120‧‧‧Control panel
130‧‧‧現場可編輯邏輯閘陣列板130‧‧‧Field editable logic gate array board
150‧‧‧插座板150‧‧‧Socket board
170‧‧‧監控模組170‧‧‧Monitoring module
Claims (8)
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW104105859A TWI510798B (en) | 2015-02-24 | 2015-02-24 | Universal test platform and test method thereof |
| JP2015088847A JP6033913B2 (en) | 2015-02-24 | 2015-04-24 | Universal test platform and test method thereof |
| CN201510230525.9A CN106199374A (en) | 2015-02-24 | 2015-05-08 | Universal test platform and test method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW104105859A TWI510798B (en) | 2015-02-24 | 2015-02-24 | Universal test platform and test method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| TWI510798B true TWI510798B (en) | 2015-12-01 |
| TW201631325A TW201631325A (en) | 2016-09-01 |
Family
ID=55407752
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW104105859A TWI510798B (en) | 2015-02-24 | 2015-02-24 | Universal test platform and test method thereof |
Country Status (3)
| Country | Link |
|---|---|
| JP (1) | JP6033913B2 (en) |
| CN (1) | CN106199374A (en) |
| TW (1) | TWI510798B (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI510798B (en) * | 2015-02-24 | 2015-12-01 | Powertech Technology Inc | Universal test platform and test method thereof |
| CN109323716B (en) * | 2018-11-01 | 2023-12-29 | 上海电气集团自动化工程有限公司 | Detection and debugging device for serial absolute encoder of servo driving system |
| CN112509631A (en) * | 2020-12-25 | 2021-03-16 | 东莞记忆存储科技有限公司 | Batch testing system and method for quality of storage particles, computer equipment and storage medium |
| US11698408B2 (en) | 2021-08-26 | 2023-07-11 | Western Digital Technologies, Inc. | Testing apparatus for data storage devices |
| US11828793B2 (en) | 2021-08-26 | 2023-11-28 | Western Digital Technologies, Inc. | Testing apparatus for temperature testing of electronic devices |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW200828325A (en) * | 2006-12-18 | 2008-07-01 | Golden Emperor Internat Ltd | System and method for testing memories |
| TW201126528A (en) * | 2010-01-20 | 2011-08-01 | King Yuan Electronics Co Ltd | Memory test equipment with extensible sample memory |
| CN102201267A (en) * | 2010-03-26 | 2011-09-28 | 上海摩波彼克半导体有限公司 | Platform system for realizing circuit verification of Nandflash flash memory controller based on FPGA (Field Programmable Gate Array) and method thereof |
| CN102332311A (en) * | 2011-10-18 | 2012-01-25 | 中国航天科技集团公司第五研究院第五一〇研究所 | FPGA (Field Programmable Gate Array)-based single event effect test method for NAND FLASH device |
| TW201310458A (en) * | 2011-08-26 | 2013-03-01 | Powertech Technology Inc | Testing interface board specially for DRAM memory packages |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08146080A (en) * | 1994-11-28 | 1996-06-07 | Sumitomo Electric Ind Ltd | Burn-in board |
| KR100548103B1 (en) * | 1998-12-31 | 2006-02-02 | 폼팩터, 인크. | Test method and assembly including a test die for testing a semiconductor product die |
| CN1609862A (en) * | 2004-11-19 | 2005-04-27 | 华南理工大学 | IP nuclear simulation confirmation platform based on PCI bus and proving method thereof |
| CN101334448B (en) * | 2008-05-23 | 2012-07-04 | 深圳市同洲电子股份有限公司 | Test platform and method for testing PC board |
| CN103809106A (en) * | 2012-11-15 | 2014-05-21 | 佛山市顺德区顺达电脑厂有限公司 | Automatic test device and method |
| TWI510798B (en) * | 2015-02-24 | 2015-12-01 | Powertech Technology Inc | Universal test platform and test method thereof |
-
2015
- 2015-02-24 TW TW104105859A patent/TWI510798B/en not_active IP Right Cessation
- 2015-04-24 JP JP2015088847A patent/JP6033913B2/en not_active Expired - Fee Related
- 2015-05-08 CN CN201510230525.9A patent/CN106199374A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW200828325A (en) * | 2006-12-18 | 2008-07-01 | Golden Emperor Internat Ltd | System and method for testing memories |
| TW201126528A (en) * | 2010-01-20 | 2011-08-01 | King Yuan Electronics Co Ltd | Memory test equipment with extensible sample memory |
| CN102201267A (en) * | 2010-03-26 | 2011-09-28 | 上海摩波彼克半导体有限公司 | Platform system for realizing circuit verification of Nandflash flash memory controller based on FPGA (Field Programmable Gate Array) and method thereof |
| TW201310458A (en) * | 2011-08-26 | 2013-03-01 | Powertech Technology Inc | Testing interface board specially for DRAM memory packages |
| CN102332311A (en) * | 2011-10-18 | 2012-01-25 | 中国航天科技集团公司第五研究院第五一〇研究所 | FPGA (Field Programmable Gate Array)-based single event effect test method for NAND FLASH device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN106199374A (en) | 2016-12-07 |
| JP6033913B2 (en) | 2016-11-30 |
| TW201631325A (en) | 2016-09-01 |
| JP2016156798A (en) | 2016-09-01 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| TWI510798B (en) | Universal test platform and test method thereof | |
| US9535117B2 (en) | System debug using an all-in-one connector | |
| JP2015025805A (en) | High-speed tester communication interface between test slice and tray | |
| TWI445974B (en) | Test system and method for ports with multi functions | |
| US20140164858A1 (en) | Testing apparatus and testing method of electronic device | |
| US11828787B2 (en) | Eye diagram capture test during production | |
| TW201316342A (en) | Method for testing parameters of memory bank and testing device | |
| TW201710699A (en) | Detecting apparatus for CPU slot connection of motherboard based on boundary scan and method thereof | |
| US20190163596A1 (en) | Functional testing of high-speed serial links | |
| WO2021238276A1 (en) | Electric leakage detection method and apparatus for cpld | |
| CN108153624B (en) | Test circuit board suitable for NGFF slot | |
| TWI759380B (en) | Pin of connector slot of circuit board conduction detection system and method thereof | |
| TWI468934B (en) | Computer motherboard testing device and testing methof thereof | |
| TWI564580B (en) | Test circuit board for usb connector testing | |
| TW201439558A (en) | Electronic apparatus, electro-static discharge detecting system and method thereof | |
| TW201502767A (en) | Detecting system and method for server motherboard | |
| TWI550295B (en) | Test circuit board for peripheral component interconnect express testing | |
| TW201710694A (en) | Testing device of address configuration signal of DIMM slot and testing method thereof | |
| TW202018509A (en) | Sas connector conduction detection system and method thereof | |
| TW201439776A (en) | Motherboard | |
| TW201312137A (en) | Test card | |
| TW201525493A (en) | Testing system for chip pins of modular chip at the same time and method thereof | |
| TWI477962B (en) | Test apparatus for testing interface of motherboard | |
| TWI459012B (en) | Testing device having plurality of connecting ports | |
| CN107783865B (en) | USB tester |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| MM4A | Annulment or lapse of patent due to non-payment of fees |