TWI509774B - A semiconductor switching device, and a method of manufacturing a semiconductor switching device - Google Patents

A semiconductor switching device, and a method of manufacturing a semiconductor switching device Download PDF

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TWI509774B
TWI509774B TW099107123A TW99107123A TWI509774B TW I509774 B TWI509774 B TW I509774B TW 099107123 A TW099107123 A TW 099107123A TW 99107123 A TW99107123 A TW 99107123A TW I509774 B TWI509774 B TW I509774B
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semiconductor
gate electrode
groove
gate
switching device
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TW201108395A (en
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Tsunekazu Saimei
Kazuya Kobayashi
Koshi Himeda
Nobuyoshi Okuda
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Murata Manufacturing Co
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    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
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    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
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    • H01L27/095—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being Schottky barrier gate field-effect transistors
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    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
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    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66848—Unipolar field-effect transistors with a Schottky gate, i.e. MESFET
    • H01L29/66856—Unipolar field-effect transistors with a Schottky gate, i.e. MESFET with an active layer made of a group 13/15 material
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
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    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
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    • H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H01L21/823456—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different shapes, lengths or dimensions
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Description

半導體開關裝置、及半導體開關裝置的製造方法
本發明係關於一種以FET(場效電晶體)等半導體元件構成開關電路等之半導體開關裝置，及半導體開關裝置之製造方法。
從第2代行動電話系統轉移至第3代行動電話系統之系統正在進展。伴隨該系統轉移，行動電話之前端部，於開關電路使用積體邏輯電路及增幅電路等之積體電路之例增加。
如此之積體電路中，不僅尋求提高開關電路單體之特性，亦尋求作為積體電路整體之***損失改善及隔離改善等之特性提高。因此，某種積體電路係將抑制型FET(以下稱為D型FET)與增強型FET(以下稱為E型FET)混載於單一半導體基板上作為半導體開關裝置之構成(例如，參照專利文獻1)。D型FET具有汲極電流開始流動時之臨限值電壓成為負值之常開特性，具有比E型FET***損失小之特徵而多用於開關電路。E型FET具有汲極電流開始流動時之臨限值電壓成為正值之常關特性，多用於增幅電路及邏輯電路。
[先前技術文獻] [專利文獻]
[專利文獻1]日本特開2005-203642號公報
第3代行動電話系統除了來自第2代行動電話系統之問題之高諧波失真(信號失真)以外，互調變失真(intermodulation distortion)亦因進入接收路徑而發生接收錯誤故而成為大問題。互調失真因存在於空中之妨害電波與發送波混雜而產生。因此第3代行動電話系統中，第2代行動電話系統中未成為問題之失真特性成為重要之特性，期望藉由減低高諧波(harmonic)失真或互調失真而改善失真特性。
本申請案發明人等發現構成開關電路之FET之電容特性之線形性對於失真特性造成大影響，因而完成本發明。
本發明之目的在於提供一種改善失真特性之構成之半導體開關裝置，及半導體開關裝置之製造方法。
本發明之半導體開關裝置，係將分別具備凹槽之複數之半導體元件例如E型FET及D型FET形成於單一之半導體基板。又，使用複數之半導體元件構成開關電路與連接於開關電路之連接電路。各半導體元件具備分別具有閘極電極、汲極電極、源極電極之閘極電極形成部、汲極電極形成部及源極電極形成部。閘極電極形成部配置於汲極電極形成部與源極電極形成部之間。開關電路以閘極電極之外形狀為矩形剖面形狀之半導體元件構成。連接電路具備閘極電極之外形狀與矩形剖面形狀不同之形狀、例如剖面V字狀或剖面T字狀等之半導體元件。
根據該構成，剖面矩形狀之閘極電極(以下稱為矩形閘極)中，浮游電容成分比剖面V字狀或剖面T字狀之閘極電極(以下稱為V型閘極及T型閘極)等有所減少。該浮游電容成分會於開關電路之關閉時殘存，成為高頻信號洩漏之原因，而使開關電路之失真特性惡化。又，矩形閘極中可形成比V型閘極或T型閘極等寬度更廣之凹槽。藉由形成寬廣凹槽，於開關電路關閉時，可緩和閘極電極與源極電極之間及閘極電極與汲極電極之間之電位梯度，而可改善D型FET之電容特性之線形性，故可提高開關電路之失真特性。
惟，若凹槽寬度增大則存在通道區域之電阻增大之虞。但，本發明於設想為對象之第3代行動電話系統中，相較於通道區域之電阻抑制，以改善失真特性為更重要之課題。因此本發明中，對於增大凹槽寬度而有效改善失真特性之開關電路，係採用凹槽寬度易增大之矩形閘極。另一方面，對於即使增大凹槽寬度對失真特性之影響亦少之連接電路，係形成V型閘極或T型閘極，而抑制E型FET之通道區域之電阻增大。又，所謂凹槽是指形成於汲極電極形成部與源極電極形成部之間之剖面凹狀之槽部，該槽部寬度即為凹槽寬度。
凹槽較好係由第1凹槽部與比第1凹槽部更深之第2凹槽部構成，且為第2凹槽部之凹槽寬度比第1凹槽部之凹槽寬狹窄之多段形狀。藉此，可進一步減少產生於凹槽之浮游電容成分，而改善半導體元件之電容特性之線形性。
較佳為，第2凹槽部之凹槽寬度相對於第1凹槽部之凹槽寬度之比，相較於具備V型閘極或T型閘極之半導體元件者，以具備矩形閘極之半導體元件者為大。藉此，可確實地改善開關電路之半導體元件之失真特性，且可抑制於連接電路中半導體元件之通道區域之電阻增大。
本發明之半導體開關裝置係於單一之半導體基板上形成有分別具備凹槽之複數之半導體元件。又，使用複數之半導體元件構成開關電路及連接於開關電路之連接電路。各半導體元件具備分別具有閘極電極、汲極電極及源極電極之閘極電極形成部、汲極電極形成部及源極電極形成部。閘極電極形成部配置於汲極電極形成部與源極電極形成部之間。凹槽係由第1凹槽部、與比第1凹槽部更深之第2凹槽部構成，且該凹槽為第2凹槽部之凹槽寬度比第1凹槽部之凹槽寬度狹窄之多段形狀。第2凹槽部之凹槽寬度相對於第1凹槽部之凹槽寬度之比，相較於構成連接電路之半導體元件者，以構成開關電路之半導體元件者為大。
藉此，可改善構成開關電路之半導體元件之電容特性之線形性。
較佳為，第2凹槽部之凹槽寬度，相較於具備與剖面形狀不同形狀之閘極電極之半導體元件者，以具備剖面矩形狀之電極之半導體元件者為寬。藉此，可進一步確實地改善開關電路之半導體元件之失真特性，同時可抑制於連接電路之半導體元件之通道區域之電阻增大。
較好於半導體基板上形成設有具備V型閘極或T型閘極之半導體元件之放大器電路。藉此，放大器電路一體化於半導體基板，而實現電路構成之高積體化及製造步驟之共通化。
本發明之製造方法係於形成V型閘極或T型閘極後形成矩形閘極。因V型閘極或T型閘極形狀複雜且製造步驟複雜而時間較長，故假若V型閘極或T型閘極之形成前形成矩形閘極，則將提高V型閘極或T型閘極之製造步驟中因熱等造成之損害波及矩形閘極之危險性。因此，製作製程藉由後形成平易之矩形閘極，可抑制損害。
根據本發明，可抑制增幅率低下或阻抗成分增加，同時可改善半導體元件之電容特性之線形性。藉此，可改善失真特性而抑制第3代行動電話系統之接收錯誤之發生等。
 <<第1實施形態>>
以下，對本發明之第1實施形態之半導體開關裝置1基於形成FET作為半導體元件之例進行說明。又本發明即使為FET之一種的HEMT(High Electron Mobility Transistor，高電子遷移率電晶體)亦可較好地實施。
圖1係半導體開關裝置1之概略剖面圖。
半導體開關裝置1具備至少包含2種半導體元件E1、D1之複數之半導體元件。此處，併置半導體元件E1與半導體元件D1之構成例例示於圖中。
半導體開關裝置1具備半導體基板2，閘極電極4A、4B，源極電極5A、5B，及汲極電極6A、6B。半導體基板2具備作為半導體層之GaAs層2A、在GaAs層2A上磊晶成長之通道層2B、在通道層2B上磊晶成長之接觸層2C。
半導體基板2具備除去接觸層2C、通道層2B及GaAs層2A之局部而形成之槽3C。槽3C區劃形成各半導體元件之區域，使GaAs層2A露出於外面。
半導體基板2具備於形成各半導體元件之區域除去接觸層2C之局部而形成之凹槽3A、3B。凹槽3A、3B使通道層2B露出於外面。
源極電極5A、5B及汲極電極6A、6B，分別形成於以接觸層2C之凹槽3A、3B之肋構成稜部之位置。源極電極5A、5B與其正下方之接觸層2C構成本發明之源極電極形成部。汲極電極6A、6B與其正下方之通道層2B構成本發明之汲極電極形成部。
閘極電極4A、4B形成於凹槽3A、3B之最底面。閘極電極4A一部分埋入於通道層2B而形成，閘極電極4B形成於通道層2B上。從閘極電極4A、4B之凹槽3A、3B之最底面突出之部位構成本發明之閘極電極形成部。
半導體元件E1係E型FET，由半導體基板2、閘極電極4A、源極電極5A及汲極電極6A構成。閘極電極4A係形成為剖面V字狀之V型閘極(以下稱為V型閘極4A)。半導體基板2中形成半導體元件E1之區域，形成凹槽3A。凹槽3A係由加工接觸層2C形成之第1凹槽部、與加工通道層2B形成之第2凹槽部而構成之剖面2段狀。第1凹槽部之凹槽寬度L1比第2凹槽部之凹槽寬度L2大。
半導體元件D1係D型FET，由半導體基板2、閘極電極4B、源極電極5B及汲極電極6B構成。閘極電極4B係形成為剖面矩形狀之矩形閘極(以下稱為矩形閘極4B)。於半導體基板2中形成半導體元件D1之區域，形成凹槽3B。凹槽3B係由加工接觸層2C形成之第1凹槽部，與加工通道層2B形成之第2凹槽部構成之剖面2段狀。第1凹槽部之凹槽寬度L1'比第2凹槽部之凹槽寬度L2'大。
本實施形態之半導體元件D1中，因採用矩形閘極4B，可減少其表面積，故與採用V型閘極或T型閘極之情形相比，可減少於半導體基板2及源極電極5B、汲極電極6B之間之浮游電容成分。又，藉由於半導體元件E1中形成寬度比凹槽寬度L2更大之凹槽寬度L2'，可緩和通道層2B之電位梯度，改善電容特性之線形性。另一方面，於半導體元件E，採用V型閘極，而抑制增幅率之降低及阻抗成分之增加。
此處，以D型FET為例對半導體元件之電容特性進行說明。
圖2(A)係顯示D型FET關閉時之源極-汲極間電容Coff與閘極-源極間電壓Vgs之關係之圖表。該圖表中，於D型FET採用矩形閘極之情形與採用V型閘極之情形進行比較顯示，閘極-源極間電壓Vgs以所謂逆方向電壓顯示。
從該圖表中可知，矩形閘極之電容Coff總是比V型閘極之電容Coff小，可抑制閘極電極與汲極電極及源極電極之間之浮游電容。
又，從該圖表中可確認，於電壓Vgs比0.8 V左右之夾斷電壓大之區域，電容Coff之變化斜率係矩形閘極比V型閘極小。可確認藉由採用矩形閘極，藉由擴大第1凹槽部之凹槽寬度，可緩和電容Coff之偏壓依存性，提高線形性。
圖2(B)係顯示源極-汲極間電容Coff，與於2段形狀之矩形閘極中第2凹槽部之凹槽寬度相對於第1凹槽部之凹槽寬度之比之L2'/L1'之關係之圖表。此處，比較顯示以閘極-源極間電壓Vgs為相同條件之數據。
從該圖表中可確認，凹槽寬度之比L2'/L1'越大，電容Coff越降低。即，可知第2凹槽部之凹槽寬度越大電容Coff越降低。
此處雖對矩形閘極中凹槽寬度之比不同之數據進行說明，但無論閘極形狀如何該關係性均成立。因此，構成開關電路之半導體元件等較好為，欲降低電容Coff之半導體元件之凹槽寬度之比，比降低其他電容Coff之必要性小之半導體元件之凹槽寬之比更大。
接著，對半導體開關裝置1之電路構成之一例進行說明。
圖3(A)係說明半導體開關裝置1之構成例之概略電路圖。半導體開關裝置1具備開關電路SW與邏輯電路LOGIC。
圖3(B)係說明開關電路SW之構成例之概略電路圖。開關電路SW由複數之半導體元件D1構成，具備輸入輸出埠PORT1、PORT2與天線埠ANT。該開關電路SW藉由輸入至控制端子之控制電壓，各半導體元件D1成為開啟狀態或關閉狀態，而選擇輸入輸出埠PORT1、PORT2之對天線埠ANT之連接。
此處，所有構成開關電路SW之半導體元件均為具備矩形閘極4B之半導體元件D1。藉此，於各半導體元件D1有關電容特性之線形性提高，開關電路SW成為具備極良好之失真特性者。
圖3(C)係說明邏輯電路LOGIC之構成例之概略電路圖。邏輯電路LOGIC由半導體元件D1與半導體元件E1構成。該邏輯電路LOGIC基於輸入至輸入埠之控制電壓Vctl將邏輯位準之電壓輸出至開關電路SW之控制端子。
此處，於邏輯電路LOGIC中，藉由設置具備V型閘極之半導體元件E1，與所有半導體元件E1之閘極電極形成部均為剖面矩形狀之情形相比，可抑制半導體元件E1之增幅率之降低及抑制阻抗成分增加。
接著，說明半導體開關裝置1之製造步驟之一例。
圖4(A)係顯示製造程序之區域分割步驟之狀態之剖面圖。
該步驟中，於區劃半導體基板2之複數之半導體元件之位置形成槽3C。具體而言，首先準備具備GaAs層2A、通道層2B及接觸層2C之平板狀半導體基板2。又，藉由蝕刻等以從接觸層2C至GaAs層2A之深度形成槽3C。該步驟結束後，移至下一歐姆電極形成步驟。
圖4(B)係顯示該製造程序中歐姆電極形成步驟之狀態之剖面圖。
該步驟中，於以槽3C區劃之各區域，形成由汲極電極6A、6B及源極電極5A、5B構成之歐姆電極。各歐姆電極藉由金屬蒸鍍法等形成。該步驟結束後，移至下一共通蝕刻步驟。
圖4(C)係顯示該製造程序中共通蝕刻步驟之狀態之剖面圖。
該步驟中，形成凹槽3A、3B各自之第1凹槽部13A、13B。具體而言，首先，以光微影術形成抗蝕膜。然後，以濕蝕刻或乾蝕刻法去除接觸層2C之局部。之後，去除抗蝕膜。該步驟結束後，移至下一E型FET蝕刻步驟。
圖4(D)係顯示該製造程序之E型FET蝕刻步驟之狀態之剖面圖。
該步驟中，形成凹槽3A之第2凹槽部13C。具體而言，首先，於半導體基板2上以光微影術形成抗蝕膜11A。於抗蝕膜11A，形成具有與V型閘極4A之下面形狀一致之錐形之抗蝕窗。接著，以光學微影術形成積層於抗蝕膜11A上之抗蝕膜11B。於抗蝕膜11B上，形成具有與V型閘極4A之俯視形狀一致之開口形狀之抗蝕窗。接著，以濕蝕刻法或乾蝕刻法等去除通道層2B之局部。該步驟結束後，移至下一E型FET閘極電極形成步驟。
圖4(E)係顯示該製造程序之E型FET閘極電極形成步驟之狀態之剖面圖。
該步驟中，形成V型閘極4A。具體而言，首先，利用前步驟形成之抗蝕膜11A、11B實施金屬蒸鍍法。接著，去除抗蝕膜11A、11B。此處，V型閘極4A之成形，係共用前步驟所利用之抗蝕膜，而削減抗蝕膜之形成程序。該步驟結束後，移至下一D型FET蝕刻步驟。
圖4(F)係顯示該製造程序之D型FET蝕刻步驟之狀態之剖面圖。
該步驟中，形成凹槽3B之第2凹槽部13D。具體而言，首先，於半導體基板2上以光微影術形成抗蝕膜11C。於抗蝕膜11C上，形成具有與矩形閘極4B之俯視形狀一致之開口形狀之抗蝕窗。接著，以濕蝕刻法或乾蝕刻法等去除通道層2B之局部。該步驟結束後，移至下一D型FET閘極電極形成步驟。
圖4(G)係顯示該製造程序之D型FET閘極電極形成步驟之狀態之剖面圖。
該步驟中，形成矩形閘極4B。具體而言，首先，利用前步驟形成之抗蝕膜11C實施金屬蒸鍍法。接著，去除抗蝕膜11C。此處，矩形閘極4B之成形，係共用前步驟所利用之抗蝕膜，而削減抗蝕膜之形成程序。
藉由以上概略之製造程序製造半導體開關裝置1。本實施形態中，因於形成製造步驟較長之V型閘極4A之後形成矩形閘極4B，故即使依次實施各類型之半導體元件之形成，亦可抑制之後形成之半導體元件之步驟對先行形成之半導體元件產生之影響。
<<第2實施形態>>
以下，對本發明之第2實施形態之半導體開關裝置21進行說明。以下說明中，對與第1實施形態相同之構成標以相同符號，省略其說明。
圖5係半導體開關裝置21之概略剖面圖。
半導體開關裝置21具備至少包含3種半導體元件E1、D1、D2之複數之半導體元件。
半導體元件D2係D型FET，由半導體基板22、閘極電極24、源極電極25及汲極電極26構成。閘極電極24係形成為V字狀之V型閘極(以下稱為V型閘極24)。於半導體基板22之形成有半導體元件D2之區域，具備去除接觸層2C之局部形成之凹槽23。凹槽23係剖面2段狀，與半導體元件E1相同尺寸之凹槽寬度。源極電極25及汲極電極26分別形成於凹槽23之肋之接觸層上。
於本實施形態之半導體元件D2藉由採用V型閘極24，比採用矩形閘極之情形，凹槽寬度L2被極小化。藉此，抑制該半導體元件D2中增寬率之降低及抑制阻抗成分增加。
接著，對半導體開關裝置1之電路構成之一例進行說明。
圖6(A)係說明半導體開關裝置1之構成例之概略電路圖。半導體開關裝置1具備開關電路SW、邏輯電路LOGIC、能量放大器PA與低雜訊放大器LNA。
圖6(B)係說明開關電路SW之構成例之概略電路圖。開關電路SW由複數之半導體元件D1構成。
此處，所有構成開關電路SW之半導體元件均係具備矩形閘極4B之半導體元件D1。藉此，各半導體元件D1之有關電容特性之線形性提高，開關電路SW成為具備極良好之失真特性者。
圖6(C)係說明邏輯電路LOGIC之構成例之概略電路圖。邏輯電路LOGIC由半導體元件D2與半導體元件E1構成。該邏輯電路LOGIC基於輸入至輸入埠之控制電壓Vctl將邏輯位準之電壓輸出至開關電路SW之控制端子。
此處，藉由以具備V型閘極之半導體元件E1、D2構成邏輯電路LOGIC，可抑制半導體元件E1、D2之增幅率之降低及抑制阻抗成分增加。
圖6(D)係說明能量放大器PA與低雜訊放大器LNA之構成例之概略電路圖。能量放大器PA與低雜訊放大器LNA由半導體元件D2構成。藉此，可抑制半導體元件D2之增幅率之降低及抑制阻抗成分增加。
<<第3實施形態>>
以下，對本發明之第3實施形態之半導體開關裝置31進行說明。以下說明中，對與第1及第2實施形態相同之構成標以相同符號，省略其說明。
圖7係半導體開關裝置31之概略剖面圖。
半導體開關裝置31具備至少包含3種半導體元件E2、D1、D3之複數之半導體元件。
半導體元件D3係D型FET，具備閘極電極34A。半導體元件E2係E型FET，具備閘極電極34B。閘極電極34A、34B係形成為剖面T字狀之T型閘極。
即使如本實施形態取代V型閘極採用T型閘極24，因與V型閘極同樣地極小化凹槽寬度，故可抑制半導體元件之增寬率之降低及抑制阻抗成分增加。
<<第4實施形態>>
以下，對本發明之第4實施形態之半導體開關裝置41進行說明。以下說明中，對與第1至第3實施形態相同之構成標以相同符號，省略其說明。
圖8係半導體開關裝置41之概略剖面圖。
半導體開關裝置41具備至少包含3種半導體元件E2、D4、D3之複數之半導體元件。
半導體元件D4係具備矩形閘極之D型FET，具備形成凹槽43之半導體基板42。凹槽43以與半導體元件D3及半導體元件E2相同尺寸之凹槽寬度構成。該半導體元件D4之構造係作為構成開關電路SW之半導體元件而採用。
如本實施形態關於凹槽寬度即使為與各半導體元件相同尺寸，藉由併用T型閘極或V型閘極與矩形閘極，可改善開關電路之失真特性。
1、21、31、41‧‧‧半導體開關裝置
2‧‧‧半導體基板
3A、3B‧‧‧凹槽
3C‧‧‧槽
4A‧‧‧閘極電極(V型閘極)
4B‧‧‧閘極電極(矩型閘極)
5A、5B‧‧‧源極電極
6A、6B‧‧‧汲極電極
E1、D1‧‧‧半導體元件
LOGIC‧‧‧邏輯電路
SW‧‧‧開關電路
圖1係本發明之第1實施形態之半導體開關裝置之概略剖面圖。
圖2(A)、(B)係圖1所示之半導體開關裝置之特性圖。
圖3(A)~(C)係圖1所示之半導體開關裝置之概略電路圖。
圖4(A)~(G)係顯示圖1所示之半導體開關裝置之製造程序之各階段狀態之剖面圖。
圖5係本發明之第2實施形態之半導體開關裝置之概略剖面圖。
圖6(A)~(C)係圖5所示之半導體開關裝置之概略電路圖。
圖7係本發明之第3實施形態之半導體開關裝置之概略剖面圖。
圖8係本發明之第4實施形態之半導體開關裝置之概略剖面圖。
1．．．半導體開關裝置
2．．．半導體基板
2A．．．GaAs層
2B．．．通道層
2C．．．接觸層
3A、3B．．．凹槽
3C．．．槽
4A．．．閘極電極(V型閘極)
4B．．．閘極電極(V型閘極)
5A、5B．．．源極電極
6A、6B．．．汲極電極
E1、D1．．．半導體元件

Claims (6)

  1. 一種半導體開關裝置，其係於半導體基板上形成分別具備凹槽之複數之半導體元件；且分別使用前述複數之半導體元件構成開關電路與連接於前述開關電路之連接電路者；各半導體元件具備：具有源極電極之源極電極形成部；具有汲極電極之汲極電極形成部；及從前述凹槽之最底面突出，且配置於前述汲極電極形成部與前述源極電極形成部之間之具有閘極電極之閘極電極形成部；其中前述開關電路係為改善失真特性而由前述閘極電極之外形狀為剖面矩形狀之半導體元件至少一個來構成；前述連接電路係為抑制阻抗值之增加而包含前述閘極電極之外形狀為與剖面矩形狀不同形狀之半導體元件至少一個；前述凹槽包含形成於前述汲極電極形成部與前述源極電極形成部之間之第1凹槽部、及於前述閘極電極形成部之周圍比前述第1凹槽部更深地形成之第2凹槽部，且前述凹槽係前述第2凹槽部之凹槽寬度比前述第1凹槽部之凹槽寬度窄之多段形狀；相較於包含與剖面矩形狀不同形狀之前述閘極電極之半導體元件，在包含剖面矩形狀之前述閘極電極之半導體元件上，前述第2凹槽部之凹槽寬度相對於前述第1凹 槽部之凹槽寬度之比為較大；且前述開關電路之前述閘極電極的前述第2凹槽部側之端部與前述第2凹槽部之端部的間隔係較前述連接電路之前述閘極電極的前述第2凹槽部側之端部與前述第2凹槽部之端部的間隔大。
  2. 如請求項1之半導體開關裝置，其中前述第2凹槽部之凹槽寬度，相較於具備與剖面形狀不同形狀之前述閘極電極之半導體元件者，以具備剖面矩形狀之前述閘極電極之半導體元件者為寬。
  3. 如請求項1之半導體開關裝置，其中構成前述開關電路之半導體元件係抑制型FET。
  4. 如請求項2之半導體開關裝置，其中構成前述開關電路之半導體元件係抑制型FET。
  5. 如請求項1至4中任一項之半導體開關裝置，其中進而於前述半導體基板上形成放大器電路，該放大器電路設有前述閘極電極之外形狀為與剖面矩形狀不同形狀之半導體元件。
  6. 一種半導體開關裝置之製造方法，其係如請求項1至5中任一項之半導體開關裝置之製造方法，且該製造方法係於形成外形狀為與剖面矩形狀不同形狀之前述閘極電極之步驟後，進行形成外形狀為剖面矩形狀之前述閘極電極之步驟。
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Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9202906B2 (en) 2013-03-14 2015-12-01 Northrop Grumman Systems Corporation Superlattice crenelated gate field effect transistor
TWI615977B (zh) * 2013-07-30 2018-02-21 高效電源轉換公司 具有匹配臨界電壓之積體電路及其製造方法

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06216327A (ja) * 1993-01-18 1994-08-05 Oki Electric Ind Co Ltd 半導体装置の製造方法
TW200520227A (en) * 2003-11-24 2005-06-16 Triquint Semiconductor Inc Monolithic integrated enhancement mode and depletion mode field effect transistors and method of making the same

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5519881A (en) * 1978-07-28 1980-02-12 Mitsubishi Electric Corp Fieldeffect transistor
JPS63299514A (ja) 1987-05-29 1988-12-07 Matsushita Electric Ind Co Ltd 半導体集積回路
JP2719142B2 (ja) * 1988-01-22 1998-02-25 三菱電機株式会社 電界効果トランジスタ
JPH065323B2 (ja) * 1989-12-28 1994-01-19 ホーヤ株式会社 ポリチオール化合物を用いて得られた光学材料及び光学製品
JPH08111424A (ja) * 1994-10-11 1996-04-30 Mitsubishi Electric Corp 半導体装置の製造方法
JPH1140578A (ja) * 1997-07-18 1999-02-12 Mitsubishi Electric Corp 半導体装置及びその製造方法
JP2000277703A (ja) 1999-03-25 2000-10-06 Sanyo Electric Co Ltd スイッチ回路装置
JP2002134736A (ja) 2000-10-24 2002-05-10 Fujitsu Ltd 電界効果型化合物半導体装置及びその製造方法
US6703638B2 (en) 2001-05-21 2004-03-09 Tyco Electronics Corporation Enhancement and depletion-mode phemt device having two ingap etch-stop layers
JP4064800B2 (ja) 2002-12-10 2008-03-19 株式会社東芝 ヘテロ接合型化合物半導体電界効果トランジスタ及びその製造方法
JP4230370B2 (ja) * 2004-01-16 2009-02-25 ユーディナデバイス株式会社 半導体装置及びその製造方法
US20050206439A1 (en) * 2004-03-22 2005-09-22 Triquint Semiconductor, Inc. Low quiescent current radio frequency switch decoder
JP2007194411A (ja) * 2006-01-19 2007-08-02 Sanyo Electric Co Ltd スイッチ集積回路装置およびその製造方法
JP2008034406A (ja) 2006-06-30 2008-02-14 Sony Corp スイッチ半導体集積回路装置
GB2449514B (en) * 2007-01-26 2011-04-20 Filtronic Compound Semiconductors Ltd A diode assembly
JP2008263146A (ja) 2007-04-13 2008-10-30 Matsushita Electric Ind Co Ltd 半導体装置およびその製造方法

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06216327A (ja) * 1993-01-18 1994-08-05 Oki Electric Ind Co Ltd 半導体装置の製造方法
TW200520227A (en) * 2003-11-24 2005-06-16 Triquint Semiconductor Inc Monolithic integrated enhancement mode and depletion mode field effect transistors and method of making the same

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