TWI505503B

TWI505503B - Vertical led chip structure and method of manufacturing the same

Info

Publication number: TWI505503B
Application number: TW099140678A
Authority: TW
Inventors: Chia Hui Shen; Tzu Chien Hung
Original assignee: Advanced Optoelectronic Tech
Priority date: 2010-11-25
Filing date: 2010-11-25
Publication date: 2015-10-21
Also published as: TW201222870A

Description

垂直結構發光二極體晶片及其製造方法 Vertical structure light emitting diode chip and manufacturing method thereof

本發明涉及一種晶片，特別係指一種垂直結構發光二極體晶片及其製造方法。 The present invention relates to a wafer, and more particularly to a vertical structure light emitting diode wafer and a method of fabricating the same.

發光二極體憑藉其高光效、低能耗、無污染等優點，已被應用於越來越多之場合之中，大有取代傳統光源之趨勢。 Light-emitting diodes have been used in more and more occasions due to their high luminous efficiency, low energy consumption, and no pollution. They have a tendency to replace traditional light sources.

發光二極體晶片作為發光二極體中最為核心之部分，其發光效率之高低直接決定了發光二極體輸出光通量之大小。然而，習知之發光二極體晶片在設計上仍存在諸多問題，嚴重影響到整個發光二極體之輸出亮度。特別地，由於發光機制之原因，直接自發光二極體晶片輸出之光基本都呈無序之放射狀，光線不能有效地被聚集，從而導致發光二極體晶片之亮度受到限制。 The light-emitting diode chip is the core part of the light-emitting diode, and the luminous efficiency directly determines the output luminous flux of the light-emitting diode. However, the conventional light-emitting diode chip still has many problems in design, which seriously affects the output brightness of the entire light-emitting diode. In particular, due to the illuminating mechanism, the light directly output from the self-luminous diode chip is substantially disordered, and the light cannot be efficiently concentrated, thereby causing the brightness of the LED chip to be limited.

本發明旨在提供一種可提升發光效率之垂直結構發光二極體晶片及其製造方法。 The present invention is directed to a vertical structure light emitting diode wafer capable of improving luminous efficiency and a method of fabricating the same.

一種垂直結構發光二極體晶片，其包括導電基板及生長於導電基板上之磊晶層，該磊晶層上形成多個盲孔，每一盲孔上封蓋有聚光透鏡，所述磊晶層包括一主要發光區及設置在主要發光區周緣之次要發光區，所述盲孔均勻地、間隔地排列於所述次要發光區中，所述垂直結構發光二極體晶片還包括設置於所述磊晶層上之電極，該電極環繞所述盲孔。 A vertical structure light-emitting diode chip includes a conductive substrate and an epitaxial layer grown on the conductive substrate, wherein the epitaxial layer forms a plurality of blind holes, and each blind hole is covered with a collecting lens, the Lei The crystal layer includes a main light-emitting area and a secondary light-emitting area disposed at a periphery of the main light-emitting area, and the blind holes are uniformly and spacedly arranged in the secondary light-emitting area The vertical structure light emitting diode chip further includes an electrode disposed on the epitaxial layer, the electrode surrounding the blind hole.

一種垂直結構發光二極體晶片之製造方法，包括步驟：1)在導電基板上設置磊晶層，所述磊晶層包括一主要發光區及設置在主要發光區周緣之次要發光區；2)蝕刻磊晶層形成多個盲孔，所述盲孔均勻地、間隔地排列於所述次要發光區中，在所述磊晶層上蒸鍍形成一電極，該電極環繞所述盲孔；3)每個盲孔頂部封蓋聚光透鏡。 A method for manufacturing a vertical structure light-emitting diode chip comprises the steps of: 1) disposing an epitaxial layer on a conductive substrate, the epitaxial layer comprising a main light-emitting region and a secondary light-emitting region disposed at a periphery of the main light-emitting region; Etching the epitaxial layer to form a plurality of blind vias, the blind vias are uniformly and spacedly arranged in the secondary light-emitting region, and an electrode is formed on the epitaxial layer by evaporation, the electrode surrounding the blind via 3) The top of each blind hole is covered with a collecting lens.

上述垂直結構發光二極體晶片之盲孔頂部放置了聚光透鏡，將由盲孔頂部出射之光進行會聚，提高了垂直結構發光二極體晶片之發光效率。 A concentrating lens is placed on the top of the blind hole of the vertical structure LED chip to condense the light emitted from the top of the blind hole, thereby improving the luminous efficiency of the vertical structure LED chip.

10‧‧‧導電基板 10‧‧‧Electrical substrate

20‧‧‧磊晶層 20‧‧‧ epitaxial layer

21‧‧‧P型半導體層 21‧‧‧P type semiconductor layer

23‧‧‧半導體激發層 23‧‧‧Semiconductor excitation layer

25‧‧‧N型半導體層 25‧‧‧N type semiconductor layer

30‧‧‧電極 30‧‧‧Electrode

40‧‧‧盲孔 40‧‧‧Blind hole

50‧‧‧透鏡 50‧‧‧ lens

圖1為本發明一實施例之垂直結構發光二極體晶片之俯視圖，其中有一部分盲孔上未放置透鏡。 1 is a top plan view of a vertical structure light emitting diode wafer according to an embodiment of the present invention, in which a lens is not placed on a portion of the blind holes.

圖2為圖1所示垂直結構發光二極體晶片沿線II-II之剖面圖。 2 is a cross-sectional view of the vertical structure LED of FIG. 1 taken along line II-II.

圖3為製造本發明一實施例之垂直結構發光二極體晶片之流程。 3 is a flow chart of manufacturing a vertical structure light emitting diode chip according to an embodiment of the present invention.

以下將結合附圖對本發明作進一步之詳細說明。 The invention will be further described in detail below with reference to the accompanying drawings.

圖1和圖2示出了本發明之一實施例之垂直結構發光二極體晶片。該垂直結構發光二極體晶片包括一導電基板10、一堆疊於導電基板10上表面之磊晶層20及一設置於磊晶層上之電極30。該磊晶層 20上開設有複數相互間隔之盲孔40。每一個盲孔40之頂部放置一個透鏡50。 1 and 2 illustrate a vertical structure light emitting diode wafer in accordance with an embodiment of the present invention. The vertical structure LED chip includes a conductive substrate 10, an epitaxial layer 20 stacked on the upper surface of the conductive substrate 10, and an electrode 30 disposed on the epitaxial layer. Epitaxial layer The upper opening 20 is provided with a plurality of blind holes 40 spaced apart from each other. A lens 50 is placed on top of each blind hole 40.

所述磊晶層20包括依次堆疊於導電基板10上表面之一P型半導體層21、一半導體激發層23及一N型半導體層25。P型半導體層21及N型半導體層25用於提供流動之電子/空穴，使電子與空穴能在介於P型半導體層21及N型半導體層25之間之半導體激發層23相結合而向四周輻射出光子。在本實施例中，N型半導體層25可為N型氮化鎵層，P型半導體層21為P型氮化鎵層，半導體激發層23可為單量子阱或多量子阱層。 The epitaxial layer 20 includes a P-type semiconductor layer 21, a semiconductor excitation layer 23, and an N-type semiconductor layer 25 which are sequentially stacked on the upper surface of the conductive substrate 10. The P-type semiconductor layer 21 and the N-type semiconductor layer 25 are used to provide flowing electrons/holes, so that electrons and holes can be combined in the semiconductor excitation layer 23 interposed between the P-type semiconductor layer 21 and the N-type semiconductor layer 25. The photons are radiated to the surroundings. In this embodiment, the N-type semiconductor layer 25 may be an N-type gallium nitride layer, the P-type semiconductor layer 21 is a P-type gallium nitride layer, and the semiconductor excitation layer 23 may be a single quantum well or a multiple quantum well layer.

所述導電基板10可由氮化鎵(GaN)基板、碳化矽(SiC)、矽(Si)、銅(Cu)、鎢化銅(CuW)等導電材質所製成。該導電基板10可以係直接生長有磊晶層20之導電基板，也可以係通過蝕刻去除發光二極體晶片之原絕緣生長基板而再鍵合之新導電基板。 The conductive substrate 10 may be made of a conductive material such as a gallium nitride (GaN) substrate, tantalum carbide (SiC), bismuth (Si), copper (Cu), or copper tungsten (CuW). The conductive substrate 10 may be a conductive substrate directly grown with the epitaxial layer 20, or may be a new conductive substrate that is re-bonded by etching to remove the original insulating growth substrate of the light-emitting diode chip.

所述電極30形成於所述磊晶層20之外周緣。該電極30呈環形。在其他實施例中，該電極30可以設置在磊晶層20之其他位置，且呈其他形狀，例如，電極30在磊晶層20之中部，且呈方形。 The electrode 30 is formed on the outer periphery of the epitaxial layer 20. The electrode 30 is annular. In other embodiments, the electrode 30 can be disposed at other locations of the epitaxial layer 20 and have other shapes, for example, the electrode 30 is in the middle of the epitaxial layer 20 and is square.

在本實施例中，所述盲孔40開設於所述磊晶層20之周緣部分，形成盲孔陣列。所述電極30環繞該等盲孔40。該等盲孔40與電極30靠近。該磊晶層20之中部並沒有開設盲孔40，以形成主要發光區，磊晶層20周緣部分形成次要發光區。該盲孔40由磊晶層20之頂面延伸至P型半導體層21處。在本實施例中，盲孔40之底面延伸至P型半導體層21頂面向下一定距離，但並未延伸至P型半導體層21之底面。在其他實施例中，盲孔40可以直接延伸至P型半導體層21之底面。在本實施例中，盲孔40為圓孔，在其他實施例中，盲孔40可為方孔等其他形狀之孔。 In this embodiment, the blind hole 40 is formed in a peripheral portion of the epitaxial layer 20 to form a blind hole array. The electrode 30 surrounds the blind holes 40. The blind holes 40 are adjacent to the electrode 30. A blind hole 40 is not formed in the middle of the epitaxial layer 20 to form a main light-emitting region, and a peripheral portion of the epitaxial layer 20 forms a secondary light-emitting region. The blind via 40 extends from the top surface of the epitaxial layer 20 to the P-type semiconductor layer 21. In the present embodiment, the bottom surface of the blind via 40 extends to a certain distance from the top of the P-type semiconductor layer 21, but does not extend to the bottom surface of the P-type semiconductor layer 21. In other embodiments, the blind vias 40 may extend directly to the bottom surface of the P-type semiconductor layer 21. In this embodiment, the blind hole 40 is a circular hole. In other embodiments, The blind hole 40 may be a hole of other shapes such as a square hole.

可以理解地，為了增加垂直結構發光二極體晶片之出光效率，可以在導電基板10與P型半導體層21之間形成一層金屬反射層。 It can be understood that a metal reflective layer can be formed between the conductive substrate 10 and the P-type semiconductor layer 21 in order to increase the light-emitting efficiency of the vertical structure light-emitting diode chip.

所述透鏡50封蓋每一盲孔40之頂部，對由該盲孔40處出射之光進行會聚，如圖2所示，透鏡50將盲孔40處之磊晶層20側向發出之光線進行會聚。每一透鏡50之頂部向上凸起，底部貼設於對應盲孔40周圍之磊晶層20上。在本實施例中，透鏡50大致呈頂部凸起之方柱狀結構，在其他實施例中，透鏡50可為其他結構，只要能會聚光即可。在本實施例中，相鄰透鏡50之間緊靠在一起，以對次要發光區發出之光線進行聚光。 The lens 50 covers the top of each blind hole 40 to converge the light emitted from the blind hole 40. As shown in FIG. 2, the lens 50 illuminates the epitaxial layer 20 at the blind hole 40 laterally. Convergence. The top of each lens 50 is convex upward, and the bottom is attached to the epitaxial layer 20 around the corresponding blind hole 40. In the present embodiment, the lens 50 is substantially in the shape of a square pillar with a convex top. In other embodiments, the lens 50 may have other structures as long as it can condense light. In this embodiment, adjacent lenses 50 are in close proximity to each other to condense light from the secondary illuminating zone.

圖3示出了製造本發明之垂直結構發光二極體晶片之方法，包括如下步驟：1)提供一絕緣基板，在該絕緣基板上生長磊晶層20，該磊晶層20包括在絕緣基板上依次生長N型半導體層25、半導體激發層23及P型半導體層21；2)利用電鍍或晶圓結合技術將導電基板10與磊晶層20之P型半導體層21結合；3)利用乾式蝕刻或濕式蝕刻(例如，鐳射剝離技術)將絕緣基板與N型半導體層25分離；4)蝕刻磊晶層20之周邊部形成多個盲孔40，該等盲孔40組成一盲孔陣列；5)在每個盲孔頂部封蓋一透鏡50； 6)在磊晶層20之周緣蒸鍍形成環形電極30。 3 illustrates a method of fabricating a vertical structure light emitting diode wafer of the present invention, comprising the steps of: 1) providing an insulating substrate on which an epitaxial layer 20 is grown, the epitaxial layer 20 being included on an insulating substrate The N-type semiconductor layer 25, the semiconductor excitation layer 23, and the P-type semiconductor layer 21 are sequentially grown; 2) the conductive substrate 10 is bonded to the P-type semiconductor layer 21 of the epitaxial layer 20 by electroplating or wafer bonding technology; 3) using a dry type Etching or wet etching (for example, laser lift-off technique) separates the insulating substrate from the N-type semiconductor layer 25; 4) etching the peripheral portion of the epitaxial layer 20 to form a plurality of blind vias 40, the blind vias 40 forming a blind via array ; 5) at the top of each blind hole is covered with a lens 50; 6) A ring electrode 30 is formed by vapor deposition on the periphery of the epitaxial layer 20.

在步驟4)中，可以利用黃光顯影技術在N型半導體層25上形成一圖案化光阻層，並按照該圖案化光阻層蝕刻磊晶層20，以形成位於磊晶層20周邊部之盲孔陣列，然後去除圖案化光阻層。 In step 4), a patterned photoresist layer may be formed on the N-type semiconductor layer 25 by a yellow light developing technique, and the epitaxial layer 20 may be etched according to the patterned photoresist layer to form a peripheral portion of the epitaxial layer 20. The blind hole array is then removed from the patterned photoresist layer.

可以理解地，所述電極30可以形成於磊晶層20之中部，所述盲孔40環繞該電極30。 It can be understood that the electrode 30 can be formed in the middle of the epitaxial layer 20, and the blind hole 40 surrounds the electrode 30.

可以理解之是，對於本領域之普通技術人員來說，可以根據本發明之技術構思做出其他各種相應之改變與變形，而所有該等改變與變形都應屬於本發明申請專利範圍第項之保護範圍。 It is to be understood that various other changes and modifications can be made in accordance with the technical concept of the present invention, and all such changes and modifications should fall within the scope of the claims of the present invention. protected range.

10‧‧‧導電基板 10‧‧‧Electrical substrate

20‧‧‧磊晶層 20‧‧‧ epitaxial layer

21‧‧‧P型半導體層 21‧‧‧P type semiconductor layer

23‧‧‧半導體激發層 23‧‧‧Semiconductor excitation layer

25‧‧‧N型半導體層 25‧‧‧N type semiconductor layer

30‧‧‧電極 30‧‧‧Electrode

40‧‧‧盲孔 40‧‧‧Blind hole

50‧‧‧透鏡 50‧‧‧ lens

Claims

一種垂直結構發光二極體晶片，其包括導電基板及生長於導電基板上之磊晶層，其改良在於：該磊晶層上形成多個盲孔，每一盲孔上封蓋有聚光透鏡，所述磊晶層包括一主要發光區及設置在主要發光區周緣之次要發光區，所述盲孔均勻地、間隔地排列於所述次要發光區中，所述垂直結構發光二極體晶片還包括設置於所述磊晶層上之電極，該電極環繞所述盲孔。 A vertical structure light-emitting diode wafer comprising a conductive substrate and an epitaxial layer grown on the conductive substrate, wherein the epitaxial layer is formed with a plurality of blind holes, and each blind hole is covered with a collecting lens The epitaxial layer includes a main light-emitting region and a secondary light-emitting region disposed at a periphery of the main light-emitting region, wherein the blind holes are uniformly and spacedly arranged in the secondary light-emitting region, and the vertical structure emits two poles The bulk wafer further includes an electrode disposed on the epitaxial layer, the electrode surrounding the blind via.

如申請專利範圍第1項所述之垂直結構發光二極體晶片，其中所述聚光透鏡之頂部向上凸起，底部貼設於對應盲孔周圍之磊晶層上。 The vertical structure light-emitting diode chip of claim 1, wherein the top of the collecting lens is convex upward, and the bottom is attached to the epitaxial layer around the corresponding blind hole.

如申請專利範圍第2項所述之垂直結構發光二極體晶片，其中所述聚光透鏡在所述磊晶層上相互抵靠。 The vertical structure light emitting diode chip of claim 2, wherein the condensing lens abuts each other on the epitaxial layer.

如申請專利範圍第2項所述之垂直結構發光二極體晶片，其中所述磊晶層包括依次生長於所述導電基板上之P型半導體層、一半導體激發層及一N型半導體層，所述盲孔由磊晶層之N型半導體層延伸至P型半導體層。 The vertical structure LED chip of claim 2, wherein the epitaxial layer comprises a P-type semiconductor layer, a semiconductor excitation layer and an N-type semiconductor layer sequentially grown on the conductive substrate, The blind via extends from the N-type semiconductor layer of the epitaxial layer to the P-type semiconductor layer.

如申請專利範圍第5項所述之垂直結構發光二極體晶片之製造方法，其中在步驟1)中還包括步驟a)提供一絕緣基板，絕緣基板上依次生長磊晶層，即N型半導體層、半導體激發層及P型半導體層；步驟b)在P型半導體層上結合一導電基板；步驟c)蝕刻去除絕緣基板。 The method for manufacturing a vertical structure light-emitting diode according to claim 5, wherein the step 1) further comprises the step of: a) providing an insulating substrate, and sequentially growing an epitaxial layer on the insulating substrate, that is, an N-type semiconductor. Layer, semiconductor excitation layer and P-type semiconductor layer; step b) in P-type semiconductor A conductive substrate is bonded to the bulk layer; and step c) etching removes the insulating substrate.

如申請專利範圍第6項所述之垂直結構發光二極體晶片之製造方法，其中所述聚光透鏡之頂部向上凸起，底部貼設於對應盲孔周圍之磊晶層上。 The method for manufacturing a vertical structure light-emitting diode wafer according to claim 6, wherein the top of the collecting lens is convex upward, and the bottom is attached to the epitaxial layer around the corresponding blind hole.