TWI502895B - Clock generator - Google Patents
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Description
本發明係有關於一種時脈產生器，特別是有關於一種可補償製程變化(process mismatch)效應的時脈產生器。The present invention relates to a clock generator, and more particularly to a clock generator that compensates for the effects of process mismatch.
第1圖為習知鎖相迴路(PLL)的部分示意圖。如圖所示，相位頻率偵測器140根據一參考時脈REF及一鎖相時脈Fvco之間的相位差，產生一充電信號Up或是一放電信號Dn。當電荷幫浦100接收到充電信號Up時，開關S1導通，因此，電流源110提供一充電電流I1，對儲存單元130充電。當電荷幫浦100接收到放電信號Dn時，開關S2導通，因此，電流源120提供一放電電流I2，對儲存單元130放電。Figure 1 is a partial schematic view of a conventional phase-locked loop (PLL). As shown, the phase frequency detector 140 generates a charging signal Up or a discharging signal Dn according to a phase difference between a reference clock REF and a phase-locked clock Fvco. When the charge pump 100 receives the charging signal Up, the switch S1 is turned on. Therefore, the current source 110 provides a charging current I1 to charge the storage unit 130. When the charge pump 100 receives the discharge signal Dn, the switch S2 is turned on. Therefore, the current source 120 supplies a discharge current I2 to discharge the storage unit 130.
然而，由於製程變化(process mismatch)效應的影響，可能會造成電荷幫浦100的充放電電流不一致，因而導致鎖相迴路在鎖定後，鎖相時脈Fvco與參考時脈REF間會產生一固定的相位差。However, due to the effect of the process mismatch, the charge and discharge current of the charge pump 100 may be inconsistent, resulting in a lock between the phase-locked clock Fvco and the reference clock REF after the phase-locked loop is locked. The phase difference.
第1B及1C圖係為充放電電流不一致的示意圖。符號Vc係為儲存單元130所儲存的電壓。如第1B圖所示，當充電電流I1小於放電電流I2時，鎖相時脈Fvco將落後參考時脈REF，並且鎖相時脈Fvco與參考時脈REF間具有相位差PH1。The 1B and 1C drawings are schematic diagrams in which the charge and discharge currents do not match. The symbol Vc is the voltage stored by the storage unit 130. As shown in FIG. 1B, when the charging current I1 is smaller than the discharging current I2, the phase-locked clock Fvco will fall behind the reference clock REF, and the phase-locked clock Fvco has a phase difference PH1 with the reference clock REF.
請參考第1C圖，當充電電流I1大於放電電流I2時，鎖相時脈Fvco將領先參考時脈REF，並且鎖相時脈Fvco 與參考時脈REF間具有相位差PH2。Referring to Figure 1C, when the charging current I1 is greater than the discharging current I2, the phase-locked clock Fvco will lead the reference clock REF, and the phase-locked clock Fvco There is a phase difference PH2 with the reference clock REF.
本發明提供一種時脈產生器，包括一第一延遲單元、一第一鎖相迴路、一第一偵測單元以及一第二延遲單元。第一延遲單元延遲一參考時脈，用以產生複數前端延遲時脈。第一鎖相迴路根據前端延遲時脈之一第一前端延遲時脈及一第一回授時脈，產生一第一鎖相時脈。第一偵測單元比較前端延遲時脈及第一回授時脈，用以得知第一回授時脈與第一前端延遲時脈之間的一第一相位差，並根據第一相位差，產生一第一切換信號。第二延遲單元延遲第一鎖相時脈，產生複數第一後端延遲時脈，並根據第一切換信號，將第一後端延遲時脈之一者作為一第一輸出時脈。The present invention provides a clock generator including a first delay unit, a first phase locked loop, a first detecting unit, and a second delay unit. The first delay unit delays a reference clock to generate a complex front end delay clock. The first phase-locked loop generates a first phase-locked clock according to the first front-end delay clock and the first feedback clock of one of the front-end delay clocks. The first detecting unit compares the front end delay clock and the first feedback clock to learn a first phase difference between the first feedback clock and the first front end delay clock, and generates according to the first phase difference. A first switching signal. The second delay unit delays the first phase-locked clock, generates a plurality of first back-end delay clocks, and uses one of the first back-end delay clocks as a first output clock according to the first switching signal.
為讓本發明之特徵和優點能更明顯易懂，下文特舉出較佳實施例，並配合所附圖式，作詳細說明如下：In order to make the features and advantages of the present invention more comprehensible, the preferred embodiments are described below, and are described in detail with reference to the accompanying drawings.
第2圖係為本發明之時脈產生器之示意圖。如圖所示，時脈產生器200包括，延遲單元210、230、一鎖相迴路220以及一偵測單元240。延遲單元210延遲一參考時脈REF，用以產生複數前端延遲時脈FD1 ~F2DN 。本發明並不限定延遲單元210的內部架構。在一可能實施例中，延遲單元210具有複數緩衝器FB1 ~FB2N ，用以對參考時脈REF進行不同程度的延遲。Figure 2 is a schematic diagram of the clock generator of the present invention. As shown, the clock generator 200 includes delay units 210, 230, a phase locked loop 220, and a detecting unit 240. The delay unit 210 delays a reference clock REF for generating a complex front end delay clock F D1 ~F 2DN . The present invention does not limit the internal architecture of the delay unit 210. In a possible embodiment, the delay unit 210 has complex buffers FB 1 ~ FB 2N for different degrees of delay of the reference clock REF.
在本實施例中，第一個前端延遲時脈FD1 具有最小的延遲幅度，而最後一個前端延遲時脈F2DN 具有最大的延遲幅 度。延遲單元210將中間的前端延遲時脈FDN 提供予鎖相迴路220，但並非用以限制本發明。在其它實施例中，可將前端延遲時脈FD1 ~F2DN 之任一者提供予鎖相迴路220。In the present embodiment, the first front end delay clock F D1 has the smallest delay amplitude, and the last front end delay clock F 2DN has the largest delay amplitude. The delay unit 210 provides the intermediate front end delay clock F DN to the phase locked loop 220, but is not intended to limit the invention. In other embodiments, any of the front end delay clocks F D1 ~F 2DN may be provided to the phase locked loop 220.
鎖相迴路220根據前端延遲時脈FDN 及一回授時脈Fdiv，產生一鎖相時脈Fvco。本發明並不限定鎖相迴路220的內部電路架構。在本實施例中，鎖相迴路220包括一相位頻率偵測器221、一電荷幫浦222、一低通濾波器223、一壓控振盪器224以及一除頻器225。The phase locked loop 220 generates a phase locked clock Fvco according to the front end delay clock F DN and a feedback clock pulse Fdiv. The present invention does not limit the internal circuit architecture of the phase locked loop 220. In this embodiment, the phase locked loop 220 includes a phase frequency detector 221, a charge pump 222, a low pass filter 223, a voltage controlled oscillator 224, and a frequency divider 225.
在初始模式下，相位頻率偵測器221接收前端延遲時脈FDN ，壓控振盪器224產生一初始的振盪頻率，經除頻器225後，產生一回授時脈Fdiv。相位頻率偵測器221根據前端延遲時脈FDN 及回授時脈Fdiv間的相位差，產生充電信號Up或放電信號Dn。In the initial mode, the phase frequency detector 221 receives the front end delay clock F DN , and the voltage controlled oscillator 224 generates an initial oscillation frequency. After the frequency divider 225 , a feedback clock Fdiv is generated. The phase frequency detector 221 generates a charging signal Up or a discharging signal Dn based on the phase difference between the front end delay clock F DN and the feedback clock Fdiv.
舉例而言，當前端延遲時脈FDN 領先回授時脈Fdiv時，相位頻率偵測器221產生充電信號Up。當前端延遲時脈FDN 落後回授時脈Fdiv時，相位頻率偵測器221產生放電信號Dn。電荷幫浦222根據充電信號Up及放電信號Dn，提供一輸出電壓Vc。低通濾波器223濾除輸出電壓Vc的高頻成分。壓控振盪器224根據低通濾波器223的輸出，產生一鎖相時脈Fvco。除頻器225對鎖相時脈Fvco除頻，用以產生回授時脈Fdiv。For example, when the current end delay clock F DN leads the feedback clock Fdiv, the phase frequency detector 221 generates a charging signal Up. When the current end delay clock F DN is behind the feedback clock Fdiv, the phase frequency detector 221 generates the discharge signal Dn. The charge pump 222 provides an output voltage Vc according to the charge signal Up and the discharge signal Dn. The low pass filter 223 filters out high frequency components of the output voltage Vc. The voltage controlled oscillator 224 generates a phase locked clock Fvco based on the output of the low pass filter 223. The frequency divider 225 divides the phase-locked clock Fvco to generate a feedback clock Fdiv.
偵測單元240比較前端延遲時脈FD1 ~F2DN 及回授時脈Fdiv，用以得知回授時脈Fdiv與前端延遲時脈FDN 之間的一相位差，並根據該相位差，產生切換信號S1 ~Sm 。本發明並不限定偵測單元240的動作時間。在一可能實施例 中，偵測單元240待鎖相迴路220進入鎖定狀態後，才開始比較前端延遲時脈FD1 ~F2DN 及回授時脈Fdiv。在另一可能實施例中，在鎖相迴路220尚未進入鎖定狀態時，偵測單元240便開始動作。The detecting unit 240 compares the front end delay clocks F D1 FF 2DN and the feedback clock pulse Fdiv to know a phase difference between the feedback clock Fdiv and the front end delay clock F DN , and generates a switching according to the phase difference. Signal S 1 ~S m . The present invention does not limit the operating time of the detecting unit 240. In a possible embodiment, the detecting unit 240 starts to compare the front end delay clock F D1 ~F 2DN and the feedback clock Fdiv after the phase locked loop 220 enters the locked state. In another possible embodiment, when the phase locked loop 220 has not entered the locked state, the detecting unit 240 starts to operate.
另外，本發明並不限定偵測單元240的內部電路架構。只要能夠判斷出複數時脈與一回授時脈間的相位差的硬體電路架構，均可作為偵測單元240。在一可能實施例中，偵測單元240係以並列或是串列方式，輸出切換信號S1 ~Sm 。In addition, the present invention does not limit the internal circuit architecture of the detecting unit 240. As long as the hardware circuit structure capable of determining the phase difference between the complex clock and the feedback clock is used as the detecting unit 240. In a possible embodiment, the detecting unit 240 outputs the switching signals S 1 to S m in a side-by-side or serial manner.
延遲單元230延遲鎖相時脈Fvco，用以產生複數後端延遲時脈BD1 ~B2DN ，並根據切換信號S1 ~Sm ，將後端延遲時脈BD1 ~B2DN 之一者作為一輸出時脈OUT。本發明並不限定延遲單元230的內部架構。在一可能實施例中，延遲單元230具有緩衝器BB1 ~BB2N ，用以對鎖相時脈Fvco進行不同程度的延遲。When the delay units 230 delay lock the Fvco clock, for generating a pulse when B D1 ~ B 2DN plural rear end delay, and switching signal S 1 ~ S m, the pulse B D1 ~ 2DN by one delay as the rear end B An output clock OUT. The present invention does not limit the internal architecture of the delay unit 230. In a possible embodiment, the delay unit 230 has buffers BB 1 ~ BB 2N for different degrees of delay of the phase-locked clock Fvco.
舉例而言，當回授時脈Fdiv領先前端延遲時脈FDN 時，延遲單元230根據回授時脈Fdiv與前端延遲時脈FDN 之間的相位差，輸出延遲幅度較小的後端延遲時脈。相反地，當回授時脈Fdiv落後前端延遲時脈FDN 時，延遲單元230根據回授時脈Fdiv與前端延遲時脈FDN 之間的相位差，輸出延遲幅度較大的後端延遲時脈。因此，輸出時脈OUT與前端延遲時脈FDN 不具相位差。For example, when the feedback clock Fdiv leads the front end delay clock F DN , the delay unit 230 outputs a back end delay clock with a small delay amplitude according to the phase difference between the feedback clock Fdiv and the front end delay clock F DN . . Conversely, when the feedback clock Fdiv is behind the front end delay clock F DN , the delay unit 230 outputs a back end delay clock having a large delay amplitude according to the phase difference between the feedback clock Fdiv and the front end delay clock F DN . Therefore, the output clock OUT and the front end delay clock F DN have no phase difference.
在本實施例中，延遲單元210所產生的前端延遲時脈FD1 ~F2DN 的數量等於延遲單元230所產生的後端延遲時脈BD1 ~B2DN 的數量。在一可能實施例中，延遲單元210的佈 局(layout)位置極接近延遲單元230的佈局位置。In the present embodiment, the number of front end delay clocks F D1 ~F 2DN generated by the delay unit 210 is equal to the number of back end delay clocks B D1 ~B 2DN generated by the delay unit 230. In a possible embodiment, the layout position of the delay unit 210 is very close to the layout position of the delay unit 230.
第3圖為本發明之時脈產生器的控制時序圖。假設，前端延遲時脈FDN 與回授時脈Fdiv之間具有一相位差PH3。在本實施例中，偵測單元240將回授時脈Fdiv與前端延遲時脈FD1 ~F2DN 作比較，用以得知回授時脈Fdiv的上升邊緣係落在哪兩個前端延遲時脈的上升邊緣之間。Fig. 3 is a timing chart showing the control of the clock generator of the present invention. It is assumed that there is a phase difference PH3 between the front end delay clock F DN and the feedback clock Fdiv. In this embodiment, the detecting unit 240 compares the feedback clock Fdiv with the front end delay clock F D1 ~F 2DN to know which two front end delay clocks the rising edge of the feedback clock Fdiv falls on. Between the rising edges.
假設，經過偵測單元240的比較後可知，回授時脈Fdiv的上升邊緣係落在前端延遲時脈FDN+1 與FDN+2 的上升邊緣之間。由於回授時脈Fdiv落後前端延遲時脈FDN 兩個區間，因此，偵測單元240透過切換信號S1 ~Sm ，從後端延遲時脈BD1 ~B2DN 中，選擇延遲幅度較小的延遲時脈作為輸出時脈OUT。因此，輸出時脈OUT的上升邊緣對齊前端延遲時脈FDN 的上升邊緣，也就是說輸出時脈OUT與前端延遲時脈FDN 之間不具有相位差。It is assumed that after the comparison by the detecting unit 240, the rising edge of the feedback clock Fdiv falls between the front edge delay clocks F DN+1 and the rising edge of F DN+2 . Since the feedback clock Fdiv is behind the front end delay clock F DN , the detecting unit 240 selects the delay amplitude from the back delay pulse B D1 ~ B 2DN through the switching signals S 1 ~ S m The delay clock is used as the output clock OUT. Therefore, the rising edge of the output clock OUT is aligned with the rising edge of the front end delay clock F DN , that is, there is no phase difference between the output clock OUT and the front end delay clock F DN .
藉由設置在鎖相迴路的前端及後端的延遲單元210、230，再配合一偵測單元，便可得知回授時脈Fdiv與前端延遲時脈FDN 之間的相位差，根據該相位差，從多個後端延遲時脈中，選擇一適當的延遲時脈作為一輸出時脈，用以補償因製程變化所造成的相位差。The phase difference between the feedback clock Fdiv and the front end delay clock F DN can be known by the delay units 210 and 230 disposed at the front end and the back end of the phase locked loop, together with a detecting unit, according to the phase difference. From a plurality of back-end delay clocks, an appropriate delay clock is selected as an output clock to compensate for the phase difference caused by the process variation.
第4圖為本發明之偵測單元之一可能實施例。如圖所示，偵測單元240包括一偵測模組410以及一比較模組420。偵測模組410包括正反器FF1 ~FF2N 。正反器FF1 ~FF2N 根據前端延遲時脈FD1 ~F2DN 與回授時脈Fdiv的上升邊緣，產生輸出信號Q1 ~Q2N 。Figure 4 is a possible embodiment of a detection unit of the present invention. As shown, the detection unit 240 includes a detection module 410 and a comparison module 420. The detection module 410 includes flip-flops FF 1 -FF 2N . The flip-flops FF 1 to FF 2N generate output signals Q 1 to Q 2N according to the rising edges of the front end delay clocks F D1 to F 2DN and the feedback clock Fdiv.
在本實施例中，正反器FF1 ~FF2N 的數量與前端延遲時 脈FD1 ~F2DN 的數量相同。本發明並不限定正反器FF1 ~FF2N 的種類。在本實施例中，正反器FF1 ~FF2N 均為D型正反器。如圖所示，正反器FF1 ~FF2N 的資料端D接收回授時脈Fdiv，其時脈端接收相對應的前端延遲時脈FD1 ~F2DN ，其輸出端產生輸出信號Q1 ~Q2N 。In the present embodiment, the number of the flip-flops FF 1 to FF 2N is the same as the number of the front-end delay clocks F D1 to F 2DN . The present invention does not limit the types of the flip-flops FF 1 to FF 2N . In the present embodiment, the flip-flops FF 1 to FF 2N are all D-type flip-flops. As shown in the figure, the data terminal D of the flip-flops FF 1 ~ FF 2N receives the feedback clock Fdiv, and the clock end receives the corresponding front-end delay clock F D1 ~ F 2DN , and the output end produces an output signal Q 1 ~ Q 2N .
比較模組420包括邏輯閘LG1 ~LGm 。邏輯閘LG1 ~LGm 接收輸出信號Q1 ~Q2N ，用以產生切換信號S1 ~Sm 。本發明並不限定邏輯閘LG1 ~LGm 的種類。在本實施例中，邏輯閘LG1 ~LGm 均為互斥或閘(XOR gate)。另外，邏輯閘LG1 ~LGm 係用接收兩相鄰的輸出信號，因此，邏輯閘LG1 ~LGm 的數量少於正反器FF1 ~FF2N 的數量。The comparison module 420 includes logic gates LG 1 ~LG m . The logic gates LG 1 ~LG m receive the output signals Q 1 ~Q 2N for generating the switching signals S 1 ~S m . The present invention does not limit the types of the logic gates LG 1 to LG m . In this embodiment, the logic gates LG 1 -LG m are all XOR gates. Further, the logic gates LG 1 to LG m receive two adjacent output signals, and therefore, the number of the logic gates LG 1 to LG m is smaller than the number of the flip-flops FF 1 to FF 2N .
第5圖為本發明之時脈產生器之另一實施例。在本實施例中，時脈產生器500包括延遲單元510、530、560、鎖相迴路520、550以及偵測單元540、570。由於延遲單元510、530、鎖相迴路520以及偵測單元540的動作原理與第2圖的延遲單元210、230、鎖相迴路220以及偵測單元240相同，故不再贅述。Figure 5 is another embodiment of the clock generator of the present invention. In this embodiment, the clock generator 500 includes delay units 510, 530, 560, phase-locked loops 520, 550, and detection units 540, 570. Since the operation principles of the delay units 510 and 530, the phase-locked loop 520, and the detecting unit 540 are the same as those of the delay units 210 and 230, the phase-locked loop 220, and the detecting unit 240 of FIG. 2, they are not described again.
在一可能實施例中，鎖相迴路550內的除頻器的特性不同於鎖相迴路520內的除頻器。舉例而言，鎖相迴路550內的除頻器係為÷4，而鎖相迴路520內的除頻器係為÷8。在本實施例中，鎖相迴路550接收延遲單元510所產生的前端延遲時脈FDN ，但並非用以限制本發明。在其它實施例中，鎖相迴路550係接收延遲單元510所產生的其它前端延遲時脈。In a possible embodiment, the characteristics of the frequency divider in the phase locked loop 550 are different from the frequency dividers in the phase locked loop 520. For example, the frequency divider in the phase-locked loop 550 is ÷4, and the frequency divider in the phase-locked loop 520 is ÷8. In the present embodiment, the phase locked loop 550 receives the front end delay clock F DN generated by the delay unit 510, but is not intended to limit the present invention. In other embodiments, phase locked loop 550 receives other front end delay clocks generated by delay unit 510.
偵測單元570比較鎖相迴路550所產生的回授時脈 Fdiv2與延遲單元510所產生的前端延遲時脈FD1 ~F2DN ，用以得知回授時脈Fdiv2與前端延遲時脈FDN 之間的相位差，再根據得知結果，產生切換信號SB1 ~SBm 。The detecting unit 570 compares the feedback clock Fdiv2 generated by the phase-locked loop 550 with the front-end delay clock F D1 ~F 2DN generated by the delay unit 510 for knowing between the feedback clock Fdiv2 and the front-end delay clock F DN The phase difference is further generated based on the result of the learning, and the switching signals SB 1 to SB m are generated.
延遲單元560延遲鎖相迴路550所產生的鎖相時脈Fvco2，用以產生複數後端延遲時脈，並根據切換信號SB1 ~SBm ，從多個後端延遲時脈中，選擇一者作為輸出時脈OUT2。The delay unit 560 delays the phase-locked clock Fvco2 generated by the phase-locked loop 550 to generate a complex back-end delay clock, and selects one of the plurality of back-end delay clocks according to the switching signals SB 1 to SB m As the output clock OUT2.
在一可能實施例中，輸出時脈OUT1與OUT2的頻率相同。藉由相位差的偵測，時脈產生器500所產生的輸出時脈OUT1與OUT2之間不具有相位差。在另一可能實施例中，輸出時脈OUT1與OUT2的頻率不同，但具倍數關係。因此，每隔一固定時間，輸出時脈OUT1的上升邊緣對齊輸出時脈OUT2的上升邊緣。In a possible embodiment, the output clocks OUT1 and OUT2 have the same frequency. By the detection of the phase difference, there is no phase difference between the output clocks OUT1 and OUT2 generated by the clock generator 500. In another possible embodiment, the output clocks OUT1 and OUT2 have different frequencies but have a multiple relationship. Therefore, every other fixed time, the rising edge of the output clock OUT1 is aligned with the rising edge of the output clock OUT2.
在本實施例中，鎖相迴路520與550係共用延遲單元510，但並非用以限制本發明。在其它實施例中，鎖相迴路520與550各自具有相對應的延遲單元，分別提供一相對應的前端延遲時脈予鎖相迴路。在此例中，不同的延遲單元係對不同的參考時脈進行延遲。In the present embodiment, the phase-locked loops 520 and 550 share the delay unit 510, but are not intended to limit the present invention. In other embodiments, the phase-locked loops 520 and 550 each have a corresponding delay unit, respectively providing a corresponding front-end delay clock to the phase-locked loop. In this example, different delay units delay the different reference clocks.
除非另作定義，在此所有詞彙(包含技術與科學詞彙)均屬本發明所屬技術領域中具有通常知識者之一般理解。此外，除非明白表示，詞彙於一般字典中之定義應解釋為與其相關技術領域之文章中意義一致，而不應解釋為理想狀態或過分正式之語態。Unless otherwise defined, all terms (including technical and scientific terms) are used in the ordinary meaning Moreover, unless expressly stated, the definition of a vocabulary in a general dictionary should be interpreted as consistent with the meaning of an article in its related art, and should not be interpreted as an ideal state or an overly formal voice.
雖然本發明已以較佳實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不 脫離本發明之精神和範圍內，當可作些許之更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。Although the present invention has been disclosed above in the preferred embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art is not The scope of the present invention is defined by the scope of the appended claims.
100、222‧‧‧電荷幫浦100, 222‧‧‧ Charge pump
110、120‧‧‧電流源110, 120‧‧‧ current source
130‧‧‧儲存單元130‧‧‧storage unit
140、221‧‧‧相位頻率偵測器140, 221‧‧‧ phase frequency detector
200‧‧‧時脈產生器200‧‧‧ clock generator
210、230‧‧‧延遲單元210, 230‧‧‧ delay unit
220‧‧‧鎖相迴路220‧‧‧ phase-locked loop
240‧‧‧偵測單元240‧‧‧Detection unit
223‧‧‧低通濾波器223‧‧‧low pass filter
224‧‧‧壓控振盪器224‧‧‧Variable Control Oscillator
225‧‧‧除頻器225‧‧‧Delephone
410‧‧‧偵測模組410‧‧‧Detection module
420‧‧‧比較模組420‧‧‧Comparative Module
REF‧‧‧參考時脈REF‧‧‧ reference clock
Fvco‧‧‧鎖相時脈Fvco‧‧‧ phase-locked clock
Up‧‧‧充電信號Up‧‧‧Charging signal
Dn‧‧‧放電信號Dn‧‧‧discharge signal
S1、S2‧‧‧開關S1, S2‧‧‧ switch
I1、I2‧‧‧充電電流I1, I2‧‧‧Charging current
FD1 ~F2DN ‧‧‧前端延遲時脈F D1 ~F 2DN ‧‧‧ Front end delay clock
Vc‧‧‧輸出電壓Vc‧‧‧ output voltage
S1 ~Sm ‧‧‧切換信號S 1 ~S m ‧‧‧Switching signal
PH1~PH3‧‧‧相位差PH1~PH3‧‧‧ phase difference
FF1 ~FF2N ‧‧‧正反器FF 1 ~ FF 2N ‧‧‧ forward and reverse
LG1 ~LGm ‧‧‧邏輯閘LG 1 ~ LG m ‧‧‧ logic gate
Q1 ~Q2N ‧‧‧輸出信號Q 1 ~Q 2N ‧‧‧Output signal
Fdiv‧‧‧回授時脈Fdiv‧‧‧Restoration clock
BD1 ~B2DN ‧‧‧後端延遲時脈B D1 ~B 2DN ‧‧‧Backend delay clock
ST1 ~STm 、SB1 ~SBm ‧‧‧切換信號ST 1 ~ST m , SB 1 ~SB m ‧‧‧Switching signal
FB1 ~FB2N 、BB1 ~BB2N ‧‧‧緩衝器FB 1 ~ FB 2N , BB 1 ~ BB 2N ‧ ‧ buffer
OUT、OUT1、OUT2‧‧‧輸出時脈OUT, OUT1, OUT2‧‧‧ output clock
第1A圖為習知鎖相迴路(PLL)的部分示意圖。Figure 1A is a partial schematic view of a conventional phase-locked loop (PLL).
第1B及1C圖係為充放電電流不一致的示意圖。The 1B and 1C drawings are schematic diagrams in which the charge and discharge currents do not match.
第2圖係為本發明之時脈產生器之示意圖。Figure 2 is a schematic diagram of the clock generator of the present invention.
第3圖為本發明之時脈產生器的控制時序圖。Fig. 3 is a timing chart showing the control of the clock generator of the present invention.
第4圖為本發明之偵測單元之一可能實施例。Figure 4 is a possible embodiment of a detection unit of the present invention.
第5圖為本發明之時脈產生器之另一實施例。Figure 5 is another embodiment of the clock generator of the present invention.
200‧‧‧時脈產生器200‧‧‧ clock generator
210、230‧‧‧延遲單元210, 230‧‧‧ delay unit
220‧‧‧鎖相迴路220‧‧‧ phase-locked loop
240‧‧‧偵測單元240‧‧‧Detection unit
221‧‧‧相位頻率偵測器221‧‧‧ phase frequency detector
222‧‧‧電荷幫浦222‧‧‧Charge pump
223‧‧‧低通濾波器223‧‧‧low pass filter
224‧‧‧壓控振盪器224‧‧‧Variable Control Oscillator
225‧‧‧除頻器225‧‧‧Delephone
FD1 ~F2DN ‧‧‧前端延遲時脈F D1 ~F 2DN ‧‧‧ Front end delay clock
FB1 ~FB2N 、BB1 ~BB2N ‧‧‧緩衝器FB 1 ~ FB 2N , BB 1 ~ BB 2N ‧ ‧ buffer
Vc‧‧‧輸出電壓Vc‧‧‧ output voltage
S1 ~Sm ‧‧‧切換信號S 1 ~S m ‧‧‧Switching signal
BD1 ~B2DN ‧‧‧後端延遲時脈B D1 ~B 2DN ‧‧‧Backend delay clock
OUT‧‧‧輸出時脈OUT‧‧‧ output clock
Up‧‧‧充電信號Up‧‧‧Charging signal
Dn‧‧‧放電信號Dn‧‧‧discharge signal
REF‧‧‧參考時脈REF‧‧‧ reference clock
Fvco‧‧‧鎖相時脈Fvco‧‧‧ phase-locked clock
Fdiv‧‧‧回授時脈Fdiv‧‧‧Restoration clock
Claims (10)
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| Application Number | Priority Date | Filing Date | Title |
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| TW101145802A TWI502895B (en) | 2012-12-06 | 2012-12-06 | Clock generator |
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| Application Number | Priority Date | Filing Date | Title |
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| TW101145802A TWI502895B (en) | 2012-12-06 | 2012-12-06 | Clock generator |
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| TW201424270A TW201424270A (en) | 2014-06-16 |
| TWI502895B true TWI502895B (en) | 2015-10-01 |
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Citations (7)
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|---|---|---|---|---|
| US6125157A (en) * | 1997-02-06 | 2000-09-26 | Rambus, Inc. | Delay-locked loop circuitry for clock delay adjustment |
| US20030076142A1 (en) * | 2001-09-28 | 2003-04-24 | Myeong-Iyong Ko | Delay locked loop with multi-phases |
| US20080211555A1 (en) * | 2004-03-05 | 2008-09-04 | Jong-Tae Kwak | Delay locked loop in semiconductor memory device |
| US20090163166A1 (en) * | 2007-12-21 | 2009-06-25 | Realtek Semiconductor Corp. | Phase lock loop with phase interpolation by reference clock and method for the same |
| US20090179708A1 (en) * | 2008-01-15 | 2009-07-16 | Fujitsu Limited | Phase lock oscillator and wireless communications device including phase lock oscillator |
| US20090267664A1 (en) * | 2008-04-29 | 2009-10-29 | Toshiya Uozumi | Pll circuit |
| TW201236375A (en) * | 2011-02-16 | 2012-09-01 | Samsung Mobile Display Co Ltd | Coarse lock detector and delay-locked loop including the same |
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2012
- 2012-12-06 TW TW101145802A patent/TWI502895B/en active
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6125157A (en) * | 1997-02-06 | 2000-09-26 | Rambus, Inc. | Delay-locked loop circuitry for clock delay adjustment |
| US20030076142A1 (en) * | 2001-09-28 | 2003-04-24 | Myeong-Iyong Ko | Delay locked loop with multi-phases |
| US20080211555A1 (en) * | 2004-03-05 | 2008-09-04 | Jong-Tae Kwak | Delay locked loop in semiconductor memory device |
| US20090163166A1 (en) * | 2007-12-21 | 2009-06-25 | Realtek Semiconductor Corp. | Phase lock loop with phase interpolation by reference clock and method for the same |
| US20090179708A1 (en) * | 2008-01-15 | 2009-07-16 | Fujitsu Limited | Phase lock oscillator and wireless communications device including phase lock oscillator |
| US20090267664A1 (en) * | 2008-04-29 | 2009-10-29 | Toshiya Uozumi | Pll circuit |
| TW201236375A (en) * | 2011-02-16 | 2012-09-01 | Samsung Mobile Display Co Ltd | Coarse lock detector and delay-locked loop including the same |
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| TW201424270A (en) | 2014-06-16 |
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