TWI500139B - Hybrid high voltage device and manufacturing method thereof - Google Patents
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本發明係有關一種混和高壓元件及其製造方法，特別是指一種降低導通阻值之混和高壓元件及其製造方法。The present invention relates to a hybrid high voltage component and a method of fabricating the same, and more particularly to a hybrid high voltage component that reduces on-resistance and a method of fabricating the same.
第1A-1C圖分別顯示先前技術之橫向雙擴散金屬氧化物半導體(lateral double diffused metal oxide semiconductor,LDMOS)元件100之剖視圖、立體圖、與上視圖，如第1A-1C圖所示，P型基板11中具有隔絕區12，其圍繞一封閉區域(如第1C圖中，隔絕區12之粗黑框線所示意)，以定義LDMOS元件100之功能區，隔絕區12與場氧化區12a例如為淺溝槽絕緣(shallow trench isolation,STI)結構或如圖所示之區域氧化(local oxidation of silicon,LOCOS)結構。LDMOS元件100包含N型井區14、閘極13、汲極15、源極16、本體區17、本體極17a、以及場氧化區12a。其中，N型井區14、汲極15與源極16係由微影技術或以部分或全部之閘極13為遮罩，以定義各區域，並分別以離子植入技術，將N型雜質，以加速離子的形式，植入定義的區域內。其中，汲極15與源極16分別位於閘極13兩側下方；本體區17與本體極17a係由微影技術或以部分或全部之閘極13為遮罩，以定義各區域，並分別以離子植入技術，將P型雜質，以加速離子的形式，植入定義的區域內。而且LDMOS元件中，閘極13有一部分位於場氧化區12a上。LDMOS元件為高壓元件，亦即其係設計用於供應較高的操作電壓。LDMOS元件本身的缺點是導通阻值提高，限制了元件的應用範圍。若欲降低LDMOS 元件導通阻值，則必須更動離子植入參數，如此會犧牲崩潰防護電壓；或是增加特定區域的離子植入步驟，如此則需要額外的微影與植入步驟，將會增加製造成本，才能達到所欲的導通阻值。1A-1C are cross-sectional, perspective, and top views, respectively, of a prior art lateral double diffused metal oxide semiconductor (LDMOS) device 100, as shown in FIGS. 1A-1C, a P-type substrate. 11 has an isolation region 12 surrounding a closed region (as indicated by the thick black border of the isolation region 12 in FIG. 1C) to define a functional region of the LDMOS device 100, for example, the isolation region 12 and the field oxide region 12a are A shallow trench isolation (STI) structure or a local oxidation of silicon (LOCOS) structure as shown. The LDMOS device 100 includes an N-type well region 14, a gate 13, a drain 15, a source 16, a body region 17, a body electrode 17a, and a field oxide region 12a. Wherein, the N-type well region 14, the drain electrode 15 and the source electrode 16 are masked by lithography techniques or with some or all of the gate electrodes 13 to define various regions, and the N-type impurities are respectively implanted by ion implantation techniques. , in the form of accelerated ions, implanted within defined areas. Wherein, the drain 15 and the source 16 are respectively located below the two sides of the gate 13; the body region 17 and the body pole 17a are masked by lithography or with some or all of the gates 13 to define regions and respectively P-type impurities are implanted into defined regions in the form of accelerated ions by ion implantation techniques. Further, in the LDMOS device, a part of the gate 13 is located on the field oxide region 12a. The LDMOS component is a high voltage component, that is, it is designed to supply a higher operating voltage. A disadvantage of the LDMOS device itself is that the conduction resistance is increased, which limits the application range of the component. If you want to lower LDMOS If the component conductance value, the ion implantation parameters must be changed, so that the collapse protection voltage is sacrificed; or the ion implantation step of a specific region is added, so that additional lithography and implantation steps are required, which will increase the manufacturing cost. Achieve the desired conduction resistance.
有鑑於此，本發明即針對上述先前技術之不足，提出一種混和高壓元件及其製造方法，在不增加製程步驟且不犧牲崩潰防護電壓的情況下，降低元件操作之導通阻值，增加元件的應用範圍。此外，本發明之混合高壓元件的離子植入參數可與低壓元件共用，亦即可整合於低壓元件之製程，以在同一晶圓上同時製造高壓元件和低壓元件。In view of the above, the present invention is directed to the above-mentioned deficiencies of the prior art, and proposes a hybrid high-voltage component and a manufacturing method thereof, which can reduce the conduction resistance value of the component operation and increase the component without increasing the process step and without sacrificing the breakdown protection voltage. Application range. In addition, the ion implantation parameters of the hybrid high voltage component of the present invention can be shared with the low voltage component, that is, integrated into the process of the low voltage component to simultaneously manufacture the high voltage component and the low voltage component on the same wafer.
本發明目的在提供一種混和高壓元件及其製造方法。It is an object of the present invention to provide a hybrid high voltage component and a method of manufacturing the same.
為達上述之目的，本發明提供了一種混和高壓元件，形成於一第一導電型基板中，該基板具有一上表面，該混和高壓元件包含：至少一橫向雙擴散金屬氧化物半導體(lateral double diffused metal oxide semiconductor,LDMOS)元件區，形成於該基板中，該LDMOS元件區中具有一第一源極、一第一汲極、一第一本體區、以及一第一閘極；以及至少一疏流元件區，形成於該基板中，且該疏流元件區之導通電阻低於該LDMOS元件區之導通電阻，該疏流元件區中具有一第二源極、一第二汲極、一第二本體區、以及一第二閘極；其中，該LDMOS元件區與該疏流元件區於一寬度方向上，交錯排列，且該LDMOS元件區之第一源極、第一汲極、第一本體區、以及第一閘極，與該疏流元件區之第二源極、第二汲極、第二本體區、以及第二閘極，分別對應實體連接或電連接。To achieve the above object, the present invention provides a hybrid high voltage component formed in a first conductivity type substrate having an upper surface, the hybrid high voltage component comprising: at least one lateral double diffusion metal oxide semiconductor (lateral double a diffused metal oxide semiconductor (LDMOS) device region formed in the substrate, the LDMOS device region having a first source, a first drain, a first body region, and a first gate; and at least one a draining element region is formed in the substrate, and an on-resistance of the draining element region is lower than an on-resistance of the LDMOS device region, wherein the draining device region has a second source, a second drain, and a a second body region and a second gate; wherein the LDMOS device region and the draining device region are staggered in a width direction, and the first source, the first drain, and the first LDMOS device region A body region and the first gate are respectively connected to the second source, the second drain, the second body region, and the second gate of the drifting element region, respectively, and are physically connected or electrically connected.
就另一觀點，本發明也提供了一種混和高壓元件製造方法，包含：提供一第一導電型基板，該基板具有一上表面；形成至少一橫向雙擴散金屬氧化物半導體(lateral double diffused metal oxide semiconductor,LDMOS)元件區於該基板中；以及形成至少一雙擴散汲極金屬氧化物半導體(double diffused drain metal oxide semiconductor,DDDMOS)元件區於該基板中；其中，該LDMOS元件區與該DDDMOS元件區於一寬度方向上，交錯排列，且該LDMOS元件區中具有一第一源極、一第一汲極、一第一本體區、以及一第一閘極，與該DDDMOS元件區中具有之一第二源極、一第二汲極、一第二本體區、以及一第二閘極，分別對應同時形成，且分別對應相互實體連接或電連接。In another aspect, the present invention also provides a method for fabricating a mixed high voltage device, comprising: providing a first conductive type substrate having an upper surface; forming at least one lateral double diffused metal oxide semiconductor (lateral double diffused metal oxide semiconductor) a semiconductor (LDMOS) device region in the substrate; and forming at least one double diffused drain metal oxide semiconductor (DDDMOS) device region in the substrate; wherein the LDMOS device region and the DDDMOS device The regions are staggered in a width direction, and the LDMOS device region has a first source, a first drain, a first body region, and a first gate, and the DDDMOS device region has A second source, a second drain, a second body, and a second gate are respectively formed at the same time, and are respectively physically or electrically connected to each other.
在其中一種較佳的實施例中，該LDMOS元件區宜包括：一第一高壓井區，具有第二導電型，形成於該上表面下之該基板中；一場氧化區，形成於該上表面上，由上視圖視之，該場氧化區位於該高壓井區中；該第一閘極，形成於該上表面上，且部分該第一閘極位於該場氧化區上；該第一源極與該第一汲極，皆具有第二導電型，分別形成於該第一閘極兩側該上表面下方，且由上視圖視之，該第一汲極與該第一源極由該第一閘極與該場氧化區隔開，其中該第一汲極形成於該第一高壓井區中；以及該第一本體區，具有第一導電型，形成於該上表面下該基板中，且該第一源極位於該第一本體區中；且該疏流元件區宜包括：一第二高壓井區，具有第二導電型，形成於該上表面下之該基板中，與該第一高壓井區連接；該第二閘極，形成於該上表面上，與該第一閘極連接；該第二源極與該第二汲極，皆具有第二導電型，分別形成於該 第二閘極兩側該上表面下方，且由上視圖視之，該第二汲極與該第二源極由該第二閘極隔開，其中該第二汲極形成於該第二高壓井區中，且該第二源極與該第一源極連接，且該第二汲極與該第一汲極連接；以及該第二本體區，具有第一導電型，形成於該上表面下該基板中，且該第二源極位於該第二本體區中。In a preferred embodiment, the LDMOS device region preferably includes: a first high voltage well region having a second conductivity type formed in the substrate under the upper surface; and an oxidation region formed on the upper surface Above view, the field oxide region is located in the high voltage well region; the first gate is formed on the upper surface, and a portion of the first gate is located on the field oxide region; the first source And the first drain has a second conductivity type, respectively formed on the upper surface of the first gate and below the upper surface, and viewed from a top view, the first drain and the first source are a first gate is spaced apart from the field oxide region, wherein the first drain is formed in the first high voltage well region; and the first body region has a first conductivity type formed in the substrate below the upper surface And the first source is located in the first body region; and the flow element region preferably includes: a second high voltage well region having a second conductivity type formed in the substrate under the upper surface, and the a first high voltage well region connected; the second gate is formed on the upper surface, and the first gate Bonding; the second source and the second drain electrode, both having a second conductivity type, respectively formed in the a second gate opposite the upper surface of the second gate, and viewed from a top view, the second drain is separated from the second source by the second gate, wherein the second drain is formed at the second high voltage In the well region, the second source is connected to the first source, and the second drain is connected to the first drain; and the second body region has a first conductivity type formed on the upper surface Lower in the substrate, and the second source is located in the second body region.
在其中一種較佳的實施例中，該疏流元件區之寬度不大於0.4um。In a preferred embodiment, the width of the flow element region is no greater than 0.4 um.
在另一種實施例中，該第一本體區及該第二本體區，與該基板間分別可由該第一高壓井區與該第二高壓井區隔開，以使該第一本體區及該第二本體區，與該基板電性不直接連接。In another embodiment, the first body region and the second body region are separated from the substrate by the first high voltage well region and the second high voltage well region, respectively, so that the first body region and the first body region The second body region is not directly connected to the substrate.
在又一種實施例中，該至少部分該第一本體區及至少部分該第二本體區可與該基板連接，或經由一第一導電型連接井區連接該基板，以使該第一本體區及該第二本體區與該基板電性連接。In still another embodiment, the at least a portion of the first body region and at least a portion of the second body region are connectable to the substrate, or the substrate is connected via a first conductive type connection well region to enable the first body region And the second body region is electrically connected to the substrate.
在又一種實施例中，該混和高壓元件可更包含：一介電層，形成於該第二閘極與該第二高壓井區上方；以及一導電層，形成於該介電層上方，且由上視圖視之，該導電層在該第二閘極與該第二汲極之間，與至少部分該第二高壓井區重疊。In still another embodiment, the hybrid high voltage component may further include: a dielectric layer formed over the second gate and the second high voltage well region; and a conductive layer formed over the dielectric layer, and Viewed from a top view, the conductive layer overlaps at least a portion of the second high voltage well region between the second gate and the second drain.
上述實施例中，該導電層宜與該第二閘極電連接。In the above embodiment, the conductive layer is preferably electrically connected to the second gate.
在另一種實施例中，該第一源極與該第二源極較佳地互相連接為一體，且該第一汲極與該第二汲極較佳地互相連接為一體，且該第一閘極與該第二閘極之通道長度宜相同，以使該LDMOS元件區與該疏流元件區形成單一元件。In another embodiment, the first source and the second source are preferably connected to each other, and the first drain and the second drain are preferably connected to each other, and the first The channel length of the gate and the second gate is preferably the same so that the LDMOS device region and the drift element region form a single component.
底下藉由具體實施例詳加說明，當更容易瞭解本發明之目的、技術內容、特點及其所達成之功效。The purpose, technical content, features and effects achieved by the present invention will be more readily understood by the detailed description of the embodiments.
本發明中的圖式均屬示意，主要意在表示製程步驟以及各層之間之上下次序關係，至於形狀、厚度與寬度則並未依照比例繪製。The drawings in the present invention are schematic and are mainly intended to represent the process steps and the relationship between the layers, and the shapes, thicknesses, and widths are not drawn to scale.
請參閱第2A-2D圖，顯示本發明的第一個實施例，本實施例顯示應用本發明之混和高壓元件200之製造方法示意圖。其中，第2A-2B與2D圖為立體示意圖，第2C圖為上視示意圖。首先，如第2A圖所示，提供基板21，其具有上表面21a，且基板21之導電型例如為P型但不限於為P型(在其他實施型態中亦可以為N型)；並且，基板21例如可以為非磊晶矽基板，亦可以為磊晶基板。接著，以離子植入技術，將例如但不限於N型雜質，以加速離子的形式，植入定義的區域內，於上表面21a下形成N型高壓井區24於基板21中。接下來，如第2B圖所示，可利用相同但不限於相同之製程步驟，形成隔絕區22與場氧化區22a於上表面21a上，由上視圖視之(未示出)，場氧化區22a位於高壓井區24中；其中，隔絕區22與場氧化區22a例如為STI結構或如圖所示之區域氧化LOCOS結構。混和高壓元件200包含至少一橫向雙擴散金屬氧化物半導體(lateral double diffused metal oxide semiconductor,LDMOS)元件區與至少另一導通電阻低於LDMOS元件區的元件區，在本發明中稱為「疏流元件區」，因其提供較低阻值的電流路徑。此疏流元件區可使用任何導通電阻低於LDMOS元件的元件結構，例如但不限於採用雙 擴散汲極金屬氧化物半導體(double diffused drain metal oxide semiconductor,DDDMOS)元件結構，其中，LDMOS元件區210與DDDMOS元件區220於寬度w 方向上，交錯排列並可實體連接或電連接。接著請參閱第2C與2D圖，形成閘極23、汲極25、源極26、本體區27、與本體極27a。其中，如圖所示，閘極23形成於上表面21a上，且部分閘極23位於場氧化區22a上。汲極25與源極26例如為N型但不限於為N型，分別位於閘極23兩側上表面21a下方，且由上視圖視之，汲極25與源極26由閘極23與場氧化區22a隔開；其中汲極25形成於高壓井區24中。本體區27例如為P型但不限於為P型，形成於上表面21a下基板21中，且源極26位於本體區27中。Referring to Figures 2A-2D, a first embodiment of the present invention is shown. This embodiment shows a schematic diagram of a method of manufacturing a hybrid high voltage component 200 to which the present invention is applied. 2A-2B and 2D are perspective views, and FIG. 2C is a top view. First, as shown in FIG. 2A, a substrate 21 having an upper surface 21a is provided, and the conductivity type of the substrate 21 is, for example, P-type but not limited to being P-type (it may be N-type in other embodiments); The substrate 21 may be, for example, a non-excipherated germanium substrate or an epitaxial substrate. Next, an ion implantation technique is used to implant, for example, but not limited to, an N-type impurity, in the form of an accelerated ion, into a defined region, and an N-type high voltage well region 24 is formed in the substrate 21 under the upper surface 21a. Next, as shown in FIG. 2B, the isolation region 22 and the field oxide region 22a may be formed on the upper surface 21a by the same but not limited to the same process steps, as viewed from above (not shown), the field oxidation region 22a is located in the high pressure well region 24; wherein the isolation region 22 and the field oxide region 22a are, for example, STI structures or regions oxidized LOCOS structures as shown. The hybrid high voltage device 200 includes at least one lateral double diffused metal oxide semiconductor (LDMOS) device region and at least another component region having a lower on-resistance than the LDMOS device region, which is referred to as "spreading" in the present invention. Component area because it provides a lower resistance current path. The shunt element region may use any element structure having a lower on-resistance than the LDMOS device, such as, but not limited to, a double diffused drain metal oxide semiconductor (DDDMOS) device structure, wherein the LDMOS device region 210 The DDDMOS device regions 220 are staggered in the width w direction and may be physically or electrically connected. Next, referring to FIGS. 2C and 2D, a gate 23, a drain 25, a source 26, a body region 27, and a body electrode 27a are formed. Here, as shown, the gate 23 is formed on the upper surface 21a, and a portion of the gate 23 is located on the field oxide region 22a. The drain 25 and the source 26 are, for example, N-type but not limited to N-type, respectively located under the upper surface 21a of both sides of the gate 23, and viewed from the top view, the drain 25 and the source 26 are connected by the gate 23 and the field The oxidation zone 22a is spaced apart; wherein the drain 25 is formed in the high pressure well zone 24. The body region 27 is, for example, P-type but not limited to being P-type, formed in the lower substrate 21 of the upper surface 21a, and the source 26 is located in the body region 27.
在本實施例中，混和高壓元件200中之LDMOS元件區210與DDDMOS元件區220於寬度w方向上，交錯排列且實體連接或電連接。並且，LDMOS元件區210與DDDMOS元件區220包含共同的高壓井區24，或亦可以視為LDMOS元件區210之高壓井區與DDDMOS元件區220之高壓井區互相實體連接。類似地，隔絕區22、閘極23、汲極25、源極26、本體區27、與本體極27a，分別對應包括位於LDMOS元件區210與DDDMOS元件區220且互相實體連接或電連接之隔絕區221與222、閘極231與232、汲極251與252、源極261與262、本體區271與272、以及本體極271a與272a。此種安排方式的優點包括：在元件規格上，相較於先前技術，應用本發明可降低高壓元件的導通阻值；在製程上，對應的隔絕區221與222、閘極231與232、汲極251與252、源極261與262、本體區271與272、以及本體極271a與272a皆 可以利用相同之製程步驟形成，而不需要另外新增製程步驟，故可降低製造成本。In the present embodiment, the LDMOS device region 210 and the DDDMOS device region 220 in the mixed high voltage device 200 are staggered and physically or electrically connected in the width w direction. Moreover, the LDMOS device region 210 and the DDDMOS device region 220 include a common high voltage well region 24, or may be considered to be physically connected to the high voltage well region of the LDMOS device region 210 and the high voltage well region of the DDDMOS device region 220. Similarly, the isolation region 22, the gate 23, the drain 25, the source 26, the body region 27, and the body electrode 27a respectively include an isolation between the LDMOS device region 210 and the DDDMOS device region 220 and are physically or electrically connected to each other. Regions 221 and 222, gates 231 and 232, gates 251 and 252, sources 261 and 262, body regions 271 and 272, and body electrodes 271a and 272a. Advantages of this arrangement include: in terms of component specifications, the application of the present invention can reduce the on-resistance of the high-voltage component in terms of component specifications; in the process, corresponding isolation regions 221 and 222, gates 231 and 232, and 汲The poles 251 and 252, the sources 261 and 262, the body regions 271 and 272, and the body poles 271a and 272a It can be formed by the same process steps without additional process steps, thus reducing manufacturing costs.
詳言之，先前技術之高壓元件應用在高壓之操作電壓下，需要場氧化區，形成氧化層加強擴散(oxide enhanced diffusion,OED)效應，使得場氧化區下的載子濃度較淡，所以當高壓元件操作於不導通的狀況下，空乏區會在場氧化區下擴大，因而降低電場，提高崩潰防護電壓，但是高壓元件導通阻值相當高，限制了元件應用的範圍。利用本發明，將LDMOS元件區210與DDDMOS元件區220於寬度w 方向(如圖中箭號所示意的方向)上，交錯排列連接，優點是：以本發明的第一個實施例而言，混和高壓元件200，操作於導通的狀況下，部分電流可以經由DDDMOS元件區220流通，因而降低了導通電阻，改善高壓元件在導通狀況下的特性。另一方面，當混和高壓元件200操作於不導通的狀況下，利用DDDMOS元件區220在寬度w 方向上相鄰的LDMOS元件區210中之場氧化區221a，在寬度w 方向上的介電層降低表面電場(RESURF)效應，將DDDMOS元件區220中通道的空乏區擴大，使其表面電場下降，以提高混和高壓元件200之崩潰防護電壓。在其中一種實施方式中，為了較佳的RESURF效應，如第2C圖所示，DDDMOS元件區220之寬度w1 ，宜不大於0.4um。第2C圖也顯示，由於閘極231與232、汲極251與252、源極261與262、本體區271與272互相連接為一體，且閘極231與232之通道長度相同，因此LDMOS元件區210與DDDMOS元件區220可形成單一元件。In detail, the high-voltage components of the prior art are applied at a high voltage operating voltage, requiring a field oxide region to form an oxide enhanced diffusion (OED) effect, so that the carrier concentration under the field oxidation region is relatively light, so when When the high-voltage component is operated in a non-conducting condition, the depletion region will expand under the field oxidation region, thereby reducing the electric field and increasing the breakdown protection voltage, but the high-voltage component conduction resistance is relatively high, which limits the range of application of the component. With the present invention, the LDMOS device region 210 and the DDDMOS device region 220 are staggered in the width w direction (in the direction indicated by the arrow in the figure), with the advantage that, in the first embodiment of the present invention, When the high voltage device 200 is mixed and operated in a conducting state, part of the current can flow through the DDDMOS device region 220, thereby lowering the on-resistance and improving the characteristics of the high voltage device under the on-state. On the other hand, when the mixed high voltage device 200 is operated in a non-conducting state, the field oxide region 221a in the LDMOS device region 210 adjacent to the width w direction by the DDDMOS device region 220, and the dielectric layer in the width w direction. The surface electric field (RESURF) effect is reduced, and the depletion region of the channel in the DDDMOS device region 220 is enlarged to reduce the surface electric field to increase the collapse protection voltage of the mixed high voltage component 200. In one embodiment, for the preferred RESURF effect, as shown in FIG. 2C, the width w1 of the DDDMOS device region 220 is preferably no greater than 0.4 um. 2C also shows that since the gates 231 and 232, the drains 251 and 252, the sources 261 and 262, and the body regions 271 and 272 are integrally connected to each other, and the gate lengths of the gates 231 and 232 are the same, the LDMOS device region is 210 and DDDMOS device region 220 may form a single component.
需說明的是，混和高壓元件200中之DDDMOS元件區220亦可以由其他形式的半導體元件取代，只要其導通阻值 低於LDMOS元件區210的導通阻值，且於寬度w 方向上，與LDMOS元件區210交錯排列且實體連接或電連接，且疏流元件區中之源極、汲極、本體區、以及閘極，分別對應實體連接或電連接源極261、汲極251、本體區271、以及閘極231即可。例如，疏流元件區中之汲極可形成於閘極一側下方，不需如DDDMOS元件區中之汲極252，與閘極232間由高壓井區24隔開，可進一步降低導通阻值。It should be noted that the DDDMOS device region 220 in the mixed high voltage device 200 may also be replaced by other types of semiconductor devices as long as the on-resistance is lower than the on-resistance of the LDMOS device region 210, and in the width w direction, and the LDMOS. The element regions 210 are staggered and physically connected or electrically connected, and the source, the drain, the body region, and the gate in the flow-down element region respectively correspond to the physical connection or electrical connection source 261, the drain 251, and the body region 271. And the gate 231 can be. For example, the drain in the region of the drift element can be formed below the gate side, without the drain 252 in the DDDMOS device region, and separated from the gate 232 by the high voltage well region 24, which can further reduce the conduction resistance. .
第3圖顯示本發明的第二個實施例，為應用本發明混和高壓元件300之立體示意圖。與第一個實施例不同，在第一個實施例中，本體區27與基板21間，由高壓井區24隔開，以使本體區27與基板21電性不連接，使混和高壓元件200可以作為電源供應電路中之上橋(high side)元件。不同地，如圖所示，本實施例之混和高壓元件300，其功能區由隔絕區32所定義；混和高壓元件300包含LDMOS元件區310與DDDMOS元件區320於寬度w 方向(如圖中箭號所示意的方向)上，交錯排列且實體連接或電連接。LDMOS元件區310包含場氧化區32a。此外，LDMOS元件區310與DDDMOS元件區320包括共同的閘極33、汲極35、源極36、本體區37、與本體極37a。與第一個實施例不同，在本實施例中，部分本體區37與基板31連接，以使本體區37與基板31電性連接，這使混和高壓元件300可以作為電源供應電路中之下橋(low side)元件。Fig. 3 shows a second embodiment of the present invention, which is a perspective view of a hybrid high voltage component 300 to which the present invention is applied. Different from the first embodiment, in the first embodiment, the body region 27 and the substrate 21 are separated by the high voltage well region 24, so that the body region 27 is electrically disconnected from the substrate 21, so that the high voltage component 200 is mixed. It can be used as a high side component in a power supply circuit. Differently, as shown in the figure, the mixed high voltage component 300 of the present embodiment has a functional area defined by the isolation region 32; the mixed high voltage component 300 includes the LDMOS device region 310 and the DDDMOS device region 320 in the width w direction (as shown in the figure) In the direction indicated by the number), staggered and physically or electrically connected. The LDMOS device region 310 includes a field oxide region 32a. Further, the LDMOS device region 310 and the DDDMOS device region 320 include a common gate 33, a drain 35, a source 36, a body region 37, and a body electrode 37a. Different from the first embodiment, in this embodiment, a portion of the body region 37 is connected to the substrate 31 to electrically connect the body region 37 with the substrate 31, which allows the hybrid high voltage component 300 to function as a lower bridge in the power supply circuit. (low side) component.
第4圖顯示顯示本發明的第三個實施例，為應用本發明混和高壓元件400之立體示意圖。如圖所示，本實施例之混和高壓元件400，其功能區由隔絕區42所定義；混和高壓元件400包含LDMOS元件區410與DDDMOS元件區420於 寬度w 方向(如圖中箭號所示意的方向)上，交錯排列且實體連接或電連接。LDMOS元件區410包含場氧化區42a。此外，LDMOS元件區410與DDDMOS元件區420包括共同的閘極43、高壓井區44、汲極45、源極46、本體區47、與本體極47a。與第二個實施例不同之處，在於本實施例中，部分本體區47與基板41之間，經由LDMOS元件區410與DDDMOS元件區420共同的P型連接井區49連接，以使本體區47與基板41電性連接，這使混和高壓元件400可以作為電源供應電路中之下橋(low side)元件。Figure 4 is a perspective view showing a third embodiment of the present invention for applying the hybrid high voltage component 400 of the present invention. As shown, the mixed high voltage component 400 of the present embodiment has a functional area defined by the isolation region 42; the mixed high voltage component 400 includes the LDMOS device region 410 and the DDDMOS device region 420 in the width w direction (as indicated by the arrow in the figure). In the direction), staggered and physically or electrically connected. The LDMOS device region 410 includes a field oxide region 42a. In addition, the LDMOS device region 410 and the DDDMOS device region 420 include a common gate 43 , a high voltage well region 44 , a drain 45 , a source 46 , a body region 47 , and a body pole 47 a . The difference from the second embodiment is that in the embodiment, a portion of the body region 47 and the substrate 41 are connected via a P-type connection well region 49 common to the DDDMOS device region 420 via the LDMOS device region 410, so that the body region is 47 is electrically connected to the substrate 41, which allows the hybrid high voltage component 400 to function as a low side component in the power supply circuit.
第5A-5B圖顯示本發明的第四個實施例，分別顯示應用本發明之DDDMOS元件區520更具體實施例的立體示意圖與上視圖。如第5A圖所示，DDDMOS元件區520形成於基板51之由隔絕區52所定義的功能區中，除包含閘極53、高壓井區54、汲極55、源極56、與本體區57、本體極57a外，更包含介電層58、導電栓59a、與導電層59。如第5A圖所示，例如但不限於以沉積技術，形成介電層58。介電層58由介電材料形成於高壓井區54以及閘極53上方，且介電層58大致覆蓋了DDDMOS元件區520所有區域，包括閘極53與汲極55間的漂移區。如圖所示，例如但不限於利用微影技術、蝕刻技術、沉積技術、化學機械研磨技術等，形成導電栓59a。需說明的是，為了方便理解，第5A圖顯示單獨一導電栓59a示意。導電栓59a例如但不限於與閘極53電連接，並可以為複數，且安排於功能區之外。如第5A與5B圖所示，利用例如但不限於微影技術、沉積技術、與蝕刻技術，以導電材料形成導電層59於介電層58上方。其中，導電材料例如但不限於為鋁銅等金屬，且導電層59例如可與DDDMOS 元件區520中之第一金屬層(未示出)利用相同製程形成。需注意的是，如第5B圖之上視圖所示，導電層59在閘極53與汲極55之間，與至少部分漂移區重疊。5A-5B are views showing a fourth embodiment of the present invention, respectively showing a perspective view and a top view of a more specific embodiment of the DDDMOS device region 520 to which the present invention is applied. As shown in FIG. 5A, the DDDMOS device region 520 is formed in the functional region defined by the isolation region 52 of the substrate 51, except for the gate 53, the high voltage well region 54, the drain 55, the source 56, and the body region 57. The body electrode 57, the conductive plug 59a, and the conductive layer 59 are further included outside the body electrode 57a. As shown in FIG. 5A, dielectric layer 58 is formed, for example, but not limited to, by deposition techniques. The dielectric layer 58 is formed of a dielectric material over the high voltage well region 54 and the gate 53 and the dielectric layer 58 substantially covers all regions of the DDDMOS device region 520, including the drift region between the gate 53 and the drain 55. As shown, the conductive plug 59a is formed, for example, but not limited to, by lithography, etching, deposition, chemical mechanical polishing, and the like. It should be noted that, for ease of understanding, FIG. 5A shows a single conductive plug 59a. The conductive plug 59a is, for example but not limited to, electrically connected to the gate 53 and may be plural and arranged outside the functional area. As shown in FIGS. 5A and 5B, a conductive layer 59 is formed over the dielectric layer 58 with a conductive material using, for example, but not limited to, lithography, deposition techniques, and etching techniques. Wherein, the conductive material is, for example but not limited to, a metal such as aluminum copper, and the conductive layer 59 can be, for example, DDDMOS A first metal layer (not shown) in the element region 520 is formed using the same process. It should be noted that, as shown in the upper view of FIG. 5B, the conductive layer 59 overlaps between the gate 53 and the drain 55 and at least partially drifts.
需說明的是，利用與至少部分漂移區重疊之導電層59，其間以介電層58隔開，且此導電層59宜與閘極53電連接。如此一來，無論DDDMOS元件區520操作於導通或不導通的情況，此導電層59產生電場，透過介電層58，影響DDDMOS元件區520通道的電場，使得操作於導通狀況時，改善閘極引發汲極漏電流(gate induced drain leakage,GIDL)；且於DDDMOS元件區520操作於不導通狀況時，改善能帶間隙穿隧效應；此外，可更提高DDDMOS元件區520崩潰防護電壓。It should be noted that the conductive layer 59 overlapping with at least part of the drift region is separated by a dielectric layer 58 and the conductive layer 59 is preferably electrically connected to the gate 53. In this way, regardless of whether the DDDMOS device region 520 is turned on or off, the conductive layer 59 generates an electric field that passes through the dielectric layer 58 and affects the electric field of the channel of the DDDMOS device region 520, so that the gate is improved when operating in a conducting state. A gate induced drain leakage (GIDL) is induced; and when the DDDMOS device region 520 operates in a non-conducting state, the band gap tunneling effect is improved; moreover, the DDDMOS device region 520 collapse protection voltage can be further improved.
第6圖顯示顯示本發明的第五個實施例，為應用本發明混和高壓元件600之上視示意圖。如圖所示，本實施例之混和高壓元件600，其功能區由隔絕區62所定義；混和高壓元件600包含複數LDMOS元件區610與複數DDDMOS元件區620於寬度w 方向(如圖中箭號所示意的方向)上，交錯排列且實體連接或電連接。LDMOS元件區610包含場氧化區62a(如圖中粗黑框線所示意)。此外，LDMOS元件區610與DDDMOS元件區620包括共同的閘極63、高壓井區64、汲極65、源極66、本體區67、與本體極67a。本實施例旨在說明本發明之混和高壓元件可包含複數LDMOS元件區與複數DDDMOS元件區。Figure 6 shows a top view showing a fifth embodiment of the present invention for applying the hybrid high voltage component 600 of the present invention. As shown, the mixed high voltage component 600 of the present embodiment has a functional area defined by the isolation region 62; the mixed high voltage component 600 includes a plurality of LDMOS device regions 610 and a plurality of DDDMOS device regions 620 in the width w direction (such as an arrow in the figure). In the illustrated direction), staggered and physically or electrically connected. The LDMOS device region 610 includes a field oxide region 62a (shown as a thick black border in the figure). In addition, the LDMOS device region 610 and the DDDMOS device region 620 include a common gate 63, a high voltage well region 64, a drain 65, a source 66, a body region 67, and a body electrode 67a. This embodiment is intended to illustrate that the hybrid high voltage device of the present invention may comprise a plurality of LDMOS device regions and a plurality of DDDMOS device regions.
第7圖顯示顯示本發明的第六個實施例，為應用本發明混和高壓元件700之上視示意圖。如圖所示，本實施例之混和高壓元件700，其功能區由隔絕區72所定義；混和高壓元件700包含複數LDMOS元件區710與複數DDDMOS元件 區720於寬度w 方向(如圖中箭號所示意的方向)上，交錯排列且實體連接或電連接。LDMOS元件區710包含場氧化區72a。此外，LDMOS元件區710與DDDMOS元件區720包括共同的閘極73(如圖中粗黑框線所示意)、高壓井區74、汲極75、源極76、本體區77、與本體極77a。本實施例旨在說明本發明之混和高壓元件中，閘極的形狀，由上視圖視之，不限於為前述各實施例中之矩形，亦可根據電性需要，調整其寬度。Figure 7 is a schematic top plan view showing a sixth embodiment of the present invention for applying the hybrid high voltage component 700 of the present invention. As shown, the hybrid high voltage component 700 of the present embodiment has a functional area defined by an isolation region 72; the hybrid high voltage component 700 includes a plurality of LDMOS device regions 710 and a plurality of DDDMOS device regions 720 in a width w direction (such as an arrow in the figure). In the illustrated direction), staggered and physically or electrically connected. The LDMOS device region 710 includes a field oxide region 72a. In addition, the LDMOS device region 710 and the DDDMOS device region 720 include a common gate 73 (shown as a thick black line in the figure), a high voltage well region 74, a drain 75, a source 76, a body region 77, and a body pole 77a. . The present embodiment is intended to explain the shape of the gate in the hybrid high-voltage device of the present invention. From the top view, it is not limited to the rectangular shape in the foregoing embodiments, and the width thereof may be adjusted according to electrical requirements.
第8圖顯示顯示本發明的第七個實施例，為應用本發明混和高壓元件800之上視示意圖。如圖所示，本實施例之混和高壓元件800，其功能區由隔絕區82所定義；混和高壓元件800包含複數LDMOS元件區810與複數DDDMOS元件區820於寬度w 方向(如圖中箭號所示意的方向)上，交錯排列且實體連接或電連接。LDMOS元件區810包含場氧化區82a。此外，LDMOS元件區810與DDDMOS元件區820包括共同的閘極83(如圖中粗黑框線所示意)、高壓井區84、汲極85、源極86、本體區87、與本體極87a。本實施例旨在說明本發明之混和高壓元件中，閘極的形狀，由上視圖視之，不限於為前述各實施例中之矩形，亦可根據電性需要，調整其寬度，並且可以如本實施例所示，由上視圖視之，具有鋸齒型。Figure 8 is a schematic top plan view showing a seventh embodiment of the present invention for applying the hybrid high voltage component 800 of the present invention. As shown, the hybrid high voltage component 800 of the present embodiment has a functional area defined by an isolation region 82. The hybrid high voltage component 800 includes a plurality of LDMOS device regions 810 and a plurality of DDDMOS device regions 820 in a width w direction (such as an arrow in the figure). In the illustrated direction), staggered and physically or electrically connected. The LDMOS device region 810 includes a field oxide region 82a. In addition, the LDMOS device region 810 and the DDDMOS device region 820 include a common gate 83 (shown as a thick black line in the figure), a high voltage well region 84, a drain 85, a source 86, a body region 87, and a body electrode 87a. . The present embodiment is intended to illustrate the shape of the gate in the hybrid high-voltage component of the present invention. From the top view, it is not limited to the rectangular shape in the foregoing embodiments, and the width may be adjusted according to electrical requirements, and may be as As shown in this embodiment, it has a sawtooth type as seen from the top view.
第9圖顯示顯示本發明的第八個實施例，為應用本發明混和高壓元件900之上視示意圖。如圖所示，本實施例之混和高壓元件900，其功能區由隔絕區92所定義；混和高壓元件900包含複數LDMOS元件區910與複數DDDMOS元件區920於寬度w 方向(如圖中箭號所示意的方向)上，交錯排 列且實體連接或電連接。LDMOS元件區910與DDDMOS元件區920包含共同的場氧化區92a(如圖中粗黑框線所示意)。此外，LDMOS元件區910與DDDMOS元件區920包括共同的閘極93、高壓井區94、汲極95、源極96、本體區97、與本體極97a。本實施例旨在說明本發明之混和高壓元件中，場氧化區的形狀，由上視圖視之，不限於為前述各實施例中之分開的矩形，亦可以如本實施例所示，由上視圖視之，具有連續的形狀，只需在DDDMOS元件區中，在混和高壓元件通道的方向上，縮減其長度即可。Figure 9 is a top plan view showing the eighth embodiment of the present invention for applying the hybrid high voltage component 900 of the present invention. As shown, the hybrid high voltage component 900 of the present embodiment has a functional area defined by the isolation region 92; the hybrid high voltage component 900 includes a plurality of LDMOS device regions 910 and a plurality of DDDMOS device regions 920 in the width w direction (such as an arrow in the figure). In the illustrated direction), staggered and physically or electrically connected. The LDMOS device region 910 and the DDDMOS device region 920 comprise a common field oxide region 92a (shown as thick black lines in the figure). In addition, the LDMOS device region 910 and the DDDMOS device region 920 include a common gate 93, a high voltage well region 94, a drain 95, a source 96, a body region 97, and a body electrode 97a. The present embodiment is intended to illustrate the shape of the field oxide region in the mixed high-voltage device of the present invention. From the top view, it is not limited to the rectangular shape in the foregoing embodiments, and may also be as shown in this embodiment. The view has a continuous shape, and it is only necessary to reduce the length of the high-voltage component channel in the DDDMOS component region.
以上已針對較佳實施例來說明本發明，唯以上所述者，僅係為使熟悉本技術者易於了解本發明的內容而已，並非用來限定本發明之權利範圍。在本發明之相同精神下，熟悉本技術者可以思及各種等效變化。例如，在不影響元件主要的特性下，可加入其他製程步驟或結構，如臨界電壓調整區等；又如，微影技術並不限於光罩技術，亦可包含電子束微影技術；再如，由上視圖視之，應用本發明之混和高壓元件不限於為矩形，亦可以為圓形或蛇形等；又如，上述所有實施例中之DDDMOS元件區皆可以由導通電阻低於LDMOS元件區之其他元件區取代。本發明的範圍應涵蓋上述及其他所有等效變化。The present invention has been described with reference to the preferred embodiments thereof, and the present invention is not intended to limit the scope of the present invention. In the same spirit of the invention, various equivalent changes can be conceived by those skilled in the art. For example, other process steps or structures, such as a threshold voltage adjustment region, may be added without affecting the main characteristics of the component; for example, the lithography technology is not limited to the reticle technology, and may also include electron beam lithography; As seen from the top view, the hybrid high voltage component to which the present invention is applied is not limited to being rectangular, but may be circular or serpentine, etc.; for example, all of the above DDDMOS device regions may have lower on-resistance than the LDMOS device. Replacement of other component areas of the zone. The above and other equivalent variations are intended to be covered by the scope of the invention.
11,21,31,41,51‧‧‧基板11,21,31,41,51‧‧‧substrate
12,22,32,42,62,72,82,92,221,222‧‧‧隔絕區12,22,32,42,62,72,82,92,221,222‧‧ ‧Isolation area
12a,22a,32a,42a,62a,72a,82a,92a,221a‧‧‧場氧化區12a, 22a, 32a, 42a, 62a, 72a, 82a, 92a, 221a ‧ ‧ field oxidation zone
13,23,33,43,53,63,73,83,93,231,232‧‧‧閘極13,23,33,43,53,63,73,83,93,231,232‧‧‧ gate
14‧‧‧井區14‧‧‧ Well Area
15,25,35,45,55,65,75,85,95,251,252‧‧‧汲極15,25,35,45,55,65,75,85,95,251,252‧‧‧bungee
16,26,36,46,56,66,76,86,96,261,262‧‧‧源極16,26,36,46,56,66,76,86,96,261,262‧‧‧ source
17,27,37,47,57,67,77,87,97,271,272‧‧‧本體區17,27,37,47,57,67,77,87,97,271,272‧‧‧ body area
17a,27a,37a,47a,57a,67a,77a,87a,97a,271a,272a‧‧‧本體極17a, 27a, 37a, 47a, 57a, 67a, 77a, 87a, 97a, 271a, 272a‧‧ ‧ body
21a‧‧‧上表面21a‧‧‧Upper surface
24,34,44,54,64,74,84,94‧‧‧高壓井區24,34,44,54,64,74,84,94‧‧‧High-pressure well area
58‧‧‧介電層58‧‧‧ dielectric layer
59‧‧‧導電層59‧‧‧ Conductive layer
59a‧‧‧導電栓59a‧‧‧ Conductive plug
100‧‧‧LDMOS元件100‧‧‧LDMOS components
200,300,400,600,700,800,900‧‧‧混和高壓元件200,300,400,600,700,800,900‧‧‧ mixed high voltage components
210,310,410,610,710,810,910‧‧‧LDMOS元件區210,310,410,610,710,810,910‧‧‧LDMOS component area
220,320,420,520,620,720,820,920‧‧‧DDDMOS元件區220,320,420,520,620,720,820,920‧‧‧DDDMOS component area
第1A圖顯示先前技術之LDMOS元件剖視圖。Figure 1A shows a cross-sectional view of a prior art LDMOS device.
第1B圖顯示先前技術之LDMOS元件立體圖。Figure 1B shows a perspective view of a prior art LDMOS device.
第1C圖顯示先前技術之LDMOS元件上視圖。Figure 1C shows a top view of a prior art LDMOS device.
第2A-2D圖顯示本發明的第一個實施例。2A-2D shows a first embodiment of the present invention.
第3圖顯示本發明的第二個實施例。Figure 3 shows a second embodiment of the invention.
第4圖顯示本發明的第三個實施例。Fig. 4 shows a third embodiment of the present invention.
第5A-5B圖顯示本發明的第四個實施例。Figures 5A-5B show a fourth embodiment of the invention.
第6圖顯示顯示本發明的第五個實施例。Fig. 6 shows a fifth embodiment showing the present invention.
第7圖顯示顯示本發明的第六個實施例。Fig. 7 shows a sixth embodiment showing the present invention.
第8圖顯示顯示本發明的第七個實施例。Fig. 8 shows a seventh embodiment showing the present invention.
第9圖顯示顯示本發明的第八個實施例。Fig. 9 shows an eighth embodiment showing the present invention.
22,221,222‧‧‧隔絕區22,221,222‧‧ ‧Isolation area
221a‧‧‧場氧化區221a‧‧ Field Oxidation Zone
23,231,232‧‧‧閘極23,231,232‧‧‧ gate
24‧‧‧高壓井區24‧‧‧High-pressure well area
25,251,252‧‧‧汲極25,251,252‧‧‧汲
26,261,262‧‧‧源極26,261,262‧‧‧ source
27,271,272‧‧‧本體區27,271,272‧‧‧ body area
27a,271a,272a‧‧‧本體極27a, 271a, 272a‧‧‧ body pole
200‧‧‧混合高壓元件200‧‧‧Hybrid high-voltage components
210‧‧‧LDMOS元件區210‧‧‧LDMOS component area
220‧‧‧DDDMOS元件區220‧‧‧DDDMOS component area
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| TW201003912A (en) * | 2008-07-09 | 2010-01-16 | Taiwan Semiconductor Mfg | Semiconductor structure |
| TW201010082A (en) * | 2008-07-09 | 2010-03-01 | Taiwan Semiconductor Mfg | Semiconductor structure |
| TW201128774A (en) * | 2010-02-01 | 2011-08-16 | Richtek Technology Corp | LDMOS device having increased punch-through voltage and method for making same |
| TW201216334A (en) * | 2010-10-04 | 2012-04-16 | Richtek Technology Corp | Method of manufacturing depletion MOS device |
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| TW201003912A (en) * | 2008-07-09 | 2010-01-16 | Taiwan Semiconductor Mfg | Semiconductor structure |
| TW201010082A (en) * | 2008-07-09 | 2010-03-01 | Taiwan Semiconductor Mfg | Semiconductor structure |
| TW201128774A (en) * | 2010-02-01 | 2011-08-16 | Richtek Technology Corp | LDMOS device having increased punch-through voltage and method for making same |
| TW201216334A (en) * | 2010-10-04 | 2012-04-16 | Richtek Technology Corp | Method of manufacturing depletion MOS device |
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