TWI500090B - 半導體封裝件之製法 - Google Patents
半導體封裝件之製法 Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims description 90
- 238000000034 method Methods 0.000 title claims description 22
- 239000010410 layer Substances 0.000 claims description 75
- 239000012790 adhesive layer Substances 0.000 claims description 54
- 235000012431 wafers Nutrition 0.000 claims description 39
- 238000004519 manufacturing process Methods 0.000 claims description 37
- 229910052751 metal Inorganic materials 0.000 claims description 30
- 239000002184 metal Substances 0.000 claims description 30
- 239000008393 encapsulating agent Substances 0.000 claims description 23
- 239000000758 substrate Substances 0.000 claims description 13
- 239000002923 metal particle Substances 0.000 claims description 12
- 239000000463 material Substances 0.000 claims description 11
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 8
- 229910052802 copper Inorganic materials 0.000 claims description 8
- 239000010949 copper Substances 0.000 claims description 8
- 238000005530 etching Methods 0.000 claims description 6
- 239000011521 glass Substances 0.000 claims description 6
- 229910001925 ruthenium oxide Inorganic materials 0.000 claims description 6
- WOCIAKWEIIZHES-UHFFFAOYSA-N ruthenium(iv) oxide Chemical compound O=[Ru]=O WOCIAKWEIIZHES-UHFFFAOYSA-N 0.000 claims description 6
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 4
- 229910000420 cerium oxide Inorganic materials 0.000 claims description 4
- 238000003486 chemical etching Methods 0.000 claims description 4
- 238000001020 plasma etching Methods 0.000 claims description 4
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 3
- 239000011247 coating layer Substances 0.000 claims description 3
- 229910052732 germanium Inorganic materials 0.000 claims description 3
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 3
- 229920000052 poly(p-xylylene) Polymers 0.000 claims description 3
- 239000000126 substance Substances 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims 1
- 230000001678 irradiating effect Effects 0.000 claims 1
- 238000005229 chemical vapour deposition Methods 0.000 description 6
- 239000000084 colloidal system Substances 0.000 description 5
- 230000000694 effects Effects 0.000 description 4
- 239000002313 adhesive film Substances 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 230000006378 damage Effects 0.000 description 2
- 238000005538 encapsulation Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 238000000465 moulding Methods 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910000422 cerium(IV) oxide Inorganic materials 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000000748 compression moulding Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000007772 electroless plating Methods 0.000 description 1
- 238000003912 environmental pollution Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/561—Batch processing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68381—Details of chemical or physical process used for separating the auxiliary support from a device or wafer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12042—LASER
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Description
本發明係關於一種半導體封裝件之製法,更詳言之,本發明係為一種避免光線破壞半導體晶片之半導體封裝件之製法。
現今,隨著科技發展的進步,電子產品的業者紛紛開發出各種不同型態之半導體封裝件,目前半導體晶片之尺寸趨於微小化,因此,須不斷地改良與克服半導體封裝件的製程技術,以與微小化之半導體晶片配合,並符合現代科技產品輕薄短小的趨勢。
請參閱第1A至1E圖,係為習知第7202107號美國專利之半導體封裝件之製法的剖面示意圖。
如第1A圖所示,提供一承載板10,且該承載板10上設有例如熱剝離膠帶(Thermal Release Tape)的黏著層11。
如第1B圖所示,提供複數半導體晶片12黏貼於該黏著層11上。
如第1C圖所示,形成封裝膠體13於該黏著層11上,以包覆該等半導體晶片12。
如第1D圖所示,加熱以移除該承載板10與該黏著層
11。
如第1E圖所示,於該封裝膠體13之底面上形成電性連接該半導體晶片12的線路層14。
不過,前述習知之半導體封裝件之製法之將半導體晶片黏貼於該熱剝離膠帶上時,容易因為該熱剝離膠帶之熱膨脹係數與模壓時經由模流之衝擊而造成該半導體晶片偏移之問題,造成後續製作重佈線路層時,因晶片偏移使得部份重佈線路層因偏移而沒有與晶片電性連接,進而造成產品的信賴度不佳,所以利用該熱剝離膠帶亦將導致製造成本無法降低。
因此,如何克服習知技術之種種問題,實為一重要課題。
為解決上述習知技術之種種問題,本發明遂揭露一種半導體封裝件之製法,係包括:提供一承載板上形成離型層及形成於該離型層上的黏著層;於該黏著層上設置複數半導體晶片;形成封裝膠體於該黏著層上,以包覆該等半導體晶片;以及從該承載板之側朝該離型層照射光線,以移除該離型層與承載板。
前述之半導體封裝件之製法中,復包括於該離型層和該黏著層之間形成有金屬層。
前述之半導體封裝件之製法中,於移除該離型層之後,復包括移除該金屬層。
前述之半導體封裝件之製法中,該金屬層之厚度為1
微米。
前述之半導體封裝件之製法中,復包括移除該黏著層,移除該金屬層與黏著層之方式為蝕刻或化學方法,且該蝕刻係為電漿蝕刻或化學蝕刻。
前述之半導體封裝件之製法中,復包括於照射該光線之前,於該封裝膠體上設置基板,以令該封裝膠體夾置於該基板和該黏著層之間。
前述之半導體封裝件之製法中,該黏著層中復分佈有複數金屬粒子。
前述之半導體封裝件之製法中,該承載板之材質係為玻璃。
前述之半導體封裝件之製法中,該基板之材質係為玻璃或矽。
前述之半導體封裝件之製法中,該離型層之材質係為非晶矽(Amorphous Silicon)、聚對二甲苯基(Parylene)或非晶相-二氧化矽(α-SiO2
)。
前述之半導體封裝件之製法中,該光線係為雷射光。
前述之半導體封裝件之製法中,復包括移除該基板。
前述之半導體封裝件之製法中,復包括於該封裝膠體上形成電性連接該半導體晶片的增層結構。
前述之半導體封裝件之製法中,各該金屬粒子係由氧化矽球體與形成於該氧化矽球體表面的金屬塗佈層所構成。
前述之半導體封裝件之製法中,該雷射光之波長係為
532奈米。
前述之半導體封裝件之製法中,該黏著層係包括核心銅層與其兩相對表面上的黏著膜。
依上所述,本發明之半導體封裝件之製法係照射光線以破壞離型層,進而移除離型層與承載板,並且可再藉由金屬層、具有複數金屬粒子的黏著層或具有核心銅層之黏著層來防止光線照射至半導體晶片與封裝膠體,而可避免該封裝膠體與半導體晶片被光線的能量破壞,達到保護該封裝膠體與半導體晶片的效果,故可順利的進行後續的製程並增進產品良率。
10、20‧‧‧承載板
11、23、23’、43‧‧‧黏著層
12、24‧‧‧半導體晶片
13、25‧‧‧封裝膠體
14‧‧‧線路層
21、51‧‧‧離型層
22‧‧‧金屬層
26‧‧‧基板
30‧‧‧金屬粒子
30a‧‧‧氧化矽球體
30b‧‧‧金屬塗佈層
431‧‧‧核心銅層
432‧‧‧黏著膜
a‧‧‧光線
第1A至1E圖係顯示習知半導體封裝件之製法之剖視示意圖;第2A至2H圖係為本發明之半導體封裝件之製法之第一實施例的剖面示意圖;第3圖係為本發明之半導體封裝件之製法之第二實施例的剖面示意圖;第4圖係為本發明之半導體封裝件之製法之第三實施例的剖面示意圖;第5圖係為本發明之半導體封裝件之製法之第四實施例的剖面示意圖;以及第6圖係為本發明之半導體封裝件之製法之第五實施例的剖面示意圖。
以下藉由特定的具體實施例說明本發明之實施方式,熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
須知,本說明書所附圖式所繪示之結構、比例、大小等,均僅用以配合說明書所揭示之內容,以供熟悉此技藝之人士之瞭解與閱讀,並非用以限定本發明可實施之限定條件,故不具技術上之實質意義,任何結構之修飾、比例關係之改變或大小之調整,在不影響本發明所能產生之功效及所能達成之目的下,均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時,本說明書中所引用之如「上」、「一」及「側」等之用語,亦僅為便於敘述之明瞭,而非用以限定本發明可實施之範圍,其相對關係之改變或調整,在無實質變更技術內容下,當亦視為本發明可實施之範疇。
以下將配合第2A至2H圖以詳細說明本發明之半導體封裝件之製法之第一實施例的剖面示意圖。
如第2A圖所示,提供一承載板20,且於該承載板20上形成有離型層21,而該承載板20之材質係為玻璃,另外該離型層21之材質係為非晶矽(Amorphous Silicon)、聚對二甲苯基(Parylene)或非晶相-二氧化矽(α-SiO2
),該離型層21可藉由化學氣相沉積(Chemical Vapor Deposition,CVD)方式形成。
如第2B圖所示,於該離型層21上形成金屬層22,且
藉由例如電漿輔助化學氣相沉積(Plasma Enhance Chemical Vapor Deposition,PECVD)、化學氣相沉積(Chemical Vapor Deposition,CVD)、物理氣相沉積(Physical Vapor Deposition,PVD)或無電電鍍等方式形成金屬層22,於本實施例中,該金屬層22之厚度為1微米,另外,該金屬層22之材質係為任意金屬。
要注意的是,本發明之實施亦可省去該金屬層22之形成,而不以本實施例為限。
如第2C圖所示,於該金屬層22上形成黏著層23。
如第2D圖所示,將複數半導體晶片24設置於該黏著層23上,並利用該黏著層23可固定該等半導體晶片24之位置,另外,該等半導體晶片24可具有複數電性連接墊,該半導體晶片24係為電性連接墊朝下黏貼至該黏著層23上。該承載板上更可具有定位記號,以提供半導體晶片24設置於黏著層23時,定位之用。
如第2E圖所示,藉由模塑製程(Molding),例如為壓縮成型(compression molding),形成封裝膠體25於該黏著層23上,以包覆該等半導體晶片24,且藉由該封裝膠體25可保護該等半導體晶片24避免遭受環境汙染、氧化或破壞。且於該封裝膠體25包覆該半導體晶片24後,更有一烘烤程序,以烘烤該封裝膠體以使其固化。
如第2F圖所示,於該封裝膠體25上設置基板26,以令該封裝膠體25夾置於該離型層21和該黏著層23之間,而該基板26的材質係為玻璃或矽。
如第2G圖所示,從該承載板20之側朝該離型層21照射例如雷射光的光線a,部分該光線a穿透該離型層21,但藉由該金屬層22阻擋該光線a接觸該黏著層23、半導體晶片24與該封裝膠體25,且該金屬層22可反射部分該光線a,此外,該金屬層22之厚度可隨著光線a之功率而有所調整。
如第2H圖所示,該離型層21受到該光線a之影響而破壞,以移除該離型層21與該承載板20,再移除該金屬層22與該黏著層23,而移除該金屬層22與黏著層23之方式為蝕刻或化學方法,例如電漿蝕刻或化學蝕刻;最後,可依需要將該基板26移除,並可於該封裝膠體25上形成電性連接該半導體晶片24的增層結構(未圖示此情形)。
請參閱第3圖,係本發明之半導體封裝件之製法之第二實施例的剖面示意圖。
本實施例大致上相同於前一實施例,其主要之不同之處在於本實施例不使用金屬層22,而使用之黏著層23’中係分佈有複數金屬粒子,並藉該等金屬粒子阻擋該光線a穿過該黏著層23’,至於本實施例之其它步驟均類似於前一實施例,故不再贅述。
請參閱第4圖,係本發明之半導體封裝件之製法之第三實施例的剖面示意圖。
本實施例大致上相同於第二實施例,其主要之不同之
處在於本實施例之金屬粒子30係由氧化矽球體30a與形成於該氧化矽球體30a表面的金屬塗佈層30b所構成,該金屬粒子30可阻擋該光線a穿過該黏著層23’,至於本實施例之其它步驟均類似於第二實施例,故不再贅述。
請參閱第5圖,係本發明之半導體封裝件之製法之第四實施例的剖面示意圖。
本實施例大致上相同於第二實施例,其主要之不同之處在於本實施例之黏著層43(例如為銅膠帶)係包括核心銅層431與其兩相對表面上的黏著膜432,並藉由該核心銅層431阻擋該光線a穿過該黏著層43,至於本實施例之其它步驟均類似於第二實施例,故不再贅述。
請參閱第6圖,係本發明之半導體封裝件之製法之第五實施例的剖面示意圖。
本實施例大致上相同於第二實施例,其主要之不同之處在於本實施例之離型層51之材質係為非晶相-二氧化矽(α-SiO2
),其可藉由化學氣相沉積(Chemical Vapor Deposition,CVD)方式形成,且該光線a係為532奈米之波長的雷射光,材質為非晶相-二氧化矽之離型層51經光線a照射後遂昇華至氣態,進而移除該離型層51與承載板20,至於本實施例之其它步驟均類似於第二實施例,故不再贅述。
另外,本實施例之黏著層23中亦可不分佈有複數金屬
粒子,即不藉該黏著層23中之該等金屬粒子來阻擋該光線a穿過該黏著層23,而是調整該光線a之能量,使該離型層51能受到該光線a之影響而破壞,但使該光線a之能量不至於破壞該等半導體晶片24,以安全地移除該離型層51。
綜上所述,本發明之半導體封裝件之製法係照射光線以破壞離型層,進而移除離型層與承載板,並且可再藉由金屬層、具有複數金屬粒子的黏著層或具有核心銅層之黏著層來防止光線照射至半導體晶片與封裝膠體,而可避免該封裝膠體與半導體晶片被光線的能量破壞,達到保護該封裝膠體與半導體晶片的效果,故可順利的進行後續的製程並增進產品良率。
上述該等實施樣態僅例示性說明本發明之功效,而非用於限制本發明,任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下,對上述該等實施態樣進行修飾與改變。此外,在上述該等實施態樣中之元件的數量僅為例示性說明,亦非用於限制本發明。因此本發明之權利保護範圍,應如後述之申請專利範圍所列。
20‧‧‧承載板
21‧‧‧離型層
22‧‧‧金屬層
23‧‧‧黏著層
24‧‧‧半導體晶片
25‧‧‧封裝膠體
26‧‧‧基板
a‧‧‧光線
Claims (17)
- 一種半導體封裝件之製法,係包括:提供一承載板,該承載板上形成有離型層及形成於該離型層上的黏著層,其中,該黏著層中復分佈有複數金屬粒子;於該黏著層上設置複數半導體晶片;形成封裝膠體於該黏著層上,以包覆該等半導體晶片;從該承載板之側朝該離型層照射光線,以移除該離型層與承載板;以及移除該黏著層。
- 如申請專利範圍第1項所述之半導體封裝件之製法,其中,各該金屬粒子係由氧化矽球體與形成於該氧化矽球體表面的金屬塗佈層所構成。
- 一種半導體封裝件之製法,係包括:提供一承載板,該承載板上形成有離型層及形成於該離型層上的黏著層,其中,該離型層和該黏著層之間復形成有金屬層;於該黏著層上設置複數半導體晶片;形成封裝膠體於該黏著層上,以包覆該等半導體晶片;從該承載板之側朝該離型層照射光線,以移除該離型層與承載板;以及移除該黏著層與金屬層。
- 如申請專利範圍第3項所述之半導體封裝件之製法,其中,移除該金屬層之方式為蝕刻或化學方法。
- 如申請專利範圍第4項所述之半導體封裝件之製法,其中,該蝕刻係為電漿蝕刻或化學蝕刻。
- 如申請專利範圍第3項所述之半導體封裝件之製法,其中,該金屬層之厚度為1微米。
- 一種半導體封裝件之製法,係包括:提供一承載板,該承載板上形成有離型層及形成於該離型層上的黏著層,其中,該黏著層係包括核心銅層與其兩相對表面上的黏著膜;於該黏著層上設置複數半導體晶片;形成封裝膠體於該黏著層上,以包覆該等半導體晶片;從該承載板之側朝該離型層照射光線,以移除該離型層與承載板;以及移除該黏著層。
- 如申請專利範圍第1、3及7項中任一項所述之半導體封裝件之製法,復包括於照射該光線之前,於該封裝膠體上設置基板,以令該封裝膠體夾置於該基板和該黏著層之間。
- 如申請專利範圍第8項所述之半導體封裝件之製法,其中,該基板之材質係為玻璃或矽。
- 如申請專利範圍第8項所述之半導體封裝件之製法,復包括移除該基板。
- 如申請專利範圍第1、3及7項中任一項所述之半導體封裝件之製法,其中,移除該黏著層之方式為蝕刻或化學方法。
- 如申請專利範圍第1、3及7項中任一項所述之半導體封裝件之製法,其中,該承載板之材質係為玻璃。
- 如申請專利範圍第11項所述之半導體封裝件之製法,其中,該蝕刻係為電漿蝕刻或化學蝕刻。
- 如申請專利範圍第1、3及7項中任一項所述之半導體封裝件之製法,其中,該離型層之材質係為非晶矽(Amorphous silicon)、聚對二甲苯基(parylene)或非晶相-二氧化矽(α-SiO2 )。
- 如申請專利範圍第1、3及7項中任一項所述之半導體封裝件之製法,其中,該光線係為雷射光。
- 如申請專利範圍第15項所述之半導體封裝件之製法,其中,該雷射光之波長係為532奈米。
- 如申請專利範圍第1、3及7項中任一項所述之半導體封裝件之製法,復包括於該封裝膠體上形成電性連接該半導體晶片的增層結構。
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CN201310183340.8A CN103811360A (zh) | 2012-11-13 | 2013-05-17 | 半导体封装件的制法 |
US14/013,512 US20140134797A1 (en) | 2012-11-13 | 2013-08-29 | Method for fabricating semiconductor package |
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US9698377B1 (en) | 2016-05-06 | 2017-07-04 | Industrial Technology Research Institute | Copolymer and resin composition, packaging film and package structure including the same |
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JP2016033969A (ja) * | 2014-07-31 | 2016-03-10 | 株式会社東芝 | 電子部品、及び電子ユニット |
JP2016213283A (ja) * | 2015-05-01 | 2016-12-15 | ソニー株式会社 | 製造方法、および貫通電極付配線基板 |
US9947570B2 (en) * | 2015-12-30 | 2018-04-17 | International Business Machines Corporation | Handler bonding and debonding for semiconductor dies |
US10083949B2 (en) * | 2016-07-29 | 2018-09-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | Using metal-containing layer to reduce carrier shock in package formation |
TWI648871B (zh) * | 2017-09-22 | 2019-01-21 | 台灣愛司帝科技股份有限公司 | 發光模組的製作方法 |
CN114106713B (zh) * | 2021-11-26 | 2023-06-30 | 矽磐微电子(重庆)有限公司 | 芯片封装用胶带及芯片封装方法 |
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