TWI497086B - Test System and Method of Semiconductor Packaging Component with Open Circuit Test - Google Patents
Test System and Method of Semiconductor Packaging Component with Open Circuit Test Download PDFInfo
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Description
本發明係關於一種具開路測試之半導體封裝構件測試系統與方法，尤指一種適用於對半導體封裝構件與測試裝置間進行開路測試、以及對半導體封裝構件進行功能性測試之測試方法與系統。The present invention relates to a semiconductor package component testing system and method with open circuit testing, and more particularly to a testing method and system suitable for performing open circuit testing between a semiconductor package component and a test device, and performing functional testing on the semiconductor package component.
半導體的封裝測試產業中，半導體封裝構件於組裝至電路板正式使用前大多會先進行功能測試，或稱系統級測試(System Level Testing，簡稱SLT)，其主要目的在於測試半導體封裝構件是否可以正常運作，以確保其功能之完整性。In the semiconductor packaging and testing industry, most of the semiconductor package components are functionally tested before they are assembled into the circuit board, or system level testing (SLT). The main purpose of the semiconductor package components is to test whether the semiconductor package components can be normal. Operate to ensure the integrity of its functions.
常見的功能測試大多直接利用公板，也就是以發表半導體封裝構件時所同步認證發表之公板作為測試中心，由公板內建之測試程式對此待測試半導體封裝構件進行測試。其中，必須由作業人員以人工的方式將待測試的半導體封裝構件置於公板上的測試插座上，再執行公板的公用程式來進行測試。然而，人工處理的方式難免因為作業員的經驗、熟練程度、或精神狀態等等因素導致判斷錯誤，或者難免也會因為人員操作移載半導體封裝構件的過程不慎而導致半導體封裝構件毀損。Most of the common functional tests use the public board directly, that is, the public board published by the synchronous certification when the semiconductor package component is published as a test center, and the semiconductor package component to be tested is tested by the test program built in the public board. Among them, the semiconductor package member to be tested must be manually placed on the test socket on the public board by the operator, and then the public board utility is executed for testing. However, the manual processing method is inevitably caused by the operator's experience, proficiency, or mental state, etc., or it is inevitable that the semiconductor package member is damaged due to careless handling of the semiconductor package member.
另外，既然以公板作為測試裝置，其通常只能進行單一的測試功能，亦即功能測試，而無法進行其他測試或偵錯功能。也就是說，當檢測結果為失敗時，系統通常會直接判定半導體封裝構件為不良品，並不會進一步檢測究竟是設備故障、接點處接觸不良、抑或真的是半導體封裝構件為瑕疵品。據此，常常會有誤判之情形發生，而導致測試的準確率降低，甚至造成半導體封裝構件無謂的損失。In addition, since the public board is used as a test device, it is usually only capable of performing a single test function, that is, a function test, and cannot perform other test or debug functions. That is to say, when the detection result is a failure, the system usually directly determines that the semiconductor package member is a defective product, and does not further detect whether the device is faulty, the contact at the contact is poor, or whether the semiconductor package member is a defective product. Accordingly, there are often cases of misjudgment, which leads to a decrease in the accuracy of the test and even a loss of semiconductor package components.
由此可知，一種可以提供即時偵測半導體封裝構件與測試設備間導通裝態之開路測試，又可以進行功能性測試(系統級測試，SLT)之測試方法、及其測試系統，實為產業界迫切的需求。Therefore, it can be seen that an open circuit test capable of detecting the conduction state between the semiconductor package component and the test device, and a test method for the functional test (system level test, SLT) and the test system thereof are actually industrial circles. Urgent needs.
本發明之主要目的係在提供一種具開路測試之半導體封裝構件測試系統與方法，俾能於半導體封裝構件進行功能測試前，先行進行開路測試，以進一步篩選無法通過開路測試之半導體封裝構件，同時又可偵錯並排除半導體封裝構件與測試座接點接觸不良之情形，而且也可確認公板模組與主控制器間的通訊程式是否運作正常，以提高測試準確率，且可減少系統出錯後之偵錯和故障排除的延宕時間，又可避免傳統因人為操作所造成的總總問題。The main object of the present invention is to provide a semiconductor package member test system and method with an open circuit test, which can perform an open circuit test before the functional test of the semiconductor package member to further screen the semiconductor package member that cannot pass the open circuit test. It can also detect and eliminate the bad contact between the semiconductor package component and the test socket contact, and also confirm whether the communication program between the public board module and the main controller is working properly to improve the test accuracy and reduce system errors. The delays in debugging and troubleshooting can avoid the total problems caused by traditional human operations.
為達成上述目的，本發明一種具開路測試之半導體封裝構件測試方法，包括以下步驟：首先，提供一半導體封裝構件至一公板模組之一測試座內，而公板 模組內儲存一測試程式，且公板模組藉由一通訊模組電性連接至一主控制器；再者，主控制器藉由通訊模組控制公板模組對半導體封裝構件進行開路測試；接著，主控制器發送一啟動訊號至公板模組，公板模組執行測試程式以對半導體封裝構件進行功能測試；以及，公板模組傳送一測試結果至主控制器，主控制器並依照測試結果對半導體封裝構件進行分類。To achieve the above object, a method for testing a semiconductor package member with an open circuit test includes the following steps: First, providing a semiconductor package member to a test socket of a male module, and a public board A test program is stored in the module, and the public board module is electrically connected to a main controller by a communication module; further, the main controller controls the public board module to open the semiconductor package component by using the communication module Testing; then, the main controller sends a start signal to the public board module, the public board module executes a test program to perform functional testing on the semiconductor package component; and the public board module transmits a test result to the main controller, the main control The semiconductor package components are classified according to the test results.
較佳的是，本發明之開路測試步驟可包括：首先，主控制器發送一測試訊號至公板模組；接著，公板模組測試半導體封裝構件與測試座之接點導通與否；以及，公板模組發送一確認訊號至主控制器。其中，於測試半導體封裝構件與測試座之接點導通與否的步驟中，公板模組可分別輸入一檢測訊號至測試座之每一接點，並檢測每一接點之回應訊號，以判斷半導體封裝構件與測試座之接點導通與否。據此，本發明之開路測試可以藉由對每一接點輸入特定訊號，並檢測其回饋的回應訊號來判斷每一接點的開路情況。Preferably, the open circuit testing step of the present invention may include: first, the main controller sends a test signal to the public board module; then, the public board module tests whether the contact between the semiconductor package component and the test socket is turned on or not; The public board module sends a confirmation signal to the main controller. In the step of testing whether the contact between the semiconductor package component and the test socket is turned on or not, the public board module can respectively input a detection signal to each contact point of the test socket, and detect the response signal of each contact point to It is judged whether the contact between the semiconductor package member and the test stand is turned on or not. Accordingly, the open circuit test of the present invention can determine the open condition of each contact by inputting a specific signal to each contact and detecting the feedback signal of the feedback.
另外，在開路測試中，當公板模組接收測試訊號時，公板模組停止一切進行中之測試。換言之，不論公板模組是處於閒置狀態、正進行功能測試、抑或正進行開路測試，只要當公板模組接收測試訊號時，公板模組則停止所有測試並重新啟動開路測試。此外，本發明之公板模組內可運行一作業系統，且於作業系統可處於恆啟動狀態，亦即於每次開路測試與功能測試後作業系統並不關閉，以便進行次一半導體封裝構件之測試。In addition, in the open circuit test, when the public board module receives the test signal, the public board module stops all ongoing tests. In other words, whether the public board module is in an idle state, is performing a functional test, or is performing an open circuit test, the public board module stops all tests and restarts the open circuit test when the public board module receives the test signal. In addition, an operating system can be operated in the public board module of the present invention, and the operating system can be in a constant starting state, that is, the operating system is not closed after each open circuit test and functional test, so as to perform the next semiconductor package member. Test.
又，為達成本發明之目的，本發明一種具開路測試之半導體封裝構件測試系統，其包括一主控制器、及一測試分類裝置，主控制器係電性連接測試分類裝置，測試分類裝置包括一供料單元、一公板模組、複數個出料單元、一通訊模組、以及一移載裝置。其中，供料單元係載置待測試之半導體封裝構件，公板模組包括有一測試座、及一儲存單元，而儲存單元儲存有一測試程式；複數個出料單元係載置完成測試並經分類後之半導體封裝構件；通訊模組係電性連接於公板模組與主控制器之間；移載裝置係移載半導體封裝構件於供料單元、公板模組上之測試座、以及複數個出料單元之間。其中，移載裝置自供料單元取得半導體封裝構件後移載至公板模組上之測試座內；主控制器藉由通訊模組控制公板模組對半導體封裝構件進行開路測試；主控制器發送一啟動訊號至公板模組，公板模組執行測試程式以對半導體封裝構件進行功能測試；公板模組傳送一測試結果至主控制器，主控制器依照測試結果對半導體封裝構件進行分類，並控制移載裝置移載半導體封裝構件至複數個出料單元。Moreover, in order to achieve the object of the present invention, a semiconductor package component testing system with an open circuit test includes a main controller and a test classification device, the main controller is an electrical connection test classification device, and the test classification device includes A feeding unit, a male board module, a plurality of discharging units, a communication module, and a transfer device. Wherein, the feeding unit is mounted with the semiconductor package component to be tested, the public board module comprises a test seat and a storage unit, and the storage unit stores a test program; the plurality of discharge units are mounted and tested and classified. The semiconductor package component; the communication module is electrically connected between the public board module and the main controller; the transfer device is a test seat for transferring the semiconductor package component on the feeding unit, the public board module, and the plurality Between the discharge units. Wherein, the transfer device obtains the semiconductor package component from the feeding unit and then transfers it to the test socket on the public board module; the main controller controls the public board module to open circuit test the semiconductor package component through the communication module; the main controller Sending a start signal to the public board module, the public board module executes a test program to perform functional test on the semiconductor package component; the public board module transmits a test result to the main controller, and the main controller performs the semiconductor package component according to the test result. Sorting and controlling the transfer device to transfer the semiconductor package member to the plurality of discharge units.
較佳的是，本發明具開路測試之半導體封裝構件測試系統，其中，開路測試係指主控制器發送一測試訊號至公板模組，公板模組測試半導體封裝構件與測試座之接點導通與否，公板模組發送一確認訊號至主控制器。其中，公板模組係分別輸入一檢測訊號至測試座之每一接點，並檢測每一接點之回應訊號，以判斷半導體封裝構件與測試座之接點導通與否。Preferably, the invention has an open circuit test semiconductor package component test system, wherein the open circuit test means that the main controller sends a test signal to the public board module, and the public board module tests the contact between the semiconductor package component and the test socket. Whether the public board module sends a confirmation signal to the main controller. The public board module inputs a detection signal to each contact of the test socket, and detects the response signal of each contact to determine whether the contact between the semiconductor package component and the test socket is conductive.
再且，本發明之公板模組的儲存單元儲存有一作業系統，而公板模組內可運行作業系統。另外，本發明之半導體封裝構件可為一堆疊式封裝晶片。Moreover, the storage unit of the public board module of the present invention stores an operating system, and the operating system can be operated in the public board module. Additionally, the semiconductor package component of the present invention can be a stacked package wafer.
2‧‧‧公板模組2‧‧‧ public board module
21‧‧‧測試座21‧‧‧ test seat
22‧‧‧儲存單元22‧‧‧ storage unit
210‧‧‧接點210‧‧‧Contacts
3‧‧‧通訊模組3‧‧‧Communication module
4‧‧‧測試分類裝置4‧‧‧Test classification device
41‧‧‧供料單元41‧‧‧Feeding unit
42‧‧‧出料單元42‧‧‧Drawing unit
43‧‧‧移載裝置43‧‧‧Transfer device
5‧‧‧主控制器5‧‧‧Master controller
As‧‧‧啟動訊號As‧‧‧Start signal
C‧‧‧半導體封裝構件C‧‧‧Semiconductor package components
Cr‧‧‧分類結果Cr‧‧‧ classification results
Cs‧‧‧確認訊號Cs‧‧‧Confirmation signal
Cp‧‧‧通訊程式Cp‧‧‧ communication program
Rs‧‧‧測試結果Rs‧‧‧ test results
Ts‧‧‧測試訊號Ts‧‧‧ test signal
Tp‧‧‧測試程式Tp‧‧‧ test program
OS‧‧‧作業系統OS‧‧‧ operating system
圖1係本發明一較佳實施例之系統架構圖。1 is a system architecture diagram of a preferred embodiment of the present invention.
圖2係本發明一較佳實施例之示意圖。2 is a schematic view of a preferred embodiment of the present invention.
圖3係本發明一較佳實施例之測試流程圖。3 is a flow chart of a test in accordance with a preferred embodiment of the present invention.
本發明具開路測試之半導體封裝構件測試系統與方法在本實施例中被詳細描述之前，要特別注意的是，以下的說明中，類似的元件將以相同的元件符號來表示。Prior to the detailed description of the semiconductor package member test system and method of the present invention having an open circuit test, it is to be noted that in the following description, like elements will be denoted by the same reference numerals.
請同時參閱圖1、及圖2，圖1係本發明具開路測試之半導體封裝構件測試系統一較佳實施例之系統架構圖，圖2係本發明具開路測試之半導體封裝構件測試系統一較佳實施例之示意圖。如圖中所示，本發明一種具開路測試之半導體封裝構件測試系統，其主要包括一主控制器5、及一測試分類裝置4，且主控制器5係電性連接測試分類裝置4。再者，測試分類裝置4包括一供料單元41、一公板模組2、三出料單元42、一通訊模組3、以及一移載裝置43。其中，供料單元41係用來載置待測試之半導體封裝構件C。Please refer to FIG. 1 and FIG. 2 together. FIG. 1 is a system architecture diagram of a semiconductor package component testing system with open circuit test according to the present invention. FIG. 2 is a comparison diagram of a semiconductor package component testing system with open circuit testing according to the present invention. A schematic of a preferred embodiment. As shown in the figure, the present invention provides a test system for a semiconductor package member having an open circuit test, which mainly includes a main controller 5 and a test classification device 4, and the main controller 5 is electrically connected to the test classification device 4. Furthermore, the test classification device 4 includes a feeding unit 41, a male board module 2, a three discharging unit 42, a communication module 3, and a transfer device 43. The feeding unit 41 is used to mount the semiconductor package member C to be tested.
再者，公板模組2包括有一測試座21、及一儲存單元22，而儲存單元22內儲存有一測試程式Tp、一通 訊程式Cp、及一作業系統OS，且公板模組2常時運行作業系統OS。然而，於此處所稱之作業系統OS為一般常見之Linux作業系統、或視窗作業系統，如Windows 2000、以及Windows XP；公板模組2係指發表半導體封裝構件C時所同步認證發表之公板；測試程式Tp係指公板模組2本身內建的測試程式；而通訊程式Cp係用來使主控制器5與公板模組2間達成資訊連接。Furthermore, the public board module 2 includes a test stand 21 and a storage unit 22, and the storage unit 22 stores a test program Tp and a pass. The program program Cp and an operating system OS, and the public board module 2 constantly runs the operating system OS. However, the operating system OS referred to herein is a common Linux operating system or a Windows operating system, such as Windows 2000 and Windows XP; the public board module 2 refers to the publicly issued certification of the semiconductor package component C. The test program Tp refers to the built-in test program of the public board module 2; and the communication program Cp is used to make an information connection between the main controller 5 and the public board module 2.
另外，如圖中所示，三個出料單元42包括良品、及不良品承載單元，其係用來載置完成測試並經分類後之半導體封裝構件C。又，通訊模組3係電性連接於公板模組2與主控制器5之間，本實施例所採用之通訊模組3為一通用型輸入輸出連接介面(General Purpose I/O，GPIO)，但並不侷限於此，其亦可為RS232、或其他等效連接介面。In addition, as shown in the figure, the three discharge units 42 include a good product and a defective product carrying unit for mounting the semiconductor package member C which has been tested and classified. Moreover, the communication module 3 is electrically connected between the public board module 2 and the main controller 5. The communication module 3 used in this embodiment is a general-purpose input/output connection interface (General Purpose I/O, GPIO). ), but not limited to this, it can also be RS232, or other equivalent connection interface.
再且，移載裝置43係用來移載半導體封裝構件C於供料單元41、公板模組2上之測試座21、以及複數個出料單元42之間。而且，當移載裝置43將半導體封裝構件C置於測試座21內並進行測試時，移載裝置43同時充當壓接機構，以施力抵接半導體封裝構件C，使其確實與測試座21電性接觸。當然，在本實施例之圖式中僅示出一移載裝置43，但本發明並不侷限於單一移載裝置43，亦可包括多個移載單元而分別負責局部移載任務。此外，在本實施例中半導體封裝構件C為一堆疊式封裝晶片。Furthermore, the transfer device 43 is used to transfer the semiconductor package member C between the supply unit 41, the test holder 21 on the male module 2, and a plurality of discharge units 42. Moreover, when the transfer device 43 places the semiconductor package member C in the test holder 21 and performs the test, the transfer device 43 simultaneously functions as a crimping mechanism to abut against the semiconductor package member C so as to be surely connected to the test holder 21. Electrical contact. Of course, only one transfer device 43 is shown in the drawings of the present embodiment, but the present invention is not limited to a single transfer device 43, and may also include a plurality of transfer units for being responsible for local transfer tasks, respectively. Further, in the present embodiment, the semiconductor package member C is a stacked package wafer.
請再一併參閱圖3，圖3係本發明一較佳實施例之測試流程圖。如圖中所示，於主控制器5啟動測試時 (步驟S105)，測試分類裝置4之移載裝置43將移載半導體封裝構件C至公板模組2上之測試座21內，並壓接該半導體封裝構件C，使其確實與測試座21內之接點210電性接觸，即步驟S205。Please refer to FIG. 3 again. FIG. 3 is a test flow chart of a preferred embodiment of the present invention. As shown in the figure, when the main controller 5 starts the test (Step S105), the transfer device 43 of the test sorting device 4 transfers the semiconductor package member C to the test socket 21 on the common plate module 2, and crimps the semiconductor package member C to make it positive with the test stand 21. The contact 210 is electrically contacted, that is, step S205.
接著，主控制器5啟動連線時(步驟S110)，主控制器5藉由通訊模組3、及通訊程式Cp與測試分類裝置4內之公板模組2建立資訊連接，即步驟S210。其中，通訊程式Cp可預先寫入而儲存於儲存單元22內。Then, when the main controller 5 starts the connection (step S110), the main controller 5 establishes an information connection with the public module 2 in the test classification device 4 via the communication module 3 and the communication program Cp, that is, step S210. The communication program Cp can be pre-written and stored in the storage unit 22.
接著，主控制器5啟動開路測試時(步驟S115)，主控制器5發送一測試訊號Ts至公板模組2，而公板模組2測試半導體封裝構件C與測試座21之接點210導通與否。亦即，公板模組2係分別輸入一檢測訊號至測試座21之每一接點210，並檢測每一接點210之回應訊號，以判斷半導體封裝構件C與測試座21之接點210導通與否，即步驟S215。若經確認全部導通，則公板模組2將發送一確認訊號Cs至主控制器5；惟若經開路測試而出現錯誤情況，則進入一般除錯程序，例如測試分類裝置4、及/或主控制器5將發出警示訊號，以利現場作業人員進行處置。及/或依照一個預定規則，將未達到通過門檻(開路測試)的半導體封裝構件C，重新送入檢測裝置之中，由符合預定規則的檢測裝置，重測未到達通過門檻(開路測試)的半導體封裝構件C，可避免原本的檢測裝置因為檢測誤差導致誤判。於此特別值得一提的是，在本實施例中，當公板模組2接收測試訊號時，公板模組2將停止一切進行中之測試。換言之，不論公板模組2是處於閒置狀態、正 進行功能測試、抑或正進行開路測試，只要當公板模組2接收測試訊號Ts時，公板模組則停止所有測試並重新啟動開路測試。Then, when the main controller 5 starts the open circuit test (step S115), the main controller 5 sends a test signal Ts to the public board module 2, and the public board module 2 tests the contact 210 between the semiconductor package member C and the test seat 21. Turn on or not. That is, the public board module 2 inputs a detection signal to each of the contacts 210 of the test socket 21, and detects the response signal of each contact 210 to determine the junction 210 between the semiconductor package member C and the test socket 21. Turns on or off, step S215. If all the conduction is confirmed, the public board module 2 will send a confirmation signal Cs to the main controller 5; however, if an error condition occurs after the open circuit test, a general debugging procedure, such as the test classification device 4, and/or The main controller 5 will send a warning signal for the on-site operator to handle. And/or according to a predetermined rule, the semiconductor package member C that has not reached the threshold (open circuit test) is re-introduced into the detecting device, and the detecting device that meets the predetermined rule retests the threshold that has not reached the pass threshold (open circuit test). The semiconductor package member C can prevent the original detecting device from being misjudged due to the detection error. It is particularly worth mentioning that in this embodiment, when the public board module 2 receives the test signal, the public board module 2 will stop all ongoing tests. In other words, regardless of whether the public board module 2 is in an idle state, Perform a functional test or an open circuit test. When the public board module 2 receives the test signal Ts, the public board module stops all tests and restarts the open circuit test.
當主控制器5接收到確認訊號Cs後，便啟動功能測試時(步驟S120)，此時主控制器5發送一啟動訊號As至公板模組2，而公板模組2內的作業系統OS便主動執行測試程式Tp以對半導體封裝構件C進行功能測試，即步驟S225。當測試程式Tp執行完畢，即功能測試完畢後，公板模組2將主動回傳測試結果Rs至主控制器5。然而，在本實施例中，作業系統OS處於恆啟動狀態，亦即於每次開路測試與功能測試後，作業系統並不關閉，以便進行次一半導體封裝構件C之測試。When the main controller 5 receives the confirmation signal Cs, the function test is started (step S120), at which time the main controller 5 sends an activation signal As to the public board module 2, and the operating system in the public board module 2 The OS actively executes the test program Tp to perform a functional test on the semiconductor package member C, that is, step S225. After the test program Tp is executed, that is, after the function test is completed, the public board module 2 will actively return the test result Rs to the main controller 5. However, in the present embodiment, the operating system OS is in a constant startup state, that is, after each open circuit test and functional test, the operating system is not turned off to perform the test of the next semiconductor package member C.
再者，當主控制器5接收到測試結果Rs後，便根據測試結果Rs對半導體封裝構件C進行分類，並發送分類結果Cr至測試分類裝置4，即步驟S125。另一方面，當測試分類裝置4接收到分類結果Cr後，便驅使移載裝置43移載半導體封裝構件C至相應的出料單元42，即步驟S225。最後，主控制器5結束連線(步驟S130)並結束測試，亦即公板模組3與主控制器5結束連線，即步驟S230。Further, when the main controller 5 receives the test result Rs, it classifies the semiconductor package member C according to the test result Rs, and transmits the classification result Cr to the test classification device 4, that is, step S125. On the other hand, when the test classification device 4 receives the classification result Cr, the transfer device 43 is caused to transfer the semiconductor package member C to the corresponding discharge unit 42, that is, step S225. Finally, the main controller 5 ends the connection (step S130) and ends the test, that is, the public board module 3 ends the connection with the main controller 5, that is, step S230.
由上可知，本發明所提供之一種具開路測試之半導體封裝構件測試系統與方法至少包括以下功效：(1).於半導體封裝構件進行功能測試前，先行進行開路測試，以進一步篩選無法通過開路測試之半導體封裝構件； (2).藉由開路測試，可偵錯並排除半導體封裝構件與測試座接點接觸不良之情形，以提高測試準確率，且可減少系統出錯後之偵錯和故障排除的延宕時間，又可避免傳統因人為操作所造成的總總問題；以及(3).採用全自動化的測試流程，且每一環節每一步驟皆嚴密監控，一旦某一步驟出錯隨即警示並記錄，現場操作人員得以輕易排除故障原因。It can be seen from the above that the semiconductor package test system and method with open circuit test provided by the present invention at least includes the following effects: (1) Before performing functional test on the semiconductor package member, an open circuit test is performed first to further filter through the open circuit. Tested semiconductor package component; (2). By open circuit test, it can detect and eliminate the bad contact between the semiconductor package component and the test socket contact, so as to improve the test accuracy, and reduce the delay of debugging and troubleshooting after the system error, and It can avoid the total problem caused by traditional human operation; and (3) adopt a fully automated test process, and each step of each step is closely monitored. Once a step is mistaken, it will be alerted and recorded, and the field operator can Easily troubleshoot the cause.
上述實施例僅係為了方便說明而舉例而已，本發明所主張之權利範圍自應以申請專利範圍所述為準，而非僅限於上述實施例。The above-mentioned embodiments are merely examples for convenience of description, and the scope of the claims is intended to be limited to the above embodiments.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
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| TW200823468A (en) * | 2006-11-20 | 2008-06-01 | Winbond Electronics Corp | Method for verifying test program and computer readable recording medium for storing program thereof |
| US20110043233A1 (en) * | 2009-08-18 | 2011-02-24 | Formfactor, Inc. | Wafer level contactor |
| CN102784761A (en) * | 2012-06-25 | 2012-11-21 | 致茂电子(苏州)有限公司 | Semi-packaged stacked wafer testing classification bench |
| TW201304027A (en) * | 2011-07-08 | 2013-01-16 | Hon Tech Inc | Test sorting machine for semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW200630624A (en) * | 2005-02-25 | 2006-09-01 | Task Technology Inc | Systematic inspection method |
| CN1982903A (en) * | 2006-06-07 | 2007-06-20 | 华为技术有限公司 | Rear-panel testing system |
| TW200823468A (en) * | 2006-11-20 | 2008-06-01 | Winbond Electronics Corp | Method for verifying test program and computer readable recording medium for storing program thereof |
| US20110043233A1 (en) * | 2009-08-18 | 2011-02-24 | Formfactor, Inc. | Wafer level contactor |
| TW201304027A (en) * | 2011-07-08 | 2013-01-16 | Hon Tech Inc | Test sorting machine for semiconductor device |
| CN102784761A (en) * | 2012-06-25 | 2012-11-21 | 致茂电子(苏州)有限公司 | Semi-packaged stacked wafer testing classification bench |
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