TWI496148B

TWI496148B - Method of programming flash memory

Info

Publication number: TWI496148B
Application number: TW102105132A
Authority: TW
Inventors: Chu Yung Liu; Hsing Wen Chang; Yao Wen Chang; Tao Cheng Lu
Original assignee: Macronix Int Co Ltd
Priority date: 2013-02-08
Filing date: 2013-02-08
Publication date: 2015-08-11
Also published as: TW201432699A

Description

快閃記憶體的可程式方法Programmable method of flash memory

本發明與非揮發性記憶體，特別針對快閃記憶體的程式化方法有關。The present invention relates to non-volatile memory, particularly to stylized methods of flash memory.

圖1是一個NAND快閃記憶體串的等效電路圖，所述的記憶體串包含與一選串電晶體12相接的位元線，電晶體12的閘極與一選串線(SSL)相接。記憶體串又包含複數個串接具有浮動閘極的記憶體晶胞16，每一個記憶體晶胞16的閘極分別和所對應的字元線WL₀ ~WL_n 電連接，記憶體串也包含一個與接地選擇線GSL相接的接地選擇電晶體14。接地選擇電晶體14置於共源線18與最後一個浮動閘極記憶體晶胞16間。當記憶體晶胞16中的記憶被移除，其閾值電壓會轉為負值而晶胞會被設定一個預設的邏輯值，如”1”，而當有記憶寫入時，晶胞的閾值電壓會轉為正值而晶胞會被設定一個預設的邏輯值，如”0”，一晶胞的預設的邏輯值常會在程式化同一字元線上的其它晶胞時受到干擾，一般來說，一個有效的程式抑制方案來避免當施壓在一字元線時其它不需程式化的記憶體晶胞不受干擾在目前並未看見。1 is an equivalent circuit diagram of a NAND flash memory string, the memory string including a bit line connected to a string transistor 12, a gate of the transistor 12 and a select string (SSL) Docked. The memory string further includes a plurality of memory cells 16 connected in series with floating gates, and the gates of each of the memory cells 16 are electrically connected to the corresponding word lines WL ₀ to WL _n respectively, and the memory strings are also connected. A ground selection transistor 14 is provided that is coupled to the ground select line GSL. The ground selection transistor 14 is placed between the common source line 18 and the last floating gate memory cell 16. When the memory in the memory cell 16 is removed, its threshold voltage will turn negative and the cell will be set to a preset logic value, such as "1", and when there is memory writing, the cell The threshold voltage will be converted to a positive value and the unit cell will be set to a preset logic value, such as "0". The preset logic value of a unit cell is often disturbed when stylizing other unit cells on the same word line. In general, an effective program suppression scheme is used to avoid uninterrupted memory cells that are not required to be stylized when applied to a word line.

本發明的主要目的是要提供一個包含一預先提升(pre-boost)階段的程式化方案來提高一在抑制位元線上被選擇晶胞的通道電位的方法。所述被選擇晶胞的閘極與一將要被施壓的字元線電連結，所述字元線是用來程式化其他位在所述字元線上的晶胞。更進一步來說，本程式化方案主要是要藉由提高受抑制的被選擇晶胞的通道電位，使得當所述字元線在提升階段受到一可程式電壓時，通道電位與所述可程式電壓在被選擇晶胞閘及所形成的壓差可減小。所述的預先提升階段被安排在提升階段前，又包含了一加一第一位準偏壓在位元線的步驟，接著加一第二位準偏壓在選串電晶體的閘極上，其中第二位準偏壓高於第一位準偏壓。所述預先提升階段還包含了在導入所述的提升階段前將選串電晶體的偏壓降至第一位準，在某些實施例中，第二與第一位準之間的差異超過選串電晶體的閾值電壓(threshold voltage)。The main object of the present invention is to provide a stylized scheme including a pre-boost phase to improve selection on a suppression bit line. A method of channel potential of a unit cell. The gate of the selected cell is electrically coupled to a word line to be applied, the word line being used to program other cells located on the word line. Furthermore, the stylization scheme mainly aims to increase the channel potential of the selected selected cell such that when the word line is subjected to a programmable voltage during the boosting phase, the channel potential and the programmable The voltage at the selected cell gate and the resulting differential pressure can be reduced. The pre-elevation phase is arranged before the boosting phase, and further includes a step of adding a first-level bias to the bit line, and then adding a second-level bias to the gate of the string-selective transistor. The second level of the quasi-bias is higher than the first level of the bias. The pre-elevation phase further includes reducing the bias voltage of the string-selective transistor to a first level prior to introducing the boosting phase, and in some embodiments, the difference between the second and first levels exceeds The threshold voltage of the string transistor is selected.

在某些實施例中，預先提升階段包括一加一第一位準偏壓在位元線的步驟，接著加一第二位準偏壓在選串電晶體的閘極上，其中第二位準偏壓高於第一位準偏壓，且第二與第一位準之間的差異超過選串電晶體的閾值電壓以便將選串電晶體打開，在選串電晶體增壓的同時，未被選取的字元線與被選取的字元線會被加壓到一通過電壓，預先提升階段還可包括在施加一可程式電壓在一所選的字元線前將選串電晶體與複數晶胞耦接的複數字元線減壓的步驟，選串電晶體的偏壓可降至第一位準。In some embodiments, the pre-push phase includes a step of adding a first level bias to the bit line, followed by a second level bias on the gate of the string transistor, wherein the second level The bias voltage is higher than the first level bias, and the difference between the second and first levels exceeds the threshold voltage of the string transistor to turn on the string transistor, while the string transistor is boosted, The selected word line and the selected word line are pressurized to a pass voltage, and the pre-up stage may further include selecting the string transistor and the complex number before applying a programmable voltage to a selected word line. The step of decompressing the complex digital element line coupled by the unit cell, the bias voltage of the selected string transistor can be reduced to the first level.

本發明另一方面也提供一方法將一快閃記憶體串中所選的記憶體晶胞的通道電位加以提升。所述的記憶體串可包含一將被抑制的所選晶胞，介於所選晶胞與選串電晶體間的上方晶胞，以及介於所選晶胞與接地選擇線間的下方晶胞。此方法有一預先提升階段用來把被抑制的所選晶胞的通道電位提升，預先提升階段包括一加一第一位準偏壓在位元線的步驟，接著加一第二位準偏壓在選串電晶體的閘極上，其中第二位準偏壓高於第一位準偏壓，且第二與第一位準之間的差異超過選串電晶體的閾值電壓。下方晶胞可選擇性地在選串電晶體增壓的同時，被施以一通過電壓。預先提升階段可進一步包括依順序將下方晶胞上的偏壓減低至一低位準或0伏，在某些實施例中，減壓的順序是自最下方與接地選擇線最接近的晶胞開始逐一向上至最接近所選晶胞的晶胞。Another aspect of the invention also provides a method for boosting the channel potential of a selected memory cell in a flash memory string. The memory string can be packaged Contains a selected unit cell to be suppressed, an upper unit cell between the selected unit cell and the selected string transistor, and a lower unit cell between the selected unit cell and the ground selection line. The method has a pre-elevation phase for boosting the channel potential of the selected selected unit cell, and the pre-elevation phase includes a step of adding a first level bias to the bit line, followed by a second level bias. On the gate of the string transistor, wherein the second level bias is higher than the first level bias, and the difference between the second and first levels exceeds the threshold voltage of the string transistor. The lower cell can be selectively applied with a pass voltage while the string transistor is boosted. The pre-elevation phase may further include sequentially reducing the bias voltage on the lower cell to a low level or 0 volts, in some embodiments, the decompression sequence is from the cell cell closest to the ground selection line at the bottom. One by one up to the unit cell closest to the selected unit cell.

在某些實施例中，預先提升階段進一步在將下方電晶體包含將選串電晶體的上的偏壓減低至低位準後，再將選串電晶體的偏壓降至第一位準的步驟。In some embodiments, the pre-elevation phase further steps to reduce the bias voltage of the string transistor to a first level after the lower transistor includes a bias voltage on the selected string transistor to a low level. .

以下所述的為本發明中所例述的實施例與所附圖示，以各種例示的方式針對本發明做更充分的闡述。所提出的各種例示應整體觀之而不應該斷章取義或以此對本發明所欲保護的範圍加以限縮，所揭露的內容是可供熟悉此領域的技藝人士完整了解。在說明書中所用的"或"字為一連接用語，可是為"和/或"。另外，冠詞"一"可視為單數或複數。"耦接"或"連接"一詞可代表元件間直接連接或間接地透過其他元件進行連接。The invention is described more fully hereinafter with reference to the embodiments of the invention and the accompanying drawings. The various exemplifications set forth herein are intended to be considered as a contin The word "or" used in the specification is a connection term, but is "and/or". In addition, the article "a" can be regarded as singular or plural. The term "coupled" or "connected" may mean direct or indirect transmission between components. Other components are connected.

本發明提供一增進通道電壓的方法，使得被選取化的晶胞的通道可被提升以確保在其他晶胞程式化時不受干擾，所述的方法包含一預先提升階段以確保所選晶胞可以具有較高的預先通道電壓。The present invention provides a method of enhancing the channel voltage such that the channel of the selected unit cell can be boosted to ensure undisturbed when other cells are programmed, the method including a pre-elevation phase to ensure the selected unit cell It can have a higher pre-channel voltage.

圖2描述一本發明中實施例的流程圖，步驟100是在程式化一所選晶胞前導入一預先提升階段，接著在步驟105時，所選晶胞的閘極電連接的一字元線在提升階段被施以一程式化電壓。2 depicts a flow diagram of an embodiment of the present invention. Step 100 is to introduce a pre-elevation phase prior to programming a selected unit cell, and then at step 105, a character of the gate of the selected unit cell is electrically connected. The line is subjected to a stylized voltage during the boost phase.

圖3描述一本發明中的一實施例的流程圖而圖4是一個用本發明中的方法來程式化的一NAND快閃記憶體串的等效電路，步驟200施加一第一位準偏壓在一抑制位元線使得V_BL= V₁ ，通常說來，V₁₌ Vcc。在步驟202時，一第二位準偏壓施加在選串電晶體的閘極上使得V_SSL= V₂ ，而V_SSL 高於V_BL 。一般說來，第二位準大於第一位準加上選串電晶體的閾值電壓V_{SSL_th} ，也就是說，V_SSL >V_BL +V_{SSL_th} 。由於第二位準與第一位準之間的差異超過選串電晶體的閾值電壓使得選串電晶體得以打開，所以位元線的通道電壓將會被提升。在步驟204時，選串電晶體的閘電壓將會自第二位準V₂ 降為第一位準V₁ 以致選串電晶體被關閉，使得在所述位元線上的所有記憶體晶胞處在浮動狀態(floated)。步驟206導入一提升階段用來將一選擇的字元線WL_s 提升至一程式化電壓V_prog =V₃ ，同時也將其他未選取的字元線提升至一通過電壓V_pass =V₄ 。程式化電壓V₃ 的大小必須足夠將與被選取的記憶體晶胞在同一字元線上但不被抑制的其他晶胞加以程式化，而通過電壓V₄ 的大小必須足夠打開未被選取的記憶體晶胞且每一未被選取的記憶體晶胞的通過電壓V₄ 可以彼此不同。下列可用來表示圖4實施例的電壓關係式：0<V₁ <V₂ V_th <V₄ <V₃ 3 depicts a flow diagram of an embodiment of the present invention and FIG. 4 is an equivalent circuit of a NAND flash memory string programmed by the method of the present invention. Step 200 applies a first level shift. Pressing on a suppression bit line causes V _{BL =} V ₁ , which is usually V _{1 =} Vcc. At step 202, a second level bias is applied to the gate of the string transistor such that V _{SSL =} V ₂ and V _{SSL is} higher than V _BL . Generally, the second level is greater than the first level plus the selected string transistor threshold voltage _V SSL_th, that _{_{is, V SSL> V BL + V}} SSL_th. Since the difference between the second level and the first level exceeds the threshold voltage of the string transistor so that the string transistor is turned on, the channel voltage of the bit line will be boosted. At step 204, the gate voltage of the selected string transistor will be reduced from the second level V ₂ to the first level V ₁ such that the selected string transistor is turned off, so that all memory cells on the bit line In a floating state (floated). Step 206 is directed to a boost phase for boosting a selected word line WL _s to a programmed voltage V _prog =V ₃ while also boosting other unselected word lines to a pass voltage V _pass =V ₄ . The size of the stylized voltage V ₃ must be sufficient to program the other cells that are on the same word line but not suppressed by the selected memory cell, and the magnitude of the pass voltage V ₄ must be sufficient to open the unselected memory. The body cells and the pass voltage V _{4 of} each of the unselected memory cells may be different from each other. The following can be used to represent the voltage relationship of the embodiment of Figure 4: 0 < V ₁ < V ₂ V _th < V ₄ < V ₃

圖5A是用來表示一NAND串400的剖面圖，圖5B是代表圖5A上一施加電壓的時序圖。NAND串400包括複數個記憶體晶胞402分別與相對應的字元線WL₀ 到WL_n 連接、一選串電晶體403將NAND串400與一位元線500耦接、與一接地選擇電晶體405將NAND串400與一源極線505耦接，NAND串形成於一p型的基板中，記憶體晶胞的源極與汲極是n型的擴散區。Figure 5A is a cross-sectional view showing a NAND string 400, and Figure 5B is a timing chart showing an applied voltage in Figure 5A. The NAND string 400 includes a plurality of memory cells 402 connected to corresponding word lines WL ₀ to WL _n , a select string transistor 403 coupling the NAND string 400 to the one bit line 500, and a ground selection The crystal 405 couples the NAND string 400 to a source line 505. The NAND string is formed in a p-type substrate. The source and drain of the memory cell are n-type diffusion regions.

在t₀ 時，位元線500開始加壓並在t₁ 達到一第一位準V₁ ，在本實施例中，位元線維持的第一位準V₁ 可為V_cc ，t₂ 時選串電晶體403開始加壓使得選串電晶體的電位V_SSL 在t₃ 達到一第二位準V₂ ，其中第二位準大於V₁ +V_{SSL_th} ，在t₄ 時，選串電晶體的電位開始自第二位準V₂ 下降並在t₅ 達到第1位準V₁ ，接著在t₅ 與t₆ 間加入一提升階段，並在t₆ 時將被選取的晶胞402-1的閘極藉由被選取的字元線WL_seclect 加壓並在t₇ 時達到V_seclect =V_prog= V₃ ，同時t₆ 時每一個未被選取的記憶體晶胞也透過與其對應連接的字元線加以升壓，並在t₇ 時達到V_unseclect =V_pass =V₄ 。在t₈ 時，所有的記憶體晶胞，包括被選取的與未被選取的開始降壓。在某些圖5B所示的實施例中，在t₉ 時V_seclect 與V_unseclect 可同時降壓至與預提升階段時相同的位準。圖5B中的V_ch 代表的是在選取的晶胞402-1的一通道電壓，在t₂ 當選串電晶體403開始增壓時，V_ch 也被位元線電壓V_BL 充電並在t₃ 時至一預提升的位準V_chin ，而所述的通道電壓會在t₆ 時藉由施加在選取的與未被選取的記憶體晶胞上的電壓提升至較高的位準V₅ 。根據本發明的實施例，提升階段時通道電壓V_ch 可由下方的關係式(1)取得： At t _0, the bit line 500 and begins to pressurize t ₁ reaches a first level V _1, in the present embodiment, the bit line to maintain a first level V ₁ may be a V _cc, t ₂ when The string selection transistor 403 starts to pressurize so that the potential V _{SSL of the} string selection transistor reaches a second level V ₂ at t ₃ , wherein the second level is greater than V ₁ +V _{SSL_th} , and at t ₄ , the string transistor is selected start the potential from the second lowered level V ₂ and t ₅ reaches a quasi-bit V _1, followed by t ₅ and t ₆ m-a lifting phase, and will be selected at the time t ₆ of the unit cell 402-1 the gate is selected by the word line _WL seclect pressurized and when t reaches _V seclect ₇ ₌ V _prog = V _3, t ₆ while each of the unselected memory cell is also connected through the corresponding The word line is boosted and reaches V _unseclect =V _pass =V ₄ at t ₇ . At t ₈ , all memory cells, including selected and unselected, begin to depressurize. In some of the embodiments shown in Figure 5B, V _seclect and V _unseclect can be _stepped down to the same level as in the pre-elevation phase at t ₉ . FIG. 5B V _ch represents the channel voltage in a selected cell 402-1, when elected t ₂ transistor 403 series supercharging is started, V _ch is also charged bit line voltage V _BL and t ₃ The time is up to a pre-elevated level V _chin , and the channel voltage is boosted to a higher level V ₅ by a voltage applied to the selected and unselected memory cells at t ₆ . According to an embodiment of the invention, the channel voltage _Vch during the boost phase can be obtained from the relation (1) below:

其中，V_chin 是預提升階段的通道電壓，V_pass 是未選取記憶體晶胞上的偏壓，V_th 是選取記憶體晶胞的閾值電壓，V_prog 是施加在被選取的字元線WL_seclect 上未受抑制晶胞的可程式電壓，N是在記憶體串400中記憶體晶胞的總數量，α和β分別代表不同的常數。Where V _chin is the channel voltage in the pre-elevation phase, V _pass is the bias voltage on the unselected memory cell, V _th is the threshold voltage at which the memory cell is selected, and V _prog is applied to the selected word line WL _The programmable voltage of the unsuppressed unit cell on the _seclect , N is the total number of memory unit cells in the memory string 400, and α and β represent different constants, respectively.

圖6繪示本發明方法的一實施例，圖7是代表本發明一施加電壓的時序圖。步驟600施加一第一位準偏壓在一抑制位元線使得V_BL= V₁ ，通常說來，V₁₌ Vcc。在步驟602時，一比V₁ 高的第二位準偏壓施加在選串電晶體的閘極上使得V_SSL= V₂ ，而V_SSL 高於V_BL 。一般說來，第二位準大於第一位準加上選串電晶體的閾值電壓V_{SSL_th} ，也就是說，V_SSL >V_BL +V_{SSL_th} 。由於第二位準與第一位準之間的差異超過選串電晶體的閾值電壓使得選串電晶體得以打開，所以位元線的通道電壓將會被提升。與步驟602同步或分時，步驟603將所有記憶體晶胞提升至一第四位準使得V_pass =V₄ ，其中第四位準可用來將通道的位準加以提升，在本實施例中，V₄ 比未受抑制晶胞的可程式電壓V_prog 為低，但比V_cc 高，在某些實施例中，步驟603可安排在步驟602前。Figure 6 is a diagram showing an embodiment of the method of the present invention, and Figure 7 is a timing chart showing an applied voltage of the present invention. Step 600 applies a bias in a first level bit line so that inhibition V _{BL =} V _1, generally speaking, V _{1 =} Vcc. In step 602, a higher level than the second bias voltage V ₁ is applied to the selected string gate of the transistor such that V _{SSL =} V _2, and V _SSL is higher than V _BL. In general, the second level is greater than the first level plus the threshold voltage V _{SSL_th of the} string transistor, that is, V _SSL >V _BL +V _{SSL_th} . Since the difference between the second level and the first level exceeds the threshold voltage of the string transistor so that the string transistor is turned on, the channel voltage of the bit line will be boosted. Time-synchronized with the step 602 or step 603 to lift all of the memory cell such that a fourth quasi-V _pass = V _4, wherein the fourth level will be used to enhance the level of the channel, in the present embodiment, V _{4 is} lower than the programmable voltage V _prog of the unsuppressed unit cell, but higher than V _cc . In some embodiments, step 603 may be arranged before step 602 .

步驟604將選串電晶體的閘電壓自第二位準降為第一位準，而記憶體晶胞的閘極電壓也降至一低位準或0V，在某些實施例中，所述的低位準為記憶體晶胞在步驟602前的閘極電壓的起始位準，在步驟606導入一提升階段用來將一被選取的字元線提升至一程式化電壓V_prog =V₃ ，同時也將其他未被選取的字元線提升至一通過電壓V_pass 。程式化電壓的大小必須足夠將與被選取的記憶體晶胞在同一字元線上但不被抑制的其他晶胞加以程式化，而通過電壓的大小必須足夠打開未被選取的記憶體晶胞。Step 604 reduces the gate voltage of the string transistor from the second level to the first level, and the gate voltage of the memory cell also drops to a low level or 0V. In some embodiments, the The low level is the starting level of the gate voltage of the memory cell before step 602. In step 606, a boosting phase is introduced to boost a selected word line to a stylized voltage V _prog =V ₃ . At the same time, other unselected word lines are also raised to a pass voltage _Vpass . The stylized voltage must be of sufficient size to be stylized with other cells that are on the same word line but not suppressed by the selected memory cell, and the pass voltage must be large enough to open the unselected memory cell.

參考圖5A與圖7，在t₀ 時，位元線500開始加壓並在t₁ 達到一第一位準V₁ ，在本實施例中，位元線的電壓V_BL 維持在第一位準V₁ ，t₂ 時選串電晶體403開始加壓使得選串電晶體的電位V_SSL 在t₃ 達到一第二位準V₂ ，其中第二位準大於V₁ +V_{SSL_th} 。t₂ 時未被選取的記憶體晶胞402與被選取的記憶體晶胞402-1也透過與其對應連接的字元線加以升壓至一第四位準V₄ ，t₄ 時，選串電晶體的電位開始自第二位準V₂ 下降並在t₅ 達到與V_BL 相同的第1位準V₁ ，每一記憶體晶胞也同時降壓至一低位準或0伏，在某些實施例中，所述的低位準為記憶體晶胞在t₂ 升壓前記憶體晶胞的閘極電壓。接著在t₅ 之後加入一與圖5B相同的提升階段。根據本發明，所述的電壓，時間與加壓間距都是可調整的。Referring to FIG 5A and FIG 7, when t _0, bit line 500 and begins to pressurize t ₁ reaches a first level V _1, in the present embodiment, the bit line voltage V _BL is maintained at the first The quasi-V ₁ , t ₂ select string transistor 403 begins to pressurize so that the potential V _{SSL of the} string-selective transistor reaches a second level V ₂ at t ₃ , wherein the second level is greater than V ₁ +V _{SSL_th} . The unselected memory cell 402 at t ₂ and the selected memory cell 402-1 are also boosted to a fourth level V ₄ , t ₄ by the word line connected thereto, and the string is selected. The potential of the transistor begins to decrease from the second level V ₂ and reaches the same first level V ₁ as V _BL at t ₅ , and each memory cell also drops to a low level or 0 volt at the same time. in some embodiments, the low level of the memory cell at t ₂ before the memory cell is boosted gate voltage. Followed by addition of a ramp-up phase in the same FIG. 5B after t _5. According to the invention, the voltage, time and pressurization spacing are adjustable.

圖8是一個NAND快閃記憶體串的等效電路，記憶體串有一被選取將被抑制的記憶體晶胞802，並有N+1個位於記憶體晶胞802與接地選擇線GSL之間的下方記憶體晶胞(M₀ ~M_N )，以及位於記憶體晶胞802與串選擇線SSL之間的上方記憶體晶胞，其中該下方記憶體晶胞距離該串選擇電晶體較該被選取記憶體晶胞為遠且該上方記憶體晶胞距離該串選擇電晶體較一被選取記憶體晶胞為近。圖9為根據本揭露的一實施例的方法，步驟900施加一第一位準偏壓V₁ 在一抑制位元線，通常說來，V₁₌ Vcc。在步驟902時，一比V₁ 高的第二位準偏壓V₂ 施加在選串電晶體的閘極上。一般說來，第二位準大於第一位準加上選串電晶體的閾值電壓V_{SSL_th} ，也就是說，V₂ >V₁ +V_{SSL_th} 。在步驟903時，與下方記憶體晶胞連接的字元線升壓至一第四位準V₄ ，在步驟904時，與上方記憶體晶胞連接的字元線升壓至一第六位準V₆ ，在步驟906時，下方記憶體晶胞以一由下往上的順序依序減壓，也就是自距離GSL最近的記憶體晶胞開始減壓至一低位準，並依序向上結束於緊鄰被選取的記憶體晶胞802的下方記憶體晶胞。在步驟908時，選串電晶體的閘極電壓降至V₁ 。在此要強調的是，步驟900至904的排列順序是可以根據需要做調整的。8 is an equivalent circuit of a NAND flash memory string having a memory cell 802 selected to be suppressed, and having N+1 between the memory cell 802 and the ground selection line GSL. a lower memory cell (M ₀ ~M _N ), and an upper memory cell located between the memory cell 802 and the string selection line SSL, wherein the lower memory cell is closer to the string selection transistor The selected memory cell is far away and the upper memory cell is closer to the selected cell than the selected memory cell. FIG. 9 illustrates a method in accordance with an embodiment of the present disclosure. Step 900 applies a first level bias voltage V ₁ to a suppression bit line, typically V _{1 =} Vcc. In step 902, a selected string is applied to the gate of the transistor V ₁ higher than the second bias voltage level V _2. In general, the second level is greater than the first level plus the threshold voltage V _{SSL_th of the} string transistor, that is, V ₂ >V ₁ +V _{SSL_th} . In step 903, the word line connected to the memory cell below the boost to a fourth level V _4, at step 904, the word line connected to the upper memory cell to a sixth boost Quasi-V ₆ , in step 906, the lower memory cell is sequentially decompressed in a bottom-up order, that is, the memory cell closest to the GSL starts to decompress to a low level, and sequentially Ends with the lower memory cell immediately adjacent to the selected memory cell 802. In step 908, the selected string transistor gate voltage drops V _1. It is emphasized here that the order of the steps 900 to 904 can be adjusted as needed.

圖10是代表本發明一施加於圖8實施例的電壓時序圖，在t₀ 時，位元線BL開始加壓並在t₁ 達到一第一位準V₁ ，位元線的電壓V_BL 維持在第一位準V₁ ，t₁ 時選串電晶體開始加壓使得選串電晶體的電位V_SSL 在t₂ 達到一第二位準V₂ ，其中第二位準大於V₁ +V_{SSL_th} 。t₂ 時上方與下方的記憶體晶胞可選擇性地透過與其對應連接的字元線加以升壓至一第四或第六位準的通過電壓V_pass =V₄ or V₆ ，其中每一個下方記憶體晶胞可被施加一相同或或不同的通過電壓，可以V_pass-x ，X=0~N來表示，每一晶胞上的通過電壓必須足以將晶胞下方的通道導通。每一個上方記憶體晶胞可被施加一與下方記憶體晶胞V_pass-x 相同或不同的通過電壓V_{pass_norm} ，一般說來，V_{pass_norm} 必須足以將上方記憶體晶胞下的通道導通。另一方面，在將位元線BL或選串電晶體施加偏壓前，通過電壓可先施加於未被選取的記憶體晶胞上，與被選取的記憶體晶胞802閘極電連接的被選取字元線以及與上方記憶體晶胞電連接的其他字元線在預提升階段時可以選擇性地施加或不施加電壓。FIG 10 is a voltage representative of the present invention is applied to a timing chart of the embodiment in FIG. 8, at the time t _0, bit line BL begins to pressurize and t ₁ reaches a first level V _1, the voltage V _BL of the bit line is maintained at a first level V _{_1,} t ₁ election series transistor such that the selected string starting pressurization transistor in the potential V _SSL t ₂ reaches a second level V _2, wherein the second level is greater than V ₁ + V _{SSL_th} . At t ₂ , the upper and lower memory cells can be selectively boosted to a fourth or sixth level pass voltage V _pass =V ₄ or V ₆ through each of the corresponding word lines connected thereto, each of which The lower memory cell can be applied with the same or different pass voltage, which can be represented by V _pass-x , X = 0~N, and the pass voltage on each cell must be sufficient to turn on the channel under the cell. Each of the upper memory cells can be applied with a _pass voltage _{Vpass_norm} that is the same as or different from the underlying memory cell _Vpass _-x . In general, _{Vpass_norm} must be sufficient to turn on the channel under the upper memory cell. On the other hand, before the bit line BL or the string transistor is biased, the pass voltage can be first applied to the unselected memory cell and electrically connected to the gate of the selected memory cell 802. The selected word line and other word lines electrically coupled to the upper memory cell may or may not be selectively applied during the pre-emphasis phase.

過了t₂ 在時間為t₃ 時，最底端具有V_{pass_0} 通過電壓的記憶體晶胞開始減壓，到t₄ 時壓降至一可為施加通過電壓前的起始值的低位準，到t₅ 時最底端上一個具有V_{pass_1} 通過電壓的記憶體晶胞壓降至一可為施加通過電壓前的起始值的低位準，依序地，下方記憶體晶胞開始由下而上自t₃ 開始到t_3+N+1 將M₀ 至M_N 逐步降壓，在t_3+N+1 時，選串電晶體的電位V_SSL 會降到一較低的位準如第一位準，接著在t_3+N+1 之後可加入一提升階段來施加可程式電壓於一與被選取的記憶體晶胞閘極電連接的字元線。本實施例的另一優點是能解決當有任何一個位於被選取的記憶體晶胞802下方的晶胞如M_N 程式化後的背格局效應(Back Pattern Effect)。由於程式化後的晶胞具有較高的閾值電壓，因此當下方記憶體晶胞通過電壓同時被移除時，通道電壓將會下降至接近0的低位準，而根據本發明實施例的逐步降壓步驟，可以避免類似情形發生，直到M_N 的通過電壓被移除，通道電壓依然可維持在一較高的位準以利接下來的提升階段。After t _{2 is} at time t ₃ , the memory cell with the V _{pass_0} pass voltage at the bottom end begins to decompress, and at t ₄ the voltage drops to a low level which can be the starting value before the pass voltage is applied. t ₅ to the bottom of the _V pass_1 reduced by having a memory cell voltages of a low level by the initial value before the voltage, sequentially, beginning below the memory cell to be applied by the From the beginning of t ₃ to t _3+N+1, M ₀ to M _{N are} stepped down step by step. At t _3+N+1 , the potential V _{SSL of the} string selection transistor is lowered to a lower level. One bit, then a boost phase can be added after t _3+N+1 to apply a programmable voltage to a word line electrically connected to the selected memory cell gate. Another advantage of this embodiment is that the unit cell can be resolved if there is any memory cell 802 beneath a positioned to be selected as a back pattern effect (Back Pattern Effect) after M _N stylized. Since the stylized unit cell has a higher threshold voltage, when the lower memory cell passes the voltage while being removed, the channel voltage will drop to a low level close to zero, and the step down in accordance with an embodiment of the present invention pressure step, to avoid a similar situation occurs, M _N until the voltage is removed by the channel voltage can still be maintained at a high level in order to facilitate the subsequent lifting phase.

表一列出圖10所式的實施例的範例電壓值。Table 1 lists example voltage values for the embodiment of the formula of Figure 10.

藉由上述的設定值，所述的NAND串的提升電壓可更有效率地抑制被選取的記憶體晶胞802以避免受到干擾。With the above set values, the boosted voltage of the NAND string can more effectively suppress the selected memory cell 802 from being disturbed.

以上實例及描述中已充分地描述本發明之方法及特徵。應理解，在不脫離本發明之精神的情況下之任何修改或改變意欲涵蓋於本發明之保護範疇中。The methods and features of the present invention have been fully described in the foregoing examples and description. It is to be understood that any modifications or changes may be made without departing from the spirit of the invention.

12，14‧‧‧電晶體12,14‧‧‧Optoelectronics

16‧‧‧記憶體晶胞16‧‧‧ memory cell

18‧‧‧源極線18‧‧‧ source line

400‧‧‧記憶體串400‧‧‧ memory strings

402‧‧‧記憶體晶胞402‧‧‧Memory cell

402-1‧‧‧被選取記憶體晶胞402-1‧‧‧Selected memory cell

403，405‧‧‧電晶體403,405‧‧‧Optoelectronics

500‧‧‧位元線500‧‧‧ bit line

505‧‧‧源極線505‧‧‧ source line

802‧‧‧被選取記憶體晶胞802‧‧‧ selected memory cell

圖1描繪一習知的快閃記憶體串等效電路Figure 1 depicts a conventional flash memory string equivalent circuit

圖2描繪根據一實施例的方法流程2 depicts a method flow in accordance with an embodiment

圖3描繪根據一實施例的方法流程3 depicts a method flow in accordance with an embodiment

圖4描繪一實施例的等效電路Figure 4 depicts an equivalent circuit of an embodiment

圖5A描繪一實施例的結構剖面圖Figure 5A depicts a cross-sectional view of an embodiment of the structure

圖5B描繪一實施例的電壓時序圖Figure 5B depicts a voltage timing diagram of an embodiment

圖6描繪根據一實施例的方法流程Figure 6 depicts a method flow in accordance with an embodiment

圖7描繪一實施例的電壓時序圖Figure 7 depicts a voltage timing diagram of an embodiment

圖8描繪一實施例的等效電路Figure 8 depicts an equivalent circuit of an embodiment

圖9描繪根據一實施例的方法流程Figure 9 depicts a method flow in accordance with an embodiment

圖10描繪一實施例的電壓時序圖Figure 10 depicts a voltage timing diagram of an embodiment

Claims

一程式化一NAND快閃記憶體的方法，所述方法包含：一預先提升階段安排在一提升階段前，其中所述預先提升階段包含：將一位元線施加偏壓至一第一電壓；將一串選擇電晶體加偏壓至一第二電壓；及將所述串選擇電晶體的偏壓降至第一電壓。A method of staging a NAND flash memory, the method comprising: pre-upgrading a phase before a lifting phase, wherein the pre-upgrading phase comprises: biasing a bit line to a first voltage; A string of select transistors is biased to a second voltage; and the bias of the string select transistor is reduced to a first voltage.

如請求項1的方法，其中所述第二電壓與第一電壓的差值大於所述串選擇電晶體的閾值電壓。The method of claim 1, wherein the difference between the second voltage and the first voltage is greater than a threshold voltage of the string selection transistor.

一程式化一NAND快閃記憶體串的方法，所述方法包含：一預先提升階段安排在一提升階段之前，所述的預先提升階段包含：將一位元線施加偏壓至一第一電壓；將一串選擇電晶體加偏壓至一第二電壓；將所有的字元線加偏壓至一第四電壓；將所述串選擇電晶體的偏壓降至第一電壓；以及將所述字元線的偏壓降至一低電壓。A method of staging a NAND flash memory string, the method comprising: arranging a pre-upgrade phase prior to a boost phase, the pre-push phase comprising: biasing a bit line to a first voltage Placing a string of select transistors to a second voltage; biasing all of the word lines to a fourth voltage; reducing the bias voltage of the string selection transistor to a first voltage; The bias voltage of the word line is reduced to a low voltage.

如請求項3的方法，其中所述第二電壓與第一電壓的差值大於所述串選擇電晶體的閾值電壓。The method of claim 3, wherein the difference between the second voltage and the first voltage is greater than a threshold voltage of the string selection transistor.

如請求項3的方法，其中所述的低電壓是字元線在加偏壓前的起始電壓。The method of claim 3, wherein the low voltage is a starting voltage of the word line before biasing.

如請求項3的方法，其中所述第一電壓為V_cc 。The method according to item 3 of the request, wherein the first voltage is V _cc.

一程式化一NAND快閃記憶體串的方法，所述方法包含：一預先提升階段安排在一提升階段之前，所述的預先提升階段包含：將一位元線施加偏壓至一第一電壓；將一串選擇電晶體加偏壓至一第二電壓；將一下方記憶體晶胞加偏壓至一第四電壓，其中該下方記憶體晶胞距離該串選擇電晶體較一被選取記憶體晶胞為遠；將一上方記憶體晶胞加偏壓至一第六電壓，其中該上方記憶體晶胞距離該串選擇電晶體較一被選取記憶體晶胞為近；以及依序降下所述下方記憶體晶胞的偏壓。 A method of staging a NAND flash memory string, the method comprising: arranging a pre-upgrade phase prior to a boost phase, the pre-push phase comprising: biasing a bit line to a first voltage And biasing a string of selective transistors to a second voltage; biasing a lower memory cell to a fourth voltage, wherein the lower memory cell is selected from the string of selected transistors The body cell is far away; an upper memory cell is biased to a sixth voltage, wherein the upper memory cell is closer to the selected cell than the selected memory cell; and sequentially lowered The bias of the lower memory cell.

如請求項7的方法，進一步加所述的第四電壓至複數個下方記憶體晶胞。 The method of claim 7, further adding the fourth voltage to a plurality of lower memory cells.

如請求項8的方法，其中所述依序降下每一下方記憶體晶胞的偏壓是依照一挨次進行的順序。 The method of claim 8, wherein the sequentially lowering the bias voltage of each of the lower memory cells is performed in an order of one pass.

如請求項9的方法，其中所述挨次進行的順序是從底端的晶胞開始逐一向上並結束於被選取記憶體晶胞的正下方的晶胞。 The method of claim 9, wherein the order in which the order is performed is one from top to bottom of the unit cell and ending at the unit cell directly below the selected memory unit cell.

如請求項8的方法，其中每一下方記憶體晶胞所提升的偏壓可彼此不同。 The method of claim 8, wherein the bias voltages raised by each of the lower memory cells are different from each other.

如請求項7的方法，其中所述的第四電壓與第六電壓相同。 The method of claim 7, wherein the fourth voltage is the same as the sixth voltage.

如請求項7的方法，其中所述第二電壓與第一電壓的差值大於所述串選擇電晶體的閾值電壓。 The method of claim 7, wherein the difference between the second voltage and the first voltage is greater than a threshold voltage of the string selection transistor.

如請求項7之方法，進一步包含將所述串選擇電晶體的偏壓降至一較低電壓。 The method of claim 7, further comprising reducing the bias voltage of the string selection transistor to a lower voltage.

如請求項14之方法，其中所述較低電壓之電壓值大小為所述的第一電壓之電壓值大小。 The method of claim 14, wherein the voltage value of the lower voltage is a magnitude of a voltage value of the first voltage.

如請求項7之方法，進一步包含在依序降下所述下方記憶體晶胞的偏壓後將所述串選擇電晶體的偏壓降至一較低電壓。 The method of claim 7, further comprising reducing the bias voltage of the string selection transistor to a lower voltage after sequentially lowering a bias voltage of the lower memory cell.

如請求項7之方法，其中將下方記憶體晶胞加偏壓至第三電壓是在將位元線施加偏壓至第一電壓之前。 The method of claim 7, wherein biasing the lower memory cell to the third voltage is prior to applying the bit line to the first voltage.

如請求項7之方法，其中將下方記憶體晶胞加偏壓至第六電壓是在將位元線施加偏壓至第一電壓之前。 The method of claim 7, wherein biasing the lower memory cell to the sixth voltage is prior to applying the bit line to the first voltage.

如請求項7之方法，其中所述的第一電壓是V_cc 。The method of claim 7, wherein the first voltage is V _cc .