WO2008030775A3 - Programming non-volatile memory with improved boosting - Google Patents

Programming non-volatile memory with improved boosting Download PDF

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Publication number
WO2008030775A3
WO2008030775A3 PCT/US2007/077402 US2007077402W WO2008030775A3 WO 2008030775 A3 WO2008030775 A3 WO 2008030775A3 US 2007077402 W US2007077402 W US 2007077402W WO 2008030775 A3 WO2008030775 A3 WO 2008030775A3
Authority
WO
WIPO (PCT)
Prior art keywords
storage elements
storage element
program disturb
voltage
storage
Prior art date
Application number
PCT/US2007/077402
Other languages
French (fr)
Other versions
WO2008030775A2 (en
Inventor
Fumitoshi Ito
Original Assignee
Sandisk Corp
Fumitoshi Ito
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US11/516,976 external-priority patent/US7440326B2/en
Application filed by Sandisk Corp, Fumitoshi Ito filed Critical Sandisk Corp
Publication of WO2008030775A2 publication Critical patent/WO2008030775A2/en
Publication of WO2008030775A3 publication Critical patent/WO2008030775A3/en

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5628—Programming or writing circuits; Data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/12—Programming voltage switching circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3418—Disturbance prevention or evaluation; Refreshing of disturbed memory data
    • G11C16/3427—Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3418—Disturbance prevention or evaluation; Refreshing of disturbed memory data

Abstract

Non-volatile storage elements are programmed in a manner that reduces program disturb/ particularly at the edges storage elements strings, by using modified pass voltages. In particular, during the programming (Vpgm) of a selected ' storage element (WLx), an isolation voltage (y) is applied to a storage element (2) proximate to the selected storage element thereby electrically dividing the channel associated with the storage elements into two isolated areas (3). Additional isolated areas (4) are formed remotely from the selected storage element by applying the isolation voltage (5) to other remote storage elements (6). The isolated channel regions associated with the storage elements are then boosted with different pass voltages (Vpass, VpassL) in order to alleviate the effects of program disturb. Thus, a standard pass voltage (Vpass) is applied to storage elements immediately adjacent to the selected storage element, and a lower pass voltage (VpassL) is applied to storage elements remote from the selected storage element. These techniques reduce the leakage of charge from adjacent boosted channel regions caused by gate induced drain leakage at the source select line and the drain select line, as well as from isolation word lines, thereby reducing program disturb effects.
PCT/US2007/077402 2006-09-06 2007-08-31 Programming non-volatile memory with improved boosting WO2008030775A2 (en)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US51715406A 2006-09-06 2006-09-06
US11/516,976 US7440326B2 (en) 2006-09-06 2006-09-06 Programming non-volatile memory with improved boosting
US11/517,154 2006-09-06
US11/516,976 2006-09-06

Publications (2)

Publication Number Publication Date
WO2008030775A2 WO2008030775A2 (en) 2008-03-13
WO2008030775A3 true WO2008030775A3 (en) 2008-05-02

Family

ID=38982715

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2007/077402 WO2008030775A2 (en) 2006-09-06 2007-08-31 Programming non-volatile memory with improved boosting

Country Status (2)

Country Link
TW (1) TWI349286B (en)
WO (1) WO2008030775A2 (en)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5715194A (en) * 1996-07-24 1998-02-03 Advanced Micro Devices, Inc. Bias scheme of program inhibit for random programming in a nand flash memory
US20050047210A1 (en) * 2001-03-06 2005-03-03 Kabushiki Kaisha Toshiba Non-volatile semiconductor memory device
US20050088890A1 (en) * 2002-11-29 2005-04-28 Yasuhiko Matsunaga NAND type flash EEPROM in which sequential programming process is performed by using different intermediate voltages
US20050174852A1 (en) * 2004-02-06 2005-08-11 Hemink Gerrit J. Self-boosting system for flash memory cells

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5715194A (en) * 1996-07-24 1998-02-03 Advanced Micro Devices, Inc. Bias scheme of program inhibit for random programming in a nand flash memory
US20050047210A1 (en) * 2001-03-06 2005-03-03 Kabushiki Kaisha Toshiba Non-volatile semiconductor memory device
US20050088890A1 (en) * 2002-11-29 2005-04-28 Yasuhiko Matsunaga NAND type flash EEPROM in which sequential programming process is performed by using different intermediate voltages
US20050174852A1 (en) * 2004-02-06 2005-08-11 Hemink Gerrit J. Self-boosting system for flash memory cells

Also Published As

Publication number Publication date
TW200832411A (en) 2008-08-01
TWI349286B (en) 2011-09-21
WO2008030775A2 (en) 2008-03-13

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