TWI495013B - 積體電路及其形成方法 - Google Patents

積體電路及其形成方法 Download PDF

Info

Publication number
TWI495013B
TWI495013B TW101112186A TW101112186A TWI495013B TW I495013 B TWI495013 B TW I495013B TW 101112186 A TW101112186 A TW 101112186A TW 101112186 A TW101112186 A TW 101112186A TW I495013 B TWI495013 B TW I495013B
Authority
TW
Taiwan
Prior art keywords
metal
forming
dielectric layer
gate structure
oxynitride
Prior art date
Application number
TW101112186A
Other languages
English (en)
Other versions
TW201312655A (zh
Inventor
Jin-Aun Ng
Maxi Chang
Jen Sheng Yang
Ta Wei Lin
Shih Hao Lo
Chih Yang Yeh
hui wen Lin
Jung Hui Kao
Yuan Tien Tu
Huan Just Lin
Chih Tang Peng
Pei Ren Jeng
Bao Ru Young
Harry Hak-Lay Chuang
Original Assignee
Taiwan Semiconductor Mfg Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiwan Semiconductor Mfg Co Ltd filed Critical Taiwan Semiconductor Mfg Co Ltd
Publication of TW201312655A publication Critical patent/TW201312655A/zh
Application granted granted Critical
Publication of TWI495013B publication Critical patent/TWI495013B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28229—Making the insulator by deposition of a layer, e.g. metal, metal compound or poysilicon, followed by transformation thereof into an insulating layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H01L21/823842—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823857—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823864—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/495—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a simple metal, e.g. W, Mo
    • H01L29/4958—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a simple metal, e.g. W, Mo with a multiple layer structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/517—Insulating materials associated therewith the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/518—Insulating materials associated therewith the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28079—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a single metal, e.g. Ta, W, Mo, Al
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28088—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a composite, e.g. TiN

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Composite Materials (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Description

積體電路及其形成方法
本發明係有關於積體電路裝置，且特別是有關於一種具有金屬閘極堆疊的積體電路裝置。
半導體裝置的製造包括許多不同的製程，各製程具有其需要的週期時間及成本。在裝置的製造上期待能夠不斷降低週期時間及成本。此外，也期待能夠在半導體的製造中減少缺陷數目及提升產率。其中的進步之一為製造具有高介電常數金屬閘極的金氧半場效電晶體(MOSET)裝置。在本發明一實施例中提供上述裝置的改善及製造方法。
本發明一實施例提供一種一種積體電路的形成方法，包括：提供一半導體基板；在該半導體基板上形成一閘極介電質；在該半導體基板及該閘極介電質上形成一金屬閘極結構；在該金屬閘極結構上形成一薄介電層，該薄介電層包括氮氧化物結合該金屬閘極的金屬；以及在該金屬閘極結構的兩側提供一層間介電層(ILD)。
本發明另一實施例提供積體電路，包括：一半導體基板；一閘極介電質，在該半導體基板上；一金屬閘極結構，在該半導體基板及該閘極介電質上；一介電層，在該金屬閘極結構上，該介電層包括氮氧化物結合該金屬閘極的金屬；以及一層間介電層(ILD)，在該金屬閘極結構的兩側。
本發明又一實施例提供一種積體電路的形成方法，包括：提供具有一高介電常數介電質的一基板；在該高介電常數介電質上形成一多晶矽閘極結構；在該多晶矽閘極結構的頂表面上形成一硬罩幕，且在該多晶矽閘極結構的側表面上形成側壁結構；在該硬罩幕形成後，在鄰接至該多晶矽閘極結構的該基板上進行一摻雜製程；在該摻雜製程後，移除該硬罩幕及該多晶矽閘極結構，但至少留下一部分的該側壁結構，以形成一溝槽；以至少一金屬材料填入該溝槽，以形成一金屬閘極；以及在該金屬閘極上形成一薄介電層，且該薄介電層與該金屬閘極的一頂表面自對準，該薄介電層包括該金屬材料。
為讓本發明之上述和其他目的、特徵、和優點能更明顯易懂，下文特舉出較佳實施例，並配合所附圖式，作詳細說明如下：
以下依本發明之不同特徵舉出數個不同的實施例。本發明中特定的元件及安排係為了簡化，但本發明並不以這些實施例為限。舉例而言，於第二元件上形成第一元件的描述可包括第一元件與第二元件直接接觸的實施例，亦包括具有額外的元件形成在第一元件與第二元件之間、使得第一元件與第二元件並未直接接觸的實施例。此外，為簡明起見，本發明在不同例子中以重複的元件符號及/或字母表示，但不代表所述各實施例及/或結構間具有特定的關係。
第1圖顯示根據本發明一實施例所形成半導體裝置的方法100的流程圖。半導體裝置包括N型場效應電晶體(NFET)及P型場效應電晶體(PFET)，上述兩者在本發明各種實施例中皆具有金屬閘極堆疊電阻。第2至15圖顯示根據本發明一或多個實施例的半導體結構200在各種製造階段的剖面圖。參照第1至16圖，半導體裝置200及其形成方法100的敘述如下。
參照第1、2圖，方法100由步驟102開始，在步驟102中提供半導體基板201，並在其上形成多晶矽閘極。半導體基板201包括矽。或者，半導體基板包括鍺、矽鍺、或其他適合的半導體材料。半導體基板也包括各種摻雜區，如n井或p井。半導體基板201包括隔離元件，例如在基板中形成淺溝槽隔離(STI)202以分開NFET及PFET電晶體。淺溝槽隔離元件202的形成包括在基板中蝕刻溝槽，並以一或多種絕緣材料填入溝槽，例如氧化矽、氮化矽、或氮氧化矽。填入的溝槽可具有多層結構，例如以具氮化矽的熱氧化襯層填入溝槽。在一實施例中，淺溝槽隔離元件202的形成係利用一系列製程，例如：成長墊氧化物(pad oxide)，形成低壓化學氣相沉積(LPCVD)層，利用光阻及罩幕圖案化淺溝槽隔離開口，在基板中蝕刻溝槽，可視需要成長熱氧化物溝槽襯層(thermal oxide trench liner)以提升溝槽的界面，以化學氣相沉積(CVD)氧化物填入溝槽，利用化學機械研磨(CMP)回蝕，以及利用氮化物剝離以自淺溝槽隔離結構移除。半導體基板201也包括在各種主動區中形成的各種n井及p井。
在基板201上淺溝槽隔離結構的兩側形成二個類似的多晶矽閘極堆疊204、206。在此實施例中，各多晶矽閘極堆疊204、206包括(在圖式中由基板201向上來看)，氧化矽界面層(silicon oxide interfacial layer；IL)、高介電常數層(HK)及蓋層(cap layer)，其整體以元件符號214代表。在各種實施例中，界面層的形成可利用化學氧化物技術、熱氧化物製程、原子層沉積(ALD)、或化學氣相沉積。高介電常數材料層的形成可利用化學氣相沉積、原子層沉積、電漿化學氣相沉積(PECVD)、或電漿原子層沉積(PEALD)。蓋層的形成可利用具矽烷(SiH4 ；silane)前趨物或其他矽類前趨物的化學氣相沉積。
在此實施例中，在氧化矽界面層(IL)/高介電常數層(HK)/蓋層上形成多晶矽層216。在此實施例中，多晶矽層216未摻雜。多晶矽層216可替代地或可額外地包括非晶矽。在多晶矽層216上形成氧化物218，且在氧化物218上形成氮化矽層220，以形成硬罩幕(HM)。應了解各層的形成(包括圖案化)為本領域所熟知，為了簡潔及清楚起見將不再詳述。
參照第1、3圖，方法100進展至步驟103，其中圍繞閘極堆疊204、206形成氮化矽密封物(SiN seal)230。在此實施例中，氮化矽密封物230的形成矽利用原子層沉積，以形成厚度大約50埃的層狀物。此外，摻雜基板201以形成暈狀區及源極及汲極(S/D)元件的淺摻雜區(LDD)。NFET及PFET裝置的源極及汲極(S/D)元件的形成係利用適當的摻質。
參照第1、4圖，方法100進行到步驟104，形成主要側壁(main side wall；MSW)。主要側壁包括氧化物(OX)層232，其鄰接於氮化矽層230的外表面及基板201的上表面。在此實施例中，氧化物層232的形成係利用ALD，以形成約30埃的厚度。主要側壁也包括在氧化物層232的外表面形成氮化矽側壁234。形成的氮化矽層的最大厚度約250埃。如第4圖所示，主要側壁鄰接多晶矽閘極堆疊204、206的側壁，且未覆蓋整個基板。
參照第1、5圖，方法100進行到步驟105，其中源極/汲極及靜電放電區(electrostatic discharge region)240完整的佈植及活化。如前述步驟103，在步驟104形成主要側壁之前，在基板201中先提供淺摻雜區。在步驟105中，進行更深的植入製程。NFET的摻雜區以P型摻質摻雜，例如硼或氟化硼(BF2 )，且PFET的摻雜區以N形摻質摻雜，例如磷或砷。摻雜區240可直接形成於基板201上、P井結構中、N井結構中、雙井結構中、或用一升起的結構。在此實施例中，源極/汲極(S/D)區活化的進行係在約1150℃下雷射回火(laser aneal；LSA)，並接著進行約有1010℃峰值的快速熱回火(rapid thermal anneal；RTA)。
參照第1、6圖，方法100進行到步驟106，其中形成矽化鎳區242以更進一步的與S/D區240接觸。在此實施例中，在步驟105形成主要側壁之後，在基板201中沉積鎳至厚度約為400埃。
參照第1、7圖，方法100進行到步驟107，其中由二個閘極堆疊移除主要側壁的氮化矽層234的一部分。如第7圖所示，與氧化物層232一樣，氮化矽層的一部分(在此標示為244)仍維持在主要側壁上。在此實施例中，此移除製程的進行係在約120℃下利用磷酸(H3 PO4 )進行濕蝕刻。此外，硬罩幕218、220由多晶矽閘極216的頂部移除。在此實施例中，藉由乾蝕刻製程移除氮化矽及氧化物硬罩幕。
參照第1、8圖，方法100進行到步驟108，其中在二個閘極堆疊204、206上形成層間介電(ILD)層250。在此實施例中，先沉積厚度約為200埃的伸張性氮化矽接觸蝕刻停止層(tensile SiN contact etch stop layer)252。而後，利用離子電漿(ion plasma；IPM)形成厚度約為2000埃的層間介電層250，在此實施例中為磷矽酸鹽玻璃(phosphate silicate glass；PSG)。
參照第1、9圖，方法100進行到步驟109，其中平坦化裝置的上表面以暴露出多晶矽閘極216。在此實施例中，係進行化學機械研磨製程。
參照第1、10圖，方法100進行到步驟110，其中遮蔽多晶矽閘極堆疊204、206的其中之一。在此實施例中，利用光阻(PR)層260遮蔽NFET閘極堆疊204的多晶矽閘極216。更明確而言，在裝置的頂表面上沉積20埃的氮化鈦硬罩幕262，而後在其上沉積光阻層260。圖案化光阻層260以遮蔽NFET的閘極堆疊204。
參照第1、11圖，方法100進行到步驟111，移除PFET閘極堆疊206中的多晶矽216。在此實施例中，藉由蝕刻將多晶矽216由PFET閘極堆疊206移除(此處更精確的敘述為溝槽而非閘極堆疊)，而在NFET閘極堆疊中的多晶矽則仍維持原封不動的由圖案化的光阻260所遮蔽，如第10圖所示。而後，在PFET閘極堆疊206中移除的多晶矽216所剩餘的溝槽中形成金屬閘極266。金屬閘極的形成可為一或多層，且在此實施例中，其依序包括下述金屬沉積：氮化鉭、氮化鈦、及鋁(包含微量的銅)。沉積金屬層覆蓋裝置的整體表面，但而後以化學機械研磨移除(包括移除光阻260)。
參照第1、12圖，方法100進行到步驟112，其中在NFET閘極堆疊204上重複進行類似的步驟。在此實施例中，既然在PFET閘極堆疊上已移除並取代多晶矽，不用圖案化光阻層覆蓋PFET閘極堆疊。例如藉由蝕刻製程將多晶矽216自NFET移除。而後，在NFET閘極堆疊204中移除多晶矽216所剩餘的溝槽中形成金屬閘極268。金屬閘極268的形成可為一或多層，且在此實施例中，其依序包括下述金屬沉積：氮化鉭、鋁化鈦、氮化鈦、及鋁(包含微量的銅)。沉積金屬層覆蓋裝置的整體表面，但而後以化學機械研磨移除(包括移除光阻260)。因此，多晶矽閘極堆疊現在皆為金屬閘極堆疊204、206。
參照第1、13a、13b圖，方法100進行到步驟113，其中多晶矽閘極堆疊的上表面上分別形成極薄金屬氮氧化物層(ultra-thin metal oxynitride film)288、286。在一實施例中，以氧電漿在20℃、900W、60秒下以氧轟擊其表面。而後，以氨電漿在400℃、75W、60秒下以氨/氮(NH3 /N2 )轟擊其表面。在另一實施例中，可利用氮電漿(無氨)。所形成極薄金屬氮氧化物層的厚度約為1奈米至10奈米。氮氧化物層只與閘極堆疊204、206中的金屬材料(如鈦、鉭、銅、鋁、鋁化鈦)反應，因此可自對準(self-aligned)。
參照第1、14圖，方法100進行到步驟114，其中在金屬閘極堆疊204、206(包括氮氧化物層288、286)上形成層間介電層290。在此實施例中，層間介電層290係未摻雜矽酸鹽玻璃(undoped silicate glass；USG)，其厚度約為1450埃。未摻雜矽酸鹽玻璃290的形成係利用矽甲烷(SiH4 )/氧化氮(N2 O)/氦在400℃下沉積形成。未摻雜矽酸鹽玻璃290可形成在磷矽酸鹽玻璃250上，或可移除磷矽酸鹽玻璃250，及/或形成額外的介電層組合。
參照第1、15圖，方法100進行到步驟115，形成接觸插塞以電性連接NFET及PFET電晶體的S/D區。在此實施例中，在層間介電層290中圖案化並蝕刻接觸開口，而後填入鎢插塞292。以化學機械研磨平坦化裝置的上表面，使得裝置如圖示。自此之後為後段製程。
本發明各種實施例揭示許多優點，應了解不同的實施例中可不具有相同的優點。上述各實施例中所述優點包括相對於以其他方法形成絕緣層，藉由電漿誘發的極薄絕緣層可提升可靠度。此外，提升晶片級單元應力。此外，藉由將任何金屬殘餘轉化至金屬氮氧化物(如鋁、銅、鈦、或鉭)以提升產率並減少短路。
本發明並不限於應用在半導體結構如FET(例如金氧半電晶體)且可延伸至其他具有金屬閘極堆疊的積體電路。例如，半導體結構可包括動態隨機存取記憶體(DRAM)單元、影像感應器、電容、及/或其他微電子裝置(此處統稱為微電子裝置)。在另一實施例中，半導體結構包括鳍式場效應電晶體。當然，本發明各實施例也可應用於其他種類的電晶體，包括單閘極電晶體、雙閘極電晶體、及其他多閘極電晶體，且可用於各種不同的應用，包括感應單元、記憶體單元、邏輯單元等。
雖然本發明已以數個較佳實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作任意之更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。
100．．．方法
200．．．半導體結構
102、103、104、105、106、107、108、109．．．步驟
110、111、112、113、114、115．．．步驟
201．．．半導體基板
202．．．淺溝槽隔離
204、206．．．閘極堆疊
214．．．氧化矽界面層/高介電常數層/蓋層
216．．．多晶矽層
218．．．氧化物
220．．．氮化矽層
230．．．氮化矽密封層
232．．．氧化物層
234．．．氮化矽側壁
240．．．靜電放電區(摻雜區)
242．．．矽化鎳區
244．．．氮化矽層的一部分
250．．．層間介電層
252．．．伸張性氮化矽接觸蝕刻停止層
260．．．光阻層
262．．．硬罩幕
266、268．．．金屬閘極
288、286．．．極薄金屬氮氧化物層
290．．．層間介電層
292．．．鎢插塞
第1圖為根據本發明一實施例，具有金屬閘極堆疊的半導體裝置的形成方法的流程圖。
第2-12、13a、13b、14-15圖為根據第1圖所示方法，在一實施例中，具有金屬閘極堆疊的N型及P型金氧半場效應電晶體(NFET及PFET)的半導體裝置之製造各階段的剖面圖。
201．．．半導體基板
242．．．矽化鎳區
292．．．鎢插塞
290．．．層間介電層
200．．．半導體結構

Claims (10)

  1. 一種積體電路的形成方法，包括：提供一半導體基板；在該半導體基板上形成一閘極介電質；在該半導體基板及該閘極介電質上形成一金屬閘極結構；在該金屬閘極結構上形成一薄介電層，該薄介電層包括氮氧化物；於該氮氧化物上執行一電漿轟擊製程，使該氮氧化物與金屬閘極結構之金屬反應並形成一金屬氮氧化物；以及在該金屬閘極結構的兩側提供一層間介電層(ILD)。
  2. 如申請專利範圍第1項所述之積體電路的形成方法，其中該金屬閘極結構包括具有銅及鈦的複數個金屬層，其中該薄介電層結合銅以形成氮氧化銅(copper oxynitride)，且結合鈦以形成氮氧化鈦(titanium oxynitride)。
  3. 如申請專利範圍第1項所述之積體電路的形成方法，其中該薄介電層的形成包括利用氧電漿。
  4. 如申請專利範圍第3項所述之積體電路的形成方法，其中該薄介電層的形成更包括利用氨電漿。
  5. 一種積體電路，包括：一半導體基板；一閘極介電質，在該半導體基板上；一金屬閘極結構，在該半導體基板及該閘極介電質 上；一介電層，在該金屬閘極結構上，該介電層包括金屬氮氧化物；以及一層間介電層(ILD)，在該金屬閘極結構的兩側。
  6. 如申請專利範圍第5項所述之積體電路，其中該金屬包括銅，且該介電層包括氮氧化銅。
  7. 如申請專利範圍第5項所述之積體電路，其中該金屬包括擇自下列群組的至少兩者：銅、鈦、鉭、及鋁。
  8. 如申請專利範圍第7項所述之積體電路，其中該介電層包括擇自下列群組的至少兩者：氮氧化銅、氮氧化鈦、氮氧化鉭、氮氧化鋁、及氮氧化鈦鋁。
  9. 一種積體電路的形成方法，包括：提供具有一高介電常數介電質的一基板；在該高介電常數介電質上形成一多晶矽閘極結構；在該多晶矽閘極結構的頂表面上形成一硬罩幕，且在該多晶矽閘極結構的側表面上形成側壁結構；在該硬罩幕形成後，在鄰接至該多晶矽閘極結構的該基板上進行一摻雜製程；在該摻雜製程後，移除該硬罩幕及該多晶矽閘極結構，但至少留下一部分的該側壁結構，以形成一溝槽；以至少一金屬材料填入該溝槽，以形成一金屬閘極；以及在該金屬閘極的一頂表面上形成一薄介電層，且該薄介電層與該金屬閘極的該頂表面自對準，該薄介電層包括該金屬材料。
  10. 如申請專利範圍第9項所述之積體電路的形成方法，其中該金屬包括銅，且該薄介電層包括氮氧化銅。
TW101112186A 2011-09-02 2012-04-06 積體電路及其形成方法 TWI495013B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US201161530845P 2011-09-02 2011-09-02
US13/244,365 US8822283B2 (en) 2011-09-02 2011-09-24 Self-aligned insulated film for high-k metal gate device

Publications (2)

Publication Number Publication Date
TW201312655A TW201312655A (zh) 2013-03-16
TWI495013B true TWI495013B (zh) 2015-08-01

Family

ID=47752473

Family Applications (1)

Application Number Title Priority Date Filing Date
TW101112186A TWI495013B (zh) 2011-09-02 2012-04-06 積體電路及其形成方法

Country Status (4)

Country Link
US (5) US8822283B2 (zh)
KR (3) KR20130025795A (zh)
CN (1) CN102983105B (zh)
TW (1) TWI495013B (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI792414B (zh) * 2021-07-13 2023-02-11 張宏森 渦流熱交換裝置

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8822283B2 (en) 2011-09-02 2014-09-02 Taiwan Semiconductor Manufacturing Company, Ltd. Self-aligned insulated film for high-k metal gate device
US8470714B1 (en) * 2012-05-22 2013-06-25 United Microelectronics Corp. Method of forming fin structures in integrated circuits
KR101927443B1 (ko) * 2012-08-22 2018-12-10 에스케이하이닉스 주식회사 반도체 소자 및 그 제조 방법
US9076766B2 (en) 2013-06-13 2015-07-07 Taiwan Semiconductor Manufacturing Co., Ltd. Mechanism for forming metal gate structure
KR102103960B1 (ko) 2013-08-16 2020-04-24 삼성디스플레이 주식회사 박막 트랜지스터 어레이 기판, 이를 포함하는 표시 장치, 및 박막 트랜지스터 어레이 기판의 제조 방법
US9190488B1 (en) * 2014-08-13 2015-11-17 Globalfoundries Inc. Methods of forming gate structure of semiconductor devices and the resulting devices
US9660106B2 (en) * 2014-08-18 2017-05-23 United Microelectronics Corp. Flash memory and method of manufacturing the same
TWI633669B (zh) 2014-12-26 2018-08-21 聯華電子股份有限公司 半導體元件及其製程
CN105826174B (zh) * 2015-01-05 2021-06-15 联华电子股份有限公司 半导体装置及其制作方法
US9779959B2 (en) * 2015-09-17 2017-10-03 Taiwan Semiconductor Manufacturing Co., Ltd. Structure and formation method of semiconductor device structure
US9911821B2 (en) * 2015-11-13 2018-03-06 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device structure and method for forming the same
US9865703B2 (en) * 2015-12-31 2018-01-09 International Business Machines Corporation High-K layer chamfering to prevent oxygen ingress in replacement metal gate (RMG) process
KR102551349B1 (ko) 2016-01-22 2023-07-04 삼성전자 주식회사 반도체 소자 및 그 제조 방법
US9806018B1 (en) * 2016-06-20 2017-10-31 International Business Machines Corporation Copper interconnect structures
US9972695B2 (en) 2016-08-04 2018-05-15 International Business Machines Corporation Binary metal oxide based interlayer for high mobility channels
US20220359287A1 (en) * 2021-05-05 2022-11-10 Taiwan Semiconductor Manufacturing Co., Ltd. Recessed contacts at line end and methods forming same

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4954867A (en) * 1987-06-18 1990-09-04 Seiko Instruments Inc. Semiconductor device with silicon oxynitride over refractory metal gate electrode in LDD structure
US20080268588A1 (en) * 2007-04-30 2008-10-30 International Business Machines Corporation RECESSED GATE CHANNEL WITH LOW Vt CORNER
US20090174002A1 (en) * 2008-01-09 2009-07-09 International Business Machines Corporation Mosfet having a high stress in the channel region

Family Cites Families (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6465309B1 (en) * 2000-12-12 2002-10-15 Advanced Micro Devices, Inc. Silicide gate transistors
US6509282B1 (en) * 2001-11-26 2003-01-21 Advanced Micro Devices, Inc. Silicon-starved PECVD method for metal gate electrode dielectric spacer
US7078306B1 (en) * 2003-03-24 2006-07-18 Integrated Device Technology, Inc. Method for forming a thin film resistor structure
US7015534B2 (en) * 2003-10-14 2006-03-21 Texas Instruments Incorporated Encapsulated MOS transistor gate structures and methods for making the same
CN100463143C (zh) * 2005-07-07 2009-02-18 中芯国际集成电路制造(上海)有限公司 具有氧化物间隔层的应变源漏cmos的集成方法
US7229873B2 (en) * 2005-08-10 2007-06-12 Texas Instruments Incorporated Process for manufacturing dual work function metal gates in a microelectronics device
US20070152276A1 (en) * 2005-12-30 2007-07-05 International Business Machines Corporation High performance CMOS circuits, and methods for fabricating the same
JP4327820B2 (ja) * 2006-06-05 2009-09-09 株式会社東芝 半導体装置およびその製造方法
US7776765B2 (en) * 2006-08-31 2010-08-17 Micron Technology, Inc. Tantalum silicon oxynitride high-k dielectrics and metal gates
US20080076216A1 (en) * 2006-09-25 2008-03-27 Sangwoo Pae Method to fabricate high-k/metal gate transistors using a double capping layer process
US8120114B2 (en) 2006-12-27 2012-02-21 Intel Corporation Transistor having an etch stop layer including a metal compound that is selectively formed over a metal gate
US20080242012A1 (en) * 2007-03-28 2008-10-02 Sangwoo Pae High quality silicon oxynitride transition layer for high-k/metal gate transistors
JP2009054951A (ja) * 2007-08-29 2009-03-12 Toshiba Corp 不揮発性半導体記憶素子及びその製造方法
US7888195B2 (en) * 2008-08-26 2011-02-15 United Microelectronics Corp. Metal gate transistor and method for fabricating the same
US8258587B2 (en) * 2008-10-06 2012-09-04 Taiwan Semiconductor Manufacturing Company, Ltd. Transistor performance with metal gate
US8294202B2 (en) 2009-07-08 2012-10-23 Taiwan Semiconductor Manufacturing Company, Ltd. Metal gate structure of a semiconductor device
CN102497895A (zh) * 2009-07-15 2012-06-13 弗雷塞尼斯医疗保健控股公司 医疗流体盒及相关***和方法
US8617946B2 (en) * 2009-11-11 2013-12-31 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuits including metal gates and fabrication methods thereof
US8436404B2 (en) * 2009-12-30 2013-05-07 Intel Corporation Self-aligned contacts
US8946828B2 (en) * 2010-02-09 2015-02-03 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device having elevated structure and method of manufacturing the same
CN102194693B (zh) * 2010-03-16 2013-05-22 中国科学院微电子研究所 一种半导体器件及其制造方法
US8685847B2 (en) * 2010-10-27 2014-04-01 International Business Machines Corporation Semiconductor device having localized extremely thin silicon on insulator channel region
US8232607B2 (en) * 2010-11-23 2012-07-31 International Business Machines Corporation Borderless contact for replacement gate employing selective deposition
CN102487015A (zh) * 2010-12-03 2012-06-06 中国科学院微电子研究所 一种半导体结构及其制造方法
US8765603B2 (en) * 2011-08-01 2014-07-01 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming a buffer layer
US8524564B2 (en) * 2011-08-05 2013-09-03 Globalfoundries Inc. Full silicidation prevention via dual nickel deposition approach
US8728908B2 (en) * 2011-08-08 2014-05-20 Globalfoundries Inc. Methods of forming a dielectric cap layer on a metal gate structure
US8822283B2 (en) * 2011-09-02 2014-09-02 Taiwan Semiconductor Manufacturing Company, Ltd. Self-aligned insulated film for high-k metal gate device
US8772168B2 (en) * 2012-01-19 2014-07-08 Globalfoundries Singapore Pte. Ltd. Formation of the dielectric cap layer for a replacement gate structure
US8765590B2 (en) * 2012-10-31 2014-07-01 International Business Machines Corporation Insulative cap for borderless self-aligning contact in semiconductor device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4954867A (en) * 1987-06-18 1990-09-04 Seiko Instruments Inc. Semiconductor device with silicon oxynitride over refractory metal gate electrode in LDD structure
US20080268588A1 (en) * 2007-04-30 2008-10-30 International Business Machines Corporation RECESSED GATE CHANNEL WITH LOW Vt CORNER
US20090174002A1 (en) * 2008-01-09 2009-07-09 International Business Machines Corporation Mosfet having a high stress in the channel region

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI792414B (zh) * 2021-07-13 2023-02-11 張宏森 渦流熱交換裝置

Also Published As

Publication number Publication date
US10388531B2 (en) 2019-08-20
US9252224B2 (en) 2016-02-02
US9779947B2 (en) 2017-10-03
US20180019133A1 (en) 2018-01-18
TW201312655A (zh) 2013-03-16
US20190341263A1 (en) 2019-11-07
CN102983105B (zh) 2015-11-25
US20140367802A1 (en) 2014-12-18
US20130056837A1 (en) 2013-03-07
KR20130025795A (ko) 2013-03-12
US20160196979A1 (en) 2016-07-07
KR20150059157A (ko) 2015-05-29
CN102983105A (zh) 2013-03-20
KR101618511B1 (ko) 2016-05-04
US8822283B2 (en) 2014-09-02
US11094545B2 (en) 2021-08-17
KR20140063552A (ko) 2014-05-27

Similar Documents

Publication Publication Date Title
TWI495013B (zh) 積體電路及其形成方法
US8853753B2 (en) Contact for high-k metal gate device
US8772147B2 (en) Spacer structures of a semiconductor device
US9685344B2 (en) Method of fabricating a semiconductor device including a plurality of isolation features
US8871625B2 (en) Spacer structure of a field effect transistor with an oxygen-containing layer between two oxygen-sealing layers
CN102117745B (zh) 半导体结构及其制造方法
CN101677088B (zh) 半导体装置的制造方法
US8664079B2 (en) Method of fabricating semiconductor device by thinning hardmask layers on frontside and backside of substrate