TWI488124B - 積體電路貼片及其製造方法 - Google Patents

積體電路貼片及其製造方法 Download PDF

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Publication number
TWI488124B
TWI488124B TW102128786A TW102128786A TWI488124B TW I488124 B TWI488124 B TW I488124B TW 102128786 A TW102128786 A TW 102128786A TW 102128786 A TW102128786 A TW 102128786A TW I488124 B TWI488124 B TW I488124B
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Taiwan
Prior art keywords
pads
semiconductor device
circuit board
disposed
patch
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TW102128786A
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English (en)
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TW201432577A (zh
Inventor
Chin Sheng Lin
Cheng Chia Kuo
Chih Cheng Lin
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Mxtran Inc
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Publication of TW201432577A publication Critical patent/TW201432577A/zh
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Publication of TWI488124B publication Critical patent/TWI488124B/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/0723—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips the record carrier comprising an arrangement for non-contact communication, e.g. wireless communication circuits on transponder cards, non-contact smart cards or RFIDs
    • G06K19/0727—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips the record carrier comprising an arrangement for non-contact communication, e.g. wireless communication circuits on transponder cards, non-contact smart cards or RFIDs the arrangement being a circuit facilitating integration of the record carrier with a hand-held device such as a smart phone of PDA
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K7/00—Methods or arrangements for sensing record carriers, e.g. for reading patterns
    • G06K7/10—Methods or arrangements for sensing record carriers, e.g. for reading patterns by electromagnetic radiation, e.g. optical sensing; by corpuscular radiation
    • G06K7/10009—Methods or arrangements for sensing record carriers, e.g. for reading patterns by electromagnetic radiation, e.g. optical sensing; by corpuscular radiation sensing by radiation using wavelengths larger than 0.1 mm, e.g. radio-waves or microwaves
    • G06K7/10237—Methods or arrangements for sensing record carriers, e.g. for reading patterns by electromagnetic radiation, e.g. optical sensing; by corpuscular radiation sensing by radiation using wavelengths larger than 0.1 mm, e.g. radio-waves or microwaves the reader and the record carrier being capable of selectively switching between reader and record carrier appearance, e.g. in near field communication [NFC] devices where the NFC device may function as an RFID reader or as an RFID tag
    • G—PHYSICS
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    • G06K7/10237—Methods or arrangements for sensing record carriers, e.g. for reading patterns by electromagnetic radiation, e.g. optical sensing; by corpuscular radiation sensing by radiation using wavelengths larger than 0.1 mm, e.g. radio-waves or microwaves the reader and the record carrier being capable of selectively switching between reader and record carrier appearance, e.g. in near field communication [NFC] devices where the NFC device may function as an RFID reader or as an RFID tag
    • G06K7/10247—Methods or arrangements for sensing record carriers, e.g. for reading patterns by electromagnetic radiation, e.g. optical sensing; by corpuscular radiation sensing by radiation using wavelengths larger than 0.1 mm, e.g. radio-waves or microwaves the reader and the record carrier being capable of selectively switching between reader and record carrier appearance, e.g. in near field communication [NFC] devices where the NFC device may function as an RFID reader or as an RFID tag issues specific to the use of single wire protocol [SWP] in NFC like devices
    • G—PHYSICS
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Description

積體電路貼片及其製造方法
本發明大致上是有關於一種積體電路貼片及其製造方法，且特別是有關於一種用以被裝設在一智慧卡上之積體電路貼片及其製造方法。
行動通訊裝置廣泛被人們使用在日常生活中。利用行動通訊裝置作為用以執行商業交易之工具將來是一種趨勢。藉由行動電話達到商業交易功能有兩個主要方法。一種是藉由從行動電話之網際網路軟體銀行下載相關軟體，而另一種是藉由應用一個具有一對應功能之SIM(用戶識別模組)卡。這兩種方法對使用者而言都是不方便的。
本發明是有關於一種積體電路貼片及其製造方法。依據本發明之一個實施例之積體電路貼片之厚度不大於300μm並可被裝設在一智慧卡上。積體電路貼片具有一個半導體裝置及一電路板；電路板可以與半導體裝置與智慧卡電性連接。
根據本發明之第一方面，提出一種積體電路貼片。積體電路貼片包括：一電路板，其具有一電路路線(circuit route)；一第一組接墊，設置在電路板之一第一表面上並被設計成適用於ISO 7816標準；以及一 個半導體裝置，配置於電路板上，用以與第一組接墊之至少一者通訊。第一組接墊排列成兩列，且半導體裝置配置於電路板上位於兩列之接墊之間的一空間中。
根據本發明之第二方面，提出一種積體電路貼片之製造方法。此方法包括下述步驟：提供一具有一電路路線之電路板；形成一第一組接墊，設置在電路板之一第一表面並被設計成適用於ISO 7816標準；以及將一個半導體裝置配置在電路板上，用以與第一組接墊之至少一者通訊。第一組接墊排列成兩列，且半導體裝置係配置於電路板上位於兩列之接墊之間的一空間中。
本發明之上述及其他實施樣態將關於下述較佳但非限制實施例之詳細說明而變得更佳理解。以下參考附圖作出下述說明。
C6‧‧‧接墊
H1‧‧‧厚度
H2‧‧‧厚度
10‧‧‧晶圓
50‧‧‧晶圓
100A‧‧‧接墊
101‧‧‧積體電路貼片
102‧‧‧信號接墊
102a‧‧‧接墊
103‧‧‧電路板
103A‧‧‧第一表面
103B‧‧‧第二表面
104‧‧‧凸塊
105‧‧‧第一組接墊
106‧‧‧導電膠
107‧‧‧半導體裝置
108‧‧‧絕緣層
109‧‧‧電路路線
111‧‧‧第二組接墊
200‧‧‧標準SIM卡
220a‧‧‧外輪廓
220b‧‧‧內輪廓
240‧‧‧行動電話
501‧‧‧絕緣層
502a‧‧‧接墊
503‧‧‧重新分配層(RDL)
504‧‧‧凸塊
506‧‧‧填膠層
701‧‧‧積體電路貼片
801‧‧‧積體電路貼片
802b‧‧‧第二組接墊
900‧‧‧Micro/Nano SIM卡
902‧‧‧信號接墊
1000‧‧‧Nano-SIM卡
1001‧‧‧積體電路貼片
1002‧‧‧信號接墊
1002b‧‧‧第二組接墊
2402‧‧‧卡插槽
第1A圖藉由顯示一第一表面繪示依據本發明之一實施例之一積體電路貼片。
第1B圖繪示積體電路貼片，其藉由顯示其之一第二表面來繪示。
第2A與2B圖分別從兩個不同側顯示積體電路貼片與SIM卡。
第3A至3D圖顯示一種利用一COF封裝技術將半導體裝置107配置在電路板103上之方法。
第4A與4B圖顯示積體電路貼片及一標準SIM卡之連接。
第5圖顯示將裝設有標準SIM卡之積體電路貼片配置在一通訊裝置之一卡插槽中。
第6A至6F圖顯示一種利用一種WLCSP封裝技術將半導體裝置107配置在電路板103上之方法。
第7A與7B圖顯示供具有8個接點之Micro-SIM卡用之一積體電路貼片之一個例子。
第8A與8B圖顯示供具有6個接點之Micro/Nano SIM卡用之一積體電路貼片之一個例子。
第9A與9B圖分別從兩個不同側顯示積體電路貼片與Micro/Nano SIM卡。
第10A與10B圖分別從兩個不同側顯示一積體電路貼片與Nano-SIM卡。
第1A圖藉由顯示一第一表面103A繪示依據本發明之一實施例之一積體電路貼片101。積體電路貼片101包括一電路板103(譬如一軟性電路板)、一第一組接墊105以及一個半導體裝置107。電路板103具有一電路路線109。第一組接墊105係被設置在電路板103之第一表面103A上並被設計成用以適用於ISO 7816標準。半導體裝置107係配置於電路板103上，用以與第一組接墊105之至少一者通訊。第一組接墊105排列成兩列，且半導體裝置107配置於電路板103上位在接墊105之兩列之間的一空間中。
ISO 7816標準係為一種關於具有多個接點之電子識別卡(特別是智慧卡)之國際標準，其由國際標準化組織(International Organization for Standardization,ISO)與國際電工委員會(International Electrotechnical Commission,IEC)聯合管理。當積體電路貼片101與智慧卡一起被使用在一 電子裝置時，具有上述半導體裝置107之積體電路貼片101可改善智慧卡之功能。電子裝置譬如是一通訊裝置，而智慧卡係為一用戶識別模組(subscriber-identity-module,SIM)卡。
第1B圖繪示積體電路貼片101，其藉由顯示其之一第二表面103B來繪示。積體電路貼片101更包括一第二組接墊111，其被設置在電路板103之第二表面103B上並具有與半導體裝置107與第一組接墊105之任何一個連接之至少一接墊。半導體裝置107與第一組接墊105中之何者連接至第二組接墊111之至少一接墊，係由積體電路貼片101之功能或應用所決定。
雖然所顯示的半導體裝置107係配置於第1A圖之電路板之第一表面103A中，基於積體電路貼片101之功能或應用半導體裝置107亦可配置於第二表面103B。第一組接墊105譬如是用來與通訊裝置接觸，而第二組接墊111是用來與SIM卡接觸。
再者，半導體裝置107可在單線連接協議(SWP)通訊協定之下，與通訊裝置與SIM卡之任何一個通訊。半導體裝置107可以與第一組接墊105之至少一者及第二組接墊111之至少一者連接，與半導體裝置107可包括一供近場通訊(NFC)功能用之控制器。上述第一組接墊105之至少一者譬如是在ISO 7816標準之下被命名為C6之接墊。第一組接墊105之接墊C6係用以在SWP通訊協定之下進行通訊。
第2A與2B圖分別從兩個不同側顯示積體電路貼片101與SIM卡200。SIM卡200譬如是標準SIM卡200(標準尺寸)。供一標準SIM卡200用之積體電路貼片101具有大約24.5mm之長度及大約14.5mm之寬度。因此，積體電路貼片101可具有不大於24.5mm之長度，不大於14.5mm之寬度 以及不大於0.3mm之厚度。
請參考第2A及2B圖，當積體電路貼片101裝設至標準SIM卡200時，配置在第二表面103B上之第二組接墊111係用以與標準SIM卡200之信號接墊102電性連接。積體電路貼片101之第一表面103A係用以與通訊裝置(未顯示於第2A圖中)電性連接。
請參考第1A及1B圖，一種積體電路貼片101之製造方法包括下述步驟。首先，提供具有電路路線109之電路板103。然後，形成設置在電路板103之第一表面103A上並被設計成適用於ISO 7816標準之第一組接墊105。接著，將半導體裝置107配置於電路板103上，用以與第一組接墊105之至少一者通訊。將第一組接墊105排列成兩列，且將半導體裝置107配置於電路板103上位於兩列之接墊105之間的一空間中。
半導體裝置107可利用一種COF(Chip-On-Film，貼片覆晶)封裝技術而被配置於電路板103上。一種利用COF封裝技術將半導體裝置107配置在電路板103上之方法係顯示於第3A至3D圖中。首先，準備一晶圓10，如第3A圖所示。晶圓10可被分割成多個半導體裝置107。半導體裝置107包括至少一接墊100A，如第3B圖所示。接著，至少一凸塊(bump)104係在半導體裝置107之至少一接墊100A上形成。此至少一凸塊104譬如是金凸塊。半導體裝置107之厚度不大於100μm。然後，準備具有至少一凸塊104之半導體裝置107以與電路板103整合。
積體電路貼片101包括至少一接墊102a，用以與半導體裝置107連接(第一組接墊105未顯示於第3B~3D圖，及第4A與4B圖中)。至少一接墊102a從第一表面103A突出，而第二組接墊111從第二表面103B突出。可 使用第二組接墊111之其中一個來傳送SWP信號以供近場通訊及/或RF非接觸通訊用。
請參考第3C圖，將一導電膠(conductive adhesive)106配置在第一表面103A上，且利用導電膠106將至少一凸塊104連接至電路板103。導電膠106可以是一異方性導電膜、一異方性導電膏或一異方性導電膠。
請參考第3D圖，一絕緣層108係形成於半導體裝置107上，並覆蓋半導體裝置107、導電膠106與至少一接墊102a。絕緣層108可包括一環氧樹脂。接著，形成積體電路貼片101。
積體電路貼片101之厚度H1不大於約300μm。半導體裝置107之厚度不大於約200μm。
於一實施例中，絕緣層108覆蓋半導體裝置107之一上表面及一側表面，且半導體裝置107之上表面上的絕緣層108之厚度不大於50μm。
於一實施例中，第一組接墊105或第二組接墊111包括一凹坑形狀部分或一***形狀部分，與凹坑形狀部分或***形狀部分分別從第一表面103A或第二表面103B突出一段至少50μm之距離。
第4A與4B圖顯示積體電路貼片101及一標準SIM卡200之連接。當將積體電路貼片101裝設至標準SIM卡200時，第二表面103B上之第二組接墊111係與標準SIM卡200電性連接。
第5圖顯示將裝設有標準SIM卡200之積體電路貼片101配置在一通訊裝置(譬如一行動電話240)之一卡插槽2402中。因為積體電路貼片101具有不大於300μm之厚度，所以裝設有標準SIM卡200之積體電路貼片101可被嵌合至行動電話240中。此外，因為積體電路貼片101具有配置在半 導體裝置107上用以保護半導體裝置107之絕緣層108，所以可延長半導體裝置107之壽命。
或者，依據本發明之另一實施例，亦可利用一WLCSP(Wafer Level Chip Scale Package，晶圓級晶片尺寸封裝)封裝技術將半導體裝置107配置於電路板103上。一種利用WLCSP封裝技術將半導體裝置107配置在電路板103上之方法係顯示於第6A至6F圖中。於第6A圖中，準備一晶圓50。晶圓50可被分割成多個半導體裝置107。如第6B圖所示，半導體裝置107具有一重新分配層(redistribution layer,RDL)503、多個凸塊504以及一絕緣層501。絕緣層501覆蓋半導體裝置107之上表面。絕緣層501可包括環氧樹脂。RDL 503係形成於半導體裝置107之下表面上，而凸塊504係形成於RDL 503上。凸塊504譬如是焊球。半導體裝置107之厚度不大於150μm。
如第6C圖所示，電路板103包括多個接墊502a，用以與半導體裝置107連接(第一組接墊105未顯示於第6A至6F圖中)。接墊502a係被配置在第一表面103A上並從第一表面103A突出。
請參考第6D圖，接墊502a係被接觸至半導體裝置107之凸塊504，且接墊502a係藉由表面黏著技術(surface mount technology,SMT)而電性連接至半導體裝置107上之凸塊504。
請參考第6E圖，一填膠層(underfill layer)506係形成於電路板103之第一表面103A上，用以覆蓋半導體裝置107之下表面。特別地，填膠層506係形成於電路板103之第一表面103A上，且在半導體裝置107上之接墊502a與凸塊504之間。RDL 503係設於半導體裝置107與電路板103之間，以與其連接，且RDL 503係與半導體裝置107一起封裝。
然後，如第6F圖所示，積體電路貼片101係被形成並可被裝設至一標準SIM 200。半導體裝置107之上表面上的絕緣層501之實質上的厚度係至少15μm且不大於20μm。積體電路貼片101之厚度H2不大於約300μm。半導體裝置107之厚度不大於約200μm。
積體電路貼片101並未被限定成裝設在一標準SIM卡上。積體電路貼片101之尺寸可被設計以匹配一SIM卡，其可以是SIM、USIM(Universal Subscriber Identity Module，萬用用戶識別模組)、UIM(User Identity Module，使用者識別模組)、RUIM(Removable User Identity Module,可移除使用者識別模組)、Micro-SIM以及Nano-SIM卡之其中一個。積體電路貼片101可被設計成匹配一標準尺寸、一Micro(微等級)尺寸以及一Nano(奈等級)尺寸SIM卡以符合不同的市場需求。積體電路貼片101之長寬比可被設計成對應至所選擇的SIM卡之一長寬比。
基於上述，依據本發明之實施例之積體電路貼片具有不大於300μm之厚度且可被嵌合至大部分的SIM卡與通訊裝置中。此外，因為積體電路貼片具有一配置在半導體裝置上之絕緣層，用以保護半導體裝置，所以可延長半導體裝置之壽命。
第7A與7B圖顯示供具有8個接點之Micro-SIM卡用之一積體電路貼片701之一個例子。供一Micro-SIM卡用之積體電路貼片701具有大約15mm之長度及大約11.8mm之寬度。
第8A與8B圖顯示供具有6個接點之Micro/Nano SIM卡用之一積體電路貼片801之一個例子。第9A與9B圖分別從兩個不同側顯示積體電路貼片801與Micro/Nano SIM卡900。請參考第8A圖，積體電路貼片801之外 輪廓220a係對應至一Micro-SIM卡並具有大約15mm之長度及大約11.8mm之寬度。積體電路貼片801之內輪廓220b係對應至一Nano-SIM卡並具有大約12.3mm之長度及大約8.8mm之寬度。積體電路貼片801與Micro/Nano SIM卡900可藉由積體電路貼片801上之第二組接墊802b與Micro/Nano SIM卡900上之信號接墊902而被電性連接。
第10A與10B圖分別從兩個不同側顯示一積體電路貼片1001與Nano-SIM卡1000。積體電路貼片1001係被設計成用以與一Nano-SIM卡一起被使用。積體電路貼片1001與Nano-SIM卡1000可藉由積體電路貼片1001上之第二組接墊1002b與Nano-SIM卡1000上之信號接墊1002而被電性連接。
將裝設有一SIM卡之積體電路貼片701、積體電路貼片801與積體電路貼片1001配置在一通訊裝置之一卡插槽中之方法係類似於第5圖所顯示者。於此將不重述。積體電路貼片701(供Micro-SIM卡用)、積體電路貼片801(供Micro/Nano SIM卡用)，與積體電路貼片1001(供Nano-SIM卡用)可被選擇以匹配待被裝設在其上之一對應的Micro-SIM卡或Nano-SIM卡。
依據本發明之本實施例之積體電路貼片可以與通訊裝置和SIM卡整合，並可被應用來達到商業交易功能。藉由將積體電路貼片配置在通訊裝置與SIM卡之間，通訊裝置可在不需要修改任何軟體的情況下具有額外功能，例如一資訊安全功能。因此，依據本發明之本實施例之積體電路貼片可以在不需要考量電信營運商、通訊裝置之型式或SIM卡之型式以及遵從市場需求的情況下，增加SIM卡與通訊裝置之間的適應性。
綜上所述，雖然本發明已以較佳實施例揭露如上，然其並非用以限定本發明。本發明所屬技術領域中具有通常知識者，在不脫離本發 明之精神和範圍內，當可作各種之更動與潤飾。因此，本發明之保護範圍當視後附之申請專利範圍所界定者為準。
101‧‧‧積體電路貼片
103‧‧‧電路板
103A‧‧‧第一表面
105‧‧‧第一組接墊
107‧‧‧半導體裝置
109‧‧‧電路路線

Claims (20)

  1. 一種積體電路貼片，包括：一電路板，具有一電路路線；一第一組接墊，設置在該電路板之一第一表面上並被設計成適用於ISO 7816標準，其中該第一組接墊係用來與一通訊裝置接觸；一第二組接墊，設置在該電路板之一第二表面上，並具有與該半導體裝置與該第一組接墊之任何一個連接之至少一接墊，該第二組接墊係用來與一SIM卡接觸；以及一半導體裝置，配置於該電路板上，用以與該第一組接墊之至少一者通訊；其中該第一組接墊與該第二組接墊係皆被排列成兩列，且該半導體裝置係配置於該電路板上位於該兩列之接墊之間的一空間中。
  2. 如申請專利範圍第1項所述之貼片，其中該半導體裝置係配置於該第一表面及該第二表面之任何一個上。
  3. 如申請專利範圍第1項所述之貼片，其中在一單線連接協議(single wire protocol,SWP)通訊協定之下，該半導體裝置與該通訊裝置與該SIM卡之任何一個通訊。
  4. 如申請專利範圍第3項所述之貼片，其中該第一組接墊之該至少一者係在該ISO 7816標準之下被命名為C6之一接墊。
  5. 如申請專利範圍第1項所述之貼片，其中該半導體裝置包括至少一接墊並利用一COF(Chip-On-Film，貼片覆晶)封裝技術配置於該電路板上，於其 中至少一凸塊係在該半導體裝置之該至少一接墊上形成以與該電路板連接，並利用一導電膠與該電路板連接。
  6. 如申請專利範圍第1項所述之貼片，其中該半導體裝置係利用一WLCSP(Wafer Level Chip Scale Package，晶圓級晶片尺寸封裝)封裝技術而配置於該電路板上，於其中一重新分配層(redistribution layer,RDL)係設於該半導體裝置與該電路板之間以與其連接，且其中該RDL係與該半導體裝置一起被封裝，且該半導體裝置係經由多個焊球而連接至該電路板。
  7. 如申請專利範圍第1項所述之貼片，其中該第一組接墊之該至少一者係在該ISO 7816標準之下被命名為C6之一接墊。
  8. 如申請專利範圍第1項所述之貼片，其中該半導體裝置與該第一組接墊之至少一者及該第二組接墊之至少一者連接，並包括一個供近場通訊(NFC)功能用之控制器。
  9. 如申請專利範圍第1項所述之貼片，其中該積體電路貼片之厚度不大於300μm。
  10. 如申請專利範圍第1項所述之積體電路貼片，其中該SIM卡係為SIM(Subscriber Identity Module，用戶識別模組)、USIM(Universal Subscriber Identity Module，萬用用戶識別模組)、UIM(User Identity Module，使用者識別模組)、RUIM(Removable User Identity Module，可移除使用者識別模組)、Micro-SIM及Nano-SIM卡之其中一個。
  11. 一種積體電路貼片之製造方法，包括：提供一具有一電路路線之電路板；形成一第一組接墊，其被設置在該電路板之一第一表面上並被設計成適 用於ISO 7816標準，其中該第一組接墊係用來與一通訊裝置接觸；形成一第二組接墊在該電路板之一第二表面上，其中該第二組接墊具有與該半導體裝置與該第一組接墊之任何一個連接之至少一接墊，其中該第二組接墊係用來與一SIM卡接觸；以及將一個半導體裝置配置在該電路板上，用以與該第一組接墊之至少一者通訊；其中該第一組接墊與該第二組接墊係皆被排列成兩列，且該半導體裝置係配置於該電路板上位於在該兩列之接墊之間的一空間中。
  12. 如申請專利範圍第11項所述之方法，其中該半導體裝置係配置於該第一表面及該第二表面之任何一個中。
  13. 如申請專利範圍第11項所述之方法，其中該半導體裝置在一SWP通訊協定之下，與該通訊裝置與該SIM卡之任何一個通訊。
  14. 如申請專利範圍第13項所述之方法，其中該第一組接墊之該至少一者係在該ISO 7816標準之下被命名為C6之一接墊。
  15. 如申請專利範圍第11項所述之方法，其中該半導體裝置包括至少一接墊並利用一COF封裝技術而配置於該電路板上，於其中至少一凸塊係在該至少一接墊上形成以與該電路板連接，並利用一導電膠與該電路板連接。
  16. 如申請專利範圍第11項所述之方法，其中該半導體裝置係利用一WLCSP封裝技術而配置於該電路板上，於其中一RDL係設於該半導體裝置與該電路板之間以與其連接，且其中該RDL係與該半導體裝置一起被封裝，且該半導體裝置係經由多個焊球而連接至該電路板。
  17. 如申請專利範圍第11項所述之方法，其中該第一組接墊之該至少一者 係在該ISO 7816標準之下被命名為C6之一接墊。
  18. 如申請專利範圍第11項所述之方法，其中該半導體裝置與該第一組接墊之至少一者及該第二組接墊之至少一者連接，並包括一供NFC功能用之控制器。
  19. 如申請專利範圍第11項所述之方法，其中該積體電路貼片之厚度不大於300μm。
  20. 如申請專利範圍第11項所述之方法，其中該SIM卡係為SIM、USIM、UIM、RUIM、Micro-SIM及Nano-SIM卡之其中一個。
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