TWI479630B - Enhanced stacked microelectronic assemblies with central contacts, systems,modules,and arrangements thereof - Google Patents

Enhanced stacked microelectronic assemblies with central contacts, systems,modules,and arrangements thereof Download PDF

Info

Publication number
TWI479630B
TWI479630B TW100146943A TW100146943A TWI479630B TW I479630 B TWI479630 B TW I479630B TW 100146943 A TW100146943 A TW 100146943A TW 100146943 A TW100146943 A TW 100146943A TW I479630 B TWI479630 B TW I479630B
Authority
TW
Taiwan
Prior art keywords
microelectronic
component
lead
dielectric
microelectronic component
Prior art date
Application number
TW100146943A
Other languages
Chinese (zh)
Other versions
TW201241984A (en
Inventor
Belgacem Haba
Wael Zohni
Richard Dewitt Crisp
Original Assignee
Tessera Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tessera Inc filed Critical Tessera Inc
Publication of TW201241984A publication Critical patent/TW201241984A/en
Application granted granted Critical
Publication of TWI479630B publication Critical patent/TWI479630B/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
    • H01L2223/64—Impedance arrangements
    • H01L2223/66—High-frequency adaptations
    • H01L2223/6605—High-frequency electrical connections
    • H01L2223/6611—Wire connections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0612—Layout
    • H01L2224/0613—Square or rectangular array
    • H01L2224/06134—Square or rectangular array covering only portions of the surface to be connected
    • H01L2224/06135—Covering only the peripheral area of the surface to be connected, i.e. peripheral arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0612—Layout
    • H01L2224/0613—Square or rectangular array
    • H01L2224/06134—Square or rectangular array covering only portions of the surface to be connected
    • H01L2224/06136—Covering only the central area of the surface to be connected, i.e. central arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/4501—Shape
    • H01L2224/45012—Cross-sectional shape
    • H01L2224/45014—Ribbon connectors, e.g. rectangular cross-section
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/4501—Shape
    • H01L2224/45012—Cross-sectional shape
    • H01L2224/45015—Cross-sectional shape being circular
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48095—Kinked
    • H01L2224/48096—Kinked the kinked part being in proximity to the bonding area on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48475—Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball
    • H01L2224/48476—Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball between the wire connector and the bonding area
    • H01L2224/48477—Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball between the wire connector and the bonding area being a pre-ball (i.e. a ball formed by capillary bonding)
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485—Material
    • H01L2224/48505—Material at the bonding interface
    • H01L2224/48599—Principal constituent of the connecting portion of the wire connector being Gold (Au)
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49174—Stacked arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/494—Connecting portions
    • H01L2224/4945—Wire connectors having connecting portions of different types on the semiconductor or solid-state body, e.g. regular and reverse stitches
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73215—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/0651—Wire or wire-like electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06562—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking at least one device in the stack being rotated or offset
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1023—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the support being an insulating substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047—Details of electrical connections between containers
    • H01L2225/1058—Bump or bump-like electrical connections, e.g. balls, pillars, posts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14618—Containers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01087—Francium [Fr]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
    • H01L2924/15331—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30107—Inductance
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance

Description

具中心接觸件之增強堆疊微電子總成以及其之系統、模組及配置Enhanced stacked microelectronic assembly with central contacts and its system, module and configuration

本發明係關於堆疊微電子總成及製造此等總成之方法，且係關於有用於此等總成中之部件。This invention relates to stacked microelectronic assemblies and methods of making such assemblies, and to components useful in such assemblies.

本申請案主張2010年12月17日申請之韓國專利申請案第10-2010-0129890號的權利，該申請案之揭示內容在此以引用之方式併入本文中。The present application claims the benefit of the Korean Patent Application No. 10-2010-0129890, filed on Dec. 17, 2010, the disclosure of which is hereby incorporated by reference.

半導體晶片通常被提供為個別預封裝單元。標準晶片具有平坦矩形本體，其中大前面具有連接至晶片之內部電路的接觸件。每一個別晶片通常安裝於一封裝中，該封裝又安裝於諸如印刷電路板之電路面板上且將晶片之接觸件連接至電路面板之導體。在許多習知設計中，晶片封裝佔據相當大地大於晶片自身之面積的電路面板之面積。如在本發明中參考具有前面之平坦晶片所使用，「晶片之面積」應被理解為指代前面之面積。在「覆晶」設計中，晶片之前面面臨封裝基板(亦即，晶片載體)之面，且晶片上之接觸件係藉由焊球或其他連接元件而直接結合至晶片載體之接觸件。又，晶片載體可經由上覆晶片之前面之端子而結合至電路面板。「覆晶」設計提供相對緊密配置；每一晶片佔據等於或稍微大於晶片之前面之面積的電路面板之面積，諸如在(例如)共同讓渡之美國專利第5,148,265號、第5,148,266號及第5,679,977號中所揭示，該等專利之揭示內容以引用之方式併入本文中。Semiconductor wafers are typically provided as individual pre-packaged units. The standard wafer has a flat rectangular body with a large front having contacts that are connected to internal circuitry of the wafer. Each individual wafer is typically mounted in a package that is in turn mounted on a circuit panel such as a printed circuit board and that connects the contacts of the wafer to the conductors of the circuit panel. In many conventional designs, the chip package occupies an area of the circuit panel that is considerably larger than the area of the wafer itself. As used in the present invention with reference to a flat wafer having the foregoing, "area of the wafer" is to be understood to refer to the area of the front. In a "flip-chip" design, the front side of the wafer faces the surface of the package substrate (i.e., the wafer carrier), and the contacts on the wafer are bonded directly to the contacts of the wafer carrier by solder balls or other connecting elements. Also, the wafer carrier can be bonded to the circuit panel via the terminals on the front side of the overlying wafer. The "flip-chip" design provides a relatively close configuration; each wafer occupies an area of a circuit panel that is equal to or slightly larger than the area of the front surface of the wafer, such as, for example, U.S. Patent Nos. 5,148,265, 5,148,266, and 5,679,977, commonly assigned to each other. The disclosures of these patents are incorporated herein by reference.

某些創新性安裝技術提供近似或等於習知覆晶結合之緊密性的緊密性。可在等於或稍微大於單一晶片自身之面積的電路面板之面積中容納該晶片的封裝通常被稱作「晶片大小之封裝(chip-sized package)」。Certain innovative mounting techniques provide closeness to or close to the tightness of conventional flip chip bonding. A package that accommodates the wafer in an area equal to or slightly larger than the area of the single wafer itself is commonly referred to as a "chip-sized package."

除了最小化由微電子總成所佔據的電路面板之平面面積以外，亦需要生產呈現垂直於電路面板之平面之低總高度或尺寸的晶片封裝。此等薄微電子封裝允許將具有安裝於其中之封裝的電路面板置放成極近接於相鄰結構，因此產生併入電路面板之產品的總大小。已提出用於在單一封裝或模組中提供複數個晶片之各種建議。在習知「多晶片模組」中，晶片並列地安裝於單一封裝基板上，該封裝基板又可安裝至電路面板。此途徑僅提供由晶片所佔據的電路面板之聚集面積的有限縮減。該聚集面積仍大於模組中之個別晶片的總表面積。In addition to minimizing the planar area of the circuit panel occupied by the microelectronic assembly, it is also desirable to produce a wafer package that exhibits a low overall height or size that is perpendicular to the plane of the circuit panel. These thin microelectronic packages allow the circuit panel with the package mounted therein to be placed in close proximity to adjacent structures, thus producing the overall size of the product incorporated into the circuit panel. Various proposals have been made for providing a plurality of wafers in a single package or module. In a conventional "multi-chip module", the wafers are mounted side by side on a single package substrate, which in turn can be mounted to a circuit panel. This approach only provides a finite reduction in the area of the assembly of the circuit panels occupied by the wafer. The aggregate area is still greater than the total surface area of the individual wafers in the module.

亦已建議以「堆疊」配置(亦即，複數個晶片置放於彼此之頂部上的配置)來封裝複數個晶片。在堆疊配置中，若干晶片可安裝於小於該等晶片之總面積的電路面板之面積中。舉例而言，前述美國專利第5,679,977號、第5,148,265號及美國專利第5,347,159號之某些實施例中揭示某些堆疊晶片配置，該等專利之揭示內容以引用之方式併入本文中。亦以引用之方式併入本文中之美國專利第4,941,033號揭示一種配置，在該配置中，晶片堆疊於彼此之頂部上且藉由與晶片相關聯之所謂「配線膜(wiring film)」上的導體而彼此互連。It has also been proposed to package a plurality of wafers in a "stacked" configuration (i.e., a configuration in which a plurality of wafers are placed on top of each other). In a stacked configuration, several wafers can be mounted in an area of a circuit panel that is smaller than the total area of the wafers. For example, certain stacked wafer configurations are disclosed in certain embodiments of the aforementioned U.S. Patent Nos. 5,679,977, 5,148,265, and U.S. Patent No. 5,347,159, the disclosures of each of each of each of each U.S. Patent No. 4,941,033, the disclosure of which is incorporated herein by reference in its entirety, the entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire all all all all all allally The conductors are interconnected to each other.

儘管在先前技術中存在此等成果，但在用於晶片(其具有實質上定位於該等晶片之中心區域中之接觸件)之多晶片封裝的狀況下，將需要進一步改良。諸如一些記憶體晶片之某些半導體晶片通常被製造成使得呈一或兩個列之接觸件實質上沿著晶片之中心軸線而定位。Despite these efforts in the prior art, further improvements are needed in the case of multi-chip packages for wafers having contacts that are substantially positioned in the central region of the wafers. Certain semiconductor wafers, such as some memory chips, are typically fabricated such that contacts in one or two columns are positioned substantially along the central axis of the wafer.

根據本發明之一態樣，一種微電子總成可包括一介電元件、一第一微電子元件、一第二微電子元件，及引線，該等引線自該第一微電子元件及該第二微電子元件之接觸件延伸至該介電元件之端子。該介電元件可具有一第一表面、一第二表面、第一孔隙及第二孔隙，該第一孔隙及該第二孔隙延伸於該第一表面與該第二表面之間且在該第一孔隙與該第二孔隙之間界定該第一表面之一中心區域，該介電元件在其上進一步具有包括曝露於該中心區域處之中心端子之導電元件。該第一微電子元件可具有一後表面及面對該介電元件之該第二表面之一前表面，該第一微電子元件具有曝露於該第一微電子元件之該前表面處之複數個接觸件。該第二微電子元件可具有面對該第一微電子元件之該後表面之一前表面，該第二微電子元件具有突出超過該第一微電子元件之一邊緣的曝露於該第二微電子元件之該前表面處之複數個接觸件。該等引線可自該第一微電子元件及該第二微電子元件之該等接觸件延伸至該等端子，該等引線之至少第一引線及第二引線使該等中心端子之一第一中心端子與該第一微電子元件及該第二微電子元件中每一者電互連。該第一引線及該第二引線可用以在該第一中心端子與該第一微電子元件及該第二微電子元件中每一者之間攜載一信號或一參考電位中至少一者。According to one aspect of the present invention, a microelectronic assembly can include a dielectric component, a first microelectronic component, a second microelectronic component, and leads, the leads being from the first microelectronic component and the The contacts of the two microelectronic components extend to the terminals of the dielectric component. The dielectric element can have a first surface, a second surface, a first aperture, and a second aperture, the first aperture and the second aperture extending between the first surface and the second surface and at the A central region of the first surface is defined between a void and the second aperture, the dielectric component further having thereon a conductive element including a central terminal exposed at the central region. The first microelectronic component can have a back surface and a front surface facing the second surface of the dielectric component, the first microelectronic component having a plurality of portions exposed to the front surface of the first microelectronic component Contacts. The second microelectronic component can have a front surface facing the back surface of the first microelectronic component, the second microelectronic component having an exposure protruding beyond the edge of the first microelectronic component to the second micro a plurality of contacts at the front surface of the electronic component. The leads may extend from the contacts of the first microelectronic component and the second microelectronic component to the terminals, at least the first lead and the second lead of the leads making the first of the center terminals first A center terminal is electrically interconnected with each of the first microelectronic component and the second microelectronic component. The first lead and the second lead can be used to carry at least one of a signal or a reference potential between the first center terminal and each of the first microelectronic component and the second microelectronic component.

在一例示性實施例中，該第一引線及該第二引線可用以在該第一中心端子與該第一微電子元件及該第二微電子元件之間攜載一共用時序信號。在一實施例中，該第一引線及該第二引線可用以攜載至少一時脈信號。在一特定實施例中，該微電子總成可進一步包括使該等中心端子之一第二中心端子與該第一微電子元件及該第二微電子元件中每一者電互連的第三引線及第四引線。該第一引線及該第二引線可用以攜載一第一差動時脈信號。該第三引線及該第四引線可用以在該第二中心端子與該第一微電子元件及該第二微電子元件之間攜載一第二差動時脈信號。該第一差動時脈信號及該第二差動時脈信號集體地傳輸一差動時脈。In an exemplary embodiment, the first lead and the second lead can be used to carry a common timing signal between the first center terminal and the first microelectronic component and the second microelectronic component. In an embodiment, the first lead and the second lead can be used to carry at least one clock signal. In a particular embodiment, the microelectronic assembly can further include a third electrically interconnecting one of the second central terminals of the central terminals with each of the first microelectronic component and the second microelectronic component Lead and fourth lead. The first lead and the second lead can be used to carry a first differential clock signal. The third lead and the fourth lead can be used to carry a second differential clock signal between the second center terminal and the first microelectronic component and the second microelectronic component. The first differential clock signal and the second differential clock signal collectively transmit a differential clock.

在一特定實施例中，該第一引線及該第二引線可用以在該第一中心端子與該第一微電子元件及該第二微電子元件中每一者之間攜載一資料信號。在一實施例中，該第一微電子元件及該第二微電子元件中每一者可具有接觸件，該等接觸件可用於使由該第一微電子元件及該第二微電子元件所共用之複數個資料信號經由包括該第一引線及該第二引線之一引線集合而輸入或輸出至該複數個中心端子之一共用端子集合，該等共用端子包括該第一中心端子。在一例示性實施例中，該第一微電子元件及該第二微電子元件中每一者可包括一記憶體儲存元件，且該第一引線及該第二引線可用以攜載可用以定址該第一微電子元件及該第二微電子元件中每一者中之記憶體之一位址信號。In a particular embodiment, the first lead and the second lead can be used to carry a data signal between the first center terminal and each of the first microelectronic component and the second microelectronic component. In one embodiment, each of the first microelectronic component and the second microelectronic component can have contacts that can be used by the first microelectronic component and the second microelectronic component The plurality of shared data signals are input or output to a common terminal set of the plurality of center terminals via a set of leads including the first lead and the second lead, and the common terminals include the first center terminal. In an exemplary embodiment, each of the first microelectronic component and the second microelectronic component can include a memory storage component, and the first lead and the second lead can be used to carry available for addressing One address signal of the memory in each of the first microelectronic component and the second microelectronic component.

在一實施例中，該介電元件之該第一表面可具有一第一周邊邊緣及在該第一孔隙與該第一邊緣之間的一第一周邊區域。該微電子總成可進一步包括自曝露於該第一周邊區域處之一第一端子延伸至該第一微電子元件之該等接觸件中至少一者的一第三引線。該第三引線可用以在該至少一第一端子與該第一微電子元件之間攜載一第一資料信號。在一特定實施例中，該介電元件之該第一表面可具有一第二周邊邊緣及在該第二孔隙與該第二邊緣之間的一第二周邊區域。該微電子總成可進一步包括自曝露於該第二周邊區域處之一第二端子延伸至該第一微電子元件之該等接觸件中至少一者的一第四引線。該第三引線可用以在該第二端子與該第二微電子元件之間攜載一第二資料信號。在一特定實施例中，該第一微電子元件可具有可用於該第一資料信號之輸入或輸出而不可用於該第二資料信號之輸入或輸出的接觸件。該第二微電子元件可具有可用於該第二資料信號之輸入或輸出而不可用於該第一資料信號之輸入或輸出的接觸件。In an embodiment, the first surface of the dielectric element can have a first peripheral edge and a first peripheral region between the first aperture and the first edge. The microelectronic assembly can further include a third lead extending from the first terminal of the first peripheral region to at least one of the contacts of the first microelectronic component. The third lead can be used to carry a first data signal between the at least one first terminal and the first microelectronic component. In a particular embodiment, the first surface of the dielectric member can have a second peripheral edge and a second peripheral region between the second aperture and the second edge. The microelectronic assembly can further include a fourth lead extending from one of the second terminals of the second peripheral region to the at least one of the contacts of the first microelectronic component. The third lead can be used to carry a second data signal between the second terminal and the second microelectronic component. In a particular embodiment, the first microelectronic component can have contacts that are available for input or output of the first data signal and that are not available for input or output of the second data signal. The second microelectronic component can have contacts that are available for input or output of the second data signal and that are not available for input or output of the first data signal.

根據本發明之另一態樣，一種微電子總成可包括一介電元件、一第一微電子元件、一第二微電子元件、一第一信號引線及一第一參考引線。該介電元件可具有對置面對之第一表面及第二表面以及延伸於該第一表面與該第二表面之間的至少一第一孔隙，該介電元件在其上進一步具有包括曝露於該第一表面處之複數個端子之導電元件。該第一微電子元件可具有一後表面及面對該介電元件之一前表面，該第一微電子元件具有曝露於該第一微電子元件之該前表面處之複數個接觸件。該第二微電子元件可包括一後表面及面對該第一微電子元件之該後表面之一前表面，該第二微電子元件具有突出超過該第一微電子元件之一邊緣的曝露於該第二微電子元件之該前表面處之複數個接觸件。該第一信號引線可通過該至少一孔隙而延伸至該介電元件上之一導電元件，且可電連接於該第一微電子元件之一第一接觸件與該介電元件之一第一端子之間。一第一參考引線可連接至該介電元件上之至少一導電元件，該第一參考引線之一部分實質上平行於該第一信號引線之一實質部分且與該第一信號引線之該實質部分間隔一實質上均一距離，使得可針對該第一信號引線而達成一所要阻抗。該第一參考引線可用以連接至一參考電位且可電連接至該第一微電子元件之至少一接觸件。In accordance with another aspect of the present invention, a microelectronic assembly can include a dielectric component, a first microelectronic component, a second microelectronic component, a first signal lead, and a first reference lead. The dielectric component can have opposing first and second surfaces and at least one first aperture extending between the first surface and the second surface, the dielectric component further having an exposure thereon a plurality of conductive elements of the terminal at the first surface. The first microelectronic component can have a back surface facing a front surface of the dielectric component, the first microelectronic component having a plurality of contacts exposed at the front surface of the first microelectronic component. The second microelectronic component can include a back surface and a front surface facing the back surface of the first microelectronic component, the second microelectronic component having an exposure protruding beyond an edge of the first microelectronic component a plurality of contacts at the front surface of the second microelectronic component. The first signal lead may extend through the at least one aperture to one of the conductive elements on the dielectric element, and may be electrically connected to one of the first contact part of the first microelectronic element and the first of the dielectric element Between the terminals. a first reference lead connectable to the at least one conductive element on the dielectric element, a portion of the first reference lead being substantially parallel to a substantial portion of the first signal lead and to the substantial portion of the first signal lead The spacing is a substantially uniform distance such that a desired impedance can be achieved for the first signal lead. The first reference lead can be connected to a reference potential and can be electrically connected to at least one contact of the first microelectronic element.

在一特定實施例中，該第一參考引線可橫越該介電元件之該第一孔隙而延伸。在一例示性實施例中，該微電子總成可進一步包括一第二孔隙，其延伸通過該介電元件；及一第二信號引線，其通過該第二孔隙而延伸至該介電元件上之一導電元件且電連接於該第二微電子元件之一接觸件與該介電元件上之一端子之間。在一實施例中，該微電子元件可進一步包括電連接至該介電元件上之導電元件的一第二參考引線，該第二參考引線之至少一部分與該第二信號引線間隔一實質上均一距離，使得可針對該第二信號引線而達成一所要阻抗。在一特定實施例中，該第一參考引線可橫越該介電元件之該第一孔隙及該第二孔隙而延伸。在一例示性實施例中，該第一參考引線之一第一部分可延伸成與該第一信號引線相隔一實質上均一距離，且該第一參考引線之第二部分可延伸成與該第二信號引線相隔一實質上均一距離。In a particular embodiment, the first reference lead can extend across the first aperture of the dielectric component. In an exemplary embodiment, the microelectronic assembly can further include a second aperture extending through the dielectric component; and a second signal lead extending through the second aperture to the dielectric component One of the conductive elements is electrically connected between one of the contacts of the second microelectronic element and one of the terminals of the dielectric element. In one embodiment, the microelectronic component can further include a second reference lead electrically connected to the conductive component on the dielectric component, at least a portion of the second reference lead being substantially uniform from the second signal lead The distance is such that a desired impedance can be achieved for the second signal lead. In a particular embodiment, the first reference lead can extend across the first aperture and the second aperture of the dielectric component. In an exemplary embodiment, a first portion of the first reference lead may extend to be substantially a uniform distance from the first signal lead, and a second portion of the first reference lead may extend to the second portion The signal leads are separated by a substantially uniform distance.

根據本發明之又一態樣，一種微電子總成可包括一介電元件、一第一微電子元件、一第二微電子元件，以及第一結合導線及第二結合導線。該介電元件可具有對置面對之第一表面及第二表面以及延伸於該第一表面與該第二表面之間的至少一孔隙，該介電元件在其上進一步具有包括複數個接觸件及複數個端子之導電元件，該等接觸件及該等端子曝露於該介電元件之該第一表面處。該第一微電子元件可具有一後表面及面對該介電元件之一前表面，該第一微電子元件具有曝露於該第一微電子元件之該前表面處之複數個接觸件。該第二微電子元件可具有一後表面及面對該第一微電子元件之該後表面之一前表面，該第二微電子元件具有曝露於該前表面處且突出超過該第一微電子元件之一邊緣之複數個接觸件。第一結合導線及第二結合導線可通過該至少一孔隙而延伸至該介電元件上之導電元件，該第一結合導線及該第二結合導線具有電連接至該第一微電子元件之一第一接觸件的第一末端及電連接至該介電元件之一第一端子的第二末端，且提供電並聯導電路徑。According to still another aspect of the present invention, a microelectronic assembly can include a dielectric component, a first microelectronic component, a second microelectronic component, and a first bonding wire and a second bonding wire. The dielectric component can have opposing first and second surfaces and at least one aperture extending between the first surface and the second surface, the dielectric component further having a plurality of contacts thereon And a plurality of conductive elements of the terminals, the contacts and the terminals being exposed at the first surface of the dielectric element. The first microelectronic component can have a back surface facing a front surface of the dielectric component, the first microelectronic component having a plurality of contacts exposed at the front surface of the first microelectronic component. The second microelectronic component can have a rear surface and a front surface facing the back surface of the first microelectronic component, the second microelectronic component having exposure to the front surface and protruding beyond the first microelectronic A plurality of contacts on one edge of the component. The first bonding wire and the second bonding wire may extend through the at least one aperture to the conductive component on the dielectric component, the first bonding wire and the second bonding wire having electrical connection to one of the first microelectronic component A first end of the first contact and a second end electrically coupled to the first terminal of the one of the dielectric elements and providing an electrically parallel conductive path.

在一例示性實施例中，該第一結合導線可接合至該等導電元件中之一第一者且可接合至該第二結合導線之一末端，使得該第一結合導線不觸碰該第一接觸件或該第一導電元件中至少一者。在一實施例中，該微電子總成可進一步包括通過該至少一孔隙而延伸至該介電元件上之導電元件的第三導電結合導線及第四導電結合導線。該第三結合導線及該第四結合導線可電連接於該第二微電子元件之一第一接觸件與該介電元件之一第二端子之間，且可提供電並聯導電路徑。在一特定實施例中，該微電子總成可進一步包括安裝於該介電元件上之至少一被動部件。In an exemplary embodiment, the first bonding wire may be coupled to one of the first conductive members and may be coupled to one end of the second bonding wire such that the first bonding wire does not touch the first bonding wire At least one of a contact or the first conductive element. In one embodiment, the microelectronic assembly can further include a third conductive bond wire and a fourth conductive bond wire that extend through the at least one aperture to the conductive component on the dielectric component. The third bonding wire and the fourth bonding wire are electrically connected between the first contact of one of the second microelectronic components and the second terminal of the dielectric component, and can provide an electrically parallel conductive path. In a particular embodiment, the microelectronic assembly can further include at least one passive component mounted to the dielectric component.

根據本發明之又一態樣，一種微電子總成可包括一介電元件、一第一微電子元件、一第二微電子元件、第一引線及第二引線。該介電元件可具有對置面對之第一表面及第二表面以及延伸於該等表面之間的一孔隙，該介電元件在其上進一步具有導電元件。該第一微電子元件可具有一後表面及面對該介電元件之一前表面，該第一微電子元件具有一第一邊緣及遠離於該第一邊緣的曝露於該第一微電子元件之該前表面處之複數個接觸件。該第二微電子元件可具有一後表面及面對該第一微電子元件之該後表面之一前表面，該第二微電子元件具有曝露於該第二微電子元件之該前表面處且突出超過該第一微電子元件之該第一邊緣的複數個接觸件，該介電元件中之該孔隙包圍該第一微電子元件及該第二微電子元件之該等接觸件。該等第一引線可自該第一微電子元件之接觸件通過該孔隙而延伸至該等導電元件中至少一些。該等第二引線可自該第二微電子元件之接觸件通過該孔隙而延伸至該等導電元件中至少一些。According to still another aspect of the present invention, a microelectronic assembly can include a dielectric component, a first microelectronic component, a second microelectronic component, a first lead, and a second lead. The dielectric member can have opposing first and second surfaces facing and an aperture extending between the surfaces, the dielectric member further having a conductive member thereon. The first microelectronic component can have a rear surface and a front surface facing the dielectric component, the first microelectronic component having a first edge and exposure to the first microelectronic component away from the first edge a plurality of contacts at the front surface. The second microelectronic component can have a back surface and a front surface facing the back surface of the first microelectronic component, the second microelectronic component having exposure to the front surface of the second microelectronic component and And a plurality of contacts protruding beyond the first edge of the first microelectronic component, the apertures in the dielectric component surrounding the contacts of the first microelectronic component and the second microelectronic component. The first leads may extend from the contacts of the first microelectronic element through the aperture to at least some of the electrically conductive elements. The second leads may extend from the contacts of the second microelectronic element through the aperture to at least some of the electrically conductive elements.

根據本發明之另一態樣，一種微電子總成可包括一介電元件、一第一微電子元件及一第二微電子元件。該介電元件可具有對置面對之第一表面及第二表面以及延伸於該等表面之間的一孔隙。該第一微電子元件可具有一後表面、面對該介電元件之一前表面及一第一邊緣，該第一微電子元件具有遠離於該第一邊緣的曝露於該第一微電子元件之該前表面處之複數個接觸件，及沿著該前表面而自該等接觸件延伸至鄰近於該第一邊緣的曝露於該前表面處之重新分佈焊墊的重新分佈導體。該第二微電子元件可具有一後表面及一前表面，該第二微電子元件具有突出超過該第一微電子元件之該第一邊緣的曝露於該第二微電子元件之該前表面處之複數個接觸件。該第一微電子元件之該等重新分佈焊墊及該第二微電子元件之該等接觸件可與該介電元件中之該孔隙對準。In accordance with another aspect of the present invention, a microelectronic assembly can include a dielectric component, a first microelectronic component, and a second microelectronic component. The dielectric member can have opposing first and second surfaces facing and a void extending between the surfaces. The first microelectronic component can have a rear surface facing a front surface of the dielectric component and a first edge, the first microelectronic component having an exposure to the first microelectronic component remote from the first edge a plurality of contacts at the front surface and a redistribution conductor extending from the contacts along the front surface to a redistribution pad exposed adjacent the first edge to the front surface. The second microelectronic component can have a rear surface and a front surface, the second microelectronic component having a front surface that protrudes beyond the first edge of the first microelectronic component and exposed to the front surface of the second microelectronic component a plurality of contacts. The redistribution pads of the first microelectronic component and the contacts of the second microelectronic component can be aligned with the apertures in the dielectric component.

在一實施例中，該介電元件可在其上具有包括曝露於該介電元件之該第一表面處之端子的導電元件。該微電子總成可進一步包括自該第一微電子元件之該等重新分佈焊墊通過該孔隙而延伸至該介電元件上之該等導電元件中之一些的第一引線，及自該第二微電子元件之該等接觸件通過該孔隙而延伸至該介電元件上之該等導電元件中之一些的第二引線。In an embodiment, the dielectric component can have a conductive element thereon including a terminal exposed at the first surface of the dielectric component. The microelectronic assembly can further include a first lead extending from the redistributable pads of the first microelectronic component through the aperture to some of the conductive elements on the dielectric component, and from the first The contacts of the two microelectronic elements extend through the aperture to a second lead of some of the conductive elements on the dielectric element.

本發明之另外態樣提供系統，該等系統併入根據本發明之前述態樣的微電子結構、根據本發明之前述態樣的複合晶片，或連同其他電子裝置的該等微電子結構及該等複合晶片兩者。舉例而言，該系統可安置於單一外殼中，該單一外殼可為一攜帶型外殼。根據本發明之此態樣中之較佳實施例的系統可比可比較之習知系統更緊密。A further aspect of the present invention provides a system incorporating the microelectronic structure according to the foregoing aspects of the present invention, the composite wafer according to the foregoing aspect of the present invention, or the microelectronic structure together with other electronic devices and Both composite wafers. For example, the system can be housed in a single housing that can be a portable housing. The system according to the preferred embodiment of this aspect of the invention may be more compact than comparable conventional systems.

本發明之另外態樣提供模組，該等模組可包括根據本發明之前述態樣的複數個微電子總成。每一模組可具有用於將信號輸送至該等微電子總成中每一者及自該等微電子總成中每一者輸送信號之一共同電介面。Additional aspects of the present invention provide modules that can include a plurality of microelectronic assemblies in accordance with the foregoing aspects of the present invention. Each module can have a common interface for delivering signals to each of the microelectronic assemblies and one of the signals transmitted from each of the microelectronic assemblies.

本發明之另外態樣提供配置，該等配置併入根據本發明之前述態樣的至少一微電子總成，及與該至少一微電子總成垂直地堆疊且與該至少一微電子總成電互連之至少一第三微電子元件。該第三微電子元件可具有不同於該至少一微電子總成之一功能的一功能。A further aspect of the present invention provides a configuration incorporating at least one microelectronic assembly in accordance with the foregoing aspects of the present invention, and stacked vertically with the at least one microelectronic assembly and with the at least one microelectronic assembly At least one third microelectronic component electrically interconnected. The third microelectronic component can have a function that is different from one of the functions of the at least one microelectronic assembly.

參看圖1，根據本發明之一實施例的堆疊微電子總成10包括第一微電子元件12及第二微電子元件14。在一些實施例中，第一微電子元件12及第二微電子元件14可為半導體晶片、晶圓或其類似者。舉例而言，第一微電子元件12及第二微電子元件14中之一者或其兩者可包括記憶體儲存元件。如本文所使用，「記憶體儲存元件」指代以一陣列而配置之多個記憶胞，連同可用以自該多個記憶胞儲存及擷取資料(諸如，用於經由電介面而輸送資料)之電路。Referring to FIG. 1, a stacked microelectronic assembly 10 in accordance with an embodiment of the present invention includes a first microelectronic component 12 and a second microelectronic component 14. In some embodiments, the first microelectronic component 12 and the second microelectronic component 14 can be semiconductor wafers, wafers, or the like. For example, one or both of the first microelectronic element 12 and the second microelectronic element 14 can include a memory storage element. As used herein, "memory storage element" refers to a plurality of memory cells configured in an array, along with data storage and retrieval from the plurality of memory cells (such as for transporting data via a dielectric interface). The circuit.

第一微電子元件12具有前表面16、遠離於前表面16之後表面18，以及延伸於該前表面與該後表面之間的第一邊緣27及第二邊緣29。第一微電子元件12之前表面16包括第一末端區域15及第二末端區域17，以及定位於第一末端區域15與第二末端區域17之間的中心區域13。第一末端區域15延伸於中心區域13與第一邊緣27之間，且第二末端區域17延伸於中心區域13與第二邊緣29之間。電接觸件20曝露於第一微電子元件12之前表面16處。如本發明所使用，導電元件「曝露於」結構之表面處的敍述指示該導電元件可用於與在垂直於該表面之方向上自該結構外部朝向該表面移動之理論點的接觸。因此，曝露於結構之表面處的端子或其他導電元件可自此表面突出；可與此表面齊平；或可相對於此表面而凹入且通過該結構中之孔或凹陷而曝露。第一微電子元件12之接觸件20在中心區域13內曝露於前表面16處。舉例而言，接觸件20可以一或兩個平行列而經配置成鄰近於第一表面16之中心。The first microelectronic element 12 has a front surface 16, a back surface 18 away from the front surface 16, and a first edge 27 and a second edge 29 extending between the front surface and the back surface. The front surface 16 of the first microelectronic element 12 includes a first end region 15 and a second end region 17, and a central region 13 positioned between the first end region 15 and the second end region 17. The first end region 15 extends between the central region 13 and the first edge 27, and the second end region 17 extends between the central region 13 and the second edge 29. Electrical contact 20 is exposed at front surface 16 of first microelectronic element 12. As used herein, the statement that the conductive element is "exposed to" the surface of the structure indicates that the conductive element can be used for contact with a theoretical point of movement from the exterior of the structure toward the surface in a direction perpendicular to the surface. Thus, terminals or other conductive elements exposed at the surface of the structure may protrude from the surface; may be flush with the surface; or may be recessed relative to the surface and exposed through holes or depressions in the structure. The contact 20 of the first microelectronic element 12 is exposed at the front surface 16 in the central region 13. For example, the contacts 20 can be disposed adjacent to the center of the first surface 16 in one or two parallel columns.

第二微電子元件14具有前表面22、遠離於前表面22之後表面24，以及延伸於該前表面與該後表面之間的第一邊緣35及第二邊緣37。第二微電子元件14之前表面22包括第一末端區域21及第二末端區域23，以及定位於第一末端區域21與第二末端區域23之間的中心區域19。第一末端區域21延伸於中心區域19與第一邊緣35之間，且第二末端區域23延伸於中心區域19與第二邊緣37之間。電接觸件26曝露於第二微電子元件14之前表面22處。第二微電子元件14之接觸件26在中心區域19內曝露於前表面22處。舉例而言，接觸件26可以一或兩個平行列而經配置成鄰近於第一表面22之中心。The second microelectronic element 14 has a front surface 22, a back surface 24 away from the front surface 22, and a first edge 35 and a second edge 37 extending between the front surface and the back surface. The front surface 22 of the second microelectronic element 14 includes a first end region 21 and a second end region 23, and a central region 19 positioned between the first end region 21 and the second end region 23. The first end region 21 extends between the central region 19 and the first edge 35, and the second end region 23 extends between the central region 19 and the second edge 37. Electrical contact 26 is exposed at front surface 22 of second microelectronic element 14. The contact 26 of the second microelectronic element 14 is exposed at the front surface 22 in the central region 19. For example, the contacts 26 can be disposed adjacent to the center of the first surface 22 in one or two parallel rows.

如在圖1中所見，第一微電子元件12及第二微電子元件14相對於彼此而堆疊。在一些實施例中，第二微電子元件14之前表面22及第一微電子元件12之後表面18彼此面對。第二微電子元件14之第二末端區域23之至少一部分上覆第一微電子元件12之第二末端區域17之至少一部分。第二微電子元件14之中心區域19之至少一部分突出超過第一微電子元件12之第二邊緣29。因此，第二微電子元件14之接觸件26定位於超過第一微電子元件12之第二邊緣29的部位中。As seen in Figure 1, the first microelectronic element 12 and the second microelectronic element 14 are stacked relative to each other. In some embodiments, the front surface 22 of the second microelectronic element 14 and the back surface 18 of the first microelectronic element 12 face each other. At least a portion of the second end region 23 of the second microelectronic element 14 overlies at least a portion of the second end region 17 of the first microelectronic element 12. At least a portion of the central region 19 of the second microelectronic element 14 protrudes beyond the second edge 29 of the first microelectronic element 12. Thus, the contact 26 of the second microelectronic element 14 is positioned in a location beyond the second edge 29 of the first microelectronic element 12.

微電子總成10進一步包括具有對置面對之第一表面32及第二表面34的介電元件30。雖然圖1展示僅一個介電元件30，但微電子總成10可包括一個以上介電元件。一或多個導電元件或端子36曝露於介電元件30之第一表面32處。至少一些端子36可相對於第一微電子元件12及/或第二微電子元件14而移動。Microelectronic assembly 10 further includes a dielectric component 30 having opposing first and second surfaces 32, 34, 34. Although FIG. 1 shows only one dielectric component 30, the microelectronic assembly 10 can include more than one dielectric component. One or more conductive elements or terminals 36 are exposed at the first surface 32 of the dielectric element 30. At least some of the terminals 36 are movable relative to the first microelectronic element 12 and/or the second microelectronic element 14.

介電元件30可進一步包括一或多個孔隙。在圖1所描繪之實施例中，介電元件30包括與第一微電子元件12之中心區域13實質上對準的第一孔隙33及與第二微電子元件14之中心區域19實質上對準的第二孔隙39，藉此提供對接觸件20及26之接取。Dielectric element 30 can further include one or more apertures. In the embodiment depicted in FIG. 1, dielectric component 30 includes a first aperture 33 that is substantially aligned with central region 13 of first microelectronic component 12 and a substantially central region 19 with second microelectronic component 14 A second aperture 39 is provided thereby providing access to the contacts 20 and 26.

如在圖1中所見，介電元件30可延伸超過第一微電子元件12之第一邊緣27及第二微電子元件14之第二邊緣35。介電元件30之第二表面34可與第一微電子元件12之前表面16毗鄰。介電元件30可由任何合適介電材料部分地或全部地製成。舉例而言，介電元件30可包含可撓性材料層，諸如，聚醯亞胺層、BT樹脂層，或通常用於製造捲帶式自動結合(「tape automated bonding,TAB」)捲帶之其他介電材料層。或者，介電元件30可包含相對剛性類板材料，諸如，厚纖維加強型環氧樹脂層(諸如，Fr-4或Fr-5板)。不管所使用之材料如何，介電元件30皆可包括單一介電材料層或多個介電材料層。As seen in FIG. 1, dielectric component 30 can extend beyond first edge 27 of first microelectronic component 12 and second edge 35 of second microelectronic component 14. The second surface 34 of the dielectric component 30 can be adjacent to the front surface 16 of the first microelectronic component 12. Dielectric element 30 can be made partially or wholly from any suitable dielectric material. For example, the dielectric component 30 can comprise a layer of flexible material, such as a polyimide layer, a BT resin layer, or commonly used in the manufacture of tape automated bonding (TAB) tapes. Other layers of dielectric material. Alternatively, dielectric component 30 can comprise a relatively rigid sheet material such as a thick fiber reinforced epoxy layer (such as a Fr-4 or Fr-5 board). Dielectric element 30 can comprise a single layer of dielectric material or a plurality of layers of dielectric material, regardless of the materials used.

介電元件30亦可包括曝露於第一表面32上之導電元件40及導電跡線42。導電跡線42將導電元件40電耦接至端子36。Dielectric element 30 can also include conductive elements 40 and conductive traces 42 that are exposed on first surface 32. Conductive traces 42 electrically couple conductive element 40 to terminal 36.

諸如黏接劑層之間隔層31可定位於第二微電子元件14之第一末端區域21與介電元件30之部分之間。若間隔層31包括黏接劑，則黏接劑將第二微電子元件14連接至介電材料30。另一間隔層60可定位於第二微電子元件14之第二末端區域23與第一微電子元件12之第二末端區域17之間。此間隔層60可包括用於將第一微電子元件12及第二微電子元件14結合在一起之黏接劑。在此狀況下，間隔層60可由晶粒附接黏接劑部分地或全部地製成，且可包含諸如聚矽氧彈性體之低彈性模數材料。然而，若兩個微電子元件12及14為由相同材料形成之習知半導體晶片，則間隔層60可由薄高彈性模數黏接劑或焊料層全部地或部分地製成，此係因為該等微電子元件將傾向於回應於溫度改變而一致地膨脹及收縮。不顧所使用之材料如何，間隔層31及60中每一者皆可包括單一層或多個層。A spacer layer 31, such as an adhesive layer, can be positioned between the first end region 21 of the second microelectronic component 14 and a portion of the dielectric component 30. If the spacer layer 31 includes an adhesive, the adhesive connects the second microelectronic component 14 to the dielectric material 30. Another spacer layer 60 can be positioned between the second end region 23 of the second microelectronic component 14 and the second end region 17 of the first microelectronic component 12. The spacer layer 60 can include an adhesive for bonding the first microelectronic element 12 and the second microelectronic element 14 together. In this case, the spacer layer 60 may be partially or wholly made of a die attach adhesive and may comprise a low modulus of elasticity material such as a polyoxyxene elastomer. However, if the two microelectronic components 12 and 14 are conventional semiconductor wafers formed of the same material, the spacer layer 60 may be made entirely or partially from a thin high modulus of elasticity adhesive or solder layer, as this Microelectronic components will tend to expand and contract uniformly in response to temperature changes. Regardless of the materials used, each of the spacer layers 31 and 60 may comprise a single layer or multiple layers.

如在圖1及圖2中所見，電連接件或引線70將第一微電子元件12之接觸件20電連接至一些導電元件40。電連接件70可包括多個導線結合件72、74。導線結合件72、74延伸通過第一孔隙33且經定向成彼此實質上平行。導線結合件72及74中每一者將接觸件20電耦接至介電元件之對應元件40。根據此實施例之多導線結合結構可藉由提供用於使電流流動於經連接接觸件之間的額外路徑而實質上減少導線結合連接件之電感。此多導線結合結構可在接觸件20與介電元件之對應元件40之間提供電並聯導電路徑。如本文所使用，「引線」為延伸於兩個導電元件之間的電連接件之部分或延伸於兩個導電元件之間的整個電連接件，諸如，包含導線結合件72、74及跡線42之引線，跡線42自第一微電子元件12之接觸件20中之一者通過導電元件40中之一者而延伸至端子36中之一者。As seen in FIGS. 1 and 2, electrical connectors or leads 70 electrically connect the contacts 20 of the first microelectronic component 12 to some of the conductive components 40. Electrical connector 70 can include a plurality of wire bonds 72, 74. The wire bonds 72, 74 extend through the first apertures 33 and are oriented substantially parallel to each other. Each of the wire bonds 72 and 74 electrically couples the contact 20 to a corresponding component 40 of the dielectric component. The multiple wire bond structure in accordance with this embodiment can substantially reduce the inductance of the wire bond connector by providing an additional path for current flow between the connected contacts. This multi-wire bonding structure provides an electrically parallel conductive path between the contact 20 and the corresponding component 40 of the dielectric component. As used herein, a "lead" is a portion of an electrical connector that extends between two conductive elements or an entire electrical connection that extends between two conductive elements, such as including wire bonds 72, 74 and traces. The lead of 42 extends from one of the contacts 20 of the first microelectronic element 12 through one of the conductive elements 40 to one of the terminals 36.

其他電連接件或引線50將第二微電子元件14之接觸件26電耦接至一些元件40。電連接件50可包括多個導線結合件52、54。導線結合件52、54延伸通過第二孔隙39且經定向成彼此實質上平行。導線結合件52及54中每一者將接觸件26電耦接至介電元件30之對應元件40。根據此實施例之多結合導線結構可藉由提供用於使電流流動於經連接接觸件之間的額外路徑而實質上減少導線結合連接件之電感。Other electrical connectors or leads 50 electrically couple the contacts 26 of the second microelectronic component 14 to some of the components 40. Electrical connector 50 can include a plurality of wire bonds 52,54. The wire bonds 52, 54 extend through the second aperture 39 and are oriented substantially parallel to each other. Each of the wire bonds 52 and 54 electrically couples the contact 26 to a corresponding component 40 of the dielectric component 30. The multiple bond wire structure in accordance with this embodiment can substantially reduce the inductance of the wire bond connector by providing an additional path for current flow between the connected contacts.

如在圖3中所見，在電連接件70中，第一結合導線52可具有與晶片接觸件20以冶金方式接合之末端52A，及與導電元件40以冶金方式接合之另一末端(未圖示)。舉例而言，結合導線可包括諸如金之金屬，該金屬可使用超音波能量、熱或其兩者而熔接至接觸件以形成與該接觸件之冶金聯結或結合。與此對比，第二結合導線54可具有以冶金方式結合至第一結合導線52之末端52A的一末端54A，及以冶金方式結合至第一結合導線52之末端的對置末端(未圖示)。As seen in FIG. 3, in the electrical connector 70, the first bond wire 52 can have a metallurgically bonded end 52A with the wafer contact 20 and another end metallurgically bonded to the conductive element 40 (not shown). Show). For example, the bond wires can include a metal such as gold that can be fused to the contacts using ultrasonic energy, heat, or both to form a metallurgical bond or bond with the contacts. In contrast, the second bonding wire 54 can have a terminal end 54A that is metallurgically bonded to the end 52A of the first bonding wire 52, and an opposite end that is metallurgically bonded to the end of the first bonding wire 52 (not shown) ).

第二結合導線54不需要觸碰導電元件140，第一結合導線52以冶金方式結合至導電元件140。取而代之，在一特定實施例中，第二結合導線54之末端54A可以使得該第二結合導線在該第二結合導線之至少一末端處不觸碰接觸件且在任一末端處可能不觸碰接觸件的方式而以冶金方式結合至第一結合導線52之末端52A。The second bond wire 54 need not touch the conductive element 140, and the first bond wire 52 is metallurgically bonded to the conductive element 140. Alternatively, in a particular embodiment, the end 54A of the second bonding wire 54 can be such that the second bonding wire does not touch the contact at at least one end of the second bonding wire and may not touch the contact at either end. The piece is metallurgically bonded to the end 52A of the first bonding wire 52.

每一結合導線52、56之末端52A、54A可包括在導線結合程序期間所形成之球。導線結合工具通常藉由使金導線之尖端自線軸前進至工具之尖端而操作。在一處理實例中，當工具在用於在第一接觸件(例如，晶片接觸件20)處形成第一導線結合件之位置中時，工具可接著將超音波能量、熱或其兩者施加至導線，直至導線之尖端熔融且形成球為止。經加熱球接著與接觸件之表面以冶金方式結合。接著，當導線結合工具之尖端移動離開第一接觸件時，球保持結合至接觸件，而在此接觸件與第二接觸件之間的結合導線之長度被放出。導線結合工具可接著將導線之第二末端附接至第二接觸件，從而在彼末端處形成與第二接觸件之冶金聯結。The ends 52A, 54A of each of the bond wires 52, 56 can include balls formed during the wire bonding procedure. Wire bonding tools typically operate by advancing the tip of the gold wire from the spool to the tip of the tool. In a processing example, when the tool is in a position for forming a first wire bond at the first contact (eg, wafer contact 20), the tool can then apply ultrasonic energy, heat, or both To the wire until the tip of the wire melts and forms a ball. The heated ball is then metallurgically bonded to the surface of the contact. Then, as the tip of the wire bonding tool moves away from the first contact, the ball remains bonded to the contact, and the length of the bonding wire between the contact and the second contact is released. The wire bonding tool can then attach the second end of the wire to the second contact to form a metallurgical bond with the second contact at the end.

可接著以略微不同方式來重複以上程序以形成第二結合導線。在此狀況下，導線結合工具可移動至一位置中，且可接著用以加熱導線之尖端以形成球，該球接著將第二結合導線之末端54A以冶金方式結合至第一結合導線之末端52A。導線結合工具可接著將第二結合導線之另一末端附接至第一結合導線之第二末端，從而在彼末端處形成與至少第一結合導線之冶金聯結。The above procedure can then be repeated in a slightly different manner to form a second bond wire. In this case, the wire bonding tool can be moved into a position and can then be used to heat the tip of the wire to form a ball which then metallurgically bonds the end 54A of the second bonding wire to the end of the first bonding wire 52A. The wire bonding tool can then attach the other end of the second bonding wire to the second end of the first bonding wire to form a metallurgical bond with the at least first bonding wire at the other end.

導電元件40中之一些可攜載信號，亦即，隨著時間而變化且通常傳送資訊之電壓或電流。舉例而言，在無限制之情況下，隨著時間而變化且表示狀態、改變、量測、時脈或時序輸入或控制或回饋輸入之電壓或電流為信號之實例。導電元件40中之其他者可提供連接至接地或電力供應電壓之連接件。連接至接地或電力供應電壓之連接件通常提供遍及為電路之操作所關注之頻率隨著時間而至少相當地穩定的電壓。當各別接觸件對之間的雙或多導線結合連接件係連接至接地或電力供應電壓時，該等連接件可尤其有益。在一實例中，雙導線連接件72、74及52、54可將各別微電子元件12、14連接至介電元件30上之接地端子。相似地，雙導線結合連接件72A、74A及52A、54A可將各別微電子元件連接至介電元件上之電力供應端子(用於經由電路面板而進一步互連至電力供應器，未圖示)。增加連接至接地或電力端子之此等連接件中導線結合件之數目可縮減接地及電力電路中之電感，此情形可幫助縮減系統中之雜訊。Some of the conductive elements 40 can carry signals, that is, voltages or currents that change over time and typically convey information. For example, without limitation, a voltage or current that changes over time and represents a state, change, measurement, clock, or timing input or control or feedback input is an example of a signal. Others of conductive elements 40 may provide connections to ground or power supply voltages. Connections connected to ground or power supply voltages typically provide voltages that are at least fairly stable over time throughout the frequency of interest for operation of the circuit. Such connectors may be particularly beneficial when the dual or multiple wire bond connections between pairs of respective contacts are connected to a ground or power supply voltage. In one example, the two-wire connectors 72, 74 and 52, 54 can connect the respective microelectronic components 12, 14 to the ground terminals on the dielectric component 30. Similarly, the dual wire bond connectors 72A, 74A and 52A, 54A can connect the respective microelectronic components to the power supply terminals on the dielectric component (for further interconnection to the power supply via the circuit panel, not shown ). Increasing the number of wire bonds in such connectors that are connected to ground or power terminals can reduce the inductance in the ground and power circuits, which can help reduce noise in the system.

根據此實施例之多結合導線結構及方法之另一可能益處係在用於將結合導線附接至諸如晶片或基板上之結合焊墊之接觸件的面積有限時縮減電感。一些晶片具有特別高之接觸密度及細微間距。此等晶片上之結合焊墊具有極有限之面積。一結構(其中第二結合導線具有附接至第一結合導線之末端的末端，但其自身不觸碰接觸件)可在不需要增加結合焊墊之大小的情況下達成雙或多結合導線結構。因此，即使當形成連接至以細微間距而配置之接觸件或具有小面積之接觸件的導線結合連接件時，亦可達成如關於圖3所描述之多結合導線結構。Another possible benefit of the multi-bonded wire structure and method according to this embodiment is to reduce the inductance when the area of the contacts for attaching the bond wires to a bond pad such as a wafer or substrate is limited. Some wafers have particularly high contact densities and fine pitches. Bond pads on such wafers have a very limited area. A structure in which the second bonding wire has an end attached to the end of the first bonding wire, but does not touch the contact itself can achieve a double or multiple bonding wire structure without increasing the size of the bonding pad . Therefore, even when a wire bonding connector that is connected to a contact disposed at a fine pitch or a contact having a small area is formed, a multi-bonding wire structure as described with respect to FIG. 3 can be achieved.

此外，具有高密度之一些微電子元件亦可具有高輸入及輸出速率，亦即，將信號傳輸至晶片上或傳輸離開晶片的高頻率。在足夠高之頻率下，連接件之電感可實質上增加。根據此實施例之多結合導線結構可藉由提供用於使電流流動於經連接接觸件之間的額外路徑而實質上減少用於接地、電力或信號傳輸之導線結合連接件之電感。In addition, some microelectronic components with high density can also have high input and output rates, i.e., high frequencies that transmit signals to or from the wafer. At sufficiently high frequencies, the inductance of the connector can be substantially increased. The multiple bond wire structure in accordance with this embodiment can substantially reduce the inductance of the wire bond connector for grounding, power or signal transmission by providing an additional path for current flow between the connected contacts.

圖4說明在第一結合導線51與第二結合導線53之間於該兩者之末端處的連接件。如在圖4中所見，在結合導線之第一末端處，球51A及53A可以冶金方式接合在一起，但以使得第二導線53之球不觸碰接觸件20的方式接合。在第二接觸件40處之結合導線之第二末端51B、53B處，可在無球形成於第二末端51B、53B處的情況下在該等導線之間製造電連接件。在此狀況下，接觸件20、40中之一者可為曝露於晶片之表面處的晶片接觸件，且接觸件20、40中之另一者可為曝露於基板之表面處的基板接觸件。如在圖4中進一步所見，第二導線結合件之第二末端53B在第二結合導線不觸碰接觸件40之情況下在51B處接合至第一結合導線。Figure 4 illustrates the connection between the first bond wire 51 and the second bond wire 53 at the ends of the two. As seen in FIG. 4, at the first end of the bond wire, the balls 51A and 53A can be metallurgically joined together, but joined in such a manner that the ball of the second wire 53 does not touch the contact 20. At the second ends 51B, 53B of the bonding wires at the second contact 40, electrical connections can be made between the wires without ball formation at the second ends 51B, 53B. In this case, one of the contacts 20, 40 can be a wafer contact exposed at the surface of the wafer, and the other of the contacts 20, 40 can be a substrate contact exposed at the surface of the substrate. . As further seen in FIG. 4, the second end 53B of the second wire bond is joined to the first bond wire at 51B without the second bond wire contacting the contact 40.

圖5說明此實施例(圖4)之變化，其中第一結合導線55具有接合至第一接觸件20之球末端55A。第二結合導線57之導線末端57B在第一接觸件20上方以冶金方式接合至第一結合導線之球末端55A。另外，第二結合導線57之球末端57A在第二接觸件40處接合至第一結合導線55之導線末端55B。FIG. 5 illustrates a variation of this embodiment (FIG. 4) in which the first bond wire 55 has a ball end 55A that is joined to the first contact 20. The wire end 57B of the second bonding wire 57 is metallurgically bonded over the first contact 20 to the ball end 55A of the first bonding wire. In addition, the ball end 57A of the second bonding wire 57 is bonded to the wire end 55B of the first bonding wire 55 at the second contact 40.

在上文所描述之實施例之另一變化中，複數個結合導線可被形成且與現有結合導線(已經在其末端處接合至接觸件)接合以在接觸件之間形成三個或三個以上並聯路徑。在此實施例中，第三結合導線可經配置成使得在第三結合導線與第一或第二結合導線(例如，導線51、53(圖4)或導線55、57(圖5))之間的聯結件不觸碰第一結合導線之末端被接合至之接觸件。必要時，可使用甚至更大數目個結合導線，其以此方式而以冶金方式接合至其他結合導線，以便提供用於使電流流動於一接觸件對之間的並聯電路徑。In another variation of the embodiments described above, a plurality of bond wires can be formed and joined to existing bond wires (which have been joined to the contacts at their ends) to form three or three between the contacts Above parallel path. In this embodiment, the third bonding wire can be configured such that the third bonding wire and the first or second bonding wire (eg, wire 51, 53 (FIG. 4) or wire 55, 57 (FIG. 5)) The inter-connecting member does not touch the contact to which the end of the first bonding wire is bonded. If desired, an even larger number of bond wires can be used that are metallurgically bonded to other bond wires in this manner to provide a parallel electrical path for current flow between a pair of contacts.

圖6說明代替結合導線而使用結合帶狀物41的電連接件，其中結合帶狀物41具有以冶金方式接合至接觸件中之一者(例如，接觸件20)的第一末端43。結合導線41具有以冶金方式接合至另一接觸件40之中間部分45，且具有接合至結合帶狀物之第一末端43的第二末端47。在結合帶狀物之第一末端43與第二末端47之間的聯結件可使得第二末端47不觸碰該第一末端被接合至之接觸件20。或者，在一變化(未圖示)中，第二末端47可觸碰第一末端43被接合至之同一接觸件20或直接與第一末端43被接合至之同一接觸件20接合。接觸件中之一者(例如，接觸件20、40中之一者)可為基板接觸件，且接觸件20、40中之另一者可為晶片接觸件。或者，接觸件20、40兩者皆可為曝露於基板之表面處的基板接觸件，或接觸件20、40兩者皆可為曝露於晶片之表面處的晶片接觸件。6 illustrates an electrical connector that uses a bond strip 41 in place of a bond wire, wherein the bond strip 41 has a first end 43 that is metallurgically bonded to one of the contacts (eg, contact 20). The bond wire 41 has a metallurgical joint to the intermediate portion 45 of the other contact 40 and has a second end 47 that is joined to the first end 43 of the bond strip. The link between the first end 43 of the bond strip and the second end 47 can be such that the second end 47 does not touch the contact 20 to which the first end is joined. Alternatively, in a variation (not shown), the second end 47 can contact the same contact 20 to which the first end 43 is joined or directly engage the same contact 20 to which the first end 43 is joined. One of the contacts (eg, one of the contacts 20, 40) can be a substrate contact, and the other of the contacts 20, 40 can be a wafer contact. Alternatively, both contacts 20, 40 can be substrate contacts exposed at the surface of the substrate, or both contacts 20, 40 can be wafer contacts exposed at the surface of the wafer.

微電子總成10(圖1)亦可包括第一囊封物80及第二囊封物82。第一囊封物80覆蓋電連接件70及介電元件30之第一孔隙33。第二囊封物82覆蓋電連接件70及介電元件30之第二孔隙39。The microelectronic assembly 10 (FIG. 1) can also include a first encapsulant 80 and a second encapsulant 82. The first encapsulant 80 covers the electrical connector 70 and the first aperture 33 of the dielectric component 30. The second encapsulant 82 covers the electrical connector 70 and the second aperture 39 of the dielectric component 30.

微電子總成10可進一步包括複數個接合單元，諸如，焊球81。焊球81附接至端子36且因此電互連至元件40、引線50及70以及接觸件20及26中至少一些。The microelectronic assembly 10 can further include a plurality of bonding units, such as solder balls 81. Solder balls 81 are attached to terminal 36 and are thus electrically interconnected to element 40, leads 50 and 70, and at least some of contacts 20 and 26.

圖7展示上文所描述之實施例之變化。在此變化中，電連接器170包括將第一微電子元件112之接觸件120電連接至對應導電元件140的第一導線結合件172，及使介電元件130之兩個導電元件140電互連的第二導線結合件174。第二導線結合件174橫越介電元件130之第一孔隙133而延伸。第二導線結合件174可經定位成與第一導線結合件172之長度之實質部分相隔均一距離。導線結合件172、174中之一者可連接至用以將信號攜載至晶片上或攜載離開晶片或其兩者的微電子元件及基板之接觸件。導線結合件172、174中之另一者可連接至用以連接至諸如接地或電力供應器或其他參考電位之參考電位的微電子元件及基板之接觸件。在一實施例中，長度之實質部分可為至少一毫米之長度或可為此導線結合件172之總長度的25%。相似地，電連接件150可包括將第二微電子元件114之接觸件126電連接至對應導電元件140的第一導線結合件152，及使介電元件130之兩個導電元件140互連的第二導線結合件154。第二導線結合件154橫越介電元件130之第二孔隙139而延伸。第二導線結合件154可經定位成與第一導線結合件152之部分相隔均一距離，亦即，至少一毫米之長度或更大，或個別導線結合件152之總長度的至少25%。根據此實施例之多結合導線結構可輔助達成用於藉由導線結合件172、152攜載之信號的所要受控制阻抗。因此，舉例而言，在一實例中，可使用諸如25微米之標準直徑的導線來形成導線結合件172、174，且其中導線結合件172之實質部分與導線結合件174間隔達自30微米至70微米之距離且平行於導線結合件174，以達成約50歐姆之特性阻抗。在一特定實施例中，導線結合件172、174可在包括相對於基板之至少一垂直分量的方向上間隔開。亦即，在導線結合件172、174之此等實質上平行部分之間的分離係至少部分地在垂直於微電子元件112之前表面的垂直方向158上，使得導線結合件172、174中任一者相比於導線結合件172、174中之另一者而與微電子元件112之彼前表面相隔較大高度。可以相似於導線結合件172、174之方式來配置提供於鄰近於微電子元件114之孔隙139處的導線結合件152、154。Figure 7 shows a variation of the embodiment described above. In this variation, the electrical connector 170 includes a first wire bond 172 that electrically connects the contact 120 of the first microelectronic component 112 to the corresponding conductive component 140, and electrically interconnects the two conductive components 140 of the dielectric component 130. A second wire bond 174 is attached. The second wire bond 174 extends across the first aperture 133 of the dielectric component 130. The second wire bond 174 can be positioned at a uniform distance from a substantial portion of the length of the first wire bond 172. One of the wire bonds 172, 174 can be coupled to a contact for carrying a signal onto or carrying a microelectronic component and substrate away from the wafer or both. The other of the wire bonds 172, 174 can be connected to contacts of a microelectronic component and substrate for connection to a reference potential such as a ground or power supply or other reference potential. In an embodiment, the substantial portion of the length may be at least one millimeter in length or may be 25% of the total length of the wire bond 172. Similarly, the electrical connector 150 can include a first wire bond 152 that electrically connects the contact 126 of the second microelectronic element 114 to the corresponding conductive element 140, and interconnects the two conductive elements 140 of the dielectric element 130. The second wire bond 154. The second wire bond 154 extends across the second aperture 139 of the dielectric component 130. The second wire bond 154 can be positioned at a uniform distance from the portion of the first wire bond 152, that is, at least one millimeter or more, or at least 25% of the total length of the individual wire bonds 152. The multiple bond wire structure in accordance with this embodiment can assist in achieving the desired controlled impedance for signals carried by the wire bonds 172, 152. Thus, for example, in one example, wires of standard diameters such as 25 microns can be used to form wire bonds 172, 174, and wherein substantial portions of wire bonds 172 are spaced from wire bonds 174 from 30 microns to A distance of 70 microns and parallel to the wire bond 174 to achieve a characteristic impedance of about 50 ohms. In a particular embodiment, the wire bonds 172, 174 can be spaced apart in a direction that includes at least one perpendicular component relative to the substrate. That is, the separation between the substantially parallel portions of the wire bonds 172, 174 is at least partially perpendicular to the surface 158 of the front surface of the microelectronic element 112 such that either of the wire bonds 172, 174 The other surface of the microelectronic component 112 is separated from the front surface of the microelectronic component 112 by a greater height than the other of the wire bonds 172, 174. Wire bonds 152, 154 provided adjacent apertures 139 of microelectronic element 114 can be configured similar to wire bonds 172, 174.

圖8展示圖7所描繪之實施例的變化。在此變化中，介電元件230包括與第一微電子元件212之接觸件220及第二微電子元件214之接觸件226兩者實質上對準的單一孔隙233，使得連接至接觸件220、226或微電子元件212、214兩者之導線結合件252、254延伸通過同一孔隙233。舉例而言，此變化包括第一導線結合件252，第一導線結合件252將第一微電子元件212之接觸件220超過孔隙233之第一邊緣235而連接至介電元件230之導電元件240。第二導線結合件254亦可將第二微電子元件214之接觸件226超過孔隙233之第一邊緣235而連接至導電元件240。儘管未圖示，但其他導線結合件可將第一微電子元件及第二微電子元件之各別接觸件220及接觸件226與超過孔隙之第二邊緣237而安置的介電元件之接觸件260電連接。囊封物280覆蓋及保護電連接件250及整個孔隙233。Figure 8 shows a variation of the embodiment depicted in Figure 7. In this variation, the dielectric component 230 includes a single aperture 233 that is substantially aligned with both the contact 220 of the first microelectronic component 212 and the contact 226 of the second microelectronic component 214 such that it is coupled to the contact 220, The wire bonds 252, 254 of both 226 or microelectronic elements 212, 214 extend through the same aperture 233. For example, the variation includes a first wire bond 252 that connects the contact 220 of the first microelectronic component 212 beyond the first edge 235 of the aperture 233 to the conductive component 240 of the dielectric component 230 . The second wire bond 254 can also connect the contact 226 of the second microelectronic element 214 beyond the first edge 235 of the aperture 233 to the conductive element 240. Although not shown, other wire bonds may contact the respective contact members 220 and contacts 226 of the first and second microelectronic components with the dielectric member disposed beyond the second edge 237 of the aperture. 260 electrical connections. The encapsulant 280 covers and protects the electrical connector 250 and the entire aperture 233.

圖9展示圖8所描繪之實施例的變化。在此變化中，介電元件330具有與第一微電子元件312之接觸件320實質上對準的第一孔隙333，及與第二微電子元件314之接觸件326實質上對準的第二孔隙339。囊封物380覆蓋介電元件330之第一孔隙333及第二孔隙339兩者。參考導線結合件352可將鄰近於第一孔隙333之導電元件340與鄰近於第二孔隙339之另一導電元件340電連接。導電元件340中之一或多者可經進一步調適用於經由總成310之一或多個端子336而與諸如接地或電力輸入之參考電位互連。參考導線結合件352可橫越第一孔隙333及第二孔隙339兩者而延伸。在圖9所示之實例中，電連接件350可進一步包括第一信號導線結合件354及第二信號導線結合件356。第一信號導線結合件354延伸通過第一孔隙333且將第一微電子元件312之接觸件320電連接至鄰近於第一孔隙333之另一導電元件340。第二信號導線結合件356延伸通過第二孔隙339且將第二微電子元件314之接觸件326電連接至鄰近於第二孔隙339的介電元件330之另一導電元件340。如上文所描述，參考導線結合件可與各別導線結合件354、356之至少實質部分間隔，以便准許達成所要特性阻抗。囊封物380覆蓋及保護參考結合導線352、第一信號導線結合件354、第二導線結合件256以及第一孔隙333及第二孔隙339。Figure 9 shows a variation of the embodiment depicted in Figure 8. In this variation, dielectric element 330 has a first aperture 333 that is substantially aligned with contact 320 of first microelectronic element 312 and a second that is substantially aligned with contact 326 of second microelectronic element 314. Pore 339. The encapsulant 380 covers both the first aperture 333 and the second aperture 339 of the dielectric component 330. The reference wire bond 352 can electrically connect the conductive element 340 adjacent the first aperture 333 with another conductive element 340 adjacent the second aperture 339. One or more of the conductive elements 340 can be further adapted to be interconnected via a one or more terminals 336 of the assembly 310 with a reference potential such as a ground or power input. The reference wire bond 352 can extend across both the first aperture 333 and the second aperture 339. In the example shown in FIG. 9, the electrical connector 350 can further include a first signal wire bond 354 and a second signal wire bond 356. The first signal wire bond 354 extends through the first aperture 333 and electrically connects the contact 320 of the first microelectronic element 312 to another conductive element 340 adjacent the first aperture 333. The second signal wire bond 356 extends through the second aperture 339 and electrically connects the contact 326 of the second microelectronic element 314 to another conductive element 340 of the dielectric element 330 adjacent the second aperture 339. As described above, the reference wire bond can be spaced from at least a substantial portion of the respective wire bonds 354, 356 to permit the desired characteristic impedance to be achieved. The encapsulant 380 covers and protects the reference bond wire 352, the first signal wire bond 354, the second wire bond 256, and the first aperture 333 and the second aperture 339.

一或多個參考導線結合件352可在介電元件之第一末端部分362與第二末端部分364之間輔助維持穩定接地或電力供應電壓。在其變化中，一或多個參考導線結合件368可電連接介電元件330之中心部分364及第二部分366上之各別接觸件。One or more reference wire bonds 352 can assist in maintaining a stable ground or power supply voltage between the first end portion 362 and the second end portion 364 of the dielectric element. In its variations, one or more of the reference wire bonds 368 can electrically connect the central portion 364 of the dielectric component 330 and the respective contacts on the second portion 366.

圖10為圖1所描繪之實施例之變化。在此變化中，介電元件430包括與第二微電子元件414之接觸件426及第一微電子元件412之邊緣429實質上對準的單一孔隙433。第一微電子元件412包括重新分佈層443，重新分佈層443將中心區域中之各別接觸件420與經定位成鄰近於邊緣429之導電元件448(例如，重新分佈焊墊)連接。Figure 10 is a variation of the embodiment depicted in Figure 1. In this variation, dielectric component 430 includes a single aperture 433 that is substantially aligned with contact 426 of second microelectronic component 414 and edge 429 of first microelectronic component 412. The first microelectronic element 412 includes a redistribution layer 443 that connects the respective contacts 420 in the central region with conductive elements 448 (eg, redistribution pads) positioned adjacent to the edges 429.

舉例而言，複數個導電跡線或重新分佈導體442可(諸如)藉由電鍍至表面416上、蝕刻結合至或層壓至表面416之金屬層或電鍍步驟與蝕刻步驟之組合而形成於第一微電子元件412之前表面416上。此等重新分佈導體442可沿著前表面416而自接觸件420延伸至曝露於鄰近於邊緣429之前表面處之各別重新分佈焊墊或導電元件448。此等重新分佈焊墊或導電元件448可與孔隙433對準。For example, a plurality of conductive traces or redistribution conductors 442 can be formed, for example, by electroplating onto surface 416, etching a metal layer bonded or laminated to surface 416, or a combination of a plating step and an etching step. A microelectronic component 412 is on the front surface 416. These redistribution conductors 442 can extend from the contact 420 along the front surface 416 to respective redistribution pads or conductive elements 448 that are exposed at a surface adjacent the edge 429. These redistribution pads or conductive elements 448 can be aligned with the apertures 433.

如在圖10中所見，第一導線結合件452將鄰近於第一微電子元件412之邊緣429的元件448與介電元件430之導電元件440連接。第一導線結合件452延伸通過孔隙433。第二導線結合件454將第二微電子元件414之接觸件426與導電元件440連接。第二導線結合件454延伸通過介電元件430之孔隙433。第二微電子元件414之一或多個接觸件426可與介電元件430中之孔隙433對準。As seen in FIG. 10, the first wire bond 452 connects the component 448 adjacent the edge 429 of the first microelectronic component 412 with the conductive component 440 of the dielectric component 430. The first wire bond 452 extends through the aperture 433. The second wire bond 454 connects the contact 426 of the second microelectronic element 414 with the conductive element 440. The second wire bond 454 extends through the aperture 433 of the dielectric element 430. One or more of the contacts 426 of the second microelectronic element 414 can be aligned with the apertures 433 in the dielectric element 430.

圖11描繪包括至少兩個堆疊且電互連之微電子總成900之配置1000。微電子總成900可為上文所描述之總成中任一者。接合單元981(例如，焊球)可曝露於微電子總成中至少一者之表面處以用於將該配置電連接至(例如)電路面板。兩個微電子總成900係經由任何合適電連接器而彼此電連接。舉例而言，該等總成可經由焊料柱(solder column)990而電互連，焊料柱990接合至各別微電子元件之介電元件930A、930B上之焊墊(未圖示)。在亦展示於圖11中之特定實施例中，可使用導電支柱992及焊料994以使兩個微電子總成900A及900B電互連。支柱992可自第一總成或自第二總成朝向另一者延伸，或提供於兩個總成上之支柱可朝向彼此延伸，且在一些狀況下，可為連接兩個總成之同一垂直柱之部分。FIG. 11 depicts a configuration 1000 including at least two stacked and electrically interconnected microelectronic assemblies 900. Microelectronic assembly 900 can be any of the assemblies described above. A bonding unit 981 (eg, a solder ball) can be exposed at a surface of at least one of the microelectronic assemblies for electrically connecting the configuration to, for example, a circuit panel. The two microelectronic assemblies 900 are electrically connected to each other via any suitable electrical connector. For example, the assemblies can be electrically interconnected via a solder column 990 that is bonded to pads (not shown) on dielectric elements 930A, 930B of the respective microelectronic components. In a particular embodiment, also shown in FIG. 11, conductive posts 992 and solder 994 can be used to electrically interconnect the two microelectronic assemblies 900A and 900B. The struts 992 can extend from the first assembly or from the second assembly toward the other, or the struts provided on the two assemblies can extend toward each other, and in some cases, can be the same to connect the two assemblies Part of the vertical column.

圖12描繪包括垂直地堆疊且與至少一微電子總成900B電互連之第三微電子元件940的配置1010，至少一微電子總成900B具有第一微電子元件912及第二微電子元件914。微電子總成900B可為上文所描述之總成中任一者。配置1010相似於圖11所示之配置1000，惟微電子總成900B係與微電子元件940堆疊除外。接合單元941(例如，焊球)可曝露於第三微電子元件940之表面處以用於將該第三微電子元件電連接至(例如)介電元件930A。第三微電子元件940可經由諸如焊料柱990及/或導電支柱992及焊料994之任何合適電連接器而與微電子總成900B電連接。12 depicts a configuration 1010 including a third microelectronic component 940 that is vertically stacked and electrically interconnected with at least one microelectronic assembly 900B, the at least one microelectronic assembly 900B having a first microelectronic component 912 and a second microelectronic component 914. Microelectronic assembly 900B can be any of the assemblies described above. Configuration 1010 is similar to configuration 1000 shown in FIG. 11, except that microelectronic assembly 900B is stacked with microelectronic element 940. Bonding unit 941 (eg, solder balls) may be exposed at the surface of third microelectronic element 940 for electrically connecting the third microelectronic element to, for example, dielectric element 930A. The third microelectronic element 940 can be electrically coupled to the microelectronic assembly 900B via any suitable electrical connector, such as solder post 990 and/or conductive post 992 and solder 994.

第三微電子元件940可具有不同於至少一微電子總成900B之功能的功能。舉例而言，第一微電子元件912及第二微電子元件914中之一者或其兩者可各別包括一記憶體儲存元件，且第三微電子元件940可具有一邏輯功能。舉例而言，第三微電子元件可在其中包括作為主要或實質功能元件之邏輯功能單元。在一特定實例中，邏輯功能元件可為處理器，處理器可為通用或專用處理器。舉例而言，處理器可尤其包括可以各種方式被稱作微處理器、中央處理單元、共同處理器或諸如圖形處理器之專用處理器的處理器。在一實例中，當第三微電子元件940包括處理器時，該第三微電子元件可經配置以連同微電子總成900B內之微電子元件中之一或多者中的至少一記憶體儲存元件而操作。以此方式，處理器可經由輸送於處理器與微電子總成900B中之記憶體儲存元件之間的信號而將資料儲存至記憶體儲存元件。舉例而言，可經由上文所描述之電連接件而將信號自微電子元件940內之處理器輸送至總成900B內之記憶體儲存元件，該等電連接件包括焊料凸塊941，及導電元件，諸如，沿著介電元件930A而延伸至與其連接之焊料柱990或支柱992之引線(未圖示)。自焊料柱990或支柱992，可沿著微電子總成900B之引線而將信號輸送至第一微電子元件912或第二微電子元件914中至少一者。The third microelectronic element 940 can have a different function than the functionality of the at least one microelectronic assembly 900B. For example, one or both of the first microelectronic element 912 and the second microelectronic element 914 can each include a memory storage element, and the third microelectronic element 940 can have a logic function. For example, a third microelectronic element can include therein a logical functional unit as a primary or substantial functional element. In a particular example, the logical functional element can be a processor and the processor can be a general purpose or special purpose processor. For example, a processor may include, in particular, a processor that can be referred to as a microprocessor, a central processing unit, a common processor, or a special purpose processor such as a graphics processor in various ways. In an example, when the third microelectronic element 940 includes a processor, the third microelectronic element can be configured to include at least one of one or more of the microelectronic elements within the microelectronic assembly 900B. Operate the components and operate. In this manner, the processor can store the data to the memory storage element via a signal transmitted between the processor and the memory storage element in the microelectronic assembly 900B. For example, signals may be transferred from a processor within microelectronic element 940 to a memory storage element within assembly 900B via electrical connectors as described above, including electrical bumps 941, and A conductive element, such as a lead (not shown) that extends along dielectric element 930A to solder post 990 or post 992 that is coupled thereto. From the solder post 990 or post 992, a signal can be routed along at least one of the first microelectronic element 912 or the second microelectronic element 914 along the leads of the microelectronic assembly 900B.

現參看圖13，根據本發明之一實施例的堆疊微電子總成500包括第一半字寬微電子元件501及第二半字寬微電子元件502。第一微電子元件501及第二微電子元件502可以相似於如上文所描述的圖1、圖7或圖11中任一者所示之堆疊組態的堆疊組態而配置，藉以，第二微電子元件之至少一部分上覆第一微電子元件，且兩個微電子元件皆上覆介電元件503。Referring now to Figure 13, a stacked microelectronic assembly 500 in accordance with an embodiment of the present invention includes a first halfword wide microelectronic component 501 and a second halfword wide microelectronic component 502. The first microelectronic element 501 and the second microelectronic element 502 can be configured similarly to the stacked configuration of the stacked configuration as shown in any of FIG. 1, FIG. 7, or FIG. 11 described above, whereby the second At least a portion of the microelectronic component overlies the first microelectronic component, and both microelectronic components overlying the dielectric component 503.

介電元件503包括與第一微電子元件501之前表面之接觸軸承區域實質上對準的第一孔隙511，藉此提供對曝露於第一孔隙511處之電接觸件521之接取。介電元件503進一步包括與第二微電子元件502之前表面之接觸軸承區域實質上對準的第二孔隙512，藉此提供對曝露於第二孔隙512處之電接觸件522之接取。如上文所描述(圖1)，接觸軸承區域可安置於每一微電子元件之中心區域中。如上文參看圖1至圖7所描述，孔隙511及512可經填充有囊封物。Dielectric element 503 includes a first aperture 511 that is substantially aligned with a contact bearing area of a front surface of first microelectronic element 501, thereby providing access to electrical contact 521 exposed at first aperture 511. Dielectric element 503 further includes a second aperture 512 that is substantially aligned with the contact bearing area of the front surface of second microelectronic element 502, thereby providing access to electrical contact 522 exposed at second aperture 512. As described above (Fig. 1), the contact bearing area can be placed in the central region of each microelectronic element. As described above with reference to Figures 1 through 7, the apertures 511 and 512 can be filled with an encapsulant.

介電元件503可具有曝露於其表面504處之導電元件531及533a，導電元件531及533a可(例如)藉由諸如導線結合件505、引線結合件或其他構件之引線部分而電耦接至第一微電子元件501之電接觸件521。介電元件503可進一步包括曝露於表面504處之導電元件532及533b，導電元件532及533b可(例如)藉由諸如導線結合件505、引線結合件或其他構件之引線部分而電耦接至第二微電子元件502之電接觸件522。在上文關於圖1至圖11所描述之實施例而描述之組態中任一者中，引線部分505可將電接觸件521耦接至導電元件531及533a且可將電接觸件522耦接至導電元件532及533b。Dielectric element 503 can have conductive elements 531 and 533a exposed at surface 504 thereof, which can be electrically coupled to, for example, by lead portions such as wire bonds 505, wire bonds, or other components. Electrical contact 521 of the first microelectronic element 501. Dielectric element 503 can further include conductive elements 532 and 533b exposed at surface 504, which can be electrically coupled to, for example, by lead portions such as wire bonds 505, wire bonds, or other components. Electrical contact 522 of second microelectronic element 502. In any of the configurations described above with respect to the embodiments described with respect to FIGS. 1-11, the lead portion 505 can couple the electrical contacts 521 to the conductive elements 531 and 533a and can couple the electrical contacts 522 Connected to conductive elements 532 and 533b.

介電元件503可進一步具有曝露於其表面504處之導電端子541、561及571，導電端子541、561及571上覆第一微電子元件501。此等端子可電耦接至第一微電子元件501之電接觸件521。端子541、561及571可以各別端子群組546、566及576而配置。可經由(例如)群組546中之端子541而在第一微電子元件501與電路面板702或其他部件(圖17)之間傳輸資料輸入/輸出信號。可經由群組566中之端子561而製造連接至一或多個電力供應電壓、參考電壓或其他參考電位(例如，接地)之電連接件。在一特定實例中，第一參考電位端子561可電連接至(例如)電路面板702或其他部件(圖17)上之第一參考電位信號，且第二參考電位端子561可電連接至電路面板或其他部件上之第二分離參考電位信號。可經由群組576中之端子571而傳輸在第一微電子元件501與外部裝置之間的位址信號。群組546、566或576中每一者中之端子541、561及571可僅電耦接至第一微電子元件501而不電耦接至第二微電子元件502，且此等端子中之一或多者可或者連接至兩個微電子元件。Dielectric element 503 can further have conductive terminals 541, 561, and 571 exposed at surface 504 thereof, and conductive terminals 541, 561, and 571 overlying first microelectronic element 501. The terminals can be electrically coupled to the electrical contacts 521 of the first microelectronic element 501. Terminals 541, 561, and 571 can be configured for respective terminal groups 546, 566, and 576. Data input/output signals may be transmitted between the first microelectronic element 501 and the circuit panel 702 or other component (FIG. 17) via, for example, the terminal 541 in the group 546. Electrical connections to one or more power supply voltages, reference voltages, or other reference potentials (eg, ground) may be fabricated via terminals 561 in group 566. In a particular example, the first reference potential terminal 561 can be electrically coupled to, for example, a first reference potential signal on the circuit panel 702 or other component (FIG. 17), and the second reference potential terminal 561 can be electrically coupled to the circuit panel. Or a second separate reference potential signal on the other component. The address signal between the first microelectronic element 501 and the external device can be transmitted via the terminal 571 in the group 576. The terminals 541, 561, and 571 in each of the groups 546, 566, or 576 may be electrically coupled only to the first microelectronic element 501 without being electrically coupled to the second microelectronic element 502, and among the terminals One or more may be connected to two microelectronic components.

介電元件503可進一步具有曝露於其表面504處之導電端子542、562及572，導電端子542、562及572上覆第二微電子元件502。此等端子可電耦接至第二微電子元件502之電接觸件522。端子542、562及572可以各別端子群組547、567及577而配置。可經由(例如)群組547中之端子542而在第二微電子元件502與電路面板702或其他部件(圖17)之間傳輸資料輸入/輸出信號。可經由群組567中之端子562而製造連接至一或多個電力供應電壓、參考電壓或其他參考電位(例如，接地)之電連接件。可經由群組577中之端子572而傳輸在第二微電子元件502與外部裝置之間的位址信號。群組547、567或577中每一者中之端子542、562及572可僅電耦接至第二微電子元件502而不電耦接至第一微電子元件501，且此等端子中之一或多者可或者連接至兩個微電子元件。Dielectric element 503 can further have conductive terminals 542, 562, and 572 exposed at surface 504 thereof, and conductive terminals 542, 562, and 572 overlying second microelectronic element 502. The terminals can be electrically coupled to the electrical contacts 522 of the second microelectronic element 502. Terminals 542, 562, and 572 can be configured for respective terminal groups 547, 567, and 577. The data input/output signals can be transmitted between the second microelectronic element 502 and the circuit panel 702 or other component (FIG. 17) via, for example, the terminal 542 in the group 547. Electrical connections to one or more power supply voltages, reference voltages, or other reference potentials (eg, ground) may be fabricated via terminals 562 in group 567. The address signal between the second microelectronic element 502 and the external device can be transmitted via the terminal 572 in the group 577. The terminals 542, 562, and 572 in each of the groups 547, 567, or 577 may be electrically coupled only to the second microelectronic element 502 without being electrically coupled to the first microelectronic element 501, and among the terminals One or more may be connected to two microelectronic components.

介電元件503可具有曝露於其表面504處且上覆第一微電子元件及第二微電子元件之至少部分的導電元件或端子553、563及573，但第一微電子元件可安置於該介電元件與第二微電子元件之間。端子553、563及573中每一者可電耦接至第一微電子元件501之電接觸件521及第二微電子元件502之電接觸件522兩者。端子553、563及573可以各別端子群組558、568及578而配置。舉例而言，可經由群組558中之特定端子553而在外部裝置與微電子元件501及502之間傳輸共用時脈信號、共用資料選通信號或其他共用信號。可經由群組568中之端子563而製造連接至一或多個電力供應電壓、參考電壓或其他參考電位(例如，接地)之共用電連接件。可經由群組578中之端子573而傳輸在第一微電子元件及第二微電子元件與外部裝置之間的共用位址信號。群組558、568或578中每一者中之端子553、563及573可電連接至第一微電子元件501及第二微電子元件502中任一者或其兩者。Dielectric element 503 can have conductive elements or terminals 553, 563, and 573 exposed at its surface 504 and overlying at least a portion of the first microelectronic element and the second microelectronic element, but the first microelectronic element can be disposed thereon Between the dielectric element and the second microelectronic element. Each of the terminals 553, 563, and 573 can be electrically coupled to both the electrical contact 521 of the first microelectronic component 501 and the electrical contact 522 of the second microelectronic component 502. Terminals 553, 563, and 573 can be configured for respective terminal groups 558, 568, and 578. For example, a shared clock signal, a shared data strobe signal, or other common signal can be transmitted between the external device and the microelectronic components 501 and 502 via a particular terminal 553 in the group 558. A common electrical connection to one or more power supply voltages, reference voltages, or other reference potentials (eg, ground) may be fabricated via terminals 563 in group 568. The shared address signal between the first microelectronic component and the second microelectronic component and the external device can be transmitted via terminal 573 in group 578. Terminals 553, 563, and 573 in each of groups 558, 568, or 578 can be electrically coupled to either or both of first microelectronic element 501 and second microelectronic element 502.

儘管在圖13中將端子群組546、547、558、566、567、568、576、577及578中每一者展示為包含四個鄰近各別端子541、542、553、561、562、563、571、572及573，但在其他實施例中，每一端子群組可包含以任何幾何組態而配置之任何數目個端子，且包含任何特定群組之端子不需要彼此鄰近。此外，兩個或兩個以上群組中之端子可重疊或彼此穿插。舉例而言，群組546中之端子541可與群組566中之端子561穿插。Although each of the terminal groups 546, 547, 558, 566, 567, 568, 576, 577, and 578 is shown in FIG. 13 as including four adjacent respective terminals 541, 542, 553, 561, 562, 563 571, 572, and 573, but in other embodiments, each terminal group can include any number of terminals configured in any geometric configuration, and the terminals including any particular group need not be adjacent to each other. Furthermore, the terminals in two or more groups may overlap or be interspersed with each other. For example, terminal 541 in group 546 can be interspersed with terminal 561 in group 566.

在一較佳實施例中，定位於第一孔隙511與第二孔隙512之間的端子553、563及573為電耦接至微電子元件501及502兩者之共用端子。然而，視堆疊微電子總成500之所要特性而定，端子553、563及573中之一或多者可僅電耦接至微電子元件501或502中之單一者。相似地，在一較佳實施例中，定位至第一孔隙511之左側的端子541、561及571僅電耦接至第一微電子元件501，且定位至第二孔隙512之右側的端子542、562及572僅電耦接至第二微電子元件502。然而，如在如圖17進一步所描述之總成或系統中，當進一步連接至電路面板或其他部件時，端子561、562、571及572中之一或多者可(例如)經由電路面板702或其他部件(圖17)中之電連接件而電耦接至微電子元件501及502兩者。In a preferred embodiment, terminals 553, 563, and 573 positioned between first aperture 511 and second aperture 512 are common terminals that are electrically coupled to both microelectronic components 501 and 502. However, depending on the desired characteristics of the stacked microelectronic assembly 500, one or more of the terminals 553, 563, and 573 can be electrically coupled only to a single one of the microelectronic elements 501 or 502. Similarly, in a preferred embodiment, the terminals 541, 561, and 571 positioned to the left of the first aperture 511 are only electrically coupled to the first microelectronic element 501 and are positioned to the terminal 542 on the right side of the second aperture 512. 562 and 572 are only electrically coupled to the second microelectronic element 502. However, as in the assembly or system as further described in FIG. 17, one or more of the terminals 561, 562, 571, and 572 may, for example, be via the circuit panel 702 when further connected to a circuit panel or other component. Or electrical connectors in other components (FIG. 17) are electrically coupled to both microelectronic components 501 and 502.

介電元件503可進一步具有在其表面504下方或安置於第二表面34(圖1)上或曝露於第二表面34處(圖1)之接地平面或電力平面509。此平面509可下伏位址信號端子571、572及573中之一或多者。此平面509可縮減傳遞通過端子571、572及573之信號中之雜訊，及/或可允許堆疊微電子總成500滿足一或多個適用標準(例如，JEDEC標準)。儘管在圖13中將平面509展示為橫越整個介電元件503而延伸之單一元件，但在其他實施例中，平面509可為離散接地平面或電力平面片段。舉例而言，平面509可包括下伏端子群組576、577及578中每一者之離散平面片段，其中平面片段之間的間隙係在孔隙511及512之部位處。儘管將堆疊微電子總成500展示為具有接地平面或電力平面509，但此接地平面或電力平面係可選的，且在一特定實施例中，可自該堆疊微電子總成省略此接地平面或電力平面。The dielectric element 503 can further have a ground plane or power plane 509 below its surface 504 or on the second surface 34 (FIG. 1) or exposed to the second surface 34 (FIG. 1). This plane 509 can underlie one or more of the address signal terminals 571, 572, and 573. This plane 509 can reduce noise in the signals transmitted through terminals 571, 572, and 573, and/or can allow stacked microelectronic assembly 500 to meet one or more applicable standards (eg, the JEDEC standard). Although plane 509 is shown in FIG. 13 as a single element that extends across the entire dielectric element 503, in other embodiments, plane 509 can be a discrete ground plane or power plane segment. For example, plane 509 can include discrete planar segments of each of underlying terminal groups 576, 577, and 578, with gaps between planar segments being at locations of apertures 511 and 512. Although the stacked microelectronic assembly 500 is shown as having a ground plane or power plane 509, this ground plane or power plane is optional, and in a particular embodiment, the ground plane can be omitted from the stacked microelectronic assembly Or power plane.

堆疊微電子總成500(藉以，第一微電子元件501或第二微電子元件502上覆該第一微電子元件或該第二微電子元件中之另一者之至少一部分)之一可能益處係提供將介電元件503之表面504處之特定端子(例如，端子541)電連接至曝露於特定微電子元件(例如，第一微電子元件501)之前表面處之特定電接觸件(例如，電接觸件521)的相對短跡線506。在諸如跡線506及507之鄰近跡線之間(特別是在具有高接觸密度及細微間距之微電子總成中)，寄生電容可相當大。在諸如堆疊微電子總成500(其中跡線相對短)之微電子總成中，可縮減寄生電容(特別是在諸如跡線506及507之鄰近跡線之間)。One of the benefits of stacking the microelectronic assembly 500 (by which the first microelectronic element 501 or the second microelectronic element 502 overlies at least a portion of the other of the first microelectronic element or the second microelectronic element) Providing electrically connecting a particular terminal (eg, terminal 541) at surface 504 of dielectric component 503 to a particular electrical contact exposed at a surface prior to a particular microelectronic component (eg, first microelectronic component 501) (eg, A relatively short trace 506 of electrical contact 521). The parasitic capacitance can be substantial between adjacent traces such as traces 506 and 507, particularly in microelectronic assemblies having high contact density and fine pitch. In a microelectronic assembly such as stacked microelectronic assembly 500 (where the traces are relatively short), the parasitic capacitance can be reduced (particularly between adjacent traces such as traces 506 and 507).

堆疊微電子總成500(藉以，第一微電子元件501或第二微電子元件502上覆該第一微電子元件或該第二微電子元件中之另一者之至少一部分)之另一可能益處係提供(例如)跡線506及508之相似長度，跡線506及508將介電元件503之表面504處之資料輸入/輸出信號端子(例如，各別端子541及542)與電接觸件531、532電連接，電接觸件531、532又與各別第一微電子元件及第二微電子元件之前表面處之各別電接觸件521及522電連接。在諸如可包括半字寬微電子元件501及502之堆疊微電子總成500的微電子總成中，具有相對相似長度之跡線506及508可允許使資料輸入/輸出信號在每一微電子元件與各別端子541及542之間的傳播延遲相對接近地匹配。此外，可提供(例如)跡線516及517之相似長度，跡線516及517將鄰近資料輸入/輸出信號端子542與各別電接觸件532電連接，電接觸件532又與各別電接觸件522電連接。Another possibility of stacking the microelectronic assembly 500 (by which the first microelectronic element 501 or the second microelectronic element 502 overlies at least a portion of the first microelectronic element or the other of the second microelectronic element) Benefits provide, for example, similar lengths of traces 506 and 508, and traces 506 and 508 will place data input/output signal terminals (eg, respective terminals 541 and 542) and electrical contacts at surface 504 of dielectric component 503. 531, 532 are electrically connected, and the electrical contacts 531, 532 are in turn electrically coupled to respective electrical contacts 521 and 522 at respective front surfaces of the respective first and second microelectronic components. In a microelectronic assembly such as stacked microelectronic assembly 500, which may include halfword wide microelectronic components 501 and 502, traces 506 and 508 having relatively similar lengths may allow data input/output signals at each microelectronic The propagation delay between the component and the respective terminals 541 and 542 is relatively closely matched. In addition, similar lengths can be provided, for example, to traces 516 and 517. Traces 516 and 517 electrically connect adjacent data input/output signal terminals 542 to respective electrical contacts 532, which in turn are in electrical contact with each other. The piece 522 is electrically connected.

堆疊微電子總成500(藉以，第一微電子元件501或第二微電子元件502上覆該第一微電子元件或該第二微電子元件中之另一者之至少一部分)之又一可能益處係提供跡線518及519之相似長度，跡線518及519將共用時脈信號端子553及/或共用資料選通信號端子553電連接至接觸件533a、533b，接觸件533a、533b又與各別微電子元件電連接。資料選通信號端子553或時脈信號端子553或其兩者可具有實質上相同負載及至各別微電子元件501及502之實質上相同電路徑長度，且至每一微電子元件之路徑長度可相對短。Yet another possibility of stacking the microelectronic assembly 500 (by which the first microelectronic element 501 or the second microelectronic element 502 overlies at least a portion of the first microelectronic element or the other of the second microelectronic elements) The benefit is to provide similar lengths of traces 518 and 519. Traces 518 and 519 electrically connect common clock signal terminal 553 and/or common data strobe signal terminal 553 to contacts 533a, 533b, and contacts 533a, 533b The individual microelectronic components are electrically connected. The data strobe signal terminal 553 or the clock signal terminal 553 or both may have substantially the same load and substantially the same electrical path length to the respective microelectronic elements 501 and 502, and the path length to each of the microelectronic elements may be Relatively short.

現參看圖14，根據本發明之一實施例的堆疊微電子總成600包括第一全字寬微電子元件601及第二全字寬微電子元件602。微電子總成600相似於圖13所示之堆疊微電子總成500，惟如下情形除外：微電子總成600可具有各自可連接至相同共用資料輸入/輸出信號端子之全字寬微電子元件，而非具有各自電連接至分離資料輸入/輸出信號端子之半字寬微電子元件。Referring now to Figure 14, a stacked microelectronic assembly 600 in accordance with an embodiment of the present invention includes a first full-width wide microelectronic component 601 and a second full-width wide microelectronic component 602. The microelectronic assembly 600 is similar to the stacked microelectronic assembly 500 shown in Figure 13, except that the microelectronic assembly 600 can have full width wide microelectronic components each connectable to the same common data input/output signal terminal. Instead of having a half-word width microelectronic component that is each electrically connected to a separate data input/output signal terminal.

第二微電子元件602之至少一部分上覆第一微電子元件601，且兩個微電子元件皆上覆介電元件603。介電元件603可具有曝露於其表面604處之導電端子651、661及671，導電端子651、661及671上覆第一微電子元件601。此等端子可電耦接至第一微電子元件601之電接觸件621。端子651、661及671可以各別端子群組656、666及676而配置。舉例而言，可經由群組656中之特定端子651而在外部裝置與第一微電子元件601之間傳輸時脈信號、資料選通信號或其他信號。可經由群組666中之端子661而製造連接至一或多個電力供應電壓、參考電壓或其他參考電位(例如，接地)之電連接件。可經由群組676中之端子671而傳輸在第一微電子元件601與外部裝置之間的位址信號。At least a portion of the second microelectronic element 602 overlies the first microelectronic element 601, and both of the microelectronic elements overlie the dielectric element 603. Dielectric element 603 can have conductive terminals 651, 661, and 671 exposed at surface 604 thereof, and conductive terminals 651, 661, and 671 overlying first microelectronic element 601. The terminals can be electrically coupled to the electrical contacts 621 of the first microelectronic component 601. Terminals 651, 661, and 671 can be configured for respective terminal groups 656, 666, and 676. For example, a clock signal, a data strobe signal, or other signal can be transmitted between the external device and the first microelectronic element 601 via a particular terminal 651 in the group 656. Electrical connections to one or more power supply voltages, reference voltages, or other reference potentials (eg, ground) may be fabricated via terminals 661 in group 666. The address signal between the first microelectronic element 601 and the external device can be transmitted via terminal 671 in group 676.

介電元件603可進一步具有曝露於其表面604處之導電元件或端子652、662及672，導電元件或端子652、662及672上覆第二微電子元件602。此等端子可電耦接至第二微電子元件602之電接觸件622。端子652、662及672可以各別端子群組657、667及677而配置。舉例而言，可經由群組657中之特定端子652而在外部裝置與第二微電子元件602之間傳輸時脈信號、資料選通信號或其他信號。可經由群組667中之端子662而製造連接至一或多個電力供應電壓、參考電壓或其他參考電位(例如，接地)之電連接件。可經由群組677中之端子672而傳輸在第二微電子元件602與外部裝置之間的位址信號。Dielectric element 603 can further have conductive elements or terminals 652, 662, and 672 exposed at surface 604 thereof, and conductive elements or terminals 652, 662, and 672 overlying second microelectronic element 602. The terminals can be electrically coupled to the electrical contacts 622 of the second microelectronic component 602. Terminals 652, 662, and 672 can be configured for respective terminal groups 657, 667, and 677. For example, a clock signal, a data strobe signal, or other signal can be transmitted between the external device and the second microelectronic element 602 via a particular terminal 652 in the group 657. Electrical connections to one or more power supply voltages, reference voltages, or other reference potentials (eg, ground) may be made via terminals 662 in group 667. The address signal between the second microelectronic element 602 and the external device can be transmitted via terminal 672 in group 677.

介電元件603可具有曝露於其表面604處且上覆第一微電子元件及第二微電子元件之至少部分的導電元件或端子643、653、663及673，但第一微電子元件可安置於該介電元件與第二微電子元件之間。端子643、653、663及673中之一些或全部可電耦接至第一微電子元件601之電接觸件621及第二微電子元件602之電接觸件622。端子643、653、663及673可以各別端子群組648、658、668及678而配置。可經由(例如)群組648中之端子643而在微電子元件601及602與電路面板702或其他部件(圖17)之間傳輸共用資料輸入/輸出信號。可經由群組658中之特定端子653而在外部裝置與微電子元件601及602之間傳輸共用時脈信號、共用資料選通信號或其他共用信號。可經由群組668中之端子663而製造連接至一或多個電力供應電壓、參考電壓或其他參考電位(例如，接地)之共用電連接件。可經由群組678中之端子673而傳輸在第一微電子元件及第二微電子元件與外部裝置之間的共用位址信號。Dielectric element 603 can have conductive elements or terminals 643, 653, 663, and 673 exposed at its surface 604 and overlying at least a portion of the first microelectronic element and the second microelectronic element, but the first microelectronic element can be disposed Between the dielectric component and the second microelectronic component. Some or all of the terminals 643, 653, 663, and 673 may be electrically coupled to the electrical contacts 621 of the first microelectronic component 601 and the electrical contacts 622 of the second microelectronic component 602. Terminals 643, 653, 663, and 673 can be configured for respective terminal groups 648, 658, 668 and 678. A common data input/output signal can be transmitted between microelectronic components 601 and 602 and circuit panel 702 or other components (FIG. 17) via, for example, terminal 643 in group 648. A common clock signal, a shared data strobe signal, or other common signal can be transmitted between the external device and the microelectronic components 601 and 602 via a particular terminal 653 in the group 658. A common electrical connection to one or more power supply voltages, reference voltages, or other reference potentials (eg, ground) may be fabricated via terminals 663 in group 668. The shared address signal between the first microelectronic component and the second microelectronic component and the external device can be transmitted via terminal 673 in group 678.

現參看圖15，堆疊微電子總成500'相似於圖13所示之堆疊微電子總成500，惟替代跡線佈線配置經展示為將第一微電子元件501之電接觸件521電耦接至以端子群組546而配置之導電端子541a及541b除外。圖15為在藉由圖13所示之參考數字14所指示之部位處圖13之部分的放大圖。在圖13中，將介電元件503之表面504處之端子541電耦接至各別電接觸件521的跡線506及507經展示為具有不等長度。圖15展示具有相等長度的將端子541a及541b電耦接至各別電接觸件521之替代引線。Referring now to Figure 15, stacked microelectronic assembly 500' is similar to stacked microelectronic assembly 500 shown in Figure 13, except that the alternate trace routing configuration is shown to electrically couple electrical contacts 521 of first microelectronic component 501. Except for the conductive terminals 541a and 541b arranged with the terminal group 546. Figure 15 is an enlarged view of a portion of Figure 13 at a portion indicated by reference numeral 14 shown in Figure 13. In FIG. 13, traces 506 and 507 that electrically couple terminals 541 at surface 504 of dielectric element 503 to respective electrical contacts 521 are shown as having unequal lengths. Figure 15 shows an alternative lead having equal lengths electrically coupling terminals 541a and 541b to respective electrical contacts 521.

介電層503'可為兩金屬層基板，藉以，可將跡線佈線於沿著介電層503'之表面504及沿著第二層(諸如，圖1所示之第二表面34)的兩個實質上平行平面中。此第二層或表面可下伏端子541a及541b，使得跡線506'及507'可延伸於端子541a之下而不直接接觸端子541a。The dielectric layer 503' can be a two metal layer substrate whereby the traces can be routed along the surface 504 of the dielectric layer 503' and along the second layer (such as the second surface 34 shown in FIG. 1). Two substantially parallel planes. This second layer or surface may underlie the terminals 541a and 541b such that the traces 506' and 507' may extend below the terminal 541a without directly contacting the terminal 541a.

跡線506'及507'可經由不同引線佈線替代例而電耦接至各別電接觸件521。在一特定實施例中，耦接至各別導線結合件505之導電元件531可通過可下伏導電元件531之導電介層孔而電連接至第二表面上之跡線506'及507'。在一實例中，跡線506'及507'可通過延伸於表面504與第二層(未圖示)之間的分離導電介層孔而電耦接至導電元件531。在另一實施例中，導電元件531可曝露於第二層(例如，第二表面34)處，且導線結合件505可直接延伸於導電元件531與各別電接觸件521之間。Traces 506' and 507' can be electrically coupled to respective electrical contacts 521 via different lead routing alternatives. In a particular embodiment, the conductive elements 531 coupled to the respective wire bonds 505 can be electrically connected to the traces 506' and 507' on the second surface through the conductive via holes of the underlying conductive elements 531. In one example, traces 506' and 507' can be electrically coupled to conductive element 531 by a separate conductive via extending between surface 504 and a second layer (not shown). In another embodiment, the conductive element 531 can be exposed at the second layer (eg, the second surface 34), and the wire bond 505 can extend directly between the conductive element 531 and the respective electrical contact 521.

如圖15所示，跡線506'可通過延伸於表面504與第二層之間的導電介層孔536且接著通過延伸於導電介層孔536與端子541a之間的跡線506"而電耦接至端子541a。跡線507'可通過延伸於表面504與第二層之間的導電介層孔537且接著通過延伸於導電介層孔537與端子541b之間的跡線507"而電耦接至端子541b。藉由在端子541a與端子541b之間中途形成導電介層孔536及537，使得跡線506'及507'可具有相等長度且跡線506"及507"可具有相等長度，可使在端子541a及541b與各別電接觸件521之間的總引線長度相同。As shown in FIG. 15, trace 506' can be electrically connected through a conductive via hole 536 extending between surface 504 and the second layer and then through trace 506 extending between conductive via hole 536 and terminal 541a. Coupled to terminal 541a, trace 507' can be electrically connected through conductive via hole 537 extending between surface 504 and the second layer and then through trace 507 extending between conductive via hole 537 and terminal 541b It is coupled to the terminal 541b. By forming conductive via holes 536 and 537 midway between terminal 541a and terminal 541b, traces 506' and 507' can be of equal length and traces 506" and 507" can have equal lengths, such that terminal 541a can be used. The total lead length between 541b and the respective electrical contacts 521 is the same.

圖16描繪模組700，模組700包括以一個單元而配置在一起之至少兩個微電子總成710，其具有用於將信號輸送至微電子總成710中每一者或自微電子總成710中每一者輸送信號之電介面720。該電介面可包括一或多個接觸件，該一或多個接觸件可用於輸送為其中之微電子元件中每一者所共有的信號或參考電位(例如，電力及接地)。微電子總成710可為上文所描述之總成中任一者。在一特定實例中，模組700可為雙排記憶體模組(「dual in-line memory module.DIMM」)或單排記憶體模組(「single in-line memory module,SIMM」)，該雙排記憶體模組(「DIMM」)或單排記憶體模組(「SIMM」)使其一或多個部分經定大小以用於***至一系統(諸如，可提供於主機板上)之其他連接器之對應槽中。在此DIMM或SIMM中，電介面可具有適於與此槽連接器內之複數個對應彈簧接觸件配合的接觸件730。此等彈簧接觸件可安置於每一槽之單一側或多個側上以與對應模組接觸件配合。各種其他模組及互連配置係可能的，其中一模組可具有未堆疊或堆疊(例如，圖11、圖12)微電子總成，或其可具有用於將電信號輸送至該模組或自該模組輸送電信號之並聯或串聯電介面，或並聯電介面與串聯電介面之組合。在模組700與另外系統介面之間的任何種類之電互連配置皆係由本發明所涵蓋。16 depicts a module 700 that includes at least two microelectronic assemblies 710 that are configured together in a unit for delivering signals to each of the microelectronic assemblies 710 or to a total of microelectronics. Each of the 710 transmits a signal interface 720. The interface can include one or more contacts that can be used to deliver a signal or reference potential (eg, power and ground) that is common to each of the microelectronic components therein. Microelectronic assembly 710 can be any of the assemblies described above. In a specific example, the module 700 can be a dual in-line memory module (DIMM) or a single in-line memory module (SIMM). A dual-row memory module ("DIMM") or a single-row memory module ("SIMM") has one or more portions sized for insertion into a system (such as available on a motherboard) In the corresponding slot of the other connectors. In this DIMM or SIMM, the interface may have contacts 730 adapted to mate with a plurality of corresponding spring contacts within the slot connector. The spring contacts can be disposed on a single side or sides of each slot to mate with corresponding module contacts. Various other modules and interconnect configurations are possible, one of which may have an unstacked or stacked (eg, FIG. 11, FIG. 12) microelectronic assembly, or it may have an electrical signal for delivery to the module Or a parallel or series interface of electrical signals from the module, or a combination of parallel dielectrics and series dielectrics. Any type of electrical interconnection configuration between module 700 and another system interface is encompassed by the present invention.

在前文所描述之微電子總成中任一者或全部中，在完成製作之後，第一微電子元件或第二微電子元件中之一或多者之後表面可至少部分地曝露於微電子總成之外部表面處。因此，在上文關於圖1所描述之總成中，第一微電子元件12之後表面18或第二微電子元件14之後表面24中之一者或其兩者可部分地或完全地曝露於已完成之總成中。後表面可部分地或完全地曝露，但一包覆成型物(overmold)或其他囊封或封裝結構可接觸微電子元件或經安置成鄰近於微電子元件。In any or all of the microelectronic assemblies described above, after completion of fabrication, one or more of the first microelectronic component or the second microelectronic component may be at least partially exposed to the surface of the microelectronics At the outer surface. Thus, in the assembly described above with respect to FIG. 1, one or both of the first microelectronic element 12 rear surface 18 or the second microelectronic element 14 rear surface 24 may be partially or completely exposed. In the completed assembly. The back surface may be partially or completely exposed, but an overmold or other encapsulation or encapsulation structure may contact the microelectronic element or be disposed adjacent to the microelectronic element.

在上文所描述之實施例中任一者中，微電子總成可包括由金屬、石墨或任何其他合適導熱材料製成之熱散播器。在一實施例中，熱散播器包括經安置成鄰近於第一微電子元件之金屬層。金屬層可曝露於第一微電子元件之後表面上。或者，熱散播器包括至少覆蓋第一微電子元件之後表面的包覆成型物或囊封物。In any of the embodiments described above, the microelectronic assembly can include a thermal spreader made of metal, graphite, or any other suitable thermally conductive material. In an embodiment, the thermal spreader includes a metal layer disposed adjacent to the first microelectronic element. The metal layer can be exposed on the surface behind the first microelectronic element. Alternatively, the heat spreader includes an overmold or encapsulant covering at least the surface behind the first microelectronic element.

如圖17所示，上文所描述之微電子總成可用於互異電子系統之建構中。舉例而言，根據本發明之一另外實施例的系統800包括如上文所描述之微電子總成806，連同其他電子部件808及810。在所描繪實例中，部件808為半導體晶片，而部件810為顯示螢幕，但可使用任何其他部件。當然，儘管圖17中出於說明清楚性起見而描繪僅兩個額外部件，但該系統可包括任何數目個此等部件。微電子總成806可為上文所描述之總成中任一者。在一另外變體中，可使用任何數目個此等微電子總成。As shown in Figure 17, the microelectronic assembly described above can be used in the construction of disparate electronic systems. For example, system 800 in accordance with another embodiment of the present invention includes microelectronic assembly 806 as described above, along with other electronic components 808 and 810. In the depicted example, component 808 is a semiconductor wafer and component 810 is a display screen, but any other components can be used. Of course, although only two additional components are depicted in FIG. 17 for clarity of illustration, the system can include any number of such components. Microelectronic assembly 806 can be any of the assemblies described above. In an additional variation, any number of such microelectronic assemblies can be used.

微電子總成806以及部件808及810安裝於共同外殼801(以虛線示意性地描繪)中，且在必要時彼此電互連以形成所要電路。在所示例示性系統中，該系統包括諸如可撓性印刷電路板之電路面板802，且該電路面板包括使部件彼此互連之眾多導體804，其中僅一個導體被描繪於圖17中。然而，此情形僅僅係例示性的；可使用用於製造電連接件之任何合適結構。Microelectronic assembly 806 and components 808 and 810 are mounted in a common housing 801 (depicted schematically in dashed lines) and are electrically interconnected with one another as necessary to form the desired circuitry. In the illustrated exemplary system, the system includes a circuit panel 802, such as a flexible printed circuit board, and includes a plurality of conductors 804 interconnecting components to one another, with only one conductor depicted in FIG. However, this situation is merely exemplary; any suitable structure for making electrical connectors can be used.

外殼801被描繪為可用於(例如)蜂巢式電話或個人數位助理中之類型的攜帶型外殼，且螢幕810曝露於該外殼之表面處。在結構806包括諸如成像晶片之感光元件的情況下，亦可提供透鏡811或其他光學裝置以用於將光路由至該結構。再次，圖17所示之簡化系統僅僅係例示性的；可使用上文所論述之結構來製造包括通常被視為固定結構之系統(諸如，桌上型電腦、路由器及其類似者)的其他系統。The housing 801 is depicted as a portable housing of the type that can be used, for example, in a cellular telephone or a personal digital assistant, and the screen 810 is exposed at the surface of the housing. Where structure 806 includes a photosensitive element such as an imaging wafer, lens 811 or other optical means may also be provided for routing light to the structure. Again, the simplified system illustrated in Figure 17 is merely exemplary; the structures discussed above can be used to fabricate other systems including systems that are generally considered to be fixed structures, such as desktop computers, routers, and the like. system.

儘管本文已參考特定實施例而描述本發明，但應理解，此等實施例僅僅說明本發明之原理及應用。因此，應理解，可對說明性實施例進行眾多修改，且可在不脫離如藉由附加申請專利範圍所界定的本發明之精神及範疇的情況下設計其他配置。Although the present invention has been described herein with reference to the specific embodiments thereof, it is understood that these embodiments are merely illustrative of the principles and applications of the invention. Therefore, it is to be understood that various modifications may be made to the illustrative embodiments, and other configurations may be devised without departing from the spirit and scope of the invention as defined by the appended claims.

應瞭解，可以不同於初始請求項中所呈現之方式的方式來組合各種附屬請求項及在各種附屬請求項中所闡述之特徵。亦應瞭解，連同個別實施例所描述之特徵可與所描述實施例中之其他者共用。It will be appreciated that various accessory request terms and features set forth in the various accessory claims can be combined in a manner different from the manner presented in the initial claim. It should also be appreciated that features described in connection with the various embodiments can be shared with others of the described embodiments.

工業適用性Industrial applicability

本發明享有廣泛的工業適用性，包括(但不限於)微電子總成及製作微電子總成之方法。The present invention enjoys a wide range of industrial applicability including, but not limited to, microelectronic assemblies and methods of making microelectronic assemblies.

10．．．堆疊微電子總成10. . . Stacked microelectronic assembly

12．．．第一微電子元件12. . . First microelectronic component

13．．．中心區域13. . . Central region

14．．．第二微電子元件14. . . Second microelectronic component

15．．．第一末端區域15. . . First end region

16．．．前表面/第一表面16. . . Front surface / first surface

17．．．第二末端區域17. . . Second end region

18．．．後表面18. . . Back surface

19．．．中心區域19. . . Central region

20．．．電接觸件/第一接觸件/晶片接觸件20. . . Electrical contact / first contact / wafer contact

21．．．第一末端區域twenty one. . . First end region

22．．．前表面/第一表面twenty two. . . Front surface / first surface

23．．．第二末端區域twenty three. . . Second end region

24．．．後表面twenty four. . . Back surface

26．．．電接觸件26. . . Electrical contact

27．．．第一邊緣27. . . First edge

29．．．第二邊緣29. . . Second edge

30．．．介電元件/介電材料30. . . Dielectric element / dielectric material

31．．．間隔層31. . . Spacer

32．．．第一表面32. . . First surface

33．．．第一孔隙33. . . First pore

34．．．第二表面34. . . Second surface

35．．．第一邊緣35. . . First edge

36．．．導電元件或端子36. . . Conductive component or terminal

37．．．第二邊緣37. . . Second edge

39．．．第二孔隙39. . . Second pore

40．．．導電元件/第二接觸件40. . . Conductive element / second contact

41．．．結合帶狀物/結合導線41. . . Bonded ribbon/bonded wire

42．．．導電跡線42. . . Conductive trace

43．．．第一末端43. . . First end

45．．．中間部分45. . . Middle part

47．．．第二末端47. . . Second end

50．．．電連接件或引線50. . . Electrical connector or lead

51．．．導線51. . . wire

51A．．．球51A. . . ball

51B．．．第二末端51B. . . Second end

52．．．導線結合件/第一結合導線/雙導線連接件52. . . Wire bond / first bond wire / double wire connector

52A．．．末端/雙導線結合連接件52A. . . End/double wire joint connector

53．．．導線53. . . wire

53A．．．球53A. . . ball

53B．．．第二末端53B. . . Second end

54．．．導線結合件/雙導線連接件54. . . Wire bond / double wire connector

54A．．．末端/雙導線結合連接件54A. . . End/double wire joint connector

55．．．導線55. . . wire

55A．．．球末端55A. . . Ball end

55B．．．導線末端55B. . . Wire end

57．．．導線57. . . wire

57A．．．球末端57A. . . Ball end

57B．．．導線末端57B. . . Wire end

60．．．間隔層60. . . Spacer

70．．．電連接件或引線70. . . Electrical connector or lead

72．．．導線結合件/雙導線連接件72. . . Wire bond / double wire connector

72A．．．雙導線結合連接件72A. . . Double wire joint

74．．．導線結合件/雙導線連接件74. . . Wire bond / double wire connector

74A．．．雙導線結合連接件74A. . . Double wire joint

80．．．第一囊封物80. . . First capsule

81．．．焊球81. . . Solder ball

82．．．第二囊封物82. . . Second encapsulation

112．．．第一微電子元件112. . . First microelectronic component

114．．．第二微電子元件114. . . Second microelectronic component

120．．．接觸件120. . . Contact

126．．．接觸件126. . . Contact

130．．．介電元件130. . . Dielectric element

133．．．第一孔隙133. . . First pore

139．．．第二孔隙139. . . Second pore

140．．．導電元件140. . . Conductive component

150．．．電連接件150. . . Electrical connector

152．．．第一導線結合件152. . . First wire bond

154．．．第二導線結合件154. . . Second wire bond

158．．．垂直方向158. . . Vertical direction

170．．．電連接器170. . . Electrical connector

172．．．第一導線結合件172. . . First wire bond

174．．．第二導線結合件174. . . Second wire bond

212．．．第一微電子元件212. . . First microelectronic component

214．．．第二微電子元件214. . . Second microelectronic component

220．．．接觸件220. . . Contact

226．．．接觸件226. . . Contact

230．．．介電元件230. . . Dielectric element

233．．．孔隙233. . . Porosity

235．．．第一邊緣235. . . First edge

237．．．第二邊緣237. . . Second edge

240．．．導電元件240. . . Conductive component

250．．．電連接件250. . . Electrical connector

252．．．第一導線結合件252. . . First wire bond

254．．．第二導線結合件254. . . Second wire bond

260．．．接觸件260. . . Contact

280．．．囊封物280. . . Encapsulation

310．．．總成310. . . Assembly

312．．．第一微電子元件312. . . First microelectronic component

314．．．第二微電子元件314. . . Second microelectronic component

320．．．接觸件320. . . Contact

326．．．接觸件326. . . Contact

330．．．介電元件330. . . Dielectric element

333．．．第一孔隙333. . . First pore

336．．．端子336. . . Terminal

339．．．第二孔隙339. . . Second pore

340．．．導電元件340. . . Conductive component

350．．．電連接件350. . . Electrical connector

352．．．參考導線結合件/參考結合導線352. . . Reference wire bond / reference bond wire

354．．．第一信號導線結合件354. . . First signal wire bond

356．．．第二信號導線結合件356. . . Second signal wire bond

362．．．第一末端部分362. . . First end portion

364．．．第二末端部分/中心部分364. . . Second end part / center part

366．．．第二部分366. . . the second part

368．．．參考導線結合件368. . . Reference wire joint

412．．．第一微電子元件412. . . First microelectronic component

414．．．第二微電子元件414. . . Second microelectronic component

416．．．前表面416. . . Front surface

420．．．接觸件420. . . Contact

426．．．接觸件426. . . Contact

429．．．邊緣429. . . edge

430．．．介電元件430. . . Dielectric element

433．．．孔隙433. . . Porosity

440．．．導電元件440. . . Conductive component

443．．．重新分佈層443. . . Redistribution layer

448．．．導電元件448. . . Conductive component

452．．．第一導線結合件452. . . First wire bond

454．．．第二導線結合件454. . . Second wire bond

500．．．堆疊微電子總成500. . . Stacked microelectronic assembly

500'．．．堆疊微電子總成500'. . . Stacked microelectronic assembly

501．．．第一半字寬微電子元件/第一微電子元件501. . . First half word wide microelectronic component / first microelectronic component

502．．．第二半字寬微電子元件/第二微電子元件502. . . Second half word wide microelectronic component / second microelectronic component

503．．．介電元件503. . . Dielectric element

504．．．表面504. . . surface

505．．．導線結合件/引線部分505. . . Wire bond/lead part

506．．．跡線506. . . Trace

506'．．．跡線506'. . . Trace

506"．．．跡線506"...trace

507．．．跡線507. . . Trace

507'．．．跡線507'. . . Trace

507"．．．跡線507"...trace

508．．．跡線508. . . Trace

509．．．接地平面或電力平面509. . . Ground plane or power plane

511．．．第一孔隙511. . . First pore

512．．．第二孔隙512. . . Second pore

516．．．跡線516. . . Trace

517．．．跡線517. . . Trace

518．．．跡線/引線518. . . Trace/lead

519．．．跡線/引線519. . . Trace/lead

521．．．電接觸件521. . . Electrical contact

522．．．電接觸件522. . . Electrical contact

531．．．導電元件/電接觸件531. . . Conductive component / electrical contact

532．．．導電元件/電接觸件532. . . Conductive component / electrical contact

533a．．．導電元件533a. . . Conductive component

533b．．．導電元件533b. . . Conductive component

536．．．導電介層孔536. . . Conductive via

537．．．導電介層孔537. . . Conductive via

541．．．導電端子541. . . Conductive terminal

541a．．．導電端子541a. . . Conductive terminal

541b．．．導電端子541b. . . Conductive terminal

542．．．導電端子/鄰近資料輸入/輸出信號端子542. . . Conductive terminal / adjacent data input / output signal terminal

546．．．端子群組546. . . Terminal group

547．．．端子群組547. . . Terminal group

553．．．導電元件或端子/共用時脈信號端子/共用資料選通信號端子/第一中心端子553. . . Conductive element or terminal / shared clock signal terminal / shared data strobe signal terminal / first center terminal

558．．．端子群組/中心端子558. . . Terminal group / center terminal

561．．．導電端子/第一參考電位端子561. . . Conductive terminal / first reference potential terminal

562．．．導電端子562. . . Conductive terminal

563．．．導電元件或端子563. . . Conductive component or terminal

566．．．端子群組566. . . Terminal group

567．．．端子群組567. . . Terminal group

568．．．端子群組568. . . Terminal group

571．．．導電端子/第二參考電位端子/位址信號端子571. . . Conductive terminal / second reference potential terminal / address signal terminal

572．．．導電端子/位址信號端子572. . . Conductive terminal / address signal terminal

573．．．導電元件或端子/位址信號端子573. . . Conductive component or terminal / address signal terminal

576．．．端子群組576. . . Terminal group

577．．．端子群組577. . . Terminal group

578．．．端子群組578. . . Terminal group

600．．．堆疊微電子總成600. . . Stacked microelectronic assembly

601．．．第一全字寬微電子元件/第一微電子元件601. . . First full-width wide microelectronic component / first microelectronic component

602．．．第二全字寬微電子元件/第二微電子元件602. . . Second full-width wide microelectronic component / second microelectronic component

603．．．介電元件603. . . Dielectric element

604．．．表面604. . . surface

621．．．電接觸件621. . . Electrical contact

622．．．電接觸件622. . . Electrical contact

643．．．導電元件或端子643. . . Conductive component or terminal

648．．．端子群組648. . . Terminal group

651．．．導電端子651. . . Conductive terminal

652．．．導電元件或端子652. . . Conductive component or terminal

653．．．導電元件或端子653. . . Conductive component or terminal

656．．．端子群組656. . . Terminal group

657．．．端子群組657. . . Terminal group

658．．．端子群組658. . . Terminal group

661．．．導電端子661. . . Conductive terminal

662．．．導電元件或端子662. . . Conductive component or terminal

663．．．導電元件或端子663. . . Conductive component or terminal

666．．．端子群組666. . . Terminal group

667．．．端子群組667. . . Terminal group

668．．．端子群組668. . . Terminal group

671．．．導電端子671. . . Conductive terminal

672．．．導電元件或端子672. . . Conductive component or terminal

673．．．導電元件或端子673. . . Conductive component or terminal

676．．．端子群組676. . . Terminal group

677．．．端子群組677. . . Terminal group

678．．．端子群組678. . . Terminal group

700．．．模組700. . . Module

710．．．微電子總成710. . . Microelectronic assembly

720．．．電介面720. . . Interface

730．．．接觸件730. . . Contact

800．．．系統800. . . system

801．．．外殼801. . . shell

802．．．電路面板802. . . Circuit panel

804．．．導體804. . . conductor

806．．．微電子總成/結構806. . . Microelectronic assembly/structure

808．．．電子部件808. . . Electronic components

810．．．電子部件/螢幕810. . . Electronic components / screen

811．．．透鏡811. . . lens

900A．．．微電子總成900A. . . Microelectronic assembly

900B．．．微電子總成900B. . . Microelectronic assembly

912．．．第一微電子元件912. . . First microelectronic component

914．．．第二微電子元件914. . . Second microelectronic component

930A．．．介電元件930A. . . Dielectric element

930B．．．介電元件930B. . . Dielectric element

940．．．第三微電子元件940. . . Third microelectronic component

941．．．接合單元/焊料凸塊941. . . Bonding unit / solder bump

981．．．接合單元981. . . Joint unit

990．．．焊料柱990. . . Solder column

992．．．導電支柱992. . . Conductive pillar

994．．．焊料994. . . solder

1000．．．配置1000. . . Configuration

1010．．．配置1010. . . Configuration

圖1為根據本發明之一實施例之堆疊微電子總成的圖解剖視立面圖；1 is a schematic cross-sectional elevational view of a stacked microelectronic assembly in accordance with an embodiment of the present invention;

圖2為圖1之堆疊總成的仰視圖；Figure 2 is a bottom plan view of the stack assembly of Figure 1;

圖3為說明本文之一實施例中微電子總成中之結合元件之間的連接件的片斷部分剖視圖；Figure 3 is a fragmentary cross-sectional view showing the connector between the bonding elements in the microelectronic assembly in one embodiment of the present invention;

圖4為進一步說明本文之一實施例中微電子總成中之結合元件之間的連接件的片斷部分剖視圖；4 is a fragmentary cross-sectional view of the connector between the bonding elements in the microelectronic assembly in one embodiment of the present invention;

圖5為說明本文之一實施例中微電子總成之變化中之結合元件之間的連接件的片斷部分剖視圖；Figure 5 is a fragmentary cross-sectional view showing the connector between the bonding elements in a variation of the microelectronic assembly in one embodiment of the present invention;

圖6為特定地說明包括有帶狀結合件之環圈狀連接件之微電子總成的片斷部分透視圖；Figure 6 is a fragmentary perspective view, in particular, illustrating a microelectronic assembly including a looped connector of a ribbon bond;

圖7為根據本發明之另一實施例之堆疊微電子總成的圖解剖視立面圖；7 is a schematic cross-sectional elevational view of a stacked microelectronic assembly in accordance with another embodiment of the present invention;

圖8為根據本發明之又一實施例之堆疊微電子總成的圖解剖視立面圖；8 is a schematic cross-sectional elevational view of a stacked microelectronic assembly in accordance with yet another embodiment of the present invention;

圖9為根據本發明之一另外實施例之堆疊微電子總成的圖解剖視立面圖；9 is a schematic cross-sectional elevational view of a stacked microelectronic assembly in accordance with another embodiment of the present invention;

圖10為根據本發明之另一實施例之堆疊微電子總成的圖解剖視立面圖；10 is a schematic cross-sectional elevational view of a stacked microelectronic assembly in accordance with another embodiment of the present invention;

圖11為根據本發明之一另外實施例之堆疊微電子配置的圖解剖視圖；11 is a diagrammatic cross-sectional view of a stacked microelectronic configuration in accordance with another embodiment of the present invention;

圖12為根據本發明之一另外實施例之堆疊微電子配置的圖解剖視圖；12 is a diagrammatic cross-sectional view of a stacked microelectronic configuration in accordance with another embodiment of the present invention;

圖13為根據本發明之又一實施例之堆疊微電子總成的圖解仰視圖；Figure 13 is a diagrammatic bottom view of a stacked microelectronic assembly in accordance with yet another embodiment of the present invention;

圖14為根據本發明之另一實施例之堆疊微電子總成的圖解仰視圖；14 is a diagrammatic bottom view of a stacked microelectronic assembly in accordance with another embodiment of the present invention;

圖15為具有替代跡線佈線配置之圖13之部分的圖解放大圖；及Figure 15 is a diagrammatic enlarged view of a portion of Figure 13 with an alternate trace wiring configuration;

圖16為根據本發明之一實施例之模組的示意性描繪；及16 is a schematic depiction of a module in accordance with an embodiment of the present invention; and

圖17為根據本發明之一實施例之系統的示意性描繪。Figure 17 is a schematic depiction of a system in accordance with an embodiment of the present invention.

10．．．堆疊微電子總成10. . . Stacked microelectronic assembly

12．．．第一微電子元件12. . . First microelectronic component

13．．．中心區域13. . . Central region

14．．．第二微電子元件14. . . Second microelectronic component

15．．．第一末端區域15. . . First end region

16．．．前表面/第一表面16. . . Front surface / first surface

17．．．第二末端區域17. . . Second end region

18．．．後表面18. . . Back surface

19．．．中心區域19. . . Central region

20．．．電接觸件/第一接觸件/晶片接觸件20. . . Electrical contact / first contact / wafer contact

21．．．第一末端區域twenty one. . . First end region

22．．．前表面/第一表面twenty two. . . Front surface / first surface

23．．．第二末端區域twenty three. . . Second end region

24．．．後表面twenty four. . . Back surface

26．．．電接觸件26. . . Electrical contact

27．．．第一邊緣27. . . First edge

29．．．第二邊緣29. . . Second edge

30．．．介電元件/介電材料30. . . Dielectric element / dielectric material

31．．．間隔層31. . . Spacer

32．．．第一表面32. . . First surface

33．．．第一孔隙33. . . First pore

34．．．第二表面34. . . Second surface

35．．．第一邊緣35. . . First edge

36．．．導電元件或端子36. . . Conductive component or terminal

37．．．第二邊緣37. . . Second edge

39．．．第二孔隙39. . . Second pore

40．．．導電元件/第二接觸件40. . . Conductive element / second contact

42．．．導電跡線42. . . Conductive trace

50．．．電連接件或引線50. . . Electrical connector or lead

52．．．導線結合件/第一結合導線/雙導線連接件52. . . Wire bond / first bond wire / double wire connector

54．．．導線結合件/雙導線連接件54. . . Wire bond / double wire connector

60．．．間隔層60. . . Spacer

70．．．電連接件或引線70. . . Electrical connector or lead

72．．．導線結合件/雙導線連接件72. . . Wire bond / double wire connector

74．．．導線結合件/雙導線連接件74. . . Wire bond / double wire connector

80．．．第一囊封物80. . . First capsule

81．．．焊球81. . . Solder ball

82．．．第二囊封物82. . . Second encapsulation

Claims (21)

一種微電子總成，其包含：一介電元件，其具有一第一表面、一第二表面、第一孔隙及第二孔隙，該第一孔隙及該第二孔隙延伸於該第一表面與該第二表面之間且在該第一孔隙與該第二孔隙之間界定該第一表面之一中心區域，該介電元件在其上進一步具有包括曝露於該中心區域處之中心端子之導電元件；一第一微電子元件，其具有一後表面及面對該介電元件之該第二表面之一前表面，該第一微電子元件具有曝露於該第一微電子元件之該前表面處之複數個接觸件；一第二微電子元件，其具有面對該第一微電子元件之該後表面之一前表面，該第二微電子元件具有突出超過該第一微電子元件之一邊緣的曝露於該第二微電子元件之該前表面處之複數個接觸件；及引線，其自該第一微電子元件及該第二微電子元件之該等接觸件延伸至該等端子，該等引線之至少第一引線及第二引線使該等中心端子之一第一中心端子與該第一微電子元件及該第二微電子元件中每一者電互連，其中該第一引線及該第二引線可用以在該第一中心端子與該第一微電子元件及該第二微電子元件中每一者之間攜載一信號或一參考電位中至少一者，其中該介電元件之該第一表面具有一第一周邊邊緣及在該第一孔隙與該第一周邊邊緣之間的一第一周邊區域，該微電子總成進一步 包含自曝露於該第一周邊區域處之一第一端子延伸至該第一微電子元件之該等接觸件中至少一者的一第三引線，該第三引線可用以在該至少一第一端子與該第一微電子元件之間攜載一第一資料信號，且其中該介電元件之該第一表面具有一第二周邊邊緣及在該第二孔隙與該第二周邊邊緣之間的一第二周邊區域，該微電子總成進一步包含自曝露於該第二周邊區域處之一第二端子延伸至該第二微電子元件之該等接觸件中至少一者的一第四引線，該第四引線可用以在該第二端子與該第二微電子元件之間攜載一第二資料信號，其中該第一微電子元件具有可用於該第一資料信號之輸入或輸出而不可用於該第二資料信號之輸入或輸出的接觸件，且該第二微電子元件具有可用於該第二資料信號之輸入或輸出而不可用於該第一資料信號之輸入或輸出的接觸件。 A microelectronic assembly comprising: a dielectric component having a first surface, a second surface, a first aperture, and a second aperture, the first aperture and the second aperture extending over the first surface A central region of the first surface is defined between the second surface and between the first aperture and the second aperture, the dielectric component further having thereon a conductive portion including a central terminal exposed at the central region a first microelectronic component having a rear surface and a front surface facing the second surface of the dielectric component, the first microelectronic component having the front surface exposed to the first microelectronic component a plurality of contacts; a second microelectronic component having a front surface facing the rear surface of the first microelectronic component, the second microelectronic component having one of protruding beyond the first microelectronic component a plurality of contacts exposed at the front surface of the second microelectronic component; and leads extending from the contacts of the first microelectronic component and the second microelectronic component to the terminals The lead to The first lead and the second lead electrically interconnect one of the first center terminals with each of the first microelectronic component and the second microelectronic component, wherein the first lead and the second lead The method may be configured to carry at least one of a signal or a reference potential between the first center terminal and each of the first microelectronic component and the second microelectronic component, wherein the first of the dielectric components The surface has a first peripheral edge and a first peripheral region between the first aperture and the first peripheral edge, the microelectronic assembly further a third lead including at least one of the contacts extending from the first terminal to the first microelectronic component at the first peripheral region, the third lead being usable at the at least one first Holding a first data signal between the terminal and the first microelectronic component, and wherein the first surface of the dielectric component has a second peripheral edge and between the second aperture and the second peripheral edge a second peripheral region, the microelectronic assembly further comprising a fourth lead extending from the second terminal of the second peripheral region to the at least one of the contacts of the second microelectronic component, The fourth lead can be used to carry a second data signal between the second terminal and the second microelectronic component, wherein the first microelectronic component has an input or output available for the first data signal and is unavailable a contact for inputting or outputting the second data signal, and the second microelectronic element has a contact member usable for input or output of the second data signal and not for input or output of the first data signal. 如請求項1之微電子總成，其中該第一引線及該第二引線可用以在該第一中心端子與該第一微電子元件及該第二微電子元件之間攜載一共用時序信號。 The microelectronic assembly of claim 1, wherein the first lead and the second lead are operable to carry a common timing signal between the first central terminal and the first microelectronic component and the second microelectronic component . 如請求項2之微電子總成，其中該第一引線及該第二引線可用以攜載至少一時脈信號。 The microelectronic assembly of claim 2, wherein the first lead and the second lead are operable to carry at least one clock signal. 如請求項3之微電子總成，其進一步包含使該等中心端子之一第二中心端子與該第一微電子元件及該第二微電子元件中每一者電互連的第五引線及第六引線，其中該第一引線及該第二引線可用以攜載一第一差動時脈信號，該第五引線及該第六引線可用以在該第二中心端子 與該第一微電子元件及該第二微電子元件之間攜載一第二差動時脈信號，其中該第一差動時脈信號及該第二差動時脈信號集體地傳輸一差動時脈。 The microelectronic assembly of claim 3, further comprising a fifth lead electrically interconnecting a second central terminal of the central terminals with each of the first microelectronic component and the second microelectronic component a sixth lead, wherein the first lead and the second lead can be used to carry a first differential clock signal, and the fifth lead and the sixth lead can be used at the second center terminal Carrying a second differential clock signal between the first microelectronic component and the second microelectronic component, wherein the first differential clock signal and the second differential clock signal collectively transmit a difference Dynamic clock. 如請求項1之微電子總成，其中該第一引線及該第二引線可用以在該第一中心端子與該第一微電子元件及該第二微電子元件中每一者之間攜載一資料信號。 The microelectronic assembly of claim 1, wherein the first lead and the second lead are usable to carry between the first center terminal and each of the first microelectronic component and the second microelectronic component A data signal. 如請求項5之微電子總成，其中該第一微電子元件及該第二微電子元件中每一者具有接觸件，該等接觸件可用於使由該第一微電子元件及該第二微電子元件所共用之複數個資料信號經由包括該第一引線及該第二引線之一引線集合而輸入或輸出至該複數個中心端子之一共用端子集合，該等共用端子包括該第一中心端子。 The microelectronic assembly of claim 5, wherein each of the first microelectronic component and the second microelectronic component has a contact, the contacts being operable to cause the first microelectronic component and the second The plurality of data signals shared by the microelectronic components are input or output to a common terminal set of the plurality of center terminals via a set of leads including the first lead and the second lead, and the common terminals include the first center Terminal. 如請求項1之微電子總成，其中該第一微電子元件及該第二微電子元件中每一者包括一記憶體儲存元件，且該第一引線及該第二引線可用以攜載可用以定址該第一微電子元件及該第二微電子元件中每一者中之記憶體之一位址信號。 The microelectronic assembly of claim 1, wherein each of the first microelectronic component and the second microelectronic component comprises a memory storage component, and the first lead and the second lead are available to carry And addressing an address signal of the memory in each of the first microelectronic component and the second microelectronic component. 一種微電子總成，其包含：一介電元件，其具有對置面對之第一表面及第二表面以及延伸於該第一表面與該第二表面之間的至少一第一孔隙，該介電元件在其上進一步具有包括曝露於該第一表面處之複數個端子之導電元件；一第一微電子元件，其具有一後表面及面對該介電元件之一前表面，該第一微電子元件具有曝露於該第一微 電子元件之該前表面處之複數個接觸件；一第二微電子元件，其包括一後表面及面對該第一微電子元件之該後表面之一前表面，該第二微電子元件具有突出超過該第一微電子元件之一邊緣的曝露於該第二微電子元件之該前表面處之複數個接觸件；一第一信號引線，其通過該至少一孔隙而延伸至該介電元件上之一導電元件，且電連接於該第一微電子元件之一第一接觸件與該介電元件之一第一端子之間；及一第一參考引線，其連接至該介電元件上之至少一導電元件，其中該第一參考引線橫越該介電元件之該第一孔隙而延伸，該第一參考引線之一部分實質上平行於該第一信號引線之一實質部分且與該第一信號引線之該實質部分間隔一實質上均一距離，使得針對該第一信號引線而達成一所要阻抗，該第一參考引線用以連接至一參考電位且電連接至該第一微電子元件之至少一接觸件。 A microelectronic assembly comprising: a dielectric member having opposing first and second surfaces and at least a first aperture extending between the first surface and the second surface, The dielectric component further has thereon a conductive component including a plurality of terminals exposed at the first surface; a first microelectronic component having a rear surface and a front surface facing the dielectric component, the first a microelectronic component having exposure to the first micro a plurality of contacts at the front surface of the electronic component; a second microelectronic component including a back surface and a front surface facing the back surface of the first microelectronic component, the second microelectronic component having a plurality of contacts protruding beyond an edge of the first microelectronic component at the front surface of the second microelectronic component; a first signal lead extending through the at least one aperture to the dielectric component a conductive element coupled between the first contact of the first microelectronic component and the first terminal of the dielectric component; and a first reference lead connected to the dielectric component At least one conductive element, wherein the first reference lead extends across the first aperture of the dielectric element, a portion of the first reference lead being substantially parallel to a substantial portion of the first signal lead and The substantial portion of a signal lead is spaced apart by a substantially uniform distance such that a desired impedance is achieved for the first signal lead, the first reference lead for connecting to a reference potential and electrically coupled to the first micro At least one contact element of subcomponent. 如請求項8之微電子總成，其進一步包含：一第二孔隙，其延伸通過該介電元件；及一第二信號引線，其通過該第二孔隙而延伸至該介電元件上之一導電元件且電連接於該第二微電子元件之一接觸件與該介電元件上之一端子之間。 The microelectronic assembly of claim 8 further comprising: a second aperture extending through the dielectric component; and a second signal lead extending through the second aperture to the dielectric component And a conductive element is electrically connected between the contact of the one of the second microelectronic element and one of the terminals of the dielectric element. 如請求項9之微電子總成，其進一步包含電連接至該介電元件上之導電元件的一第二參考引線，該第二參考引線之至少一部分與該第二信號引線間隔一實質上均一距離，使得針對該第二信號引線而達成一所要阻抗。 The microelectronic assembly of claim 9 further comprising a second reference lead electrically coupled to the conductive element on the dielectric element, at least a portion of the second reference lead being substantially uniform from the second signal lead The distance is such that a desired impedance is achieved for the second signal lead. 如請求項9之微電子總成，其中該第一參考引線橫越該介電元件之該第一孔隙及該第二孔隙而延伸。 The microelectronic assembly of claim 9, wherein the first reference lead extends across the first aperture and the second aperture of the dielectric component. 如請求項11之微電子總成，其中該第一參考引線之一第一部分延伸成與該第一信號引線相隔一實質上均一距離，且該第一參考引線之第二部分延伸成與該第二信號引線相隔一實質上均一距離。 The microelectronic assembly of claim 11, wherein the first portion of the first reference lead extends a substantially uniform distance from the first signal lead, and the second portion of the first reference lead extends to the first portion The two signal leads are separated by a substantially uniform distance. 一種微電子總成，其包含：一介電元件，其具有對置面對之第一表面及第二表面以及延伸於該第一表面與該第二表面之間的至少一孔隙，該介電元件在其上進一步具有包括複數個接觸件及複數個端子之導電元件，該等接觸件及該等端子曝露於該介電元件之該第一表面處；一第一微電子元件，其具有一後表面及面對該介電元件之一前表面，該第一微電子元件具有曝露於該第一微電子元件之該前表面處之複數個接觸件；一第二微電子元件，其具有一後表面及面對該第一微電子元件之該後表面之一前表面，該第二微電子元件具有曝露於該前表面處且突出超過該第一微電子元件之一邊緣之複數個接觸件；及第一結合導線及第二結合導線，其通過該至少一孔隙而延伸至該介電元件上之導電元件，該第一結合導線及該第二結合導線具有電連接至該第一微電子元件之一第一接觸件的第一末端及電連接至該介電元件之一第一端子的第二末端，且提供電並聯導電路徑，其中該第一結 合導線接合至該等導電元件中之一第一者且接合至該第二結合導線之一末端，使得該第一結合導線不觸碰該第一接觸件或該第一導電元件中至少一者。 A microelectronic assembly comprising: a dielectric member having opposing first and second surfaces and at least one aperture extending between the first surface and the second surface, the dielectric The component further has thereon a conductive component including a plurality of contacts and a plurality of terminals, the contacts and the terminals being exposed at the first surface of the dielectric component; a first microelectronic component having a first a rear surface and a front surface facing the dielectric element, the first microelectronic element having a plurality of contacts exposed at the front surface of the first microelectronic element; and a second microelectronic element having a a rear surface and a front surface facing the back surface of the first microelectronic component, the second microelectronic component having a plurality of contacts exposed at the front surface and projecting beyond an edge of the first microelectronic component And a first bonding wire and a second bonding wire extending through the at least one aperture to the conductive component on the dielectric component, the first bonding wire and the second bonding wire having electrical connection to the first microelectronic yuan One of the first electrical contact and a first end connected to the second end of the first terminal to one of the dielectric member, and provide a conductive path electrically in parallel, wherein the first junction a bonding wire bonded to one of the first conductive members and bonded to one end of the second bonding wire such that the first bonding wire does not touch at least one of the first contact or the first conductive member . 如請求項13之微電子總成，其進一步包含通過該至少一孔隙而延伸至該介電元件上之導電元件的第三導電結合導線及第四導電結合導線，該第三結合導線及該第四結合導線電連接於該第二微電子元件之一第一接觸件與該介電元件之一第二端子之間，且提供電並聯導電路徑。 The microelectronic assembly of claim 13, further comprising a third conductive bonding wire and a fourth conductive bonding wire extending through the at least one aperture to the conductive component on the dielectric component, the third bonding wire and the third The four bonding wires are electrically connected between the first contact of one of the second microelectronic components and the second terminal of one of the dielectric components and provide an electrically parallel conductive path. 如請求項13之微電子總成，其進一步包含安裝於該介電元件上之至少一被動部件。 The microelectronic assembly of claim 13 further comprising at least one passive component mounted on the dielectric component. 一種微電子總成，其包含：一介電元件，其具有對置面對之第一表面及第二表面以及延伸於該等表面之間的一孔隙；一第一微電子元件，其具有一後表面、面對該介電元件之一前表面及一第一邊緣，該第一微電子元件具有遠離於該第一邊緣的曝露於該第一微電子元件之該前表面處之複數個接觸件，及沿著該前表面而自該等接觸件延伸至鄰近於該第一邊緣的曝露於該前表面處之重新分佈焊墊的重新分佈導體；及一第二微電子元件，其具有一後表面及一前表面，該第二微電子元件具有突出超過該第一微電子元件之該第一邊緣的曝露於該第二微電子元件之該前表面處之複數個接觸件，該第一微電子元件之該等重新分佈焊墊及該第二微電 子元件之該等接觸件係與該介電元件中之該孔隙對準。 A microelectronic assembly comprising: a dielectric member having opposing first and second surfaces and an aperture extending between the surfaces; a first microelectronic component having a a rear surface facing a front surface of the dielectric component and a first edge, the first microelectronic component having a plurality of contacts exposed at the front surface of the first microelectronic component away from the first edge And a redistribution conductor extending along the front surface from the contacts to a redistribution pad exposed adjacent the first edge to the front surface; and a second microelectronic component having a a second microelectronic component having a plurality of contacts protruding beyond the first edge of the first microelectronic component and exposed to the front surface of the second microelectronic component, the first surface and a front surface, the first The redistributed pads of the microelectronic component and the second microelectronic The contacts of the sub-element are aligned with the aperture in the dielectric element. 如請求項16之微電子總成，其中該介電元件在其上具有包括曝露於該介電元件之該第一表面處之端子的導電元件，該總成進一步包含自該第一微電子元件之該等重新分佈焊墊通過該孔隙而延伸至該介電元件上之該等導電元件中之一些的第一引線，及自該第二微電子元件之該等接觸件通過該孔隙而延伸至該介電元件上之該等導電元件中之一些的第二引線。 The microelectronic assembly of claim 16, wherein the dielectric component has thereon a conductive component including a terminal exposed at the first surface of the dielectric component, the assembly further comprising the first microelectronic component The redistribution pads extend through the apertures to first leads of some of the conductive elements on the dielectric component, and the contacts from the second microelectronic component extend through the apertures to a second lead of some of the conductive elements on the dielectric element. 一種微電子系統，其包含根據請求項1、8、13或16中任一項之一結構，及電連接至該結構之一或多個其他電子部件。 A microelectronic system comprising a structure according to any one of claims 1, 8, 13 or 16, and electrically connected to one or more other electronic components of the structure. 如請求項18之微電子系統，其進一步包含一外殼，該結構及該等其他電子部件安裝至該外殼。 The microelectronic system of claim 18, further comprising a housing to which the structure and the other electronic components are mounted. 一種微電子模組，其包括根據請求項1、8、13或16中任一項之複數個微電子總成，該模組具有用於將信號輸送至該等微電子總成中每一者及自該等微電子總成中每一者輸送信號之一共同電介面。 A microelectronic module comprising a plurality of microelectronic assemblies according to any one of claims 1, 8, 13, or 16, the module having means for transmitting signals to each of the microelectronic assemblies And a common electrical interface of one of the signals from each of the microelectronic assemblies. 一種微電子配置，其包括根據請求項1、8、13或16中任一項之至少一微電子總成，及與該至少一微電子總成垂直地堆疊且與該至少一微電子總成電互連之至少一第三微電子元件，該第三微電子元件具有不同於該至少一微電子總成之一功能的一功能。 A microelectronic configuration comprising at least one microelectronic assembly according to any one of claims 1, 8, 13 or 16, and stacked vertically with the at least one microelectronic assembly and with the at least one microelectronic assembly At least one third microelectronic component electrically interconnected, the third microelectronic component having a function different from one of the functions of the at least one microelectronic assembly.
TW100146943A 2010-12-17 2011-12-16 Enhanced stacked microelectronic assemblies with central contacts, systems,modules,and arrangements thereof TWI479630B (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR20100129890A KR101118711B1 (en) 2010-12-17 2010-12-17 Enhanced stacked microelectric assemblies with central contacts
US13/080,876 US8787032B2 (en) 2010-12-17 2011-04-06 Enhanced stacked microelectronic assemblies with central contacts

Publications (2)

Publication Number Publication Date
TW201241984A TW201241984A (en) 2012-10-16
TWI479630B true TWI479630B (en) 2015-04-01

Family

ID=44168899

Family Applications (1)

Application Number Title Priority Date Filing Date
TW100146943A TWI479630B (en) 2010-12-17 2011-12-16 Enhanced stacked microelectronic assemblies with central contacts, systems,modules,and arrangements thereof

Country Status (8)

Country Link
US (2) US8787032B2 (en)
EP (1) EP2652783A1 (en)
JP (1) JP2013546197A (en)
KR (1) KR101118711B1 (en)
CN (1) CN103370785B (en)
BR (1) BR112013015111A2 (en)
TW (1) TWI479630B (en)
WO (1) WO2012082177A1 (en)

Families Citing this family (34)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8896126B2 (en) * 2011-08-23 2014-11-25 Marvell World Trade Ltd. Packaging DRAM and SOC in an IC package
KR101061531B1 (en) * 2010-12-17 2011-09-01 테세라 리써치 엘엘씨 Enhanced stacked microelectronic assemblies with central contacts and improved ground or power distribution
US8338963B2 (en) * 2011-04-21 2012-12-25 Tessera, Inc. Multiple die face-down stacking for two or more die
US8928153B2 (en) 2011-04-21 2015-01-06 Tessera, Inc. Flip-chip, face-up and face-down centerbond memory wirebond assemblies
US8952516B2 (en) 2011-04-21 2015-02-10 Tessera, Inc. Multiple die stacking for two or more die
US8633576B2 (en) 2011-04-21 2014-01-21 Tessera, Inc. Stacked chip-on-board module with edge connector
US9013033B2 (en) 2011-04-21 2015-04-21 Tessera, Inc. Multiple die face-down stacking for two or more die
US8823165B2 (en) 2011-07-12 2014-09-02 Invensas Corporation Memory module in a package
US8569884B2 (en) 2011-08-15 2013-10-29 Tessera, Inc. Multiple die in a face down package
US8653646B2 (en) 2011-10-03 2014-02-18 Invensas Corporation Stub minimization using duplicate sets of terminals for wirebond assemblies without windows
US8405207B1 (en) 2011-10-03 2013-03-26 Invensas Corporation Stub minimization for wirebond assemblies without windows
EP2766928A1 (en) 2011-10-03 2014-08-20 Invensas Corporation Stub minimization with terminal grids offset from center of package
JP5947904B2 (en) 2011-10-03 2016-07-06 インヴェンサス・コーポレイション Stub minimization for multi-die wirebond assemblies with orthogonal windows
US8659139B2 (en) 2011-10-03 2014-02-25 Invensas Corporation Stub minimization using duplicate sets of signal terminals in assemblies without wirebonds to package substrate
EP2764543A2 (en) 2011-10-03 2014-08-13 Invensas Corporation Stub minimization for multi-die wirebond assemblies with parallel windows
US8610260B2 (en) 2011-10-03 2013-12-17 Invensas Corporation Stub minimization for assemblies without wirebonds to package substrate
US9287249B2 (en) * 2012-04-11 2016-03-15 Panasonic Intellectual Property Management Co., Ltd. Semiconductor device
US8848392B2 (en) 2012-08-27 2014-09-30 Invensas Corporation Co-support module and microelectronic assembly
US9368477B2 (en) 2012-08-27 2016-06-14 Invensas Corporation Co-support circuit panel and microelectronic packages
US8848391B2 (en) 2012-08-27 2014-09-30 Invensas Corporation Co-support component and microelectronic assembly
CN103000543A (en) * 2012-12-18 2013-03-27 可天士半导体（沈阳）有限公司 High-reliability bonding method
TWI567844B (en) * 2013-01-18 2017-01-21 聯華電子股份有限公司 Layout structure of electronic element and testing method of the same thereof
US9070423B2 (en) 2013-06-11 2015-06-30 Invensas Corporation Single package dual channel memory with co-support
US9123555B2 (en) 2013-10-25 2015-09-01 Invensas Corporation Co-support for XFD packaging
US10418330B2 (en) 2014-04-15 2019-09-17 Micron Technology, Inc. Semiconductor devices and methods of making semiconductor devices
JP2015216263A (en) * 2014-05-12 2015-12-03 マイクロン テクノロジー， インク． Semiconductor device
US9281296B2 (en) 2014-07-31 2016-03-08 Invensas Corporation Die stacking techniques in BGA memory package for small footprint CPU and memory motherboard design
US9691437B2 (en) 2014-09-25 2017-06-27 Invensas Corporation Compact microelectronic assembly having reduced spacing between controller and memory packages
US9543277B1 (en) * 2015-08-20 2017-01-10 Invensas Corporation Wafer level packages with mechanically decoupled fan-in and fan-out areas
US9484080B1 (en) 2015-11-09 2016-11-01 Invensas Corporation High-bandwidth memory application with controlled impedance loading
US9679613B1 (en) 2016-05-06 2017-06-13 Invensas Corporation TFD I/O partition for high-speed, high-density applications
EP3343600A1 (en) * 2016-12-28 2018-07-04 Siemens Aktiengesellschaft Semiconductor module with a first and a second connecting element for connecting a semiconductor chip and method of manufacturing
CN108037816A (en) * 2017-12-21 2018-05-15 曙光信息产业(北京)有限公司 Through-flow device and immersion liquid-cooled suit business device
US11876067B2 (en) * 2021-10-18 2024-01-16 Nanya Technology Corporation Semiconductor package and method of manufacturing the same

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020127775A1 (en) * 1999-12-23 2002-09-12 Rambus Inc. Redistributed bond pads in stacked integrated circuit die package
US20040145054A1 (en) * 2002-09-06 2004-07-29 Tessera, Inc. Components, methods and assemblies for stacked packages
US20050116358A1 (en) * 2003-11-12 2005-06-02 Tessera,Inc. Stacked microelectronic assemblies with central contacts
TW201044536A (en) * 2009-03-13 2010-12-16 Tessera Research Llc Microelectronic assembly with impedance controlled wirebond and conductive reference element

Family Cites Families (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02174255A (en) 1988-12-27 1990-07-05 Mitsubishi Electric Corp Semiconductor integrated circuit
US5148266A (en) 1990-09-24 1992-09-15 Ist Associates, Inc. Semiconductor chip assemblies having interposer and flexible lead
US5679977A (en) 1990-09-24 1997-10-21 Tessera, Inc. Semiconductor chip assemblies, methods of making same and components for same
US5148265A (en) 1990-09-24 1992-09-15 Ist Associates, Inc. Semiconductor chip assemblies with fan-in leads
WO1996038031A2 (en) 1995-05-26 1996-11-28 Rambus, Inc. Chip socket assembly and chip file assembly for semiconductor chips
US7525813B2 (en) * 1998-07-06 2009-04-28 Renesas Technology Corp. Semiconductor device
SE519108C2 (en) 1999-05-06 2003-01-14 Sandvik Ab Coated cutting tool for machining gray cast iron
US6414396B1 (en) * 2000-01-24 2002-07-02 Amkor Technology, Inc. Package for stacked integrated circuits
JP2001223324A (en) * 2000-02-10 2001-08-17 Mitsubishi Electric Corp Semiconductor device
JP2002076252A (en) * 2000-08-31 2002-03-15 Nec Kyushu Ltd Semiconductor device
SG95637A1 (en) * 2001-03-15 2003-04-23 Micron Technology Inc Semiconductor/printed circuit board assembly, and computer system
SG106054A1 (en) 2001-04-17 2004-09-30 Micron Technology Inc Method and apparatus for package reduction in stacked chip and board assemblies
US6385049B1 (en) 2001-07-05 2002-05-07 Walsin Advanced Electronics Ltd Multi-board BGA package
TW557556B (en) 2002-09-10 2003-10-11 Siliconware Precision Industries Co Ltd Window-type multi-chip semiconductor package
US6812580B1 (en) * 2003-06-09 2004-11-02 Freescale Semiconductor, Inc. Semiconductor package having optimized wire bond positioning
US7095104B2 (en) 2003-11-21 2006-08-22 International Business Machines Corporation Overlap stacking of center bus bonded memory chips for double density and method of manufacturing the same
JP2005251957A (en) 2004-03-04 2005-09-15 Renesas Technology Corp Semiconductor device
US7078808B2 (en) * 2004-05-20 2006-07-18 Texas Instruments Incorporated Double density method for wirebond interconnect
KR101070913B1 (en) 2005-05-19 2011-10-06 삼성테크윈 주식회사 Stacked die package
US7402911B2 (en) * 2005-06-28 2008-07-22 Infineon Technologies Ag Multi-chip device and method for producing a multi-chip device
KR100690247B1 (en) * 2006-01-16 2007-03-12 삼성전자주식회사 Double encapsulated semiconductor package and manufacturing method thereof
TWI306658B (en) * 2006-08-07 2009-02-21 Chipmos Technologies Inc Leadframe on offset stacked chips package
US20080088030A1 (en) * 2006-10-16 2008-04-17 Formfactor, Inc. Attaching and interconnecting dies to a substrate
US7772683B2 (en) * 2006-12-09 2010-08-10 Stats Chippac Ltd. Stacked integrated circuit package-in-package system
KR101479461B1 (en) 2008-10-14 2015-01-06 삼성전자주식회사 Stack package and method of manufacturing the same
KR101601847B1 (en) 2009-05-21 2016-03-09 삼성전자주식회사 semiconductor package

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020127775A1 (en) * 1999-12-23 2002-09-12 Rambus Inc. Redistributed bond pads in stacked integrated circuit die package
US20040145054A1 (en) * 2002-09-06 2004-07-29 Tessera, Inc. Components, methods and assemblies for stacked packages
US20050116358A1 (en) * 2003-11-12 2005-06-02 Tessera,Inc. Stacked microelectronic assemblies with central contacts
TW201044536A (en) * 2009-03-13 2010-12-16 Tessera Research Llc Microelectronic assembly with impedance controlled wirebond and conductive reference element

Also Published As

Publication number Publication date
JP2013546197A (en) 2013-12-26
TW201241984A (en) 2012-10-16
EP2652783A1 (en) 2013-10-23
CN103370785A (en) 2013-10-23
CN103370785B (en) 2016-11-23
US20120155049A1 (en) 2012-06-21
US20140239513A1 (en) 2014-08-28
KR101118711B1 (en) 2012-03-12
US9461015B2 (en) 2016-10-04
WO2012082177A1 (en) 2012-06-21
US8787032B2 (en) 2014-07-22
BR112013015111A2 (en) 2016-09-20

Similar Documents

Publication Publication Date Title
TWI479630B (en) Enhanced stacked microelectronic assemblies with central contacts, systems,modules,and arrangements thereof
JP5827342B2 (en) Improved stacked microelectronic assembly with central contact and improved ground or power distribution
US9640515B2 (en) Multiple die stacking for two or more die
US8436457B2 (en) Stub minimization for multi-die wirebond assemblies with parallel windows
US8345441B1 (en) Stub minimization for multi-die wirebond assemblies with parallel windows
US9312239B2 (en) Enhanced stacked microelectronic assemblies with central contacts and improved thermal characteristics
US9281266B2 (en) Stacked chip-on-board module with edge connector
TWI503947B (en) Multiple die stacking for two or more die in microelectronic packages, modules, and systems
CN103620774A (en) Flip-chip, face-up and face-down wirebond combination package
JP2003110084A (en) Semiconductor device
TW202125758A (en) Organic interposers for integrated circuit packages
KR101811738B1 (en) Enhanced stacked microelectric assemblies with central contacts
KR101088353B1 (en) Enhanced stacked microelectronic assemblies with central contacts and improved ground or power distribution
KR20120068685A (en) Enhanced stacked microelectric assemblies with central contacts
KR20120068664A (en) Enhanced stacked microelectronic assemblies with central contacts and improved ground or power distribution

Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees