TWI478251B - Casting mold device for packaging semiconductor elements - Google Patents
Casting mold device for packaging semiconductor elements Download PDFInfo
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- TWI478251B TWI478251B TW101112197A TW101112197A TWI478251B TW I478251 B TWI478251 B TW I478251B TW 101112197 A TW101112197 A TW 101112197A TW 101112197 A TW101112197 A TW 101112197A TW I478251 B TWI478251 B TW I478251B
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Description
本發明係有關於一種鑄模裝置，更具體而言，係一種用於封裝半導體元件之鑄模裝置。The present invention relates to a molding apparatus, and more particularly to a molding apparatus for packaging a semiconductor element.
在半導體製程中，半導體的晶片經由複數個導線將晶片上的輸入輸出單元(I/O)連接至基板上，為防止晶片與導線受到環境與灰塵的影響，因此會將晶片與導線利用環氧樹脂封裝保護。傳統的封裝方法為將一定量的塑料置於加熱室加熱後，使該塑料融化，再以柱塞將熔膠經流道(runner)系統填入模穴，以覆蓋晶片與導線。最後，再經過加熱使塑料硬化，完成半導體封裝。In a semiconductor process, a semiconductor wafer is connected to an input/output unit (I/O) on a wafer via a plurality of wires. To prevent the wafer and the wires from being affected by the environment and dust, the wafer and the wire are made of epoxy. Resin package protection. The conventional packaging method is to melt a certain amount of plastic after being heated in a heating chamber, and then melt the plastic into a cavity through a runner system to cover the wafer and the wire with a plunger. Finally, the plastic is hardened by heating to complete the semiconductor package.
請參閱第4圖，現有的半導體封裝製程用之鑄模裝置4包括注膠腔410；以該注膠腔410為中心向外形成之複數流道420；形成於該鑄模裝置4之流道420下方之複數模穴440；以及連接各該模穴440與流道420之注膠孔4201，其中，該注膠腔410之開口係連通至該鑄模裝置4之底面。是種鑄模裝置4的缺點在於各該流道420的模穴440與注膠腔410之距離不同，導致封裝膠體430注入每一模穴440之時間也不一致，距注膠腔410較遠的模穴440可能因封裝膠體430受熱時間較長，樹脂逐漸固化，極易造成金線偏移(wire sweep)或在封裝件中產生空隙(void)，甚至無法填滿模穴440。而該空隙在之後的固化過程中容易發生爆米花效應(popcorn effect)；金線偏移則可能導致相鄰導線接觸造成短路，因而導致廢品，降低封裝良率。Referring to FIG. 4, the existing molding apparatus 4 for semiconductor packaging process includes a glue injection chamber 410; a plurality of flow channels 420 formed outwardly from the glue injection chamber 410; formed under the flow path 420 of the mold device 4 The plurality of cavity 440; and the injection hole 4201 connecting the cavity 440 and the flow channel 420, wherein the opening of the injection cavity 410 is connected to the bottom surface of the mold device 4. A disadvantage of the molding apparatus 4 is that the distance between the cavity 440 of each flow path 420 and the injection cavity 410 is different, and the time for the encapsulation colloid 430 to be injected into each cavity 440 is also inconsistent, and the mold is far from the injection cavity 410. The hole 440 may be heated for a long time by the encapsulant 430, and the resin gradually solidifies, which may easily cause a wire sweep or a void in the package, or even fill the cavity 440. The void is prone to popcorn effect during the subsequent curing process; gold wire offset may cause short circuit contact between adjacent wires, resulting in waste and lowering package yield.
Tsuji等人於第5,672,550號美國專利中揭露將注膠腔設置於各封裝陣列之中間位置，以平均拉近與各個模穴間之間距，藉以縮短流道長度並且使樹脂到達各個模穴間的時間均相同。然而，其流道設計，仍難以完全避免上述缺陷之形成。In U.S. Patent No. 5,672,550, the disclosure of the entire disclosure of the entire disclosure of the entire disclosure of the entire disclosure of the disclosure of the disclosure of the disclosure of the disclosure of The time is the same. However, with its runner design, it is still difficult to completely avoid the formation of the aforementioned defects.
另一種改善方式則係如Yokoyama等人在第5,470,219號美國專利所揭示者，藉由加設加熱與冷卻單元，以控制流道中膠體之溫度，以調整黏度與固化度等流動特性。然而，此裝置之架設極為複雜，在溫度控制上也極為耗能，在無量好隔熱或距離控制時亦可能有熱交換不完全之問題，尤其是在冷卻與加熱間往往造成無謂的能量浪費。由於此方法須要較精密的控制以及能量的給予，故使整體之製造成本也隨之增加。In another embodiment, the heating and cooling unit is added to control the temperature of the colloid in the flow path to adjust the flow characteristics such as viscosity and degree of solidification, as disclosed in U.S. Patent No. 5,470,219. However, the installation of this device is extremely complicated, and it is also extremely energy-intensive in temperature control. In the case of insufficiency of heat insulation or distance control, there may be problems of incomplete heat exchange, especially in the case of cooling and heating, which often causes unnecessary energy waste. . Since this method requires more precise control and energy giving, the overall manufacturing cost is also increased.
因此，鑒於上述之問題，如何提供一種用於封裝半導體元件之鑄模裝置，使封裝膠體注入各該模穴的時間相同，以完整包覆每一個半導體元件，提升封裝品質，實已成為目前亟欲解決之課題。Therefore, in view of the above problems, how to provide a molding apparatus for packaging semiconductor components, the same time for injecting the encapsulant into each of the cavities, to completely cover each of the semiconductor components, and to improve the package quality has become a current desire Solve the problem.
本發明提供一種用於封裝半導體元件之鑄模裝置，包括：第一模具，係具有相對之第一表面及第二表面，且該第一模具具有：形成於該第一模具中以容納封裝膠體之至少一注膠腔，且該注膠腔具有連通至該第一表面之開口；位於該注膠腔正下方之複數第一模穴，且具有連通至該第二表面之凹穴；以及各別形成於該第一模具中之澆口，以各別連通該注膠腔及複數第一模穴；第二模具，係具有對應該複數第一模穴之複數第二模穴；以及柱塞，係可移動地設於該注膠腔之開口內，俾自該開口向該複數澆口擠壓該封裝膠體至該複數第一模穴。The present invention provides a molding apparatus for packaging a semiconductor component, comprising: a first mold having opposite first and second surfaces, and the first mold having: formed in the first mold to accommodate the encapsulant At least one injection cavity, the injection cavity having an opening connected to the first surface; a plurality of first cavity directly below the injection cavity, and having a cavity connected to the second surface; a gate formed in the first mold to respectively connect the injection cavity and the plurality of first cavities; the second mold has a plurality of second cavities corresponding to the plurality of first cavities; and a plunger And being movably disposed in the opening of the glue injection chamber, and pressing the encapsulation colloid from the opening to the plurality of gates to the plurality of first cavities.
本發明之用於封裝半導體元件之鑄模裝置係將澆口形成於該第一模具中，且上下連通該注膠腔及複數第一模穴，由於該澆口位於該注膠腔及複數第一模穴之間，各該第一模穴與注膠腔之間距差異不大，因而可以直接將熔融之封裝膠體灌注至複數第一模穴，因此無習知技術造成封裝膠體因流道過長固化度變高之顧慮。本發明之鑄模裝置可使封裝膠體注入各該第一模穴的時間相同，可令每一個半導體元件被封裝膠體完整包覆，大幅提升封裝品質。The mold device for packaging a semiconductor component of the present invention has a gate formed in the first mold, and communicates the injection cavity and the plurality of first cavity up and down, since the gate is located in the injection cavity and the first plurality Between the cavities, there is little difference between the first cavity and the injection cavity, so that the molten encapsulant can be directly poured into the plurality of first cavities, so that the encapsulation colloid is too long due to the flow path. The concern that the degree of cure becomes high. The mold device of the invention can inject the encapsulant into the first cavity at the same time, so that each semiconductor component is completely covered by the encapsulant, thereby greatly improving the package quality.
以下係藉由特定之具體實施例詳細說明本發明之技術內容及實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明的優點及功效。本發明亦可藉由其它不同的具體實施例加以施行或應用，本說明書中的各項細節亦可基於不同觀點與應用，在不悖離本發明之精神下進行各種修飾與變更。The technical contents and embodiments of the present invention are described in detail below by way of specific embodiments, and those skilled in the art can readily understand the advantages and functions of the present invention from the disclosure of the present disclosure. The present invention may be embodied or applied in various other specific embodiments, and various modifications and changes can be made without departing from the spirit and scope of the invention.
須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如“上”、“下”、“第一”、“第二”及“一”等之用語，亦僅為便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。It is to be understood that the structure, the proportions, the size, and the like of the present invention are intended to be used in conjunction with the disclosure of the specification, and are not intended to limit the invention. The conditions are limited, so it is not technically meaningful. Any modification of the structure, change of the proportional relationship or adjustment of the size should remain in this book without affecting the effects and the objectives that can be achieved by the present invention. The technical content disclosed in the invention can be covered. In the meantime, the terms "upper", "lower", "first", "second" and "one" are used in the description for convenience of description, and are not intended to limit the invention. Changes in the scope of implementation, changes or adjustments in their relative relationship, are considered to be within the scope of the present invention.
本發明之第一實施例係如第1A圖所示，本發明之用於封裝半導體元件之鑄模裝置具有第一模具110與第二模具120，其中，該第一模具110具有第一表面110a及第二表面110b。該第一模具110之中形成有一凹槽空間，並具有連通至該第一模具110之第一表面110a的開口，作為裝載封裝膠體之注膠腔111。於該注膠腔111之正下方，該第一模具110之第二表面110b形成有複數第一模穴113，並且設有一澆口112於該注膠腔111下及第一模穴113上，各別直接連通該注膠腔111及複數第一模穴113，以提供封裝膠體直接灌注而不須另外透過流道進行傳輸。該第二模具120具有複數第二模穴123，係對應該複數第一模穴113，例如對應至第一模穴113連通至第二表面110b之凹穴，第一模穴113和第二模穴123兩者可結合形成一容納空間，提供待封裝之半導體晶片等元件之置放。A first embodiment of the present invention is as shown in FIG. 1A. The mold apparatus for packaging a semiconductor component of the present invention has a first mold 110 and a second mold 120, wherein the first mold 110 has a first surface 110a and Second surface 110b. A recess space is formed in the first mold 110, and has an opening connected to the first surface 110a of the first mold 110 as a glue injection chamber 111 for loading the encapsulant. The second surface 110b of the first mold 110 is formed with a plurality of first cavities 113, and a gate 112 is disposed under the injection cavity 111 and the first cavity 113. The injection chamber 111 and the plurality of first cavities 113 are directly connected to each other to provide direct encapsulation of the encapsulant without additional transmission through the flow channel. The second mold 120 has a plurality of second cavities 123 corresponding to the plurality of first cavities 113, for example, corresponding to the cavities of the first cavities 113 connected to the second surface 110b, the first cavities 113 and the second molds. The holes 123 can be combined to form a receiving space for providing placement of components such as semiconductor wafers to be packaged.
如第1B圖所示，本發明之鑄模裝置復包括可移動地設於該注膠腔111之第一表面110a開口內的柱塞140，俾自該注膠腔111之開口向該複數澆口112擠壓該封裝膠體130至複數第一模穴113。亦即待封裝之半導體晶片114係置於該第一模穴113與第二模穴123之結合空間中，於注膠腔111中裝載封裝膠體130，並將柱塞140可移動地設於注膠腔111，以柱塞140自該第一模具110之第一表面110a處之之開口擠壓封裝膠體130，封裝膠體130經澆口112由上至下灌注至第一模穴113與第二模穴123之結合空間中。之後可依加熱固化步驟固化封裝膠體130，並分離該第一模具110與第二模具120，取出半導體封裝件。As shown in FIG. 1B, the mold apparatus of the present invention further includes a plunger 140 movably disposed in the opening of the first surface 110a of the glue injection chamber 111, and the opening from the injection chamber 111 to the plurality of gates 112 encapsulates the encapsulant 130 to a plurality of first cavities 113. That is, the semiconductor wafer 114 to be packaged is placed in the joint space of the first cavity 113 and the second cavity 123, the encapsulant 130 is loaded in the injection cavity 111, and the plunger 140 is movably disposed on the injection. The adhesive cavity 111 is extruded from the opening of the first surface 110a of the first mold 110 by the plunger 140, and the encapsulant 130 is poured into the first cavity 113 and the second through the gate 112 from the top to the bottom. The cavity 123 is in the combined space. Then, the encapsulant 130 can be cured according to the heat curing step, and the first mold 110 and the second mold 120 are separated, and the semiconductor package is taken out.
本發明復提供較佳之實施方式，如第2圖所示，本發明之第一模具210提供複數個注膠腔211，每一個注膠腔211皆配有複數個澆口212，且單一該注膠腔211係供注膠至該複數第一模穴213，俾藉由至少一該澆口212連通各該第一模穴213和注膠腔211，且由於該注膠腔211之橫截面面積大於至少二該澆口212之佈設範圍，各該澆口212之長度不會過長，各該第一模穴213和注膠腔211的間距相同，於利用柱塞240擠壓封裝膠體130時，封裝膠體130注入第一模穴213與第二模穴223構成之結合空間的時間相同，可在同一時間內進行大量的半導體元件封裝，且可令每一個半導體元件被封裝膠體完整包覆，大幅提升封裝品質。The present invention provides a preferred embodiment. As shown in FIG. 2, the first mold 210 of the present invention provides a plurality of glue injection chambers 211, each of which is provided with a plurality of gates 212, and the single gate is provided. The glue chamber 211 is for injection molding to the plurality of first cavity 213, and the first cavity 213 and the glue injection cavity 211 are connected by at least one gate 212, and the cross-sectional area of the injection cavity 211 is The length of each of the gates 212 is not too long, and the distance between each of the first cavity 213 and the glue injection cavity 211 is the same. When the package body 130 is squeezed by the plunger 240, the package body 130 is squeezed by the plunger 240. The encapsulation colloid 130 is injected into the bonding space formed by the first cavity 213 and the second cavity 223 for the same time, and a large number of semiconductor components can be packaged at the same time, and each semiconductor component can be completely covered by the encapsulant. Greatly improve the quality of the package.
於另一較佳之實施方式中，如第3圖所示，在封裝較大型的元件(如晶圓314)時，可使用較大之第一模穴313，至少兩個該澆口312連通該相同之注膠腔311及相同之第一模穴313，並與對應的第二模穴323結合。俾於封裝較 大型的元件時，元件的各個部分亦獲良好的包覆。於一具體實施例中，該澆口312係可連通至第一模穴313之角落In another preferred embodiment, as shown in FIG. 3, when packaging a larger component (such as wafer 314), a larger first cavity 313 can be used, at least two of which are connected to the gate 312. The same injection cavity 311 and the same first cavity 313 are combined with the corresponding second cavity 323.封装In the package comparison In the case of large components, the various parts of the component are also well covered. In a specific embodiment, the gate 312 is connectable to the corner of the first cavity 313
本發明之用於封裝半導體元件之鑄模裝置設計主要係令注膠腔下方直接對應模穴，且澆口由上至下連通注膠腔和模穴，縮短封裝膠體輸送距離，且較佳地，注膠腔到各該模穴的距離大致相同，則封裝膠體注入每一模穴的時間一致，避免使用長度較長的流道導致封裝膠體受熱固化度變高，使金線偏移或產生空隙等降低封裝良率等問題，故而提升封裝品質。The mold device for packaging a semiconductor component of the present invention is mainly designed to directly correspond to the cavity below the injection cavity, and the gate communicates the injection cavity and the cavity from top to bottom, shortening the distance of the package colloid, and preferably, The distance between the injection cavity and each cavity is substantially the same, and the time for the encapsulation gel to be injected into each cavity is the same. Avoiding the use of a long length of the flow channel leads to a high degree of heat curing of the encapsulant, causing the gold wire to shift or create a void. Such as to reduce the package yield and other issues, thus improving the package quality.
上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。The above embodiments are intended to illustrate the principles of the invention and its effects, and are not intended to limit the invention. Any of the above-described embodiments may be modified by those skilled in the art without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be as set forth in the appended claims.
110,210‧‧‧第一模具110,210‧‧‧First mould
110a‧‧‧第一表面110a‧‧‧ first surface
110b‧‧‧第二表面110b‧‧‧ second surface
120‧‧‧第二模具120‧‧‧Second mold
111,211,311‧‧‧注膠腔111,211,311‧‧‧ injection cavity
112,212,312‧‧‧澆口112, 212, 312‧‧ ‧ gate
113,213,313‧‧‧第一模穴113,213,313‧‧‧ first cavity
123,223,323‧‧‧第二模穴123,223,323‧‧‧Second cavity
114‧‧‧半導體晶片114‧‧‧Semiconductor wafer
130‧‧‧封裝膠體130‧‧‧Package colloid
140,240‧‧‧柱塞140,240‧‧‧Plunger
314‧‧‧晶圓314‧‧‧ wafer
4‧‧‧鑄模裝置4‧‧‧Molding device
410‧‧‧注膠腔410‧‧‧ injection cavity
420‧‧‧流道420‧‧‧ flow path
4201‧‧‧注膠孔4201‧‧‧ injection hole
430‧‧‧封裝膠體430‧‧‧Package colloid
440‧‧‧模穴440‧‧‧ cavity
第1A及1B圖係為本發明之用於封裝半導體元件之鑄模裝置的剖視圖，其中，第1A圖係顯示模具構造示意圖，第1B圖係顯示柱塞擠壓封裝膠體之示意圖；第2圖係顯示本發明之具有複數注膠腔之鑄模裝置；第3圖係顯示本發明之具有複數澆口連通相同注膠腔及相同第一模穴之鑄模裝置；以及第4圖係顯示習知半導體封裝裝置之剖視圖。1A and 1B are cross-sectional views showing a molding apparatus for packaging a semiconductor element of the present invention, wherein FIG. 1A is a schematic view showing a mold structure, and FIG. 1B is a schematic view showing a plunger extrusion encapsulant; A molding apparatus having a plurality of injection chambers of the present invention is shown; FIG. 3 is a view showing a molding apparatus having a plurality of gates connected to the same injection cavity and the same first cavity; and FIG. 4 is a view showing a conventional semiconductor package A cross-sectional view of the device.
110．．．第一模具110. . . First mold
110a．．．第一表面110a. . . First surface
110b．．．第二表面110b. . . Second surface
120．．．第二模具120. . . Second mold
111．．．注膠腔111. . . Injection cavity
112．．．澆口112. . . Gate
113．．．第一模穴113. . . First cavity
123．．．第二模穴123. . . Second cavity
114．．．半導體晶片114. . . Semiconductor wafer
130．．．封裝膠體130. . . Encapsulant
140．．．柱塞140. . . Plunger
Claims (5)
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW101112197A TWI478251B (en) | 2012-04-06 | 2012-04-06 | Casting mold device for packaging semiconductor elements |
| CN2012101165248A CN103358467A (en) | 2012-04-06 | 2012-04-19 | Mold apparatus for packaging semiconductor assembly |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW101112197A TWI478251B (en) | 2012-04-06 | 2012-04-06 | Casting mold device for packaging semiconductor elements |
Publications (2)
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| TWI575620B (en) * | 2016-03-10 | 2017-03-21 | 南茂科技股份有限公司 | Manufacturing method and manufacturing apparatus of fingerprint identification chip package structure |
| TW201735280A (en) * | 2016-03-31 | 2017-10-01 | Epimx Co Ltd | Hot melt adhesive packaging machine to push hot melt adhesive at low pressure massively and precisely for preventing the overflow by the linking-up motion of a pushing-pressing mechanism |
| EP3961682A1 (en) * | 2020-08-24 | 2022-03-02 | STMicroelectronics S.r.l. | A method of manufacturing semiconductor devices, and corresponding tool |
| CN116417352B (en) * | 2023-04-07 | 2023-10-13 | 江苏中科智芯集成科技有限公司 | Preparation method of semiconductor packaging structure |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| TW201139100A (en) * | 2010-05-03 | 2011-11-16 | Powertech Technology Inc | Transfer mold tooling having 3D runners |
| TW201145410A (en) * | 2010-06-11 | 2011-12-16 | Advanced Semiconductor Eng | Chip package mold chase |
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| CN100463129C (en) * | 2006-02-09 | 2009-02-18 | 夏普株式会社 | Semiconductor device manufacturing method and semiconductor device manufacturing apparatus |
| WO2010092853A1 (en) * | 2009-02-10 | 2010-08-19 | 三洋電機株式会社 | Frame package manufacturing method |
| CN101887861B (en) * | 2010-06-11 | 2012-01-11 | 日月光半导体制造股份有限公司 | Chip packaging mould |
| CN101973095B (en) * | 2010-08-26 | 2013-01-09 | 安徽中鼎泰克汽车密封件有限公司 | Armature rubber vulcanizing and spring assembling process for air-braking antilock brake system (ABS) electromagnetic valve |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW201139100A (en) * | 2010-05-03 | 2011-11-16 | Powertech Technology Inc | Transfer mold tooling having 3D runners |
| TW201145410A (en) * | 2010-06-11 | 2011-12-16 | Advanced Semiconductor Eng | Chip package mold chase |
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| CN103358467A (en) | 2013-10-23 |
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