TWI475726B - Light-emitting diode and a method of manufacturing the same - Google Patents
Light-emitting diode and a method of manufacturing the same Download PDFInfo
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Description
本發明係有關一種發光二極體，特別是關於一種使用凹坑(pitted)層以降低缺陷密度的發光二極體及其製造方法。 The present invention relates to a light-emitting diode, and more particularly to a light-emitting diode using a pitted layer to reduce the defect density and a method of manufacturing the same.
於藍寶石基板上磊晶氮化鎵層是製造發光二極體(LED)的常用製程技術。然而，氮化鎵磊晶層與藍寶石基板兩者之間的晶格常數與熱膨脹係數(CTE)存在有極大差異，因此，會於氮化鎵磊晶層內產生高密度的線差排缺陷(threading dislocation)，其密度可高達109~1011/平方公分。此種高密度線差排缺陷會大大限制了發光二極體的發光效率。此外，發光二極體所使用的半導體材質具有高折射係數，會使發光二極體所產生的光受到侷限(trapped)。因此，從主動區所發射的大部分光線，將被侷限於半導體內部，且這些被侷限的光有可能會被較厚的基板所吸收。 The epitaxial gallium nitride layer on a sapphire substrate is a common process technology for fabricating light-emitting diodes (LEDs). However, the lattice constant between the gallium nitride epitaxial layer and the sapphire substrate is greatly different from the coefficient of thermal expansion (CTE), and therefore, a high-density line difference discharge defect is generated in the gallium nitride epitaxial layer ( Threading dislocation), its density can be as high as 109~1011/cm ^ 2 . Such high-density line-difference defects greatly limit the luminous efficiency of the light-emitting diode. In addition, the semiconductor material used in the light-emitting diode has a high refractive index, which causes the light generated by the light-emitting diode to be trapped. Therefore, most of the light emitted from the active region will be confined to the interior of the semiconductor, and these confined lights may be absorbed by the thicker substrate.
為了解決上述問題，通常在磊晶前先進行藍寶石基板的蝕刻圖形化，以形成圖案化藍寶石基板(patterned sapphire substrate，PSS)。圖樣化藍寶石基板可藉橫向磊晶生長(epitaxial lateral overgrown)降低氮化鎵晶格中錯位之密度，達到增加輻射結合，提升內部量子效率。此外，藉由基板表面幾何形狀之 變化，可以改變發光二極體的散射機制，使主動區所產生的大部分光線都能射出，因而增加光萃取效率(light extraction efficiency)。 In order to solve the above problem, the sapphire substrate is usually patterned by etching before epitaxy to form a patterned sapphire substrate (PSS). The patterned sapphire substrate can reduce the density of misalignment in the gallium nitride crystal lattice by epitaxial lateral overgrown, thereby increasing the radiation bonding and improving the internal quantum efficiency. In addition, by the surface geometry of the substrate The change can change the scattering mechanism of the light-emitting diode, so that most of the light generated by the active region can be emitted, thereby increasing the light extraction efficiency.
然而，雖然位於圖案化藍寶石基板之平坦表面上方的缺陷密度很低，但是，位於圖案化藍寶石基板之突出形狀上方的缺陷密度卻相當高，且該缺陷會傳播擴散至發光二極體元件內，因此，亟需提出一種新穎的發光二極體結構及其製造方法，用以進一步降低圖案化藍寶石基板之突出形狀上方的缺陷密度。 However, although the defect density above the flat surface of the patterned sapphire substrate is very low, the defect density above the protruding shape of the patterned sapphire substrate is quite high, and the defect propagates and diffuses into the light emitting diode element. Therefore, there is a need to propose a novel light emitting diode structure and a method of fabricating the same to further reduce the defect density above the protruding shape of the patterned sapphire substrate.
本發明實施例提出一種發光二極體及其製造方法，特別關於一種氮化物發光二極體，用以降低缺陷密度，以提高發光二極體的發光效率。 Embodiments of the present invention provide a light emitting diode and a method of fabricating the same, and more particularly to a nitride light emitting diode for reducing defect density to improve luminous efficiency of a light emitting diode.
根據本發明實施例，發光二極體包含圖案化基板、至少一緩衝層、凹坑層及發光元件。其中，圖案化基板具有複數突出部分，且相鄰突出部分之間具有平坦區域。緩衝層形成於圖案化基板上，其中緩衝層至少填滿圖案化基板之突出部分之間的空隙。具複數凹坑的凹坑層形成於緩衝層上。發光元件形成於凹坑層上並填滿凹坑。 According to an embodiment of the invention, the light emitting diode comprises a patterned substrate, at least one buffer layer, a pit layer and a light emitting element. Wherein, the patterned substrate has a plurality of protruding portions, and the adjacent protruding portions have a flat region therebetween. A buffer layer is formed on the patterned substrate, wherein the buffer layer fills at least a gap between the protruding portions of the patterned substrate. A pit layer having a plurality of pits is formed on the buffer layer. A light emitting element is formed on the pit layer and fills the pit.
100‧‧‧發光二極體 100‧‧‧Lighting diode
11‧‧‧圖案化基板 11‧‧‧ patterned substrate
111‧‧‧突出部分 111‧‧‧ highlight
112‧‧‧平坦區域 112‧‧‧flat area
11A‧‧‧基層 11A‧‧‧ grassroots
11B‧‧‧圖案層 11B‧‧‧ pattern layer
12‧‧‧緩衝層 12‧‧‧ Buffer layer
13‧‧‧成核層 13‧‧‧Nuclear layer
14‧‧‧凹坑層 14‧‧‧ pit layer
141‧‧‧凹坑 141‧‧‧ pit
15‧‧‧發光元件 15‧‧‧Lighting elements
151‧‧‧n型摻雜層 151‧‧‧n-type doped layer
152‧‧‧主動層 152‧‧‧ active layer
153‧‧‧p型摻雜層 153‧‧‧p-type doped layer
第一A圖至第一F圖的剖面圖顯示本發明實施例之形成低缺陷密度之發光二極體(IED)的各個製程步驟。 The cross-sectional views from the first A to the first F show various process steps for forming a low defect density light emitting diode (IED) according to an embodiment of the present invention.
第一A圖至第一F圖的剖面圖顯示本發明實施例之形成低缺陷密度之發光二極體(LED)100的各個製程步驟，圖式僅顯示與實施例相關的層級。 The cross-sectional views from the first A to the first F show various process steps for forming a low defect density light emitting diode (LED) 100 in accordance with an embodiment of the present invention, and the drawings only show the levels associated with the embodiments.
如第一A圖所示，首先提供一圖案化基板(patterned substrate)11，其具有複數突出部分111，例如錐狀體，其可為角錐體(pyramid)或圓錐體(cone)。突出部分111的頂部可以是尖銳的(如圖所示)，也可以是平坦的。相鄰突出部分111之間具有平坦區域112。在本實施例中，圖案化基板11為藍寶石經由蝕刻所形成的圖案化藍寶石基板(patterned sapphire substrate,PSS)，但不限定於此。 As shown in FIG. A, a patterned substrate 11 is first provided having a plurality of protruding portions 111, such as a tapered body, which may be a pyramid or a cone. The top of the protruding portion 111 may be sharp (as shown) or flat. A flat region 112 is provided between adjacent protruding portions 111. In the present embodiment, the patterned substrate 11 is a patterned sapphire substrate (PSS) formed by etching sapphire, but is not limited thereto.
第一B圖顯示另一種圖案化基板11，其係於基層11A上形成具有複數突出部分111的圖案層11B。其中，圖案層11B之突出部分111彼此間可以是相連的，也可以為分離的。基層11A與圖案層11B的材質可以是相同的，也可以為相異。一般來說，基層11A的材質可以為砷化鎵(GaAs)、鍺(Ge)表面形成鍺化矽(SiGe)、矽(Si)表面形成碳化矽(SiC)、鋁(A1)表面形成氧化鋁(Al2O3)、氮化鎵(GaN)、氮化銦(InN)、氮化鋁(AlN)、藍寶石(sapphire)、玻璃、石英或其組合，但不限定於此。圖案層11B的材質可以為二氧化矽(SiO2)、碳化矽(SiC)、氮化矽(SiNx)或其組合，但不以此為限。 The first B diagram shows another patterned substrate 11 which is formed on the base layer 11A to form a pattern layer 11B having a plurality of protruding portions 111. The protruding portions 111 of the pattern layer 11B may be connected to each other or may be separated. The material of the base layer 11A and the pattern layer 11B may be the same or different. Generally, the material of the base layer 11A may be gallium arsenide (GaAs), germanium (Ge) surface forming germanium telluride (SiGe), germanium (Si) surface forming tantalum carbide (SiC), and aluminum (A1) surface forming aluminum oxide. (Al 2 O 3 ), gallium nitride (GaN), indium nitride (InN), aluminum nitride (AlN), sapphire, glass, quartz or a combination thereof, but is not limited thereto. The material of the pattern layer 11B may be cerium oxide (SiO2), tantalum carbide (SiC), tantalum nitride (SiNx) or a combination thereof, but is not limited thereto.
接下來，如第一C圖所示，形成至少一緩衝層12於圖案化基板11上，其中緩衝層12至少填滿圖案化基板11之突出部分111間的空隙。換句話說，緩衝層12的頂面等於或高於圖案化基板11之突出部分111的頂部，因而形成具平坦頂面的緩衝層12。在一實施例中，緩衝層12高於 突出部分111之高度等於或大於5奈米，較佳為等於或大於10奈米。在另一實施例中，緩衝層12高於突出部分111之高度等於或小於100奈米，較佳為等於或小於50奈米。在本實施例中，緩衝層12的形成係於大約1080℃的溫度下磊晶成長。緩衝層包含未摻雜氮化鎵、n型氮化鎵、氮化鋁、氮化鋁鎵、氮化鎂、氮化矽或其任意組合。對於第一C圖所示的結構，緩衝層12位於突出部分111上方所具有的缺陷遠較平坦區域112上方的缺陷來得多。 Next, as shown in FIG. C, at least one buffer layer 12 is formed on the patterned substrate 11, wherein the buffer layer 12 fills at least the gap between the protruding portions 111 of the patterned substrate 11. In other words, the top surface of the buffer layer 12 is equal to or higher than the top of the protruding portion 111 of the patterned substrate 11, thus forming the buffer layer 12 having a flat top surface. In an embodiment, the buffer layer 12 is higher than The height of the protruding portion 111 is equal to or greater than 5 nm, preferably equal to or greater than 10 nm. In another embodiment, the height of the buffer layer 12 above the protruding portion 111 is equal to or less than 100 nm, preferably equal to or less than 50 nm. In the present embodiment, the formation of the buffer layer 12 is epitaxially grown at a temperature of approximately 1080 °C. The buffer layer comprises undoped gallium nitride, n-type gallium nitride, aluminum nitride, aluminum gallium nitride, magnesium nitride, tantalum nitride or any combination thereof. For the structure shown in the first C-picture, the buffer layer 12 has a defect located above the protruding portion 111 much more than a defect above the flat region 112.
第一D圖顯示第一C圖的另一種實施態樣，亦即，於形成緩衝層12之前，更額外形成一成核(nucleation)層13於圖案化基板11上，例如形成於圖案化基板11之突出部分111的表面。於部分範例中，成核層13亦可形成於圖案化基板11之平坦區域112的表面。在本實施例中，於大約500℃的溫度下，磊晶成長厚度大約為40~90奈米(nm)的成核層13於圖案化基板11上。接著，於大約1050℃的溫度下，對成核層13進行再結晶(recrystallization)製程。 The first D diagram shows another embodiment of the first C-picture, that is, a nucleation layer 13 is additionally formed on the patterned substrate 11 before forming the buffer layer 12, for example, on the patterned substrate. The surface of the protruding portion 111 of 11. In some examples, the nucleation layer 13 may also be formed on the surface of the planar region 112 of the patterned substrate 11. In the present embodiment, the nucleation layer 13 having a thickness of about 40 to 90 nanometers (nm) is epitaxially grown on the patterned substrate 11 at a temperature of about 500 °C. Next, the nucleation layer 13 is subjected to a recrystallization process at a temperature of about 1050 °C.
請再回到第一C圖，如同前述，緩衝層12位於突出部分111上方所具有的缺陷遠較平坦區域112上方的缺陷來得多。此種缺陷可稱為差排亦可稱位錯(Dislocation)，在材料科學中，指晶體材料的一種內部微觀缺陷，即原子的局部不規則排列(晶體學缺陷)。從幾何角度看，可視為晶體中已滑移部分與未滑移部分的分界線，差排主要有3種形式：刃差排(Edge type dislocations)、螺旋差排(Screw type dislocations)以及混合差排(Mixed type dislocations)。由差排(dislocation)的理論可知，差排不會終止於晶體內部，會形成差排環(dislocation loops)、分支到其他 差排處或延伸至晶體表面。在異質磊晶中，基板和磊晶薄膜之間晶格不匹配所產生的應變經常成會引起差排的產生。當磊晶薄膜持續成長到超越臨界厚度時，將會使位於基板和磊晶薄膜界面之間的差排延伸，其移動方式將會貫穿整個晶體而到達晶體的頂端或表面。因此，這部份差排就被稱之為貫穿式差排(threading dislocation)。 Returning to the first C diagram, as before, the buffer layer 12 has a defect located above the protruding portion 111 much more than the defect above the flat region 112. Such defects can be referred to as dislocations, or dislocations. In materials science, an internal microscopic defect of a crystalline material, that is, a local irregular arrangement of atoms (crystallographic defects). From a geometric point of view, it can be regarded as the boundary between the slipped part and the unsliding part of the crystal. There are three main types of difference: Edge type dislocations, Screw type dislocations, and mixing differences. Mixed type dislocations. According to the theory of dislocation, the difference does not end inside the crystal, which will form dislocation loops and branch to other Displace or extend to the surface of the crystal. In heteroepitaxial epitaxy, the strain generated by the lattice mismatch between the substrate and the epitaxial film often causes the generation of a poor row. As the epitaxial film continues to grow beyond the critical thickness, the difference between the substrate and the epitaxial film interface will extend, moving through the entire crystal to the top or surface of the crystal. Therefore, this part of the difference is called threading dislocation.
差排缺陷在氮化物成長扮演重要的角色，很多氮化物的異質結構需要降低成長溫度，此種低溫成長會在差排頂端造成凹坑(pit)，例如：“V型缺陷(V-defect)”的形成，此種缺陷乃以六個同系列的平面構成，呈現一六角型的形貌。此種缺陷形成與差排極度相關，大多產生於混合差排，但仍有少部分形成在刃差排之上。Wuet al.認為此種缺陷乃因成長過程的動力學極限導致表面隨差排位置呈現一低陷的現象。由於成長的動力學極限導致表面形貌以最慢成長的平面所決定，所以若在之後成長高溫GaN，V型缺陷將被填平而不在表面所發現。 Dislocation defects play an important role in nitride growth. Many nitride heterostructures need to lower the growth temperature. Such low temperature growth will cause pits at the top of the difference, for example: "V-defect" The formation of such defects is composed of six planes of the same series, showing a hexagonal shape. Such defect formation is extremely correlated with the difference row, and is mostly generated by the mixed difference row, but a small portion is still formed above the edge difference row. Wu et al. believe that this defect is caused by the kinetic limit of the growth process, which causes the surface to exhibit a low trapping position. Since the kinetic limit of growth causes the surface topography to be determined by the slowest growing plane, if high temperature GaN is grown later, the V-type defects will be filled and not found on the surface.
請參考第一E圖所示，於凹坑(pit)成長條件下形成凹坑層14於緩衝層12上，凹坑層14的凹坑141大部分集中在圖案化基板11之突出部分111的上方，在平坦區域112上方的凹坑數目很少，兩者的凹坑分佈密度可以差別到1或2個數量級。於本發明中，凹坑層14的存在有效地阻止許多差排延伸進入後續成長的磊晶層。 Referring to FIG. E, a pit layer 14 is formed on the buffer layer 12 under pit growth conditions, and the pits 141 of the pit layer 14 are mostly concentrated on the protruding portion 111 of the patterned substrate 11. Above, the number of pits above the flat region 112 is small, and the pit density of the two can be different by one or two orders of magnitude. In the present invention, the presence of the pit layer 14 effectively prevents many of the rows from extending into the subsequently growing epitaxial layer.
在本實施例中，凹坑層14的凹坑成長條件可藉由控制溫度或/且成長速率來達到。在一實施例中，凹坑層14的成長溫度介於500~900℃，較佳為800-900℃。在另一實施例中，凹坑層14(例如氮化鎵，但不限定於此)的成長速率介於1~6微米/小時，較佳為4~6微米/小時。本實 施例之凹坑層14的厚度小於或等於6微米，較佳為小於或等於3微米。本實施例之凹坑層14的凹坑141孔徑小於或等於6微米，較佳為小於或等於3微米。換句話說，本實施例之凹坑141的高度大約相等於其孔徑。 In the present embodiment, the pit growth condition of the pit layer 14 can be achieved by controlling the temperature or/and the growth rate. In one embodiment, the pit layer 14 has a growth temperature between 500 and 900 ° C, preferably between 800 and 900 ° C. In another embodiment, the pit layer 14 (e.g., gallium nitride, but not limited thereto) has a growth rate of from 1 to 6 microns per hour, preferably from 4 to 6 microns per hour. Real The thickness of the pit layer 14 of the embodiment is less than or equal to 6 microns, preferably less than or equal to 3 microns. The pit 141 of the pit layer 14 of the present embodiment has a pore diameter of less than or equal to 6 μm, preferably less than or equal to 3 μm. In other words, the height of the dimples 141 of the present embodiment is approximately equal to its aperture.
如第一F圖所示，形成發光元件15於凹坑層14上，並填滿凹坑層14的凹坑141。在本實施例中，於大約1080℃的溫度下，首先形成n型摻雜層151於凹坑層14上，接著形成主動層152於n型摻雜層151上，再形成p型摻雜層153於主動層152上。於部分範例中，n型摻雜層151填滿凹坑141。於部分範例中，發光元件15的形成方法包含首先形成一中間層(未顯示於圖中)於凹坑層14上，中間層用以填滿凹坑141，接著形成一n型摻雜層151於中間層上，其次形成一主動層152於n型摻雜層151上，然後形成一p型摻雜層153於主動層152上。中間層、n型摻雜層151、主動層152及p型摻雜層153的材質可以為III族氮化物，但不限定於此。如前所述，由於凹坑層14可有效阻隔因突出部分111所造成缺陷的傳播擴散，因而得以大量地降低本實施例所形成之n型摻雜層151(以及後續的主動層152及p型摻雜層153)的缺陷密度，例如使得n型摻雜層151的缺陷密度小於或等於5*105/平方公分。 As shown in the first F diagram, the light-emitting element 15 is formed on the pit layer 14 and fills the pits 141 of the pit layer 14. In this embodiment, an n-type doped layer 151 is first formed on the pit layer 14 at a temperature of about 1080 ° C, and then an active layer 152 is formed on the n-type doped layer 151 to form a p-type doped layer. 153 is on the active layer 152. In some examples, the n-doped layer 151 fills the pits 141. In some examples, the method of forming the light-emitting element 15 includes first forming an intermediate layer (not shown) on the pit layer 14, the intermediate layer filling the pits 141, and then forming an n-type doped layer 151. On the intermediate layer, an active layer 152 is formed on the n-type doped layer 151, and then a p-type doped layer 153 is formed on the active layer 152. The material of the intermediate layer, the n-type doping layer 151, the active layer 152, and the p-type doping layer 153 may be a group III nitride, but is not limited thereto. As described above, since the pit layer 14 can effectively block the propagation diffusion of the defects caused by the protruding portion 111, the n-type doping layer 151 formed in the present embodiment (and the subsequent active layers 152 and p) can be largely reduced. The defect density of the doping layer 153) is, for example, such that the defect density of the n-type doping layer 151 is less than or equal to 5*105/cm 2 .
以上所述僅為本發明之較佳實施例而已，並非用以限定本發明之申請專利範圍；凡其它未脫離發明所揭示之精神下所完成之等效改變或修飾，均應包含在下述之申請專利範圍內。 The above description is only the preferred embodiment of the present invention, and is not intended to limit the scope of the present invention; all other equivalent changes or modifications which are not departing from the spirit of the invention should be included in the following Within the scope of the patent application.
100‧‧‧發光二極體 100‧‧‧Lighting diode
11‧‧‧圖案化基板 11‧‧‧ patterned substrate
111‧‧‧突出部分 111‧‧‧ highlight
112‧‧‧平坦區域 112‧‧‧flat area
12‧‧‧緩衝層 12‧‧‧ Buffer layer
14‧‧‧凹坑層 14‧‧‧ pit layer
141‧‧‧凹坑 141‧‧‧ pit
15‧‧‧發光元件 15‧‧‧Lighting elements
151‧‧‧n型摻雜層 151‧‧‧n-type doped layer
152‧‧‧主動層 152‧‧‧ active layer
153‧‧‧p型摻雜層 153‧‧‧p-type doped layer
Claims (23)
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| TW101116585A TWI475726B (en) | 2012-05-09 | 2012-05-09 | Light-emitting diode and a method of manufacturing the same |
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| TW101116585A TWI475726B (en) | 2012-05-09 | 2012-05-09 | Light-emitting diode and a method of manufacturing the same |
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| TW201347234A TW201347234A (en) | 2013-11-16 |
| TWI475726B true TWI475726B (en) | 2015-03-01 |
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| TWI626767B (en) * | 2017-07-17 | 2018-06-11 | Crystalwise Tech Inc | Ultraviolet light-emitting diode and its substrate and the substrate thereof law |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW200908374A (en) * | 2007-08-07 | 2009-02-16 | Jinn-Kong Sheu | Light emitting diode and method for fabricating the same |
| CN100563036C (en) * | 2007-07-11 | 2009-11-25 | 中国科学院半导体研究所 | A kind of method of utilizing patterned substrate to improve GaN base LED luminous efficiency |
| CN101866831A (en) * | 2009-04-20 | 2010-10-20 | 武东星 | Epitaxial substrate with low surface defect density and manufacturing method thereof |
| US20110263128A1 (en) * | 2010-04-22 | 2011-10-27 | Luminus Devices, Inc. | Selective wet etching and textured surface planarization processes |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100563036C (en) * | 2007-07-11 | 2009-11-25 | 中国科学院半导体研究所 | A kind of method of utilizing patterned substrate to improve GaN base LED luminous efficiency |
| TW200908374A (en) * | 2007-08-07 | 2009-02-16 | Jinn-Kong Sheu | Light emitting diode and method for fabricating the same |
| CN101866831A (en) * | 2009-04-20 | 2010-10-20 | 武东星 | Epitaxial substrate with low surface defect density and manufacturing method thereof |
| US20110263128A1 (en) * | 2010-04-22 | 2011-10-27 | Luminus Devices, Inc. | Selective wet etching and textured surface planarization processes |
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| TW201347234A (en) | 2013-11-16 |
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