TWI470819B - Semiconductor device, fabrication process, and electronic device - Google Patents

Semiconductor device, fabrication process, and electronic device Download PDF

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TWI470819B
TWI470819B TW101104458A TW101104458A TWI470819B TW I470819 B TWI470819 B TW I470819B TW 101104458 A TW101104458 A TW 101104458A TW 101104458 A TW101104458 A TW 101104458A TW I470819 B TWI470819 B TW I470819B
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semiconductor substrate
electrode layer
vertical hole
semiconductor
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TW201242062A (en
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Masaya Nagata
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Sony Corp
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    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
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    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
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    • H—ELECTRICITY
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    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14643—Photodiode arrays; MOS imagers
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    • H01L27/144—Devices controlled by radiation
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Description

半導體裝置，製造方法，以及電子裝置Semiconductor device, manufacturing method, and electronic device

本發明係關於半導體裝置、製造方法以及電子裝置，特定而言係關於可藉以減小製作成本之半導體裝置、製造方法以及電子裝置。The present invention relates to a semiconductor device, a manufacturing method, and an electronic device, and more particularly to a semiconductor device, a manufacturing method, and an electronic device which can reduce manufacturing costs.

以CMOS(互補金屬氧化物半導體)影像感測器為代表之固態成像裝置已開始使用WL-CSP(晶圓級晶片大小封裝)。WL-CSP涉及在自一半導體基板切掉晶片之前形成端子及佈線。Solid-state imaging devices typified by CMOS (Complementary Metal Oxide Semiconductor) image sensors have begun to use WL-CSP (Wafer Level Wafer Size Package). WL-CSP involves forming terminals and wiring before cutting a wafer from a semiconductor substrate.

WL-CSP製造步驟包含一製程，舉例而言，藉由該製程形成自一半導體基板之背部通向該半導體基板內部之金屬墊的一細垂直孔(通孔)。形成垂直孔係極大地影響半導體元件之製作成本之一製程。The WL-CSP fabrication step includes a process by which, for example, a fine vertical via (via) of a metal pad from the back of a semiconductor substrate to the interior of the semiconductor substrate is formed. Forming a vertical hole system greatly affects one of the manufacturing costs of the semiconductor element.

已使用DRIE(深反應性離子蝕刻)作為一前段製程來在一矽晶圓中形成垂直孔。然而，DRIE涉及高裝置成本。此外，DRIE需要一光微影步驟，其中在將一光敏物質施加至一矽晶圓表面之後以圖案形式將其曝光。DRIE (Deep Reactive Ion Etching) has been used as a front-end process to form vertical holes in a wafer. However, DRIE involves high device costs. In addition, DRIE requires a photolithography step in which a photosensitive material is exposed in a pattern after it is applied to a wafer surface.

作為一對策，已提出使用利用一雷射鑽之一基板成形技術來在一矽晶圓中形成一垂直孔之一製程。使用一雷射鑽之製程藉由一雷射光束之輻照在一基板中形成一垂直孔，且不需要一光微影步驟。此外，由於一雷射鑽裝置較便宜，因此雷射鑽製程比DRIE製程在製作成本方面有利得多。As a countermeasure, it has been proposed to use a substrate forming technique using a laser drill to form a vertical hole in a wafer. The process of using a laser drill forms a vertical hole in a substrate by irradiation of a laser beam, and does not require a photolithography step. In addition, because a laser drilling apparatus is relatively inexpensive, the laser drilling process is much more advantageous in terms of manufacturing cost than the DRIE process.

然而，舉例而言，藉助一雷射鑽非常難以以使得在垂直孔到達半導體基板內部之金屬墊時即停止鑽孔之此一準確度來控制該製程。However, by way of example, it is very difficult to control the process with the aid of a laser drill such that the vertical hole reaches the metal pad inside the semiconductor substrate, i.e., the accuracy of stopping the drilling.

就此而言，JP-A-2007-305995揭示一半導體裝置製造方法，藉由該方法將一金屬凸塊安置於一半導體基板內部之金屬墊上，且其中藉助到達該金屬凸塊之一雷射鑽來形成一垂直孔。在此方法中，金屬凸塊用作形成垂直孔之雷射鑽之一停止件。舉例而言，將一15 μm厚之電鍍鎳用作金屬凸塊。In this regard, JP-A-2007-305995 discloses a semiconductor device manufacturing method by which a metal bump is placed on a metal pad inside a semiconductor substrate, and by means of a laser drill reaching one of the metal bumps To form a vertical hole. In this method, the metal bumps serve as a stop for the laser drill that forms the vertical holes. For example, a 15 μm thick electroplated nickel is used as the metal bump.

然而，如前述公開案中所揭示使用一金屬凸塊作為雷射鑽之一停止件需要一低雷射輸出以避免穿透金屬凸塊。因此，垂直孔處理花費一長時間。形成用作金屬凸塊之15 μm厚的電鍍鎳亦花費一長時間。用於在一半導體基板中形成垂直孔之長處理時間增加了製作成本。However, the use of a metal bump as a stop for a laser drill as disclosed in the foregoing publication requires a low laser output to avoid penetration of the metal bump. Therefore, vertical hole processing takes a long time. It takes a long time to form a 15 μm thick electroplated nickel used as a metal bump. The long processing time for forming vertical holes in a semiconductor substrate increases the manufacturing cost.

設想增加金屬凸塊之厚度將避免即使在一高雷射鑽輸出下穿透金屬凸塊。然而，形成一厚金屬凸塊增加了額外時間。It is envisaged that increasing the thickness of the metal bumps will avoid penetrating the metal bumps even at a high laser drill output. However, forming a thick metal bump adds extra time.

因此，需要藉由減小垂直孔處理時間之方式來減小製作成本。Therefore, it is necessary to reduce the manufacturing cost by reducing the vertical hole processing time.

因此，期望提供減小製作成本之方式。Therefore, it is desirable to provide a way to reduce manufacturing costs.

本發明之一實施例係關於一種半導體裝置，其包含：一半導體基板，其包含一半導體；一電極層，其形成於該半導體基板內部之一第一表面側上；一框架層，其層壓於該 半導體基板之該第一表面上；一導體層，其形成於一孔隙部分中，該孔隙部分係藉由以使得在該半導體基板之該第一表面上曝露該電極層之一方式來處理該半導體基板及該框架層而形成；一垂直孔，其自該半導體基板之一第二表面至該導體層穿過該半導體基板而形成；及一佈線層，其在該垂直孔之一端部處經由該導體層電連接至該電極層，且其延伸至該半導體基板之該第二表面。An embodiment of the invention relates to a semiconductor device comprising: a semiconductor substrate comprising a semiconductor; an electrode layer formed on a first surface side of the interior of the semiconductor substrate; a frame layer laminated In this a first surface of the semiconductor substrate; a conductor layer formed in a void portion, the void portion being processed by exposing the electrode layer to the first surface of the semiconductor substrate Forming a substrate and the frame layer; forming a vertical hole formed from a second surface of the semiconductor substrate to the conductor layer through the semiconductor substrate; and a wiring layer passing through one end of the vertical hole A conductor layer is electrically connected to the electrode layer and extends to the second surface of the semiconductor substrate.

本發明之另一實施例係關於一種用於製造一半導體裝置之方法。該方法包含：在在包含一半導體之一半導體基板內部之一第一表面側上形成一電極層；將一框架層層壓於該半導體基板之該第一表面上；在一孔隙部分中形成一導體層，該孔隙部分係藉由以使得在該半導體基板之該第一表面上曝露該電極層之一方式來處理該半導體基板及該框架層而形成；自該半導體基板之一第二表面至該導體層穿過該半導體基板形成一垂直孔；形成一佈線層，該佈線層在該垂直孔之一端部處經由該導體層電連接至該電極層，且其延伸至該半導體基板之該第二表面。Another embodiment of the invention is directed to a method for fabricating a semiconductor device. The method includes: forming an electrode layer on a first surface side inside a semiconductor substrate including a semiconductor; laminating a frame layer on the first surface of the semiconductor substrate; forming a hole in a void portion a conductor layer formed by processing the semiconductor substrate and the frame layer in such a manner as to expose the electrode layer on the first surface of the semiconductor substrate; from a second surface of the semiconductor substrate to The conductor layer forms a vertical hole through the semiconductor substrate; forming a wiring layer electrically connected to the electrode layer via the conductor layer at one end of the vertical hole, and extending to the semiconductor substrate Two surfaces.

本發明之再一實施例係關於一種電子裝置，其包含一半導體裝置，該半導體裝置包含：一半導體基板，其包含一半導體；一電極層，其形成於該半導體基板內部之一第一表面側上；一框架層，其層壓於該半導體基板之該第一表面上；一導體層，其形成於一孔隙部分中，該孔隙部分係藉由以使得在該半導體基板之該第一表面上曝露該電極層之一方式來處理該半導體基板及該框架層而形成；一垂直 孔，其自該半導體基板之一第二表面至該導體層穿過該半導體基板而形成；及一佈線層，其在該垂直孔之一端部處經由該導體層電連接至該電極層，且其延伸至該半導體基板之該第二表面。Still another embodiment of the present invention relates to an electronic device including a semiconductor device including: a semiconductor substrate including a semiconductor; and an electrode layer formed on a first surface side of the semiconductor substrate a frame layer laminated on the first surface of the semiconductor substrate; a conductor layer formed in a void portion, the void portion being formed on the first surface of the semiconductor substrate Forming one of the electrode layers to process the semiconductor substrate and the frame layer; a vertical a hole formed from a second surface of the semiconductor substrate to the conductor layer through the semiconductor substrate; and a wiring layer electrically connected to the electrode layer via the conductor layer at one end of the vertical hole, and It extends to the second surface of the semiconductor substrate.

根據本發明之實施例，電極層形成於半導體基板內部之一第一表面側上，框架層層壓於半導體基板之第一表面上，且導體層形成於孔隙部分中，該孔隙部分係藉由以使得在半導體基板之第一表面上曝露電極層之一方式來處理半導體基板及框架層而形成。垂直孔係自該半導體基板之一第二表面至該導體層穿過該半導體基板而形成，且形成佈線層，該佈線層在該垂直孔之一端部處經由該導體層電連接至該電極層，且其延伸至該半導體基板之該第二表面。According to an embodiment of the invention, the electrode layer is formed on one of the first surface sides of the semiconductor substrate, the frame layer is laminated on the first surface of the semiconductor substrate, and the conductor layer is formed in the aperture portion, the aperture portion being The semiconductor substrate and the frame layer are formed by exposing the semiconductor layer to the first surface of the semiconductor substrate. a vertical hole is formed from a second surface of the semiconductor substrate to the conductive layer through the semiconductor substrate, and a wiring layer is formed, and the wiring layer is electrically connected to the electrode layer via the conductor layer at one end of the vertical hole And extending to the second surface of the semiconductor substrate.

根據本發明之實施例，可減小製作成本。According to an embodiment of the present invention, the manufacturing cost can be reduced.

下文將參照附圖詳細闡述本發明之一實施例。An embodiment of the present invention will be described in detail below with reference to the accompanying drawings.

圖1係圖解說明根據本發明之一實施例之一固態成像裝置之一例示性結構的一剖面圖。1 is a cross-sectional view illustrating an exemplary structure of a solid-state imaging device according to an embodiment of the present invention.

參照圖1，一固態成像裝置11經組態以包含偵測來自一被攝體之光的一感測器單元12，及藉由其自底部表面側提取來自感測器單元12之輸出信號的一垂直孔佈線單元13。感測器單元12及垂直孔佈線單元13在頂部表面側上覆蓋有一玻璃基板14。Referring to FIG. 1, a solid-state imaging device 11 is configured to include a sensor unit 12 that detects light from a subject, and by which an output signal from the sensor unit 12 is extracted from the bottom surface side. A vertical hole wiring unit 13. The sensor unit 12 and the vertical hole wiring unit 13 are covered with a glass substrate 14 on the top surface side.

感測器單元12包含根據所接收光輸出電荷信號之複數個 光電二極體21，及在光電二極體21上聚集光之晶片上微透鏡22。儘管未圖解說明，但感測器單元12亦具有其他組件，包含一濾色片、一浮動擴散部，及各種電晶體。The sensor unit 12 includes a plurality of charge signals according to the received light output The photodiode 21 and the microlens 22 on the wafer on which the light is collected on the photodiode 21. Although not illustrated, the sensor unit 12 also has other components, including a color filter, a floating diffusion, and various transistors.

垂直孔佈線單元13係由層壓於矽晶圓31之頂部表面(圖1中之上側)上之一金屬墊32、一玻璃密封劑33，及一停止件層34組態。玻璃基板14安置於玻璃密封劑33及停止件層34之頂部表面上。此外，垂直孔佈線單元13係由形成於穿過矽晶圓31形成之一垂直孔35之內表面及底部表面上(圖1中之下側上)之一絕緣膜36、一金屬晶種層37，及一電鍍層38組態。一焊料遮罩39形成於絕緣膜36及電鍍層38之底部表面上，且一焊料球40經安置穿過焊料遮罩39且與電鍍層38接觸。The vertical hole wiring unit 13 is configured by laminating a metal pad 32, a glass sealant 33, and a stopper layer 34 on the top surface (the upper side in FIG. 1) of the germanium wafer 31. The glass substrate 14 is disposed on the top surfaces of the glass sealant 33 and the stopper layer 34. Further, the vertical via wiring unit 13 is formed of an insulating film 36, a metal seed layer formed on the inner surface and the bottom surface (on the lower side in FIG. 1) of one of the vertical holes 35 formed through the germanium wafer 31. 37, and a plating layer 38 configuration. A solder mask 39 is formed on the bottom surface of the insulating film 36 and the plating layer 38, and a solder ball 40 is disposed through the solder mask 39 and in contact with the plating layer 38.

矽晶圓31係一薄半導體基板。一個氧化物膜31b係形成於一矽層31a之頂部表面上。The germanium wafer 31 is a thin semiconductor substrate. An oxide film 31b is formed on the top surface of a tantalum layer 31a.

金屬墊32係形成於矽晶圓31之氧化物膜31b內部之一金屬層，具體而言位於頂部表面側上矽晶圓31內部，且用作輸出來自感測器單元12之信號之一電極。舉例而言，諸如鋁、銅、鎢、鎳及鉭金屬用於金屬墊32。The metal pad 32 is formed on one of the metal layers inside the oxide film 31b of the germanium wafer 31, specifically on the top surface side, inside the germanium wafer 31, and serves as an electrode for outputting a signal from the sensor unit 12. . For example, metals such as aluminum, copper, tungsten, nickel, and tantalum are used for the metal pad 32.

玻璃密封劑33係將玻璃基板14接合至矽晶圓31之一密封劑。一孔隙部分42(參見圖2)係形成於玻璃密封劑33中，且玻璃密封劑33用作為停止件層34提供一框架之一層。The glass sealant 33 bonds the glass substrate 14 to one of the sealants of the germanium wafer 31. A void portion 42 (see Fig. 2) is formed in the glass sealant 33, and the glass sealant 33 serves as a stop layer 34 to provide a layer of a frame.

停止件層34係一導體層，其填充以使得在矽晶圓31之頂部表面上曝露金屬墊32之一方式形成於氧化物膜31b及玻璃密封劑33中之孔隙部分。停止件層34以與玻璃密封劑33 實質上相同之厚度形成，舉例而言，約50 μm，較佳地10 μm至100 μm。舉例而言，停止件層34可使用銀或銅形成，如下文參照圖6所闡述。The stopper layer 34 is a conductor layer which is filled so as to be formed in the pore portion of the oxide film 31b and the glass sealant 33 in such a manner that the metal pad 32 is exposed on the top surface of the tantalum wafer 31. Stop layer 34 with glass sealant 33 Substantially the same thickness is formed, for example, about 50 μm, preferably 10 μm to 100 μm. For example, the stop layer 34 can be formed using silver or copper, as explained below with reference to FIG.

垂直孔35係一細孔，其經形成以將形成於矽晶圓31之頂部表面側上之金屬墊32接線至矽晶圓31之底部表面，且垂直孔35實質上正交於矽晶圓31之底部表面。絕緣膜36使矽晶圓31之底部表面側絕緣。金屬晶種層37係一導線，透過其將來自感測器單元12之信號引導至矽晶圓31之底部表面側。金屬晶種層37係經由垂直孔35之端部處之停止件層34電連接至金屬墊32，且延伸至矽晶圓31之底部表面。The vertical hole 35 is a fine hole formed to connect the metal pad 32 formed on the top surface side of the germanium wafer 31 to the bottom surface of the germanium wafer 31, and the vertical hole 35 is substantially orthogonal to the germanium wafer The bottom surface of 31. The insulating film 36 insulates the bottom surface side of the tantalum wafer 31. The metal seed layer 37 is a wire through which signals from the sensor unit 12 are guided to the bottom surface side of the germanium wafer 31. The metal seed layer 37 is electrically connected to the metal pad 32 via the stopper layer 34 at the end of the vertical hole 35 and extends to the bottom surface of the germanium wafer 31.

舉例而言，電鍍層38係在藉由蝕刻形成金屬晶種層37時用作一遮罩之一層。焊料遮罩39係一遮罩，其在將一導線外部連接至焊料球40時防止一焊料附著至不期望部分。焊料球40係連接至來自感測器單元12之信號透過其輸出至外部之導線的一端子。For example, the plating layer 38 serves as a layer of a mask when the metal seed layer 37 is formed by etching. The solder mask 39 is a mask that prevents a solder from adhering to an undesired portion when externally connecting a wire to the solder ball 40. The solder ball 40 is connected to a terminal of a wire from which the signal from the sensor unit 12 is output to the outside.

下文參照圖2至圖5闡述垂直孔佈線單元13之製造步驟。The manufacturing steps of the vertical hole wiring unit 13 will be described below with reference to FIGS. 2 to 5.

首先，在圖2中所表示之第一步驟中，在矽晶圓31之氧化物膜31b中形成金屬墊32。舉例而言，金屬墊32表示連接至感測器單元12之選擇電晶體(未圖解說明)之信號線之一端(BEOL：後段製程)。First, in the first step shown in FIG. 2, a metal pad 32 is formed in the oxide film 31b of the germanium wafer 31. For example, the metal pad 32 represents one end of a signal line (BEOL: Back End Process) that is connected to a selection transistor (not illustrated) of the sensor unit 12.

在第二步驟中，在矽晶圓31之頂部表面側上對應於金屬墊32之氧化物膜31b之一部分中形成一孔隙部分41，從而曝露金屬墊32。如自頂部表面所觀看，孔隙部分41經形成以具有小於金屬墊32之一區域，且氧化物膜31b上覆於金 屬墊32之邊緣上。具體而言，考量到用於形成孔隙部分41之製程限度，將金屬墊32形成一較大尺寸。In the second step, a void portion 41 is formed in a portion of the oxide film 31b corresponding to the metal pad 32 on the top surface side of the tantalum wafer 31, thereby exposing the metal pad 32. The pore portion 41 is formed to have a smaller area than the metal pad 32 as viewed from the top surface, and the oxide film 31b is overlaid on the gold On the edge of the pad 32. Specifically, the metal pad 32 is formed into a larger size in consideration of the process limits for forming the void portion 41.

在第三步驟中，在矽晶圓31與金屬墊32之頂部表面上形成玻璃密封劑33。亦在感測器單元12(圖1)之頂部表面上形成玻璃密封劑33。In the third step, a glass sealant 33 is formed on the top surface of the germanium wafer 31 and the metal pad 32. A glass sealant 33 is also formed on the top surface of the sensor unit 12 (Fig. 1).

在第四步驟中，在玻璃密封劑33中形成孔隙42，從而曝露金屬墊32。如自頂部表面所觀看，孔隙部分42係以大於形成於氧化物膜31b中之孔隙部分41之區域之一尺寸形成於玻璃密封劑33中，以便確保金屬墊32曝露於頂部表面側上。上覆於金屬墊32之邊緣上之氧化物膜31b亦曝露於頂部表面側上。In the fourth step, the pores 42 are formed in the glass sealant 33, thereby exposing the metal pad 32. The pore portion 42 is formed in the glass sealant 33 in a size larger than one of the regions of the void portion 41 formed in the oxide film 31b as viewed from the top surface, in order to ensure that the metal pad 32 is exposed on the top surface side. The oxide film 31b overlying the edge of the metal pad 32 is also exposed on the top surface side.

應注意，在第四步驟中，如圖4中所圖解說明，與在玻璃密封劑33中形成孔隙部分42同時，在形成於感測器單元12之頂部表面上之玻璃密封劑33中形成一孔隙部分43。圖4圖解說明形成於玻璃密封劑33中之孔隙部分42，及經形成用於感測器單元12之孔隙部分43。It should be noted that in the fourth step, as illustrated in FIG. 4, while forming the pore portion 42 in the glass sealant 33, a glass sealant 33 formed on the top surface of the sensor unit 12 is formed. Pore portion 43. FIG. 4 illustrates the aperture portion 42 formed in the glass sealant 33, and the aperture portion 43 formed for the sensor unit 12.

在第五步驟中，在形成於氧化物膜31b中之孔隙部分41中，及在形成於玻璃密封劑33中之孔隙部分42中形成停止件層34。可藉由使用諸如絲網印刷、噴塗及柱形凸塊形成方法來形成停止件層34。In the fifth step, the stopper layer 34 is formed in the pore portion 41 formed in the oxide film 31b, and in the pore portion 42 formed in the glass sealant 33. The stopper layer 34 can be formed by using methods such as screen printing, spray coating, and stud bump formation.

圖5A示意性表示絲網印刷。在絲網印刷中，將作為停止件層34之材料的一導電膏51置於具有對應於形成於玻璃密封劑33中之孔隙部分42之一孔之一絲網52的頂部表面上，且使用一橡皮輥53將其攤鋪於絲網52上。因此，透過該孔 穿過絲網52之膏51填充孔隙部分42且形成停止件層34。Fig. 5A schematically shows screen printing. In screen printing, a conductive paste 51 as a material of the stopper layer 34 is placed on the top surface of the screen 52 having a hole corresponding to one of the aperture portions 42 formed in the glass sealant 33, and one is used. The rubber roller 53 spreads it on the screen 52. Therefore, through the hole The void portion 42 is filled through the paste 51 of the screen 52 and forms a stopper layer 34.

圖5B示意性表示噴塗。在噴塗中，透過一噴嘴54將作為停止件層34之材料的導電膏51噴射至跡線部分中。膏51填充形成於玻璃密封劑33中之孔隙部分42，且形成停止件層34。Fig. 5B schematically shows spraying. In the spraying, the conductive paste 51 as a material of the stopper layer 34 is ejected into the trace portion through a nozzle 54. The paste 51 fills the void portion 42 formed in the glass sealant 33, and forms a stopper layer 34.

停止件層34係以此方式形成，且具有與玻璃密封劑33大約相同之厚度(舉例而言，約50 μm)。The stopper layer 34 is formed in this manner and has approximately the same thickness as the glass sealant 33 (for example, about 50 μm).

在圖3中所圖解說明之接下來第六步驟中，經由玻璃密封劑33將玻璃基板14接合至矽晶圓31之頂部表面。此外，在此步驟中，藉由研磨矽晶圓31之底部表面側(BGR：背部研磨)減小矽晶圓31之厚度。In the next sixth step illustrated in FIG. 3, the glass substrate 14 is bonded to the top surface of the germanium wafer 31 via a glass sealant 33. Further, in this step, the thickness of the tantalum wafer 31 is reduced by grinding the bottom surface side (BGR: back grinding) of the tantalum wafer 31.

在第七步驟中，使用一雷射鑽穿過金屬墊32至停止件層34形成垂直孔35。此處，雷射鑽停止在(舉例而言)比JP-A-2007-305995中所揭示之金屬凸塊厚之停止件層34處，且即使在一高輸出下也不會進一步前進。具體而言，藉由一高輸出雷射鑽在不穿透停止件層34之情形下形成垂直孔35。In a seventh step, a vertical hole 35 is formed through a metal pad 32 to the stop layer 34 using a laser drill. Here, the laser drill is stopped at, for example, the stopper layer 34 which is thicker than the metal bump disclosed in JP-A-2007-305995, and does not advance further even at a high output. In particular, the vertical aperture 35 is formed by a high output laser drill without penetrating the stop layer 34.

在第八步驟中，在垂直孔35及矽晶圓31之底部表面上形成絕緣膜36。In the eighth step, an insulating film 36 is formed on the vertical holes 35 and the bottom surface of the germanium wafer 31.

在第九步驟中，移除垂直孔35之端部表面處之絕緣膜36以將停止件層34曝露於垂直孔35。接著，將金屬晶種層37層壓於停止件層34及絕緣膜36上。因此，停止件層34及金屬晶種層37彼此電連接。隨後形成圖1中所展示之電鍍層38、焊料遮罩39，及焊料球40。In the ninth step, the insulating film 36 at the end surface of the vertical hole 35 is removed to expose the stopper layer 34 to the vertical hole 35. Next, the metal seed layer 37 is laminated on the stopper layer 34 and the insulating film 36. Therefore, the stopper layer 34 and the metal seed layer 37 are electrically connected to each other. A plating layer 38, a solder mask 39, and a solder ball 40 as shown in FIG. 1 are then formed.

此完成了垂直孔佈線單元13。由於停止件層34係藉由將膏51(圖5A及圖5B)裝填至形成於玻璃密封劑33中之孔隙部分42中而形成，因此停止件層34可具有厚約50 μm之一厚度。此外，由於使用了絲網印刷或噴塗，可更快速地形成停止件層34，舉例而言，諸如濺鍍方法中所需處理時間之約1/2至1/10。This completes the vertical hole wiring unit 13. Since the stopper layer 34 is formed by filling the paste 51 (Figs. 5A and 5B) into the void portion 42 formed in the glass sealant 33, the stopper layer 34 may have a thickness of about 50 μm. Further, since screen printing or spraying is used, the stopper layer 34 can be formed more quickly, for example, about 1/2 to 1/10 of the processing time required in the sputtering method.

因此，如在該製造方法之前述製造步驟中增加停止件層34之厚度允許使用比在JP-A-2007-305995中所揭示的製造方法中所使用之雷射鑽高輸出之一雷射鑽。高輸出雷射鑽使得可在一較短之時間段內形成垂直孔35，且因此可自相關技術之垂直孔佈線單元13的製造時間縮短垂直孔佈線單元13的製造時間。此又縮短固態成像裝置11作為一整體之製造時間，且減小固態成像裝置11之製作成本。Therefore, increasing the thickness of the stopper layer 34 as in the aforementioned manufacturing steps of the manufacturing method allows the use of one of the laser drills having a higher output than the laser drill used in the manufacturing method disclosed in JP-A-2007-305995. . The high output laser drill makes it possible to form the vertical holes 35 in a short period of time, and thus the manufacturing time of the vertical hole wiring unit 13 can be shortened by the manufacturing time of the vertical hole wiring unit 13 of the related art. This in turn shortens the manufacturing time of the solid-state imaging device 11 as a whole, and reduces the manufacturing cost of the solid-state imaging device 11.

舉例而言，藉由增加JP-A-2007-305995中所揭示之金屬凸塊之厚度來使雷射鑽停止在金屬凸塊處或許有可能。然而，增加金屬凸塊之厚度不僅花費一長時間來形成金屬凸塊，而且可導致金屬凸塊接觸毗鄰金屬凸塊。相比而言，停止件層34在固態成像裝置11之垂直孔佈線單元13之製造方法中不會發生此一接觸，乃因停止件層34係經形成以便填充形成於玻璃密封劑33中之孔隙部分。For example, it may be possible to stop the laser drill at the metal bump by increasing the thickness of the metal bump disclosed in JP-A-2007-305995. However, increasing the thickness of the metal bumps not only takes a long time to form the metal bumps, but also causes the metal bumps to contact adjacent metal bumps. In contrast, the stopper layer 34 does not occur in the manufacturing method of the vertical hole wiring unit 13 of the solid-state imaging device 11, because the stopper layer 34 is formed so as to be filled in the glass sealant 33. Part of the pores.

此外，由於雷射鑽孔之裝置成本比DRIE之裝置成本便宜，因此就此而言亦可降低固態成像裝置11之製作成本。In addition, since the cost of the laser drilling apparatus is lower than that of the DRIE apparatus, the manufacturing cost of the solid-state imaging apparatus 11 can also be reduced in this respect.

此外，所形成之厚約50 μm之停止件層34可可靠地使垂直孔35之雷射鑽處理停止，且可容易控制雷射鑽製程。此 外，停止件層34之厚度使得雷射鑽製程容易控制，且即使當存在垂直孔35之深度之某種變化時亦可在停止件層34與金屬晶種層37之間獲得一期望之接觸。因此，可認為固態成像裝置11具有針對垂直孔35之深度變化之一穩健設計。Further, the formed stop layer 34 having a thickness of about 50 μm can reliably stop the laser drilling process of the vertical holes 35, and the laser drilling process can be easily controlled. this In addition, the thickness of the stop layer 34 allows the laser drilling process to be easily controlled and achieves a desired contact between the stop layer 34 and the metal seed layer 37 even when there is some variation in the depth of the vertical holes 35. . Therefore, it can be considered that the solid-state imaging device 11 has a robust design for one of the depth variations of the vertical holes 35.

圖6係可用作停止件層34之一材料清單。FIG. 6 is a bill of materials that can be used as one of the stop layers 34.

如上文所闡述，由於垂直孔35係藉由雷射鑽孔形成於矽晶圓31中，因此停止件層34較佳地使用具有比矽(Si)之熔點(1,410℃)高之一熔點之一材料形成，以便使雷射鑽之進展在停止件層34處停止。此外，由於即使使用具有比矽低之一熔點之一材料亦可在垂直孔佈線單元13中將停止件層34製成約50 μm厚，因此雷射鑽可在停止件層34處停止且不會穿透此厚層。As explained above, since the vertical holes 35 are formed in the germanium wafer 31 by laser drilling, the stopper layer 34 is preferably used to have a melting point higher than the melting point (1, 410 ° C) of germanium (Si). A material is formed to stop the progress of the laser drill at the stop layer 34. Further, since the stopper layer 34 can be made to be about 50 μm thick in the vertical hole wiring unit 13 even if one material having a melting point lower than that of the crucible is used, the laser drill can be stopped at the stopper layer 34 and Will penetrate this thick layer.

具有比矽低之熔點之停止件層34材料之實例包含銀(Ag：熔點961℃)、金(Au：熔點1,063℃)，及銅(Cu：熔點1,083℃)。Examples of the material of the stopper layer 34 having a melting point lower than enthalpy include silver (Ag: melting point 961 ° C), gold (Au: melting point 1,063 ° C), and copper (Cu: melting point 1,083 ° C).

具有比矽高之熔點之停止件層34材料之實例包含鉻(Cr：熔點1,890℃)、銥(Ir：熔點2,410℃)、鉬(Mo：熔點2,610℃)、鈮(Nb：熔點2,468℃)、鎳(Ni：熔點1,453℃)、鈀(Pd：熔點1,552℃)、鉑(Pt：熔點1,769℃)、釕(Ru：熔點2,250℃)、鉭(Ta：熔點2,998℃)、釩(V：熔點1,890℃)、鎢(W：熔點3,410℃)，及鋯(Zr：熔點1,852℃)。Examples of the material of the stopper layer 34 having a higher melting point than yttrium include chromium (Cr: melting point 1,890 ° C), cerium (Ir: melting point 2,410 ° C), molybdenum (Mo: melting point 2, 610 ° C), cerium (Nb: melting point 2, 468 ° C) Nickel (Ni: melting point 1,453 ° C), palladium (Pd: melting point 1,552 ° C), platinum (Pt: melting point 1, 769 ° C), ruthenium (Ru: melting point 2, 250 ° C), ruthenium (Ta: melting point 2,998 ° C), vanadium (V: Melting point 1,890 ° C), tungsten (W: melting point 3,410 ° C), and zirconium (Zr: melting point 1,852 ° C).

舉例而言，易於以一膏形式購得之銀及銅較佳地用作停止件層34。除了上文例示之材料之外，諸如氮化鈦(TiN) 及氮化鉭(TaN)之化合物亦可用作停止件層34。氮化鈦及氮化鉭具有分別為2,930℃及3,090℃之熔點，遠高於矽之熔點，且因此雷射鑽之進展可更可按期望停止於使用氮化鈦或氮化鉭在前述厚度範圍中形成的停止件層34處。For example, silver and copper, which are readily available in a paste form, are preferably used as the stop layer 34. In addition to the materials exemplified above, such as titanium nitride (TiN) A compound of tantalum nitride (TaN) can also be used as the stopper layer 34. Titanium nitride and tantalum nitride have melting points of 2,930 ° C and 3,090 ° C, respectively, which are much higher than the melting point of tantalum, and thus the progress of the laser drill can be stopped as desired using titanium nitride or tantalum nitride at the aforementioned thickness. At the stop layer 34 formed in the range.

應注意形成於垂直孔佈線單元13之前述實例性結構中之金屬墊32之頂部表面上之停止件層34可形成於金屬墊32之底部表面上。It should be noted that the stopper layer 34 formed on the top surface of the metal pad 32 in the foregoing exemplary structure of the vertical hole wiring unit 13 may be formed on the bottom surface of the metal pad 32.

圖7表示包含形成於金屬墊32之底部表面上之一停止件層34'之一矽晶圓31。舉例而言，停止件層34'可藉由在圖2中所闡述之第一步驟中在金屬墊32之前形成停止件層34'來形成於金屬墊32之底部表面上。FIG. 7 shows a wafer 31 comprising a stopper layer 34' formed on the bottom surface of the metal pad 32. For example, the stop layer 34' can be formed on the bottom surface of the metal pad 32 by forming a stop layer 34' in front of the metal pad 32 in the first step illustrated in FIG.

圖8係圖解說明安裝於一電子裝置中之一成像器之一例示性結構之一方塊圖。Figure 8 is a block diagram illustrating an exemplary structure of one of the imagers mounted in an electronic device.

如圖8中所圖解說明，一成像器101經組態以包含一光學系統102、一快門單元103、一成像裝置104、一驅動電路105、一信號處理電路106、一監視器107，及一記憶體108，且能夠捕獲一靜止影像及一運動影像兩者。As illustrated in FIG. 8, an imager 101 is configured to include an optical system 102, a shutter unit 103, an imaging device 104, a driving circuit 105, a signal processing circuit 106, a monitor 107, and a The memory 108 is capable of capturing both a still image and a moving image.

光學系統102係由一或多個透鏡組態，且將被攝體之影像光(入射光)引導至成像裝置104上，從而在成像裝置104之光接收表面(感測器單元)上形成一影像。The optical system 102 is configured by one or more lenses, and guides image light (incident light) of the subject onto the imaging device 104, thereby forming a light on the light receiving surface (sensor unit) of the imaging device 104. image.

快門單元103安置於光學系統102與成像裝置104之間，且在驅動電路105之控制下控制成像裝置104之曝光時間。The shutter unit 103 is disposed between the optical system 102 and the imaging device 104, and controls the exposure time of the imaging device 104 under the control of the driving circuit 105.

前述例示性結構之一固態成像裝置11用作成像裝置104。成像裝置104根據透過光學系統102及快門單元103在 光接收表面上形成之影像累積一定時間週期內之信號電荷。接著，根據自驅動電路105供應之驅動信號(時序信號)傳送累積於成像裝置104中之信號電荷。The solid-state imaging device 11 of one of the aforementioned exemplary structures is used as the imaging device 104. The imaging device 104 is in accordance with the transmission optical system 102 and the shutter unit 103. The image formed on the light receiving surface accumulates signal charges for a certain period of time. Next, the signal charges accumulated in the imaging device 104 are transmitted in accordance with a driving signal (timing signal) supplied from the driving circuit 105.

驅動電路105輸出控制成像裝置104之傳送操作及快門單元103之快門操作之驅動信號，以便驅動成像裝置104及快門單元103。The drive circuit 105 outputs a drive signal for controlling the transfer operation of the imaging device 104 and the shutter operation of the shutter unit 103 to drive the imaging device 104 and the shutter unit 103.

信號處理電路106處理來自成像裝置104之輸出信號電荷。將在信號處理電路106中之信號處理之後所獲得之影像(影像資料)供應至監視器107並在其上顯示，且/或供應至記憶體108且儲存(記錄)於其中。Signal processing circuit 106 processes the output signal charge from imaging device 104. The image (image material) obtained after the signal processing in the signal processing circuit 106 is supplied to and displayed on the monitor 107, and/or supplied to the memory 108 and stored (recorded) therein.

如上文所組態之成像器101包含由可如上文以低成本製作之固態成像裝置11實現之成像裝置104。因此，成像器101可以低成本製作。The imager 101 configured as above includes an imaging device 104 implemented by a solid-state imaging device 11 that can be fabricated at a low cost as described above. Therefore, the imager 101 can be manufactured at low cost.

除了雷射鑽孔之外，諸如DRIE及乾式蝕刻之技術可用於處理垂直孔35。In addition to laser drilling, techniques such as DRIE and dry etching can be used to process the vertical holes 35.

可將固態成像裝置11組態為一背側照明CMOS固態成像裝置、一前側照明CMOS固態成像裝置，或一CCD(電荷耦合裝置)固態成像裝置。本發明亦適用於除固態成像裝置之外的半導體裝置(半導體元件)，舉例而言，包含經組態以包含整合在一IC(積體電路)晶片上之一邏輯電路之一邏輯晶片。The solid-state imaging device 11 can be configured as a back side illumination CMOS solid-state imaging device, a front side illumination CMOS solid-state imaging device, or a CCD (Charge Coupled Device) solid-state imaging device. The present invention is also applicable to a semiconductor device (semiconductor device) other than a solid-state imaging device, for example, including a logic chip configured to include one of logic circuits integrated on an IC (integrated circuit) wafer.

應注意本發明並不限於前述實施例，且亦可進行在本發明之主旨內之各種修改。It should be noted that the present invention is not limited to the foregoing embodiments, and various modifications within the gist of the present invention are also possible.

本發明含有與2011年3月11日在日本專利局提出申請之 日本優先權專利申請案JP 2011-054389中所揭示之標的物相關之標的物，該申請案之全部內容以引用方式併入本文中。The present invention contains an application filed with the Japanese Patent Office on March 11, 2011. The subject matter of the subject matter disclosed in the Japanese Priority Patent Application No. 2011-054389, the entire contents of which is incorporated herein by reference.

11‧‧‧固態成像裝置11‧‧‧ Solid-state imaging device

12‧‧‧感測器單元12‧‧‧Sensor unit

13‧‧‧垂直孔佈線單元13‧‧‧Vertical hole wiring unit

14‧‧‧玻璃基板14‧‧‧ glass substrate

21‧‧‧光電二極體21‧‧‧Photoelectric diode

22‧‧‧晶片上微透鏡22‧‧‧Microlens on wafer

31‧‧‧矽晶圓31‧‧‧矽 wafer

31a‧‧‧矽層31a‧‧‧ layer

31b‧‧‧氧化物膜31b‧‧‧Oxide film

32‧‧‧金屬墊32‧‧‧Metal pad

33‧‧‧玻璃密封劑33‧‧‧Glass sealant

34‧‧‧停止件層34‧‧‧stop layer

34'‧‧‧停止件層34'‧‧‧stop layer

35‧‧‧垂直孔35‧‧‧Vertical holes

36‧‧‧絕緣膜36‧‧‧Insulation film

37‧‧‧金屬晶種層37‧‧‧metal seed layer

38‧‧‧電鍍層38‧‧‧Electroplating

39‧‧‧焊料遮罩39‧‧‧ solder mask

40‧‧‧焊料球40‧‧‧ solder balls

41‧‧‧孔隙部分41‧‧‧Pore section

42‧‧‧孔隙部分42‧‧‧Pore section

43‧‧‧孔隙部分43‧‧‧Pore section

51‧‧‧導電膏51‧‧‧ conductive paste

52‧‧‧絲網52‧‧‧Screen

53‧‧‧橡皮輥53‧‧‧Rubber roller

54‧‧‧噴嘴54‧‧‧Nozzles

101‧‧‧成像器101‧‧‧ Imager

102‧‧‧光學系統102‧‧‧Optical system

103‧‧‧快門單元103‧‧‧Shutter unit

104‧‧‧成像裝置104‧‧‧ imaging device

105‧‧‧驅動電路105‧‧‧Drive circuit

106‧‧‧信號處理電路106‧‧‧Signal Processing Circuit

107‧‧‧監視器107‧‧‧Monitor

108‧‧‧記憶體108‧‧‧ memory

圖1係圖解說明根據本發明之一實施例之一固態成像裝置之一例示性結構的一剖面圖。1 is a cross-sectional view illustrating an exemplary structure of a solid-state imaging device according to an embodiment of the present invention.

圖2係解釋一垂直孔佈線單元之製造步驟之一圖示。Figure 2 is a diagram showing one of the manufacturing steps of a vertical hole wiring unit.

圖3係解釋該垂直孔佈線單元之製造步驟之圖示。Figure 3 is a diagram for explaining the manufacturing steps of the vertical hole wiring unit.

圖4係表示一孔隙部分形成於一玻璃密封劑及一感測器單元中之狀態之一圖示。Figure 4 is a view showing a state in which a void portion is formed in a glass sealant and a sensor unit.

圖5A及圖5B係解釋絲網印刷及噴塗之圖示。5A and 5B are diagrams for explaining screen printing and painting.

圖6係列出可用作一停止件層之材料之一圖示。Figure 6 is a series of illustrations of one of the materials that can be used as a stop layer.

圖7係圖解說明包含形成於一金屬墊之底部表面上之一停止件層之一矽晶圓之一圖示。Figure 7 is a diagram illustrating one of the wafers including one of the stop layers formed on the bottom surface of a metal pad.

圖8係表示安裝於一電子裝置中之一成像器之一例示性結構之一方塊圖。Figure 8 is a block diagram showing an exemplary structure of one of the imagers mounted in an electronic device.

11‧‧‧固態成像裝置11‧‧‧ Solid-state imaging device

12‧‧‧感測器單元12‧‧‧Sensor unit

13‧‧‧垂直孔佈線單元13‧‧‧Vertical hole wiring unit

14‧‧‧玻璃基板14‧‧‧ glass substrate

21‧‧‧光電二極體21‧‧‧Photoelectric diode

22‧‧‧晶片上微透鏡22‧‧‧Microlens on wafer

31‧‧‧矽晶圓31‧‧‧矽 wafer

31a‧‧‧矽層31a‧‧‧ layer

31b‧‧‧氧化物膜31b‧‧‧Oxide film

32‧‧‧金屬墊32‧‧‧Metal pad

33‧‧‧玻璃密封劑33‧‧‧Glass sealant

34‧‧‧停止件層34‧‧‧stop layer

35‧‧‧垂直孔35‧‧‧Vertical holes

36‧‧‧絕緣膜36‧‧‧Insulation film

37‧‧‧金屬晶種層37‧‧‧metal seed layer

38‧‧‧電鍍層38‧‧‧Electroplating

39‧‧‧焊料遮罩39‧‧‧ solder mask

40‧‧‧焊料球40‧‧‧ solder balls

Claims (10)

一種半導體裝置，其包括：一半導體基板，其包含一半導體；一電極層，其形成於該半導體基板內部之一第一表面側上；一框架層，其層壓於該半導體基板之該第一表面上；一導體層，其直接形成於該電極層上及該半導體基板之該第一表面上；一垂直孔，其自該半導體基板之一第二表面至該導體層穿過該半導體基板而形成；及一佈線層，其在該垂直孔之一端部處經由該導體層電連接至該電極層，且其延伸至該半導體基板之該第二表面，該佈線層與該電極層係藉由設置於其間之一絕緣層而物理分隔。 A semiconductor device comprising: a semiconductor substrate comprising a semiconductor; an electrode layer formed on a first surface side of the interior of the semiconductor substrate; and a frame layer laminated to the first of the semiconductor substrate a conductive layer formed directly on the electrode layer and on the first surface of the semiconductor substrate; a vertical hole extending from the second surface of the semiconductor substrate to the conductive layer through the semiconductor substrate And a wiring layer electrically connected to the electrode layer via the conductor layer at one end of the vertical hole, and extending to the second surface of the semiconductor substrate, the wiring layer and the electrode layer being It is physically separated by an insulating layer disposed therebetween. 如請求項1之半導體裝置，其中該框架層係將一玻璃基板接合至該半導體基板之該第一表面之一密封劑。 The semiconductor device of claim 1, wherein the frame layer bonds a glass substrate to one of the first surfaces of the semiconductor substrate. 如請求項1之半導體裝置，其中該佈線層係經由該導體層而電連接至該電極層，其中在該電極層與該導體層之間的該電連接係僅在該垂直孔之該端部處，該端部處位於該導體層內。 The semiconductor device of claim 1, wherein the wiring layer is electrically connected to the electrode layer via the conductor layer, wherein the electrical connection between the electrode layer and the conductor layer is only at the end of the vertical hole Wherein the end is located within the conductor layer. 一種用於製造一半導體裝置之方法，該方法包括：在在包含一半導體之一半導體基板內部之一第一表面側上形成一電極層； 將一框架層層壓於該半導體基板之該第一表面上；直接在該電極層上及該半導體基板之該第一表面上形成一導體層；自該半導體基板之一第二表面至該導體層穿過該半導體基板形成一垂直孔；及形成一佈線層，該佈線層在該垂直孔之一端部處經由該導體層電連接至該電極層，且其延伸至該半導體基板之該第二表面，該佈線層與該電極層係藉由設置於其間之一絕緣層而物理分隔。 A method for fabricating a semiconductor device, the method comprising: forming an electrode layer on a first surface side of a semiconductor substrate including a semiconductor; Laminating a frame layer on the first surface of the semiconductor substrate; forming a conductor layer directly on the electrode layer and on the first surface of the semiconductor substrate; from a second surface of the semiconductor substrate to the conductor Forming a vertical hole through the semiconductor substrate; and forming a wiring layer electrically connected to the electrode layer via the conductor layer at one end of the vertical hole, and extending to the second of the semiconductor substrate The surface layer and the electrode layer are physically separated by an insulating layer disposed therebetween. 如請求項4之方法，其中該佈線層係經由該導體層而電連接至該電極層，其中在該電極層與該導體層之間的該電連接係僅在該垂直孔之該端部處，該端部處位於該導體層內。 The method of claim 4, wherein the wiring layer is electrically connected to the electrode layer via the conductor layer, wherein the electrical connection between the electrode layer and the conductor layer is only at the end of the vertical hole The end is located within the conductor layer. 如請求項4之方法，其中該垂直孔係藉由自該半導體基板之該第二表面雷射鑽孔穿過該電極層至該導體層而形成。 The method of claim 4, wherein the vertical hole is formed by laser drilling a second surface of the semiconductor substrate through the electrode layer to the conductor layer. 如請求項4之方法，其中該導體層係藉由用一導電膏材料填充一孔隙部分而形成，該孔隙部分係藉由處理該半導體基板及該框架層以曝露該半導體基板之該第一表面上之該電極層所形成。 The method of claim 4, wherein the conductor layer is formed by filling a void portion with a conductive paste material, the void portion being exposed to the first surface of the semiconductor substrate by processing the semiconductor substrate and the frame layer The electrode layer is formed thereon. 如請求項7之方法，其中用該導電膏材料填充該孔隙部分係藉由自包含一網版印刷製程、一噴塗製程及一柱形凸塊製程之群組中所選擇之至少一製程所執行。 The method of claim 7, wherein filling the void portion with the conductive paste material is performed by at least one selected from the group consisting of: a screen printing process, a spray process, and a column bump process. . 一種電子裝置，其包括： 一半導體裝置，其包含一半導體基板，其包含一半導體，一電極層，其形成於該半導體基板內部之一第一表面側上，一框架層，其層壓於該半導體基板之該第一表面上，一導體層，其直接形成於該電極層上及該半導體基板之該第一表面上，一垂直孔，其自該半導體基板之一第二表面至該導體層穿過該半導體基板而形成，及一佈線層，其在該垂直孔之一端部處經由該導體層電連接至該電極層，且其延伸至該半導體基板之該第二表面，該佈線層與該電極層係藉由設置於其間之一絕緣層而物理分隔。 An electronic device comprising: A semiconductor device comprising a semiconductor substrate comprising a semiconductor, an electrode layer formed on a first surface side of the interior of the semiconductor substrate, and a frame layer laminated on the first surface of the semiconductor substrate a conductor layer directly formed on the electrode layer and on the first surface of the semiconductor substrate, a vertical hole formed from a second surface of the semiconductor substrate to the conductor layer through the semiconductor substrate And a wiring layer electrically connected to the electrode layer via the conductor layer at one end of the vertical hole, and extending to the second surface of the semiconductor substrate, the wiring layer and the electrode layer being disposed by Physically separated by one of the insulating layers. 如請求項9之電子裝置，其中該佈線層係經由該導體層而電連接至該電極層，其中在該電極層與該導體層之間的該電連接係僅在該垂直孔之該端部處，該端部位於該導體層內。The electronic device of claim 9, wherein the wiring layer is electrically connected to the electrode layer via the conductor layer, wherein the electrical connection between the electrode layer and the conductor layer is only at the end of the vertical hole Wherein the end is located within the conductor layer.
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