TWI470733B - 溝渠絕緣製程 - Google Patents

溝渠絕緣製程 Download PDF

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TWI470733B
TWI470733B TW101131197A TW101131197A TWI470733B TW I470733 B TWI470733 B TW I470733B TW 101131197 A TW101131197 A TW 101131197A TW 101131197 A TW101131197 A TW 101131197A TW I470733 B TWI470733 B TW I470733B
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trench
sidewall
layer
substrate
opening
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TW101131197A
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TW201409611A (zh
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Yung Fa Lin
Chia Hao Chang
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Anpec Electronics Corp
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Priority to TW101131197A priority Critical patent/TWI470733B/zh
Priority to US13/628,051 priority patent/US8846489B2/en
Priority to CN201210378608.9A priority patent/CN103681452B/zh
Priority to US14/100,023 priority patent/US20140087540A1/en
Publication of TW201409611A publication Critical patent/TW201409611A/zh
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76205Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02225Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/0223Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
    • H01L21/02233Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
    • H01L21/02236Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor
    • H01L21/02238Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor silicon in uncombined form, i.e. pure silicon
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/3086Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/32Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers using masks

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)

Description

溝渠絕緣製程
本發明係有關於半導體製程技術領域,特別是有關於一種溝渠絕緣製程,利用側壁子製程及/或熱氧化技術來達到無縫的溝渠充填。
在積體電路的應用中,不同功能元件常建構於單一晶片上,為了確保每個獨立的元件可以不被周圍其他元件所干擾,因此元件間電性上的隔絕特別重要。
區域矽氧化(local oxidation of silicon,LOCOS)是早期常見的隔絕方法,具有製程簡單以及低成本之優點,但伴隨著製程能力的進步以及元件的微縮(scaling),因LOCOS製程造成之鳥嘴(bird’s beak)以及場氧化層變薄(field oxide thinning)等問題變得嚴重,因此,後續發展出溝渠絕緣(shallow trench isolation,STI)製程來解決LOCOS上之問題。
STI製程是利用挖出溝渠後填入絕緣材料來隔絕主動區域,雖可克服LOCOS的缺點,但也會有研磨淺碟(dishing)以及次啟始電壓突增(sub-threshold kink effect)等問題要克服,且隨著元件微縮,要達到無縫(void free)的溝渠填入技術變得更加困難。
因此,本發明之目的即提供一種改良的溝渠絕緣製程,配合側壁 子製程及/或熱氧化製程來達到溝渠填入,而無須增加製程複雜度。
根據本發明一實施例,提供一種溝渠絕緣製程,包含有:提供一基底,其上設有一墊層以及一硬遮罩層;於該硬遮罩層形成至少一開口;經由該開口蝕刻該基底,形成一第一溝渠;於該第一溝渠的側壁上形成一側壁子;經該第一溝渠蝕刻該基底,於該第一溝渠下方形成一第二溝渠;進行一熱氧化製程,利用該側壁子作為一保護層,氧化該第二溝渠內的該基底,直到該第二溝渠被一氧化層填滿;移除該側壁子,顯露出該第一溝渠的側壁;於顯露出來的該第一溝渠的側壁上形成一襯墊層;以及進行一化學氣相沈積製程,沈積一介電層,填滿該第一溝渠。
根據本發明另一實施例,提供一種溝渠絕緣製程,包含有:提供一基底,其上設有一墊層以及一硬遮罩層;於該硬遮罩層形成至少一開口;於該開口的側壁上形成一側壁子;經由該開口蝕刻該基底,形成一溝渠;以及進行一熱氧化製程,利用該側壁子作為一保護層,氧化該溝渠內的該基底,直到該溝渠被一氧化層填滿。
根據本發明又另一實施例,提供一種溝渠絕緣製程,包含有:提供一基底,其上設有一墊層以及一硬遮罩層;於該硬遮罩層形成至少一開口;經由該開口蝕刻該基底至一預定深度,形成一凹陷區域;於該開口的側壁上形成一側壁子;經由該開口以及該凹陷區域蝕刻該基底,形成一溝渠;以及進行一熱氧化製程,利用該側壁子作為一保護層,氧化該溝渠內的該基底,直到該溝渠被一氧化層填滿。
為讓本發明之上述目的、特徵及優點能更明顯易懂,下文特舉較佳實施方式,並配合所附圖式,作詳細說明如下。然而如下之較佳 實施方式與圖式僅供參考與說明用,並非用來對本發明加以限制者。
請參閱第1圖至第4圖,其為依據本發明一實施例所繪示的溝渠絕緣製程示意圖。首先,如第1圖所示,提供一基底10,例如,半導體基底,接著於基底10表面形成一矽氧墊層12以及一硬遮罩層14,例如氮化矽層。硬遮罩層14亦可以是複數層結構,例如,氮化矽層加上矽氧層。然後,利用微影及蝕刻製程,於硬遮罩層14形成開口14a,圖案化厚的硬遮罩層14定義出主動區域AA的位置。再以硬遮罩層14為蝕刻遮罩,經由開口14a蝕刻矽氧墊層12以及基底10直到一第一預定深度,形成一第一溝渠102。
如第2圖所示,接著於第一溝渠102的側壁上形成側壁子16,例如氮化矽側壁子。形成側壁子16方法,例如,先沈積一均厚的氮化矽層,覆蓋住側壁子16,並順應的覆蓋住第一溝渠102的側壁及底部,再以非等向性蝕刻製程回蝕刻該氮化矽層。接下來,再進行乾蝕刻製程,利用側壁子16作為蝕刻遮罩,繼續經由第一溝渠102蝕刻基底10至一第二預定深度,如此在第一溝渠102下方形成一第二溝渠104。第二溝渠104的開口寬度大小,可以藉由側壁子16的厚度來控制。
如第3圖所示,接著進行一熱氧化製程,例如,在溫度介於800-1200℃,以水蒸汽、氧氣,或內含少量氯化氫或氮氣的水蒸汽或氧氣,製程壓力介於600-760托耳(torr)的條件下,利用側壁子16作為保護層,氧化第二溝渠104內的基底10,直到第二溝渠104最 後被氧化層18填滿,而在氧化層18表面上留下楔形凹陷結構18a。
如第4圖所示,接著移除側壁子16,顯露出第一溝渠102的側壁,再進行一氧化製程,於顯露出來的第一溝渠102的側壁上形成一氧化襯墊層20,隨後,進行一化學氣相沈積(CVD)製程,全面的沈積一介電層22,例如,矽氧層,使介電層22填滿第一溝渠102。由於第二溝渠104係以氧化層18填滿,降低了深寬比,故後續以CVD製程填充第一溝渠102時的製程餘裕度較高,進而達到高品質、無縫的溝渠充填。
請參閱第5圖至第7圖,其為依據本發明另一實施例所繪示的溝渠絕緣製程示意圖。首先,如第5圖所示,同樣提供一基底10,例如,半導體基底,接著於基底10表面形成一矽氧墊層12以及一硬遮罩層14,例如氮化矽層。硬遮罩層14亦可以是複數層結構,例如,氮化矽層加上矽氧層。然後,利用微影及蝕刻製程,於硬遮罩層14形成開口14a。
如第6圖所示,接著於開口14a的側壁上形成側壁子16,例如氮化矽側壁子。形成側壁子16方法,例如,先沈積一均厚的氮化矽層,覆蓋住側壁子16,並順應的覆蓋住開口14a的側壁及底部,再以非等向性蝕刻製程回蝕刻該氮化矽層。接下來,再進行乾蝕刻製程,利用側壁子16作為蝕刻遮罩,繼續經由開口14a蝕刻基底10至一預定深度,如此在開口14a下方形成一溝渠114,其開口寬度大小,可以藉由側壁子16的厚度來控制,例如,側壁子16的厚度可以小於開口14a寬度的四分之一。
如第7圖所示,進行一熱氧化製程,例如,在溫度介於 800-1200℃,以水蒸汽、氧氣,或內含少量氯化氫或氮氣的水蒸汽或氧氣,製程壓力介於600-760托耳(torr)的條件下,利用側壁子16作為保護層,氧化基底10,直到溝渠114最後被氧化層18填滿,而在氧化層18表面上留下楔形凹陷結構18a,同時,會產生輕微的鳥嘴18b。此實施例係利氮化矽側壁子之厚度,縮減絕緣溝渠之寬度,以提高積集度。
請參閱第8圖至第10圖,其為依據本發明又另一實施例所繪示的溝渠絕緣製程示意圖。首先,如第8圖所示,同樣提供一基底10,例如,半導體基底,接著於基底10表面形成一矽氧墊層12以及一硬遮罩層14,例如氮化矽層。硬遮罩層14亦可以是複數層結構,例如,氮化矽層加上矽氧層。然後,利用微影及蝕刻製程,於硬遮罩層14形成開口14a。繼續經由開口14a蝕刻基底10至一第一預定深度(小於0.2微米),如此形成一凹陷區域122。
如第9圖所示,接著於開口14a的側壁上形成側壁子16,例如氮化矽側壁子。形成側壁子16方法,例如,先沈積一均厚的氮化矽層,覆蓋住側壁子16,並順應的覆蓋住開口14a的側壁及底部,再以非等向性蝕刻製程回蝕刻該氮化矽層。接下來,再進行乾蝕刻製程,利用側壁子16作為蝕刻遮罩,繼續經由開口14a以及凹陷區域122蝕刻基底10至一第二預定深度,如此形成一溝渠124,其開口寬度大小,可以藉由側壁子16的厚度來控制。
如第10圖所示,進行一熱氧化製程,例如,在溫度介於800-1200℃,以水蒸汽、氧氣,或內含少量氯化氫或氮氣的水蒸汽或氧氣,製程壓力介於600-760托耳(torr)的條件下,利用側壁子16 作為保護層,氧化基底10,直到溝渠124最後被氧化層18填滿,而在氧化層18表面上留下楔形凹陷結構18a,同時,會產生輕微的鳥嘴18b。相較於第7圖,由於有凹陷區域122,使得側壁子16可以保護住主動區域的轉角處,故第10圖中的鳥嘴18b較不易伸入主動區域也較不明顯,因此更能有效的利用主動區域之面積。
以上所述僅為本發明之較佳實施例,凡依本發明申請專利範圍所做之均等變化與修飾,皆應屬本發明之涵蓋範圍。
10‧‧‧基底
12‧‧‧矽氧墊層
14‧‧‧硬遮罩層
14a‧‧‧開口
16‧‧‧側壁子
18‧‧‧氧化層
18a‧‧‧楔形凹陷結構
18b‧‧‧鳥嘴
20‧‧‧氧化襯墊層
22‧‧‧介電層
102‧‧‧第一溝渠
104‧‧‧第二溝渠
114‧‧‧溝渠
122‧‧‧凹陷區域
124‧‧‧溝渠
AA‧‧‧主動區域
第1圖至第4圖為依據本發明一實施例所繪示的溝渠絕緣製程示意圖。
第5圖至第7圖為依據本發明另一實施例所繪示的溝渠絕緣製程示意圖。
第8圖至第10圖為依據本發明又另一實施例所繪示的溝渠絕緣製程示意圖。
10‧‧‧基底
12‧‧‧矽氧墊層
14‧‧‧硬遮罩層
18‧‧‧氧化層
18a‧‧‧楔形凹陷結構
20‧‧‧氧化襯墊層
22‧‧‧介電層
AA‧‧‧主動區域

Claims (19)

  1. 一種溝渠絕緣製程,包含有:提供一基底,其上設有一墊層以及一硬遮罩層;於該硬遮罩層形成至少一開口;經由該開口蝕刻該基底,形成一第一溝渠;於該第一溝渠的側壁上形成一側壁子;經該第一溝渠蝕刻該基底,於該第一溝渠下方形成一第二溝渠;進行一熱氧化製程,利用該側壁子作為一保護層,氧化該第二溝渠內的該基底以形成一氧化層,直到該第二溝渠被該氧化層填滿;移除該側壁子,顯露出該第一溝渠的側壁;於顯露出來的該第一溝渠的側壁上形成一襯墊層;以及進行一化學氣相沈積製程,沈積一介電層,填滿該第一溝渠。
  2. 如申請專利範圍第1項所述之溝渠絕緣製程,其中該墊層為一矽氧墊層。
  3. 如申請專利範圍第1項所述之溝渠絕緣製程,其中該側壁子為一氮化矽層。
  4. 如申請專利範圍第1項所述之溝渠絕緣製程,其中該熱氧化製程係在溫度介於800-1200℃,以水蒸汽、氧氣,或內含少量氯化氫或氮氣的水蒸汽或氧氣,製程壓力介於600-760托耳的條件下進行。
  5. 如申請專利範圍第1項所述之溝渠絕緣製程,其中該第二溝渠的開口寬度大小,藉由該側壁子的厚度來控制。
  6. 如申請專利範圍第1項所述之溝渠絕緣製程,其中該襯墊層係為一氧化襯墊層。
  7. 如申請專利範圍第1項所述之溝渠絕緣製程,其中該氧化層表面具有一楔形凹陷結構。
  8. 一種溝渠絕緣製程,包含有:提供一基底,其上設有一墊層以及一硬遮罩層;於該硬遮罩層形成至少一開口;於該開口的側壁上形成一側壁子;經由該開口蝕刻該基底,形成一溝渠;以及進行一熱氧化製程,利用該側壁子作為一保護層,氧化該溝渠內的該基底以形成一氧化層,直到該溝渠被該氧化層填滿。
  9. 如申請專利範圍第8項所述之溝渠絕緣製程,其中該墊層為一矽氧墊層。
  10. 如申請專利範圍第8項所述之溝渠絕緣製程,其中該側壁子為一氮化矽層。
  11. 如申請專利範圍第8項所述之溝渠絕緣製程,其中該熱氧化製程係在溫度介於800-1200℃,以水蒸汽、氧氣,或內含少量氯化氫或氮氣的水蒸汽或氧氣,製程壓力介於600-760托耳的條件下進行。
  12. 如申請專利範圍第8項所述之溝渠絕緣製程,其中該側壁子的厚度小於該開口的寬度的四分之一。
  13. 如申請專利範圍第8項所述之溝渠絕緣製程,其中該氧化層表面具有一楔形凹陷結構。
  14. 一種溝渠絕緣製程,包含有:提供一基底,其上設有一墊層以及一硬遮罩層;於該硬遮罩層形成至少一開口;經由該開口蝕刻該基底至一預定深度,形成一凹陷區域;於該開口的側壁上形成一側壁子;經由該開口以及該凹陷區域蝕刻該基底,形成一溝渠;以及進行一熱氧化製程,利用該側壁子作為一保護層,氧化該溝渠內的該基底以形成一氧化層,直到該溝渠被該氧化層填滿。
  15. 如申請專利範圍第14項所述之溝渠絕緣製程,其中該預定深度小於0.2微米。
  16. 如申請專利範圍第14項所述之溝渠絕緣製程,其中該墊層為一 矽氧墊層。
  17. 如申請專利範圍第14項所述之溝渠絕緣製程,其中側壁子為一氮化矽層。
  18. 如申請專利範圍第14項所述之溝渠絕緣製程,其中該熱氧化製程係在溫度介於800-1200℃,以水蒸汽、氧氣,或內含少量氯化氫或氮氣的水蒸汽或氧氣,製程壓力介於600-760托耳的條件下進行。
  19. 如申請專利範圍第14項所述之溝渠絕緣製程,其中該氧化層表面具有一楔形凹陷結構。
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CN201210378608.9A CN103681452B (zh) 2012-08-28 2012-10-09 沟渠绝缘工艺
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