TWI463755B - 使用掃瞄雷射之差排工程 - Google Patents
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- 239000004065 semiconductor Substances 0.000 claims abstract description 55
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- 230000008030 elimination Effects 0.000 claims 2
- 238000003379 elimination reaction Methods 0.000 claims 2
- 230000001360 synchronised effect Effects 0.000 claims 2
- 235000012431 wafers Nutrition 0.000 description 27
- 238000005516 engineering process Methods 0.000 description 9
- 238000005224 laser annealing Methods 0.000 description 7
- 239000000758 substrate Substances 0.000 description 6
- 230000008859 change Effects 0.000 description 3
- 230000007547 defect Effects 0.000 description 3
- 238000006073 displacement reaction Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 238000010521 absorption reaction Methods 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 239000011540 sensing material Substances 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 229910005540 GaP Inorganic materials 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000011156 evaluation Methods 0.000 description 1
- 230000001747 exhibiting effect Effects 0.000 description 1
- HZXMRANICFIONG-UHFFFAOYSA-N gallium phosphide Chemical compound [Ga]#P HZXMRANICFIONG-UHFFFAOYSA-N 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- 238000005286 illumination Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000002086 nanomaterial Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- 238000004627 transmission electron microscopy Methods 0.000 description 1
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Description
本發明係關於在半導體裝置內使用掃描雷射操縱差排之系統及方法。
目前65奈米(nm)或更微小的技術已經廣泛使用應變工程(strain engineering)將裝置效能最佳化,此範圍內差排的產生與不受控制的行為是常見問題來源,因為這些缺陷提供漏電路徑,也導致非所要的局部應變變化。同時,利用差排動作故意釋放應變層是準備其上可成長應變層的基板之常見技術。
積體電路製程技術之經濟性的決定因素為良率,也就是所處理晶片良好總數的百分比。複雜積體電路的良率通常只有幾個百分點,影響良率的一項主要因素就是矽內或其上建立積體電路的其他半導體晶圓內存在的結晶缺陷。某些結晶缺陷可歸類成差排,這可能是在高溫製程中出現大應變時所引發的。
在半導體裝置內產生圖案應變區的方法之示範具體實施例包含將光束局部導引至半導體的本體表面部分上;並且使用光束操縱半導體本體之表面部分附近的複數個差排,該光束的特徵在於具有掃描速度,用以產生圖案應變區。
在半導體裝置內產生圖案應變區的方法之示範具體實施例包含將雷射光束局部導引至半導體本體的表面部分上、在第一操作模式或第二操作模式內操作雷射光束;該雷射光束之特徵在於具有掃描速度,並且使用雷射光束操縱半導體本體之表面部分附近的複數個差排,用以產生圖案應變區,在該第一操作模式與該第二操作模式期間操縱該複數個差排。
操縱半導體裝置上差排的系統之示範具體實施例包含具有複數個差排的半導體本體;以及配置成在該半導體本體之表面部分上局部產生雷射光束的可移動式雷射,該可移動式雷射之特徵在於具有掃瞄速度,該可移動式雷射利用調整雷射光束的溫度與掃描速度,操縱該半導體本體表面部分附近的複數個差排。
與本發明有關的標的在本說明書中會特別指出並在申請專利範圍內提出。從下列參考附圖的實施方式中,將會瞭解本發明的上述目的與其他目的、特徵和優點。
本發明及其許多特徵和優點細節都將由非限制性的具體實施例以附圖的圖解以及下述的說明,作更完整的表達。吾人應該注意,圖式內說明的元件並未按照比例繪製。熟知或習用的組件與處理技術之說明可省略,以避免不必要地模糊本發明細節。此處使用的範例僅為了幫助瞭解本發明的實踐,並且進一步讓熟知本技術的人士實踐本發明。因此,範例不應用於限制本發明的範疇。
本發明的示範具體實施例提供利用光束(例如雷射光束)操縱許多半導體技術內差排之系統及方法。照射到光束的差排會在光束入射時移動,對差排評估進行時間與空間控制。這種系統及方法提供說明此處所提排放與衝浪這兩種現象之操作模式,這些現象可用來執行許多差排操縱。
本發明者已經瞭解此處說明的系統及方法消除絕緣層上矽晶(silicon on insulator,SOI)技術裝置內存在的差排。此處所說明的系統及方法進一步控制高溫雷射退火(laser annealing,LSA)期間差排的成長,並使局部(圖案)的層應變鬆弛(relaxation)。此處所述的系統及方法進一步產生無軸向應變區,並且消除鬆弛應變層內的貫穿式差排(threading dislocations)。這種系統及方法進一步產生特定差排圖案以及相關應變場,當成用於控制磊晶島(epitaxial island)與奈米結構的成長空間之模板。
為了更瞭解本發明及其操作,現在請參閱圖式,圖1說明一部分半導體本體或晶圓,一般標示為10。根據一個示範具體實施例,晶圓由矽製成。當然,其他合適材料也可用來形成晶圓,像是鍺、磷化鎵、砷化鎵等。晶圓10位在絕緣層上,例如表面崁埋氧化物的層,顯示成位在虛線12之下。半導體本體10製造成包含主動區14,其上電流流動並且要形成像是電晶體積體電路之類的半導體裝置。晶圓組態經過變化可達成許多目標,並且應該不受此處所示組態之限制。換言之,此處說明的組態僅用於說明操縱半導體技術與半導體基板上差排之方法,因此不應限制本發明示範具體實施例的範疇。
根據一個示範具體實施例,由箭頭16表示的移動光束直接掃過晶圓10的表面部分,尤其是掃過晶圓10上設置的主動區14。更特別的是,光束16將晶圓10局部加熱,讓晶圓10上呈現差排,最重要就是在主動區14上形成差排,增加移動性。差排因為預先存在的應變(例如矽晶圓上的SiGe)而移動,並且因為光源(例如雷射)本身產生較大應力場沿著光束移動。隨著將差排驅動至崁埋氧化物層和淺溝渠氧化物內,這可有效免於形成不必要的漏電路徑。
光束可透過任何來源形式產生,像是雷射,設置成改變溫度、切換速度、吸收外型以及光束點大小。不過,也可使用其他光源的光束,例如像是燈泡。為了簡化起見,此處的方法將以使用掃描雷射裝置的雷射光束來說明。這種裝置用在掃描雷射退火(LSA)組態當中,來如所述移動差排。不過,在本發明的其他示範具體實施例內可使用其他組態,並且不受限於此處揭露的範例。
根據一個示範具體實施例,對雷射光束16進行控制,如此可實施兩操縱差排的相異操作模式。此處將第一操作模式稱為「排放(blow-down)」,在此操作模式內,來自雷射光束16的應力將差排驅動至基板或至吸收散熱器(absorbing sink),像是崁埋的氧化物(buried oxide,BOX)層18,或至淺溝渠絕緣(shallow trench isolation,STI)結構19,如圖1內所示。此操作模式可以消除晶圓10內已經存在的差排。
圖2內顯示排放技術如何操縱半導體裝置上差排之較佳說明。在晶圓表面22之下事先存在的差排或差排迴圈,一般標示為20,受到具有箭頭26指示之掃描方向的雷射光束24之照射。雷射光束24局部加熱晶圓表面22之下的區域。結果,雷射光束24熱點之下的差排20大小增加,如圖示。差排20移動到光束入射之處。箭頭28指示差排的動作。差排20到達的最高速率小於雷射光束24的掃描速度時,如圖2內所示,其本身就會發生排放現象。差排20成長到微米大小,但在雷射光束24通過差排20之後停止成長,如圖3A圖和圖3B內所示。圖3A說明雷射光束24通過差排20之前,而圖3B則說明雷射光束24通過差排20之後。雖然使用LSA組態說明排放效果,使用快閃退火組態也可發生排放效果。
圖4用放大圖說明晶圓10的部分側視剖面圖。此示範圖顯示利用直接穿透式電子顯微鏡(transmission electron microscopy,TEM)所觀察到的排放現象。不過,也可使用觀察排放現象的其他工具及方法。此示範圖顯示利用攝氏1250度(C)雷射掃描進行差排20排放並遠離主動區14。
圖5A至圖5B說明根據一個示範具體實施例的第二操作模式。此第二操作模式稱為「衝浪(surfing)」。使用之前說明此操作模式的範例,當雷射光束24的局部熱點溫度夠高,並且雷射應力與事先存在層應變的組合大到可使得差排20的速度符合雷射光束24的速度,則便發生衝浪。換言之,差排速率到達的最高值等於或超過雷射光束掃描速度就會發生衝浪。在此操作模式內,雷射光束24受控制,如此差排20的一端跟隨雷射光束24移動熱點,造成差排成長超過雷射掃描長度。圖5A說明雷射光束熱點通過差排之前的差排,而圖5B說明雷射光束熱點通過差排之後的差排。如所示,差排20的一端往雷射光束24的掃描方向26隨之移動。根據一個具體實施例,衝浪只發生在LSA組態內。
根據一個示範具體實施例,衝浪可利用將差排從差排來源移動至其他區,用於產生所要的差排圖案或應變工程圖案的鬆弛特定區。換言之,雷射光束可用來沿著許多「蝕刻素描」(etch-a-sketch)方式所要的路徑,從在一層上任何點畫出差排。
根據一個示範具體實施例,雷射光束的溫度以及停留時間(雷射點厚度/LSA掃描速度)在半導體技術內操縱許多種差排大小中扮演重要的角色。高溫讓差排變的更活躍並且根據所要的操作模式,雷射光束的掃描速度將決定差排是否成長超過掃描長度。根據一個示範具體實施例,衝浪型成長一般發生在雷射光束溫度大約高於攝氏1250度並且掃描速度大於1毫秒(millisecond,ms)時。在顯著較低溫或較短停留時間上,不會發生衝浪。例如:雷射光束以絕對溫度1498度(Kelvin,K)掃描時,40奈米(nano-micron,nm)差排迴圈上不會發生衝浪,在以1624K掃描時就會發生衝浪。如此,可調整溫度與掃描速度,避免將差排從晶圓一部分拖曳到另一部分。吾人應該瞭解,根據應用情況,不同的晶圓材料會影響將差排從半導體技術移出或移入所需的溫度與停留時間。
根據一個示範具體實施例,雷射掃描方向也在分別操縱許多種半導體技術內差排之中扮演重要角色。差排只在指定滑行平面內移動,因此在滑行平面上與雷射光束掃描方向垂直的差排將不會展現出衝浪現象。只有在滑行平面上沿著掃描方向的差排才有衝浪現象。如此可控制雷射光束,這樣只能操縱滑行平面上一個方向內的差排,以獲得所要差排圖案或所要非對稱鬆弛程度。不過,當雷射通過差排時,在某些程度內所有差排都將展現出排放現象。
根據一個示範具體實施例,利用新增應變層至晶圓10也可操縱晶圓10上的差排。因為差排回應應變來移動(熱誤配),在晶圓10的現有差排上新增其他應變可讓差排移動更迅速。例如:在晶圓上新增50nm,1%應變層經過1498K雷射掃描時會發生衝浪。
因為差排對於不同應變感應材料具有不同的回應,所以也可使用不同應變感應材料來操縱差排。換言之,差排在某些材料上比較好移動,某些則否。例如:差排的移動性降低為例如三分之一,在具有上述應變層上進行1498K掃描時在差排上也不會發生衝浪。
根據本發明的一個示範具體實施例,此處所述的方法可用來操縱差排,如此可提供無軸向層鬆弛或應變產生。圖6說明如何提供無軸向層鬆弛或應變產生。在此示範圖內,晶圓10製造成包含植入區50和非植入區52。根據一個具體實施例,光柵掃描產生器從內含差排的植入區光柵掃描至非植入區,以排列的差排填入後者。在操作上,植入區經過雷射光束16照射,如此非植入區52內的應變往一個方向釋放,藉此應變只流在一個方向。這種組態可用於許多應用當中。
根據一個示範具體實施例,衝浪技術也可用於從鬆弛的應變層中移除貫穿式差排,如圖7內所示。在此,利用讓在衝浪模式內運作的雷射光束通過光柵,將任何貫穿式差排(即是延伸於表面者)掃出相關區域。如此移除其上要建構微電子裝置的晶圓區域內之潛在漏電路徑來源。
在上面的具體實施例內,利用改變溫度、清掃速度、吸收外型以及雷射光束24點大小可有效改變差排演進。許多塑造技術都可用來預測上述現象,並可經過直接實驗觀察來驗證。
在此已經說明過本發明的較佳具體實施例,但精通此技術的人士就可了解到,目前與未來可在不悖離下列申請專利範圍的範疇下進行各種修改與增強。這些申請專利範圍應該對本發明構成適當保護。
10...晶圓
12...虛線
14...主動區
16...箭頭
18...崁埋的氧化物層
19...淺溝渠絕緣結構
20...差排
22...晶圓表面
24...雷射光束
26...箭頭
28...箭頭
50...植入區
52...非植入區
圖1至圖3為根據本發明的一個示範具體實施例,要進行操縱基板差排排放技術的示範半導體裝置之許多示意剖面圖;
圖4說明根據本發明示範具體實施例展現出排放現象的晶圓部分側剖面圖之示範微縮照片;
圖5A和圖5B為根據本發明的其他示範具體實施例,要進行操縱基板差排衝浪技術的示範半導體裝置之剖面圖;
圖6為根據本發明的一個示範具體實施例,要進行操縱基板差排衝浪技術來允許產生非軸向應變區的示範半導體裝置之剖面圖;以及
圖7為根據本發明的一個示範具體實施例,要進行衝浪技術從鬆弛的應變層中移除貫穿式差排的示範半導體裝置之剖面圖。
這些實施方式藉由參考附圖的範例來解釋本發明的較佳具體實施例,以及優點與特徵。
10...晶圓
12...虛線
14...主動區
16...箭頭
18...崁埋的氧化物層
19...淺溝渠絕緣結構
Claims (10)
- 一種自一半導體裝置移除差排之方法,包含以下步驟:局部指引一光束到一半導體本體的一表面部分上,該半導體本體包含該半導體裝置的主動區域;以及使用該光束操縱在該半導體本體之該表面部分附近的複數個差排,該光束的特徵在於具有一掃描速度;其中操縱該複數個差排包含使用該光束直接掃描該複數個差排,如此將該複數個差排驅動離開該半導體本體的該表面部分並進入一埋藏氧化層,該埋藏氧化層設置成一連續的且未中斷的層位於該半導體裝置的主動區域下方且位於鄰近該主動區域的一矽溝槽隔離區域的下方,以及該掃描致能消除該半導體本體上該複數個差排。
- 如申請專利範圍第1項之方法,其中該光束用以控制掃描期間該複數個差排的移動。
- 如申請專利範圍第1項之方法,其中當該複數個差排以低於該光束掃描速度的最高速率移動時,該光束驅動該複數個差排遠離該半導體本體的該表面部分。
- 如申請專利範圍第1項之方法,其中當該光束掃描通過該複數個差排時,每一該複數個差排的至少一端與該光束的該掃描方向同步並往此方向移動。
- 如申請專利範圍第1項之方法,其中使用該光束在該半導體本體上產生特定差排圖案,來操縱該複數個差排。
- 一種自一半導體裝置移除差排之方法,包含以下步驟:局部指引一雷射光束到一半導體本體的一表面部分上,該半導體本體包含該半導體裝置的主動區域;在一第一操作模式或一第二操作模式內操作該雷射光束,該雷射光束的特徵在於具有一掃描速度;以及使用該雷射光束操縱該半導體本體之表面部分附近的複數個差排以產生該圖案應變區;其中該第一操作模式包含使用該雷射光束直接掃描該複數個差排,如此將該複數個差排驅動離開該半導體本體的該表面部分並進入一埋藏氧化層,該埋藏氧化層設置成一連續的且未中斷的層位於該半導體裝置的主動區域下方且位於鄰近該主動區域的一矽溝槽隔離區域的下方,以及該掃描致能消除該半導體本體上該複數個差排。
- 如申請專利範圍第6項之方法,其中該雷射光束可操作控制掃描期間該複數個差排的移動。
- 如申請專利範圍第6項之方法,其中當該複數個差排以低於該雷射光束掃描速度的最高速率移動時,該雷射光束驅動該複數個差排遠離該半導體本體的該表面部分。
- 如申請專利範圍第6項之方法,其中當該雷射光束掃描通過該複數個差排時,每一該複數個差排的至少一端與該雷射光束的該掃描方向同步並往此方向移動。
- 一種操縱半導體裝置上差排之系統,包含:包含主動區域的一半導體本體,其具有複數個差排,該半導體本體設置於一連續的且未中斷的埋藏氧化層上,該等主動區域與一矽溝槽隔離區域配置於該半導體本體的下方;以及一可移動雷射,其配置成在該半導體本體的表面部分上局部產生一雷射光束,該可移動式雷射的特徵在於具有一掃描速度,該可移動是雷射利用調整該雷射光束的該溫度與該掃描速度,操縱該半導體本體之表面部分上的該複數個差排,如此將該複數個差排從該半導體本體驅動進入該埋藏氧化層。
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US (5) | US8138066B2 (zh) |
EP (1) | EP2332168B1 (zh) |
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KR (1) | KR101475992B1 (zh) |
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2008
- 2008-10-01 US US12/242,990 patent/US8138066B2/en not_active Expired - Fee Related
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2009
- 2009-07-24 WO PCT/EP2009/059552 patent/WO2010037577A1/en active Application Filing
- 2009-07-24 EP EP09781028A patent/EP2332168B1/en not_active Not-in-force
- 2009-07-24 KR KR1020117007783A patent/KR101475992B1/ko not_active IP Right Cessation
- 2009-07-24 JP JP2011529490A patent/JP5005115B2/ja not_active Expired - Fee Related
- 2009-07-24 AT AT09781028T patent/ATE534139T1/de active
- 2009-09-28 TW TW098132667A patent/TWI463755B/zh not_active IP Right Cessation
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2012
- 2012-02-14 US US13/372,713 patent/US20120138823A1/en not_active Abandoned
- 2012-08-02 US US13/565,018 patent/US20120294322A1/en not_active Abandoned
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2014
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Patent Citations (6)
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TW200409293A (en) * | 2001-11-30 | 2004-06-01 | Koninkl Philips Electronics Nv | Method of manufacturing a semiconductor device |
CN1441463A (zh) * | 2002-02-28 | 2003-09-10 | 株式会社液晶先端技术开发中心 | 半导体薄膜的形成方法和半导体薄膜的形成装置 |
TW200403512A (en) * | 2002-08-23 | 2004-03-01 | Toppoly Optoelectronics Corp | Description of the invention |
TW200529422A (en) * | 2003-12-05 | 2005-09-01 | Ibm | Method of fabricating strained SSOI wafers |
CN1770391A (zh) * | 2004-11-01 | 2006-05-10 | 国际商业机器公司 | 半导体结构及其制造方法 |
TW200638463A (en) * | 2005-04-29 | 2006-11-01 | Taiwan Semiconductor Mfg Co Ltd | Method of forming locally strained transistor |
Also Published As
Publication number | Publication date |
---|---|
EP2332168B1 (en) | 2011-11-16 |
US8865571B2 (en) | 2014-10-21 |
JP2012504857A (ja) | 2012-02-23 |
JP5005115B2 (ja) | 2012-08-22 |
US20140154873A1 (en) | 2014-06-05 |
US20100081259A1 (en) | 2010-04-01 |
KR101475992B1 (ko) | 2014-12-30 |
EP2332168A1 (en) | 2011-06-15 |
ATE534139T1 (de) | 2011-12-15 |
US20120294322A1 (en) | 2012-11-22 |
US20120138823A1 (en) | 2012-06-07 |
US8138066B2 (en) | 2012-03-20 |
KR20110081965A (ko) | 2011-07-15 |
US8865572B2 (en) | 2014-10-21 |
WO2010037577A1 (en) | 2010-04-08 |
US20140154872A1 (en) | 2014-06-05 |
TW201015807A (en) | 2010-04-16 |
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