TWI460843B - 電磁屏蔽結構及其製作方法 - Google Patents

電磁屏蔽結構及其製作方法 Download PDF

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TWI460843B
TWI460843B TW100109929A TW100109929A TWI460843B TW I460843 B TWI460843 B TW I460843B TW 100109929 A TW100109929 A TW 100109929A TW 100109929 A TW100109929 A TW 100109929A TW I460843 B TWI460843 B TW I460843B
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substrate
electromagnetic shielding
shielding
stainless steel
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TW201240060A (en
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Ming Che Wu
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Universal Scient Ind Shanghai
Universal Global Scient Ind Co
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    • H01—ELECTRIC ELEMENTS
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    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
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    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
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Description

電磁屏蔽結構及其製作方法
本發明有關於一種電磁屏蔽結構及其製作方法，且特別是有關於一種提高電磁屏蔽效能之電磁屏蔽結構及其製作方法。
現今的電子產品中所使用到的電子電路元件皆須具備電磁屏蔽結構(EMI Shielding Structure)。其主要用途為防止各種電路元件之間的互相產生的電磁干擾現象發生。於各項電子產品之中，惟有具備優秀的電磁屏蔽結構才得以穩定且具備高可靠度的運作，並且受到使用者信賴與青睞。因此，電腦、手機、交通載具、導航系統、家用家電等各項領域，皆需要使用到電磁屏蔽結構的相關技術。
相關技術於製作電磁屏蔽結構時，其受限於濺鍍製程方法的厚度不均勻性影響，導致整體結構過於龐大，或製程時間拉長，造成電磁屏蔽效果不佳及生產成本增加。因此，致力於研發厚度均勻化的電磁屏蔽結構，為當前電磁屏蔽結構研發改良的首要目的。
本發明實施例在於提供一種具有提高電磁屏蔽效能的電磁屏蔽結構及其製作方法。
本發明實施例提供一種電磁屏蔽結構，其包括：一基板、至少一晶片單元、一封裝層及一電磁屏蔽單元。晶片單元設置於基板的表面且電性連接於基板，封裝層設置於基板上且覆蓋晶片單元。電磁屏蔽單元包括一第一屏蔽鍍層、一第二屏蔽鍍層及一第三屏蔽鍍層。第一屏蔽鍍層披覆封裝層的外表面及基板的側表面，第二屏蔽鍍層披覆第一屏蔽鍍層的外表面，第三屏蔽鍍層披覆第二屏蔽鍍層的外表面。
除此之外，本發明實施例還提供一種電磁屏蔽結構的製作方法，其包括步驟：設置至少一晶片單元於一基板表面上。成形一封裝層於基板上以覆蓋晶片單元。將一第一屏蔽鍍層同時覆蓋封裝層的外表面及基板的側表面。將一第二屏蔽鍍層覆蓋第一屏蔽鍍層的外表面。將一第三屏蔽鍍層覆蓋第二屏蔽鍍層的外表面。即可得到本發明之電磁屏蔽結構。
綜上所述，本發明實施例所提供的電磁屏蔽結構藉由濺鍍製程與化學無電鍍製程的交互應用，可提升鍍層的接著強度並使得電磁屏蔽單元的上方與側方厚度極為均勻。進一步達成提高電磁屏蔽效能以及降低生產成本的功效。
為使能更進一步瞭解本發明之特徵及技術內容，請參閱以下有關本發明之詳細說明與附圖，但是此等說明與所附圖式僅係用來說明本發明，而非對本發明的權利範圍作任何的限制。
請參閱圖1所示，其為本發明的電磁屏蔽結構之其中一實施例的剖面示意圖。根據本發明電磁屏蔽結構的其中一實施例，其包括：一基板1、至少一晶片單元2、一封裝層3及一電磁屏蔽單元4。
基板1可為一電路板，例如軟性印刷電路板(FPCB)或非軟性印刷電路板。而晶片單元2設置於基板1上，並且晶片單元2電性連接於基板1。其中，晶片單元2的數量並不加以限制，視產品需求而設置不同數量之晶片單元2於基板1上。封裝層3設置於基板1上且覆蓋晶片單元2。封裝層3可為不同種類之封裝材料，例如：熱固性膠體、環氧樹脂等。
電磁屏蔽單元4是由三個電磁屏蔽層所構成，其分別為一第一屏蔽鍍層41、一第二屏蔽鍍層42及一第三屏蔽鍍層43。第一屏蔽鍍層41披覆封裝層3的外表面及基板1的側表面，其中第一屏蔽鍍層41更包括一第一不鏽鋼濺鍍層411及一銅濺鍍層412(請參閱圖1A所示，其為電磁屏蔽單元4的局部放大示意圖)。也就是說，第一不鏽鋼濺鍍層411披覆封裝層3的表面及基板1的側表面，銅濺鍍層412披覆第一不鏽鋼濺鍍層411的表面。
再者，第二屏蔽鍍層42披覆第一屏蔽鍍層41的外表面。換句話說，第一屏蔽鍍層41的所有表面皆被第二屏蔽鍍層42所覆蓋。其中，第二屏蔽鍍層42為一化學銅鍍層421。
另外，第三屏蔽鍍層43披覆第二屏蔽鍍層42的外表面。其中，第三屏蔽鍍層43為一第二不鏽鋼濺鍍層431。
上述第一不繡鋼濺鍍層411、第二不繡鋼濺鍍層431及銅濺鍍層412可為一厚度介於0.05 um至0.15 um之間的金屬鍍層，化學銅鍍層421可為一厚度介於1 um至3 um之間的金屬鍍層。
若欲形成良好的電磁屏蔽作用，則整體結構需要具有接地之特性。因此，電磁屏蔽單元4與基板1需要有接觸關係存在，以形成電性連接關係。透過第一屏蔽鍍層41覆蓋於基板1的側表面，使得基板1與電磁屏蔽單元4形成電性連接。
請參閱圖2A至圖2E所示，其分別為本發明之其中一實施例的第一、二、三、四及五步驟製作方法的剖面示意圖。根據本發明電磁屏蔽結構的製作方法，其包括步驟：
第一步驟(請參閱圖2A)，首先，設置至少一晶片單元2於一基板1表面上，並且晶片單元2與基板1形成電性連接。
第二步驟(請參閱圖2B)，成形一封裝層3於基板1上且覆蓋晶片單元2。亦即，基板1上的所有晶片單元2皆被封裝層3包覆於其中。
第三步驟(請參閱圖2C)，將一第一屏蔽鍍層41同時覆蓋封裝層3的外表面及基板1的側表面。其中，第一屏蔽鍍層41以濺鍍製程方法，鍍著披覆於封裝層3的外表面及基板1的側表面。更進一步地，第一屏蔽鍍層41包括一第一不鏽鋼濺鍍層411及一銅濺鍍層412。因此，第一不鏽鋼濺鍍層411同時覆蓋封裝層3的外表面及基板1的側表面，銅濺鍍層412覆蓋第一不鏽鋼濺鍍層411的表面。然而，濺鍍製程方法使得待鍍物上方與側方的厚度比約為3：1，造成待鍍物上方與側方的厚度不均。為滿足最小厚度需求，將於下一步驟設法增加待鍍物側方的厚度，使得上方與側方的厚度更為趨近。
第四步驟(請參閱圖2D)，將一第二屏蔽鍍層42覆蓋第一屏蔽鍍層41的外表面。其中，第二屏蔽鍍層42以化學無電鍍製程的方法，鍍著披覆於第一屏蔽鍍層41的外表面。亦即，第二屏蔽鍍層42為一化學銅鍍層421，其與第一屏蔽鍍層41所使用的濺鍍製程不同。利用化學無電鍍製程，可針對待鍍物的側表面加厚，藉此彌補上一步驟造成的待鍍物厚度不均之問題。因此，從圖2D中可清楚看出，第二屏蔽鍍層42的側方厚度較上方厚度來的厚。
第五步驟(請參閱圖2E)，將一第三屏蔽鍍層43覆蓋第二屏蔽鍍層42的外表面。其中，第三屏蔽鍍層43以濺鍍製程方法，鍍著披覆於第二屏蔽鍍層42的外表面。亦即，第三屏蔽鍍層43為一第二不鏽鋼濺鍍層431，其與第一屏蔽鍍層41同樣為濺鍍製程。到此階段，即完成本發明的電磁屏蔽結構。
透過上述的各步驟所得到的電磁屏蔽結構，藉由濺鍍製程與化學無電鍍製程的交互應用，使得電磁屏蔽單元4上方與側方的厚度比約為1：1，不僅改善電磁屏蔽結構的電磁屏蔽功效，更可大幅降低生產成本。因為以往的製程方法，上方與側方厚度不均，為使側方厚度達到最小的電磁屏蔽厚度需求，勢必使得上方的厚度超過最小電磁屏蔽的厚度需求，形成多餘的鍍層厚度。
請參閱圖3所示，其為本發明晶圓級電磁防護結構的製作方法之各步驟流程示意圖。圖中之S301~S305分別為本發明其中一實施例的第一步驟至第五步驟。透過圖3可更為了解本發明之整體製作方法流程。
[實施例的可能功效]
根據本發明實施例，上述的電磁屏蔽結構藉由濺鍍製程與化學無電鍍製程的交互應用，可提升鍍層的接著強度並使得電磁屏蔽單元的上方與側方厚度極為均勻。進一步達成提高電磁屏蔽效能以及降低生產成本的功效。
以上所述僅為本發明之實施例，其並非用以侷限本發明之專利範圍。
1．．．基板
2．．．晶片單元
3．．．封裝層
4．．．電磁屏蔽單元
41．．．第一屏蔽鍍層
411．．．第一不鏽鋼濺鍍層
412．．．銅濺鍍層
42．．．第二屏蔽鍍層
421．．．化學銅鍍層
43．．．第三屏蔽鍍層
431．．．第二不鏽鋼濺鍍層
圖1為本發明電磁屏蔽結構的其中一實施例之剖面示意圖。
圖1A為圖1之電磁屏蔽單元的局部放大示意圖。
圖2A為本發明電磁屏蔽結構的其中一實施例之第一步驟剖面示意圖。
圖2B為本發明電磁屏蔽結構的其中一實施例之第二步驟剖面示意圖。
圖2C為本發明電磁屏蔽結構的其中一實施例之第三步驟剖面示意圖。
圖2D為本發明電磁屏蔽結構的其中一實施例之第四步驟剖面示意圖。
圖2E為本發明電磁屏蔽結構的其中一實施例之第五步驟剖面示意圖。
圖3為本發明晶電磁屏蔽結構的製作方法之各步驟流程示意圖。
1．．．基板
2．．．晶片單元
3．．．封裝層
4．．．電磁屏蔽單元
41．．．第一屏蔽鍍層
42．．．第二屏蔽鍍層
43．．．第三屏蔽鍍層

Claims (3)

  1. 一種電磁屏蔽結構，其包括：一基板；至少一晶片單元，其設置於該基板的表面且電性連接於該基板；一封裝層，其設置於該基板上且覆蓋上述至少一晶片單元；以及一電磁屏蔽單元，其包括：一第一屏蔽鍍層，該第一屏蔽鍍層更包括一第一不鏽鋼濺鍍層及一銅濺鍍層，該第一不鏽鋼濺鍍層披覆於該封裝層的表面及該基板的側表面，該銅濺鍍層披覆於該第一不鏽鋼濺鍍層的表面；一第二屏蔽鍍層，其為一披覆該銅濺鍍層的外表面的化學銅鍍層；以及一第二不鏽鋼濺鍍層，其披覆該化學銅鍍層的外表面。
  2. 如申請專利範圍第1項所述之電磁屏蔽結構，其中該基板為印刷電路板。
  3. 一種電磁屏蔽結構的製作方法，其包括步驟：設置至少一晶片單元於一基板表面上；成形一封裝層於該基板上以覆蓋上述至少一晶片單元；將一第一屏蔽鍍層同時覆蓋該封裝層及該基板，其中該第一屏蔽鍍層更包括一第一不鏽鋼濺鍍層及一銅濺鍍層，該第一不鏽鋼濺鍍層同時覆蓋該封裝層的外表面及該基板的側表面，該銅濺鍍層覆蓋該第一不鏽鋼濺鍍層的表面； 將一第二屏蔽鍍層覆蓋該第一屏蔽鍍層的銅濺鍍層的外表面，其中該第二屏蔽鍍層為一化學銅鍍層；以及將一第二不鏽鋼濺鍍層覆蓋該化學銅鍍層的外表面。
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