TWI460836B - 半導體晶片及其製造方法 - Google Patents

半導體晶片及其製造方法 Download PDF

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Publication number
TWI460836B
TWI460836B TW099143643A TW99143643A TWI460836B TW I460836 B TWI460836 B TW I460836B TW 099143643 A TW099143643 A TW 099143643A TW 99143643 A TW99143643 A TW 99143643A TW I460836 B TWI460836 B TW I460836B
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Taiwan
Prior art keywords
layer
nickel
width
copper pillar
copper
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TW099143643A
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English (en)
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TW201203482A (en
Inventor
Chien Ling Hwang
Ying Jui Huang
Zheng-Yi Lim
Yi Yang Lei
Cheng Chung Lin
Chung Shi Liu
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Taiwan Semiconductor Mfg
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Publication of TW201203482A publication Critical patent/TW201203482A/zh
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Publication of TWI460836B publication Critical patent/TWI460836B/zh

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Description

半導體晶片及其製造方法
本發明係有關於半導體封裝製程，且特別是有關於一種覆晶封裝之導電凸塊之結構及其製造方法。
覆晶技術於半導體裝置封裝中扮演著不可或缺的角色。覆晶微機電組成(assembly)包含使用焊料凸塊作為內連線，直接電性連接面朝下(face down)之電子元件至基材(例如電路板)上。由於覆晶封裝相較於其他封裝方法具有尺寸、效能、及設計彈性上的優勢，使覆晶封裝的使用率大幅成長。
近來，已發展出銅柱(copper pillar)技術。電子元件藉由銅柱來取代焊料凸塊，連接電子元件及基材。銅柱技術可使凸塊橋接的機率達到最低，減少電路的電容負載，及可使電子元件在更高的頻率下操作。
然而，傳統的焊料凸塊及銅柱製程仍具有缺點。例如，在傳統的焊料凸塊製程中，係使用焊料作為罩幕以蝕刻底下的凸塊下金屬層(under bump metallurgy，UBM)。然而，凸塊下金屬層可能會在蝕刻製程中受到橫向的侵蝕，造成凸塊下金屬層的底切(undercut)。凸塊下金屬層的底切可能會於焊料凸塊製程中導致應力產生。此種應力可能會造成底下的基材中的低介電常數介電層破裂。在銅柱製程中，應力可能沿著銅柱及用以連接電子元件的焊料之間的界面破裂，亦會沿著底切及銅柱之間的界面破裂，因而可能會導致高漏電流並嚴重影響可靠度。
因此，業界所需的是一種改良的結構及方法，來形成適於半導體晶圓之導電柱體，且具有良好的電性效能。
本發明係提供一種半導體晶片，包括：一基材；一連接墊，位於此基材上；一凸塊下金屬層，位於此連接墊上；一銅柱，位於此凸塊下金屬層上，此銅柱具有一頂面及一凹型側壁，其中此頂面具有一第一寬度；一鎳蓋層，具有一頂面及一底面，位於此銅柱之此頂面上，此鎳蓋層之底面具有一第二寬度，其中此第二寬度對此第一寬度之比例為約0.93至1.07；以及一焊料，位於此鎳蓋層之此頂面上。
本發明亦提供一種半導體晶片之製造方法，包括：提供一基材；形成一連接墊於此基材上；沉積一凸塊下金屬層於此連接墊上；形成一銅柱於此凸塊下金屬層上；沉積一鎳層於此銅柱上，其中此鎳層及此銅柱之間具有一界面；沉積一焊料於此鎳層上；在一水溶液中蝕刻此鎳層及此銅柱，此水溶液包含55至85體積百分比的磷酸、小於1體積百分比的以疊氮為主之化合物及小於1體積百分比的錫；以及在蝕刻此鎳層及此銅柱後，蝕刻此凸塊下金屬層。
本發明更提供一種半導體晶片之製造方法，包含：提供一基材；形成一連接墊於此基材上；沉積一含銅之凸塊下金屬層於此連接墊上；沉積一鎳層於此凸塊下金屬層上；沉積一焊料於此鎳層上：以及在一水溶液中蝕刻此鎳層及此凸塊下金屬層，此水溶液包含36至42體積百分比的磷酸、2至3體積百分比的硝酸、44至49體積百分比的醋酸及2至3體積百分比的錫。
為讓本發明之上述和其他目的、特徵、和優點能更明顯易懂，下文特舉出較佳實施例，並配合所附圖式，作詳細說明如下：
本發明接下來將詳加討論各種的實施例的製造及討論。然而，值得注意的是，本發明所提供之這些實施例僅提供本發明之發明概念，且其可以寬廣的形式應用於各種特定情況下。在此所討論之實施例僅用於舉例說明，並非以各種形式限制本發明。
第1至14圖顯示為依照本發明一或多個實施例之結構於各種製造階段之剖面圖。在此所述之詞彙“基材”意指為半導體基材，且在其上形成有各種膜層及積體電路元件。基材可包含矽或化合物半導體，例如砷化鎵、磷化銦、矽/鍺或碳化矽。在某些實施例中，膜層可包含介電層、摻雜層、金屬層、多晶矽層及/或可連接一膜層至其他一或多個膜層之通孔插塞(via plug)。在某些實施例中，積體電路元件可包含電晶體、電阻及/或電容。基材可為含複數個半導體晶片製造於基材表面上之晶圓的一部分，其中每個晶片包含一或多個積體電路。這些半導體晶片係由晶片間的切割道(未顯示)所分隔。以下的製程步驟將在基材表面的複數個半導體晶片上進行。
參見第1圖，提供一部分的基材101，其表面上具有複數個半導體晶片。在第1圖所顯示之一部分的基材101僅包含多個晶片中之一晶片的一部分。複數個內連線層103形成於基材101之表面上。內連線層103包含位於一或多層介電層中之一或多層導電層。導電層與積體電路電性連接，並提供積體電路至較上方的膜層的電性連接。內連線層103中的介電層可包含，例如介電常數介於約2.9至3.8的低介電常數材料、介電常數介於約2.5至2.9的超低介電常數材料、前述之組合或其類似物。一般而言，介電常數越低的介電層越易碎，且易於脫層而導致膜層破裂。
第一保護層105形成於內連線層103上，以保護積體電路元件及內連線層103免於受到損壞及污染。第一保護層105可為一或多層膜層，且通常包含例如未摻雜之矽玻璃(USG)、氮化矽(SiN)、二氧化矽、氮氧化矽。第一保護層105可避免或減少對於積體電路的水氣、機械(mechanical)及熱的損壞。
繼續參見第1圖，連接墊107形成於第一保護層105上。連接墊107與內連線層103中的導電層電性接觸，並提供與底下之積體電路元件電性連接。在一實施例中，連接墊107可包含導電材料，例如鋁、鋁合金、銅、銅合金或前述之組合。連接墊107可由物理氣相沉積作沉積，例如使用含導電材料之濺鍍靶材進行濺鍍沉積，接著以光學微影及蝕刻來圖案化沉積層以形成連接墊107。
參見第2圖，第二保護層109形成於第一保護層105及連接墊107上。第二保護層109可包含一或多個膜層，其可包含如前述之第一保護層所列之可用材料。第一保護層105及第二保護層109可具有相同或不同的材料。第二保護層109可由合適的沉積技術(例如化學氣相沉積)沉積於第一保護層105及連接墊107上。在沉積後，接著進行光學微影及蝕刻於連接墊107上的第二保護層109中，選擇性地定義開口111。第二保護層109部分地覆蓋連接墊107，剩餘在開口111中之連接墊107的表面則暴露於外。第二保護層109可吸收或釋放由基材封裝所導致的熱或機械應力。
參見第3圖，緩衝層113形成於第二保護層109及連接墊107上。緩衝層113包含聚亞醯胺、聚苯噁唑(polybenzoxazole，PBO)或環氧樹脂，且厚度為約2 μm至10 μm。緩衝層113作為應力緩衝，以在組裝製程中減少傳遞至第一保護層105及第二保護層109的應力。在某些實施例中，首先沉積緩衝層113覆於第二保護層109上，並填滿開口111以覆蓋連接墊107之暴露表面。沉積緩衝層113後，接著以光學微影及圖案化來選擇性定義一包含一部分的保護層109中的開口111及一部分的緩衝層113中的開口之結合開口(combined opening)。此結合開口115暴露出一部分的連接墊。結合開口115具有側壁114。
參見第4圖，凸塊下金屬層117形成於緩衝層113上、內襯於結合開口115之側壁114，及接觸連接墊107之暴露部分。在某些實施例中，凸塊下金屬層117可包含多層導電材料，例如銅層117a加上鈦層117b。凸塊下金屬層117中之每一層皆可使用電鍍製程形成，例如電化學電鍍，或可依照所使用之材料選用使用其他製程，例如濺鍍、蒸鍍、無電電鍍或電漿輔助式化學氣相沉積(PECVD)。
參見第5圖，光阻層119形成於凸塊下金屬層117上，並經圖案化以形成孔洞121，其暴露出至少位於結合開口115及連接墊107之暴露部分上之一部分的凸塊下金屬層117。光阻層扮演用於形成導電凸塊之金屬沉積製程之模具。光阻材料可填滿開口，適於使用在此製程中。
參見第6圖，可以蒸鍍、電鍍或網印方式形成銅層，填充一部分之孔洞121，以形成凸塊下金屬層117上之銅柱123。銅柱123可為純銅或銅合金。銅柱123具有頂面125。
鎳蓋層127形成於銅柱123之頂面125上，並填充一部分之孔洞121。在一實施例中，在含鎳之無電電鍍溶液中浸鍍基材101，形成鎳蓋層127。鎳係以化學反應製程沉積於銅柱123之表面125上。鎳蓋層127具有底面129及頂面131。在銅柱123及鎳蓋層127之間定義有一界面。
繼續參見第6圖，焊料133沉積於孔洞121中，焊料133填充鎳蓋層127之頂面131上的一部分的孔洞121。依照本發明一實施例，焊料133包含無鉛焊料或共晶焊料。焊料133的熔點低於銅柱123及鎳蓋層127的熔點。
參見第7圖，移除光阻層119，並接著暴露出焊料133、鎳蓋層127、銅柱123及凸塊下金屬層117。
參見第8A圖，進行第一蝕刻製程以蝕刻鎳蓋層127。在一實施例中，將基材101浸入至包含55至85體積百分比的磷酸、小於1體積百分比的以疊氮為主之化合物及小於1體積百分比的錫的水溶液中。在某些實施例中，水溶液包含體積百分比約70的磷酸。不受到理論的限制，可相信的是，以疊氮為主之化合物限制了對銅的蝕刻，錫限制了對焊料的蝕刻。此溶液可維持在約30至70℃的預定範圍內。既然在銅柱123及焊料133的表面之蝕刻反應受到抑制，係選擇性蝕刻了鎳蓋層127。儘管存在有蝕刻抑制劑，水溶液仍蝕刻一小部分的焊料133及鎳蓋層127。水溶液對於蝕刻焊料133及鎳蓋層127相對速率比例為小於約1/15，且對蝕刻於銅柱123及鎳蓋層127的相對速率比例為小於約1/20。
參見第8B圖，進行第二蝕刻製程以蝕刻凸塊下金屬層117。在一實施例中，首先，以包含氨水(NH4 OH)、磷酸、硝酸、氫氟酸或硫酸之水溶液濕蝕刻凸塊下金屬層117之銅層117a。在濕蝕刻之後，銅柱123具有凹形側壁。接著，以包含體積百分比小於1%的氫氟酸之水溶液濕蝕刻凸塊下金屬層117之鈦層117b。在其他實施例中，在包含含Cl2 、CFx 或CHFx 的氣態環境下乾蝕刻凸塊下金屬層117之鈦層117b。凸塊下金屬層117的第二蝕刻製程可包含濕蝕刻、乾蝕刻或前述之組合。
在蝕刻凸塊下金屬層117後，形成經蝕刻的鎳蓋層127及經蝕刻的銅柱123。經蝕刻的鎳蓋層127具有第一寬度W1。第一寬度W1鄰近於經蝕刻的鎳蓋層127與經蝕刻的銅柱123之間的界面。換句話說，第一寬度W1靠近鎳層127的底面129。經蝕刻的銅柱123具有第二寬度W2。第二寬度W2鄰近於經蝕刻的鎳蓋層127及經蝕刻的銅柱123之間的界面。換句話說，第二寬度W2鄰近於銅柱123之頂面。第一寬度W1對第二寬度W2的比例為約0.93至0.99，不管其機制為何，此比例可減少鎳蓋層127及銅柱123之間的界面的應力，而這些應力可能會在隨後的製程中產生沿著銅柱與底部填充材料(用於密封元件與晶片間的空隙)之間的界面的破裂。
第9圖顯示第8A及8B圖中的各種製程步驟，其中鎳蓋層127、銅柱123及凸塊下金屬層117的銅層117a係同時被蝕刻。在一實施例中，將基材101浸入至包含36至42體積百分比的磷酸、2至3體積百分比的硝酸、44至49體積百分比的醋酸及2至3體積百分比的錫的水溶液中。在某些實施例中，水溶液包含約40體積百分比的磷酸。可相信的是，錫抑制了對於焊料133的蝕刻。此溶液可維持在約30℃至45℃的預定溫度下。水溶液中對於焊料133及鎳蓋層127的相對蝕刻速率為小於1/13，對於銅柱123及鎳蓋層127的相對蝕刻速率為介於1/3及5之間。在經濕蝕刻製程之後，銅柱123具有凹形側壁。
在移除凸塊下金屬層117中的一部分之銅層117a後，凸塊下金屬層117之鈦層117b未由銅層117a所覆蓋的部分，可能會如同前述被濕蝕刻或乾蝕刻。
在經過蝕刻凸塊下金屬層117之一部分的銅層117a後，形成經蝕刻的鎳蓋層127及經蝕刻的銅柱123。經蝕刻的鎳蓋層127具有第一寬度W1。第一寬度W1鄰近於經蝕刻的鎳蓋層127及經蝕刻的銅柱123之間的界面。換句話說，第一寬度W1鄰近於經蝕刻的鎳蓋層127之底面129。經蝕刻的銅柱具有第二寬度W2。第二寬度W1鄰近於經蝕刻的鎳蓋層127及經蝕刻的銅柱123之間的界面。換句話說，第二寬度W2鄰近於銅柱123之頂面125。第一寬度W1對第二寬度W2的比例為約0.93至1.07。當比例為1時，在銅柱123及鎳蓋層127之間具有平滑的界面。不管其機制為何，上述之第一寬度W1對第二寬度W2的比例可減少在鎳蓋層127及銅柱123之間的界面的應力，而此種應力可沿著銅柱123及底部填充材料(用於在隨後製程中密封元件及晶片間之空隙)之間的界面產生破裂。
參見第10圖，焊料133係經回焊以覆蓋鎳蓋層127之頂面131。回焊製程可軟化及/或融化焊料133，但無法軟化及/或融化鎳蓋層127及銅柱123，以使焊料133可沿著頂面131流動。
第11圖顯示前述之銅柱結構在與元件135接合後之剖面圖。為了簡化以便於說明，元件135僅顯示為簡單的晶片，而無更詳細的構造。在一實施例中，元件135可包含半導體晶片、封裝基材、電路板或其他類似之合適元件。基材101及元件135可能經由銅柱123作電性連接。在一實施例中，接合方法放置一焊球137於焊料133上，以接合銅柱123及元件133。
在接合製程後，在基材101及電性元件133之間定義出一間隙。底部填充材料138可填充至此間隙中，以保護銅柱123及增加封裝的可靠度。底部填充材料139減少銅柱123、基材101及元件133之間的應力，且在堆疊的電子元件中均勻地傳遞熱。底部填充材料139可包含，但不限於，環氧樹脂、聚亞醯胺、其他熱塑性或熱固性材料、或其他合適之相似材料。
第12至14圖顯示第6圖至第9圖所述之導電凸塊製造之製程步驟之變化例。在第12圖中重複的標號代表與第6圖所示之元件相同或相似。
參見第12圖，鎳層141形成於凸塊下金屬層117上，並填充一部分之孔洞121。在一實施例中，在含鎳之無電電鍍溶液中浸鍍基材101，形成鎳層141。接著，鎳係以化學反應製程沉積至凸塊下金屬層117之表面上。接著，沉積焊料143至孔洞121中，填充焊料143在鎳層141頂面上之一部分的孔洞121中。依照本發明一實施例，焊料143包含無鉛焊料或共晶焊料。
參見第13圖，移除光阻層119，暴露出焊料143、鎳層141及凸塊下金屬層171。
參見第14圖，同時蝕刻鎳層141及凸塊下金屬層117之銅層117。在一實施例中，在含36至42體積百分比的磷酸、2至3體積百分比的硝酸、44至49體積百分比的醋酸、及2至2體積百分比的錫之水溶液中浸鍍基材101。在某些實施例中，水溶液包含體積百分比約40的磷酸。可相信的是，錫抑制了對於焊料的蝕刻。溶液可保持在約30℃至約45℃之間的預定溫度中。在水溶液中，焊料143對鎳層141的相對蝕刻比例為小於1/13，銅層117a對鎳層141的相對蝕刻比例為1/3至5。此蝕刻製程可在鎳層141及凸塊下金屬層117之銅層117a之間產生平滑的界面。平滑的界面可減少應力，而底下低介電常數材料降低破裂的機率。因此，可改善某些在傳統焊料凸塊之製程中可能會有的缺點。
在移除未被鎳層141所覆蓋之銅層117a後，未被銅層117a所覆蓋之凸塊下金屬層117之鈦層117b係經含體積百分比小於1的氫氟酸之水溶液蝕刻。在其他實施例中，含Cl2 、CFx 或CHFx 的氣態環境下乾蝕刻含凸塊下金屬層117之鈦層117b。凸塊下金屬層117之蝕刻製程可包含濕蝕刻、乾蝕刻或前述之組合。
本發明之各種實施例可用於解決傳統導電凸塊製程之缺點。例如，第一寬度W1對第二寬度W2的適當比例將減少應力，而此種會沿著導電柱123及焊料133/137(在隨後製程中用於連接元件)之間的界面產生破裂。在各種實施例中，將可提供在鎳蓋層127及銅柱123之間具有合適的界面形狀，亦可提供在鎳層141及凸塊下金屬層117之間具有合適的界面形狀，並將可提高組裝的產率。
雖然本發明已以數個較佳實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作任意之更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。此外，熟知本領域技藝人士將可依照本發明所揭示之現有或未來所發展之特定程序、機器、製造、物質之組合、功能、方法或步驟達成相同的功能或相同的結果。因此本發明之保護範圍包含這些程序、機器、製造、物質之組合、功能、方法或步驟。再者，每一申請專利範圍皆可視為建構一單獨的實施例，且各申請專利範圍及實施例之結合皆在本發明之範圍中。
101‧‧‧基材
103‧‧‧內連線層
105‧‧‧第一保護層
107‧‧‧連接墊
109‧‧‧第二保護層
111‧‧‧開口
113‧‧‧緩衝層
114‧‧‧側壁
115‧‧‧結合開口
117‧‧‧凸塊下金屬層
117a‧‧‧銅層
117b‧‧‧鈦層
119‧‧‧光阻層
121‧‧‧孔洞
123‧‧‧銅柱
125‧‧‧銅柱頂面
127‧‧‧鎳蓋層
129‧‧‧鎳蓋層底面
131‧‧‧鎳蓋層頂面
133‧‧‧焊料
135‧‧‧元件
137‧‧‧焊球
139‧‧‧底部填充材料
141‧‧‧鎳層
143‧‧‧焊材
W1‧‧‧第一寬度
W2‧‧‧第二寬度
第1~7、8A、8B、9~14圖顯示依照本發明實施例之結構在各種製造階段之剖面圖。
107．．．連接墊
109．．．第二保護層
113．．．緩衝層
117．．．凸塊下金屬層
117a．．．銅層
117b．．．鈦層
123．．．銅柱
127．．．鎳蓋層
131．．．鎳蓋層頂面
133．．．焊料

Claims (10)

  1. 一種半導體晶片，包括：一基材；一連接墊，位於該基材上；一凸塊下金屬層，位於該連接墊上；一銅柱，位於該凸塊下金屬層上，該銅柱具有一頂面及一內凹之弧形側壁，其中該頂面具有一第一寬度；一鎳蓋層，具有一頂面及一底面，位於該銅柱之該頂面上，該鎳蓋層之底面具有一第二寬度，其中該第二寬度對該第一寬度之比例為約0.93至1.07；以及一焊料，位於該鎳蓋層之該頂面上。
  2. 如申請專利範圍第1項所述之半導體晶片，更包含在該銅柱及該鎳蓋層之間有一平滑界面。
  3. 如申請專利範圍第1項所述之半導體晶片，其中該第二寬度對該第一寬度之比例為約0.93至0.99。
  4. 一種半導體晶片之製造方法，包括：提供一基材；形成一連接墊於該基材上；沉積一凸塊下金屬層於該連接墊上；形成一銅柱於該凸塊下金屬層上；沉積一鎳層於該銅柱上，其中該鎳層及該銅柱之間具有一界面；沉積一焊料於該鎳層上；在一水溶液中蝕刻該鎳層及該銅柱，該水溶液包含55至85體積百分比的磷酸、小於1體積百分比的以疊氮為主之化合物及小於1體積百分比的錫；以及在蝕刻該鎳層及該銅柱後，蝕刻該凸塊下金屬層。
  5. 如申請專利範圍第4項所述之半導體晶片之製造方法，其中以水溶液蝕刻該鎳層之步驟係在30℃至70℃下進行。
  6. 如申請專利範圍第4項所述之半導體晶片之製造方法，其中在蝕刻鎳層、該銅柱及蝕刻該凸塊下金屬層之之後，鄰近於該界面之經蝕刻的銅柱具有一第一寬度，鄰近於該界面之經蝕刻的鎳層具有一第二寬度，且該第二寬度對該第一寬度之比例為約0.93至0.99。
  7. 如申請專利範圍第4項所述之半導體晶片之製造方法，其中該銅柱為凹形。
  8. 一種半導體晶片之製造方法，包含：提供一基材；形成一連接墊於該基材上；沉積一含銅之凸塊下金屬層於該連接墊上；沉積一鎳層於該凸塊下金屬層上；沉積一焊料於該鎳層上：以及在一水溶液中蝕刻該鎳層及該凸塊下金屬層，該水溶液包含36至42體積百分比的磷酸、2至3體積百分比的硝酸、44至49體積百分比的醋酸及2至3體積百分比的錫。
  9. 如申請專利範圍第8項所述之半導體晶片之製造方法，其中在該水溶液中之蝕刻步驟係在30℃至45℃下進行。
  10. 如申請專利範圍第8項所述之半導體晶片之製造方法，更包含於該凸塊下金屬層上及該鎳層底下形成一銅柱，因而於該銅柱及該鎳層之間形成一界面，其中鄰近於該界面之該銅柱具有一第一寬度，鄰近於該界面之該鎳層具有一第二寬度，且該第二寬度對該第一寬度之比例為約0.93至1.07。
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