TWI457896B - Gate driver - Google Patents
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- TWI457896B TWI457896B TW101119994A TW101119994A TWI457896B TW I457896 B TWI457896 B TW I457896B TW 101119994 A TW101119994 A TW 101119994A TW 101119994 A TW101119994 A TW 101119994A TW I457896 B TWI457896 B TW I457896B
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Description
本發明係有關於一種閘極驅動器,尤指一種可以降低輸入雜訊的閘極驅動器。The present invention relates to a gate driver, and more particularly to a gate driver that can reduce input noise.
請參考第1圖,第1圖為習知液晶顯示面板100的示意圖。如第1圖所示,液晶顯示面板100包含有閘極驅動器110以及源極驅動器120,其中閘極驅動器110連接至多條掃描線G1、G2、G3、...,且用以循序驅動該些掃描線以開啟掃描線上的薄膜電晶體(Thin-film transistor,TFT),而源極驅動器120則連接至多條資料線D1、D2、...,且用來將顯示資料傳送至像素的像素電極中。由於第1圖所示之液晶顯示面板100的操作應為本領域中具有通常知識者所熟知,故細節在此不予贅述。Please refer to FIG. 1 , which is a schematic diagram of a conventional liquid crystal display panel 100 . As shown in FIG. 1 , the liquid crystal display panel 100 includes a gate driver 110 and a source driver 120 , wherein the gate driver 110 is connected to the plurality of scan lines G1 , G2 , G3 , . . . The scan line is turned on to turn on a thin film transistor (TFT) on the scan line, and the source driver 120 is connected to the plurality of data lines D1, D2, ..., and is used to transmit the display data to the pixel electrode of the pixel. in. Since the operation of the liquid crystal display panel 100 shown in FIG. 1 should be well known to those of ordinary skill in the art, the details are not described herein.
當液晶顯示面板100在操作時,源極驅動器120所輸出的資料訊號會透過資料線與掃描線之間的耦合電容Cgd影響到掃描線的電壓準位,特別是當掃描線的電壓準位為低閘極電壓準位時,此影響會瞬間影響到閘極驅動器110中P型基板(P-substrate)的電壓,進而造成內部邏輯訊號產生突波(glitch)。另外,若是之後源極驅動器120採用的高速介面技術,邏輯電壓降至1.8V時,上述耦合電容干擾問題會更加地嚴重。When the liquid crystal display panel 100 is in operation, the data signal outputted by the source driver 120 affects the voltage level of the scan line through the coupling capacitance Cgd between the data line and the scan line, especially when the voltage level of the scan line is At low gate voltage levels, this effect transiently affects the voltage of the P-substrate in the gate driver 110, which in turn causes glitches in the internal logic signal. In addition, if the high-speed interface technology used by the source driver 120 is followed, the coupling capacitor interference problem will be more serious when the logic voltage is reduced to 1.8V.
目前針對上述問題的解決方法是在閘極驅動器110上加入電阻電容濾波器,然而,由於所需過濾雜訊的寬度常常會因不同的面板尺寸、氧化銦錫(Indium-Tin Oxide,ITO)層的電阻值或是晶片貼合狀況而有所差異,故造成設計上的困擾。The current solution to the above problem is to add a resistor-capacitor filter to the gate driver 110. However, the width of the required filtering noise is often due to different panel sizes, Indium-Tin Oxide (ITO) layers. The resistance value or the wafer bonding condition varies, which causes design troubles.
因此,本發明的目的之一在於提供一種閘極驅動器,其利用邏輯電路來自動判斷出受雜訊干擾的異常訊號,並將之處理成正常訊號,以解決上述的問題。Accordingly, it is an object of the present invention to provide a gate driver that utilizes a logic circuit to automatically determine an abnormal signal that is subject to noise interference and process it into a normal signal to solve the above problem.
依據本發明一實施例,一種閘極驅動器包含有一接收單元以及一設定/重置閂鎖型式電路,該接收單元用來接收一第一訊號以及一第二訊號,其中該第一訊號與該第二訊號為互補訊號;該設定/重置閂鎖型式電路,用來接收該第一訊號與該第二訊號,並降低該第一訊號之雜訊以產生一處理後第一訊號。According to an embodiment of the invention, a gate driver includes a receiving unit and a set/reset latch type circuit, the receiving unit is configured to receive a first signal and a second signal, wherein the first signal and the first The second signal is a complementary signal; the set/reset latch type circuit is configured to receive the first signal and the second signal, and reduce the noise of the first signal to generate a processed first signal.
請參考第2圖,第2圖為依據本發明一實施例之閘極驅動器200的示意圖,如第2圖所示,閘極驅動器200耦接於一時序控制器(timing controller)202,且包含一接收單元210、一設定/重置閂鎖型式電路(SR latching-type circuit)220以及一處理電路230。閘極驅動器200與時序控制器202係製作於一液晶顯示面板上,且閘極 驅動器200自時序控制器202接收一時脈訊號CPV與其互補訊號CPVB及其他控制訊號(未繪示)以循序產生多個閘極控制訊號VG 至該液晶顯示面板上的掃描線。Referring to FIG. 2, FIG. 2 is a schematic diagram of a gate driver 200 according to an embodiment of the present invention. As shown in FIG. 2, the gate driver 200 is coupled to a timing controller 202 and includes A receiving unit 210, a SR latching-type circuit 220, and a processing circuit 230. The gate driver 200 and the timing controller 202 are formed on a liquid crystal display panel, and the gate driver 200 receives a clock signal CPV and its complementary signal CPVB and other control signals (not shown) from the timing controller 202 to sequentially generate more The gate control signal V G is to the scan line on the liquid crystal display panel.
在閘極驅動器200的操作上,首先,接收單元210自時序控制器202接收時脈訊號CPV及其互補訊號CPVB。接著,設定/重置閂鎖型式電路220接收時脈訊號CPV及其互補訊號CPVB,並降低時脈訊號CPV的雜訊以產生一處理後時脈訊號CPVI。最後,處理電路230接收處理後時脈訊號CPVI與其他來自時序控制器202的控制訊號(未繪示)以循序產生多個閘極控制訊號VG 至該液晶顯示面板上的掃描線。In operation of the gate driver 200, first, the receiving unit 210 receives the clock signal CPV and its complementary signal CPVB from the timing controller 202. Then, the set/reset latch type circuit 220 receives the clock signal CPV and its complementary signal CPVB, and reduces the noise of the clock signal CPV to generate a processed clock signal CPVI. Finally, the processing circuit 230 receives the processed clock signal CPVI and other control signals (not shown) from the timing controller 202 to sequentially generate a plurality of gate control signals V G to the scan lines on the liquid crystal display panel.
詳細來說,請參考第3圖所示之設定/重置閂鎖型式電路220的示意圖,設定/重置閂鎖型式電路220包含有一第一邏輯電路310、一閂鎖電路320以及一第二邏輯電路330,其中第一邏輯電路310包含有兩個反向器312、314以及兩個反及閘(NAND)316、318,閂鎖電路320為一設定/重置反及閘閂鎖器(SR NAND latch),且包含有兩個交互耦合的反及閘322、324,第二邏輯電路330則包含有一反及閘332以及一反向器334。此外,當閘極驅動器被啟動時,反及閘的輸入訊號VP 會直接被設為“1”。In detail, referring to the schematic diagram of the set/reset latch type circuit 220 shown in FIG. 3, the set/reset latch type circuit 220 includes a first logic circuit 310, a latch circuit 320, and a second. The logic circuit 330, wherein the first logic circuit 310 includes two inverters 312, 314 and two NAND gates 316, 318, and the latch circuit 320 is a set/reset reverse gate latch ( SR NAND latch, and includes two mutually coupled anti-gates 322, 324, and the second logic circuit 330 includes a reverse gate 332 and an inverter 334. In addition, when the gate driver is activated, the input signal V P of the reverse gate is directly set to "1".
在設定/重置閂鎖型式電路220的操作上,首先,反向器312接收互補訊號CPVB以產生一反向後互補訊號,接著反及閘316接收 時脈訊號CPV與反向後互補訊號以產生一設定訊號SETB;同時間,反向器314接收時脈訊號CPV以產生一反向後時脈訊號,接著反及閘318接收互補訊號CPVB與反向後時脈訊號以產生一重置訊號RSTB。接著,閂鎖電路320接收設定訊號SETB與重置訊號RSTB,並產生一輸出訊號Q,其中輸出訊號Q可視為經過雜訊處理後的時脈訊號。最後,輸出訊號Q經過反及閘332與反向器334的處理後產生一處理後時脈訊號CPVI。In the operation of setting/resetting the latch type circuit 220, first, the inverter 312 receives the complementary signal CPVB to generate a reverse post-complement signal, and then the gate 316 receives The clock signal CPV and the reverse post-complement signal generate a set signal SETB; at the same time, the inverter 314 receives the clock signal CPV to generate a reverse post-clock signal, and then the gate 318 receives the complementary signal CPVB and the reverse direction. The pulse signal generates a reset signal RSTB. Then, the latch circuit 320 receives the set signal SETB and the reset signal RSTB, and generates an output signal Q, wherein the output signal Q can be regarded as a clock signal after the noise processing. Finally, the output signal Q is processed by the inverse gate 332 and the inverter 334 to generate a processed clock signal CPVI.
請參考第4圖,第4圖為時脈訊號CPV、互補訊號CPVB與處理後時脈訊號CPVI的時序圖。如第4圖所示,當時脈訊號CPV與互補訊號CPVB分別為(1,0)時,設定訊號SETB為“0”,處理後時脈訊號CPVI為“1”;且當時脈訊號CPV與互補訊號CPVB分別為(0,1)時,重置訊號RSTB為“0”,處理後時脈訊號CPVI為“0”。亦即,設定/重置閂鎖型式電路220會自動處理掉時脈訊號CPV與互補訊號CPVB分別為(1,1)、或是分別為(0,0)時的錯誤狀態(亦即第4圖所示的突波402、404)。Please refer to FIG. 4, which is a timing diagram of the clock signal CPV, the complementary signal CPVB, and the processed clock signal CPVI. As shown in Figure 4, when the pulse signal CPV and the complementary signal CPVB are (1, 0) respectively, the setting signal SETB is "0", and the processed clock signal CPVI is "1"; and the pulse signal CPV is complementary. When the signal CPVB is (0, 1), the reset signal RSTB is “0”, and the clock signal CPVI is “0” after processing. That is, the set/reset latch type circuit 220 automatically processes the error state when the clock signal CPV and the complementary signal CPVB are (1, 1) or respectively (0, 0) (ie, 4th) The glitch 402, 404) shown in the figure.
此外,第3圖所示的設定/重置閂鎖型式電路220僅為範例說明,而並非作為本發明的限制,於本發明之其他實施例中,閂鎖電路320可以被替換為其他形式的閂鎖器,且第一邏輯電路310亦可以採用其他的電路架構以產生設定訊號SETB及重置訊號RSTB。另外,第二邏輯電路330的架構亦僅為一範例說明,其可以被替換為其他形式的邏輯電路,或是直接被移除以使得閂鎖電路320的輸 出Q直接作為設定/重置閂鎖型式電路220的輸出。上述設計上的變化均應隸屬於本發明的範疇。In addition, the set/reset latch type circuit 220 shown in FIG. 3 is merely illustrative and not a limitation of the present invention. In other embodiments of the present invention, the latch circuit 320 may be replaced with other forms. The latch circuit, and the first logic circuit 310 can also adopt other circuit architectures to generate the setting signal SETB and the reset signal RSTB. In addition, the architecture of the second logic circuit 330 is also merely an example, which may be replaced with other forms of logic circuits, or directly removed to cause the latch circuit 320 to lose. Output Q is directly used as the output of the set/reset latch type circuit 220. Variations in the above design are all within the scope of the present invention.
此外,本發明的設定/重置閂鎖型式電路220並不僅限於用來處理來自時序控制器的時脈訊號CPV與互補訊號CPVB,而是可以用來處理其他的互補訊號以消除掉類似突波的雜訊干擾。In addition, the set/reset latch type circuit 220 of the present invention is not limited to processing the clock signal CPV and the complementary signal CPVB from the timing controller, but can be used to process other complementary signals to eliminate similar surges. Noise interference.
簡要歸納本發明,於本發明的閘極驅動器中,包含有一設定/重置閂鎖型式電路,其可以用來接收第一訊號及與其互補的第二訊號,並降低第一訊號的雜訊以產生一處理後第一訊號。相較於習知技術,本發明之具有設定/重置閂鎖型式電路的閘極驅動器可以廣泛應用於各種面板中,具有簡單的架構,且可以確實降低雜訊干擾,以解決習知技術的問題。Briefly summarized, the gate driver of the present invention includes a set/reset latch type circuit that can be used to receive the first signal and the second signal complementary thereto, and to reduce the noise of the first signal. A first signal after processing is generated. Compared with the prior art, the gate driver of the present invention having a set/reset latch type circuit can be widely applied to various panels, has a simple structure, and can reliably reduce noise interference to solve the conventional technology. problem.
以上所述僅為本發明之較佳實施例,凡依本發明申請專利範圍所做之均等變化與修飾,皆應屬本發明之涵蓋範圍。The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.
100‧‧‧液晶顯示面板100‧‧‧LCD panel
110、200‧‧‧閘極驅動器110, 200‧‧ ‧ gate driver
120‧‧‧源極驅動器120‧‧‧Source Driver
202‧‧‧時序控制器202‧‧‧Sequence Controller
210‧‧‧接收單元210‧‧‧ Receiving unit
220‧‧‧設定/重置閂鎖型式電路220‧‧‧Set/Reset Latch Type Circuit
230‧‧‧處理電路230‧‧‧Processing Circuit
310‧‧‧第一邏輯電路310‧‧‧First logic circuit
312、314、334‧‧‧反向器312, 314, 334‧‧‧ reverser
316、318、322、324、332‧‧‧反及閘316, 318, 322, 324, 332‧‧ ‧ anti-gate
320‧‧‧閂鎖電路320‧‧‧Latch circuit
330‧‧‧第二邏輯電路330‧‧‧Second logic circuit
Cgd‧‧‧耦合電容Cgd‧‧‧Coupling Capacitor
TFT‧‧‧薄膜電晶體TFT‧‧‧thin film transistor
G1~G3‧‧‧掃描線G1~G3‧‧‧ scan line
D1~D2‧‧‧資料線D1~D2‧‧‧ data line
第1圖為習知液晶顯示面板100的示意圖。FIG. 1 is a schematic view of a conventional liquid crystal display panel 100.
第2圖為依據本發明一實施例之閘極驅動器200的示意圖。2 is a schematic diagram of a gate driver 200 in accordance with an embodiment of the present invention.
第3圖為第2圖所示之設定/重置閂鎖型式電路的示意圖。Figure 3 is a schematic diagram of the set/reset latch type circuit shown in Figure 2.
第4圖為第3圖所示之時脈訊號CPV、互補訊號CPVB與處理後時脈訊號CPVI的時序圖。Figure 4 is a timing diagram of the clock signal CPV, the complementary signal CPVB, and the processed clock signal CPVI shown in Figure 3.
200‧‧‧閘極驅動器200‧‧ ‧ gate driver
202‧‧‧時序控制器202‧‧‧Sequence Controller
210‧‧‧接收單元210‧‧‧ Receiving unit
220‧‧‧設定/重置閂鎖型式電路220‧‧‧Set/Reset Latch Type Circuit
230‧‧‧處理電路230‧‧‧Processing Circuit
Claims (7)
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TW101119994A TWI457896B (en) | 2012-06-04 | 2012-06-04 | Gate driver |
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TWI457896B true TWI457896B (en) | 2014-10-21 |
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Cited By (1)
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TWI569244B (en) * | 2016-02-05 | 2017-02-01 | 聯詠科技股份有限公司 | Display apparatus, gate driver and operation method thereof |
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TW200502891A (en) * | 2003-07-09 | 2005-01-16 | Samsung Electronics Co Ltd | Shift register, scan driving circuit and display apparatus having the same |
US20060082391A1 (en) * | 2004-10-15 | 2006-04-20 | David Hsu | Set-reset (S-R) latch based deglitch circuit |
US7557643B2 (en) * | 2007-01-08 | 2009-07-07 | Sandisk Corporation | De-glitch circuit |
TW201110551A (en) * | 2009-06-01 | 2011-03-16 | Sharp Kk | Level shifter circuit, scanning line driving device and display apparatus |
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TW200502891A (en) * | 2003-07-09 | 2005-01-16 | Samsung Electronics Co Ltd | Shift register, scan driving circuit and display apparatus having the same |
US20060082391A1 (en) * | 2004-10-15 | 2006-04-20 | David Hsu | Set-reset (S-R) latch based deglitch circuit |
US7557643B2 (en) * | 2007-01-08 | 2009-07-07 | Sandisk Corporation | De-glitch circuit |
TW201110551A (en) * | 2009-06-01 | 2011-03-16 | Sharp Kk | Level shifter circuit, scanning line driving device and display apparatus |
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Publication number | Priority date | Publication date | Assignee | Title |
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TWI569244B (en) * | 2016-02-05 | 2017-02-01 | 聯詠科技股份有限公司 | Display apparatus, gate driver and operation method thereof |
US9847053B2 (en) | 2016-02-05 | 2017-12-19 | Novatek Microelectronics Corp. | Display apparatus, gate driver and operation method thereof |
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