TWI456633B - 含有釕電極之半導體元件及製造此元件之方法 - Google Patents

含有釕電極之半導體元件及製造此元件之方法 Download PDF

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TWI456633B
TWI456633B TW096135896A TW96135896A TWI456633B TW I456633 B TWI456633 B TW I456633B TW 096135896 A TW096135896 A TW 096135896A TW 96135896 A TW96135896 A TW 96135896A TW I456633 B TWI456633 B TW I456633B
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layer
forming
contact hole
diffusion barrier
plug
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TW200845152A (en
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Jin-Hyock Kim
Jae-Sung Roh
Seung-Jin Yeom
Kee-Jeung Lee
Han-Sang Song
Deok-Sin Kil
Young-Dae Kim
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Hynix Semiconductor Inc
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    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
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    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/32115—Planarisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/65—Electrodes comprising a noble metal or a noble metal oxide, e.g. platinum (Pt), ruthenium (Ru), ruthenium dioxide (RuO2), iridium (Ir), iridium dioxide (IrO2)
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
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    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76865—Selective removal of parts of the layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/7687—Thin films associated with contacts of capacitors

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Claims (42)

  1. 一種半導體元件，包含：半導體基板；在該半導體基板上之絕緣圖案，及在該絕緣圖案上之蝕刻停止層，該絕緣圖案與該蝕刻停止層界定曝露半導體基板之接觸孔；第一栓，填充該接觸孔之下部；擴散障壁層，於該第一栓上方以及該接觸孔之殘留部之底部中與側壁上形成；第二栓，於該擴散障壁層上形成並填充該接觸孔；及儲存節點，耦接至並形成於該第二栓上，其中該絕緣圖案包含：第一絕緣層，具有填充有該第一栓之第一子接觸孔；及第二絕緣層，具有第二子接觸孔，其中該擴散障壁層與該第二栓係形成於該第二子接觸孔中，其中該第二子接觸孔係形成於該第二絕緣層與該蝕刻停止層中。
  2. 如申請專利範圍第1項之半導體元件，其中該第二子接觸孔具有比該第一子接觸孔之曝露表面區域大的曝露表面區域。
  3. 如申請專利範圍第1項之半導體元件，其中該第一栓包含多晶矽層，該擴散障壁層包含氮化鈦層，及該第二栓包含釕層。
  4. 如申請專利範圍第1項之半導體元件，其中該第一栓包 含多晶矽層，該擴散障壁層包含氮化鈦層，及該第二栓包含藉由執行物理氣相沈積法而形成的釕層。
  5. 如申請專利範圍第1項之半導體元件，其中該儲存節點包含釕層或氧化釕層。
  6. 如申請專利範圍第1項之半導體元件，其中該蝕刻停止層包含氮化物系層。
  7. 如申請專利範圍第1項之半導體元件，其中更包含於該第一栓與該擴散障壁層之間形成的歐姆接觸層。
  8. 如申請專利範圍第7項之半導體元件，其中該歐姆接觸層包含矽化鈦層。
  9. 如申請專利範圍第4項之半導體元件，其中該物理氣相沈積法係在不使用氧氣體下執行。
  10. 一種製造半導體元件之方法，包含：提供一半導體基板；於該半導體基板上形成絕緣結構，該絕緣結構包含接觸孔；於該接觸孔之一部分中形成第一栓；於該接觸孔之殘留部分之底部中與側壁上形成擴散障壁層；在不使用氧氣體下於該擴散障壁層上形成第二栓並填充該接觸孔；及於該第二栓上方形成儲存節點。
  11. 如申請專利範圍第10項之方法，其中形成該絕緣結構包含：於該半導體基板上形成第一絕緣層，以提供該接觸孔 之一部分；及於該第一絕緣層上形成第二絕緣層及於該第二絕緣層上形成蝕刻停止層，以提供該接觸孔之殘留部分。
  12. 如申請專利範圍第11項之方法，其中該蝕刻停止層包含氮化物系層，且該第一與該第二絕緣層包含氧化物系層。
  13. 如申請專利範圍第10項之方法，其中該接觸孔之殘留部分具有比填充有該第一栓之接觸孔部分的曝露表面區域大的曝露表面區域。
  14. 如申請專利範圍第10項之方法，其中形成該擴散障壁層包含：於該絕緣結構上以及在該接觸孔之殘留部分的底部與側壁中形成導電層，用以作為該擴散障壁層；及藉由執行化學機械研磨製程平坦化該導電層，以曝露該絕緣結構之表面。
  15. 如申請專利範圍第10項之方法，其中形成擴散障壁層包含：於該絕緣結構上以及在該接觸孔之殘留部分的底部與側壁中形成導電層，用以作為該擴散障壁層；及執行回蝕刻製程使得部分該導電層殘留在該接觸孔之殘留部分的底部與側壁中。
  16. 如申請專利範圍第14項之方法，其中使用化學氣相沈積法或連續流動沈積法形成該導電層，以具有範圍從約50Å到約300Å的厚度。
  17. 如申請專利範圍第15項之方法，其中使用化學氣相沈 積法或連續流動沈積法形成該導電層，以具有範圍從約50Å到約300Å的厚度。
  18. 如申請專利範圍第14項之方法，其中該擴散障壁層包含氮化鈦層。
  19. 如申請專利範圍第15項之方法，其中該擴散障壁層包含氮化鈦層。
  20. 如申請專利範圍第10項之方法，其中形成該第二栓包含：於該絕緣結構與該擴散障壁層上形成導電層；及藉由執行化學機械研磨製程來平坦化該導電層，以曝露該絕緣結構之表面。
  21. 如申請專利範圍第10項之方法，其中形成該第二栓包含：於該絕緣結構與該擴散障壁層上形成導電層；及於該導電層上執行回蝕刻製程，以曝露該絕緣結構之表面。
  22. 如申請專利範圍第20項之方法，其中使用物理氣相沈積法形成該導電層。
  23. 如申請專利範圍第21項之方法，其中使用物理氣相沈積法形成該導電層。
  24. 如申請專利範圍第20項之方法，其中該第二栓包含釕層。
  25. 如申請專利範圍第21項之方法，其中該第二栓包含釕層。
  26. 如申請專利範圍第10項之方法，其中該第一栓包含多晶矽層，該擴散障壁層包含氮化鈦層，及該第二栓包含 釕層。
  27. 如申請專利範圍第26項之方法，其中更包含在該第一栓與該擴散障壁層間形成歐姆接觸層。
  28. 如申請專利範圍第27項之方法，其中該歐姆接觸層包含矽化鈦層。
  29. 如申請專利範圍第10項之方法，其中該儲存節點包含釕層或氧化釕層。
  30. 一種製造半導體元件之方法，包含：提供一半導體基板；於該半導體基板上形成絕緣結構，該絕緣結構包含接觸孔；於該接觸孔之一部分中形成第一栓；於該絕緣結構上形成蝕刻停止層；於該接觸孔之殘留部分之底部中與側壁上形成擴散障壁層；於該擴散障壁層上形成第二栓，並填充該接觸孔；及於該第二栓上方形成儲存節點，其中形成該絕緣結構包含：於該半導體基板上形成第一絕緣層，以提供該接觸孔之一部分；及於該第一絕緣層上形成第二絕緣層及於該第二絕緣層上形成該蝕刻停止層，以提供該接觸孔之殘留部分。
  31. 如申請專利範圍第30項之方法，其中該蝕刻停止層包含氮化物系層，且該第一與該第二絕緣層包含氧化物系層。
  32. 如申請專利範圍第30項之方法，其中該接觸孔之殘留 部分具有比填充有該第一栓之接觸孔部分的曝露表面區域大的曝露表面區域。
  33. 如申請專利範圍第30項之方法，其中形成該擴散障壁層包含：於該絕緣結構上以及在該接觸孔之殘留部分的底部與側壁中形成導電層，用以作為該擴散障壁層；及藉由執行化學機械研磨製程平坦化該導電層，以曝露該絕緣結構之表面。
  34. 如申請專利範圍第30項之方法，其中形成擴散障壁層包含：於該絕緣結構上以及在該接觸孔之殘留部分的底部與側壁中形成導電層，用以作為該擴散障壁層；及執行回蝕刻製程使得部分該導電層殘留在該接觸孔之殘留部分的底部與側壁中。
  35. 如申請專利範圍第33項之方法，其中該擴散障壁層包含氮化鈦層。
  36. 如申請專利範圍第30項之方法，其中形成該第二栓包含：於該絕緣結構與該擴散障壁層上形成導電層；及於該導電層上執行回蝕刻製程，以曝露該絕緣結構之表面。
  37. 如申請專利範圍第36項之方法，其中在不使用氧氣體下使用物理氣相沈積法形成該導電層。
  38. 如申請專利範圍第36項之方法，其中該第二栓包含釕層。
  39. 如申請專利範圍第30項之方法，其中該第一栓包含多 晶矽層，該擴散障壁層包含氮化鈦層，及該第二栓包含釕層。
  40. 如申請專利範圍第30項之方法，其中更包含在該第一栓與該擴散障壁層間形成歐姆接觸層。
  41. 如申請專利範圍第40項之方法，其中該歐姆接觸層包含矽化鈦層。
  42. 如申請專利範圍第30項之方法，其中該儲存節點包含釕層或氧化釕層。
TW096135896A 2007-05-04 2007-09-27 含有釕電極之半導體元件及製造此元件之方法 TWI456633B (zh)

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CN101299421A (zh) 2008-11-05
US7781336B2 (en) 2010-08-24
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CN101299421B (zh) 2011-04-06

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