TWI456577B - 反及閘快閃記憶體啓動裝置及使用方法 - Google Patents

反及閘快閃記憶體啓動裝置及使用方法 Download PDF

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Publication number
TWI456577B
TWI456577B TW099126604A TW99126604A TWI456577B TW I456577 B TWI456577 B TW I456577B TW 099126604 A TW099126604 A TW 099126604A TW 99126604 A TW99126604 A TW 99126604A TW I456577 B TWI456577 B TW I456577B
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TW
Taiwan
Prior art keywords
gate
flash memory
terminal
counting
electrically connected
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TW099126604A
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English (en)
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TW201207860A (en
Inventor
Kuo Shu Hung
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Hon Hai Prec Ind Co Ltd
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Priority to TW099126604A priority Critical patent/TWI456577B/zh
Priority to US12/947,726 priority patent/US8370565B2/en
Publication of TW201207860A publication Critical patent/TW201207860A/zh
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Publication of TWI456577B publication Critical patent/TWI456577B/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/24—Resetting means
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/4401—Bootstrapping
    • G06F9/4403—Processor initialisation

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Security & Cryptography (AREA)
  • Read Only Memory (AREA)

Claims (6)

  1. 一種反及閘快閃記憶體啟動裝置，其包括一中央處理器及與該中央處理器電性連接的一反及閘快閃記憶體和一同步動態隨機記憶體，其改良在於：所述反及閘快閃記憶體預存儲一段用於啟動系統的引導載入程式，所述反及閘快閃記憶體啟動裝置還包括一脈衝計數單元，所述脈衝計數單元與中央處理器電性連接，所述脈衝計數單元包括一計數器、一及閘、一第一反閘及一第二反閘，所述及閘包括三輸入端，所述計數器包括計數端子0-7，其中計數端子0和計數端子1電性連接於及閘的二輸入端，計數端子2藉由第一反閘電性連接於及閘的另一輸入端，計數端子3與第二反閘電性連接，計數端子5與反及閘快閃記憶體電性連接，所述脈衝計數單元藉由產生脈衝訊號初始化該反及閘快閃記憶體，以使該反及閘快閃記憶體使能，所述中央處理器藉由該反及閘快閃記憶體讀取所述引導載入程式並將該引導載入程式轉移到同步動態隨機記憶體繼而啟動系統。
  2. 如申請專利範圍第1項所述之反及閘快閃記憶體啟動裝置，其中所述反及閘快閃記憶體包括一讀使能引腳及一檢測引腳，當檢測引腳由高電平轉為低電平再轉為高電平時，該中央處理器控制讀使能引腳讀取所述引導載入程式。
  3. 如申請專利範圍第1項所述之反及閘快閃記憶體啟動裝置，其中所述反及閘快閃記憶體包括一命令鎖存訊號引腳，所述及閘的輸出端與命令鎖存訊號引腳電性連接。
  4. 如申請專利範圍第1項所述之反及閘快閃記憶體啟動裝置，其中所述反及閘快閃記憶體包括一位址鎖存訊號引腳、一晶片使能引腳及一資料輸入 輸出引腳，所述計數端子2與位址鎖存訊號引腳電性連接，所述計數端子3藉由第二反閘與晶片使能引腳電性連接，所述計數端子5與資料輸入輸出引腳電性連接。
  5. 如申請專利範圍第1項所述之反及閘快閃記憶體啟動裝置，其中所述計數器還包括一中斷端子及一保護端子，所述中斷端子與保護端子同時電性連接於計數端子4，當該計數端子4置位1時，該計數器停止計數，該保護端子置為高阻。
  6. 如申請專利範圍第1項所述之反及閘快閃記憶體啟動裝置，其中所述反及閘快閃記憶體包括一寫使能引腳，所述脈衝計數單元包括一計數器及一延時器，所述計數器包括一時鐘端子，所述時鐘端子接收中央處理器的時種訊號，該時鐘端子藉由延時器與寫使能引腳電性連接。
TW099126604A 2010-08-10 2010-08-10 反及閘快閃記憶體啓動裝置及使用方法 TWI456577B (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
TW099126604A TWI456577B (zh) 2010-08-10 2010-08-10 反及閘快閃記憶體啓動裝置及使用方法
US12/947,726 US8370565B2 (en) 2010-08-10 2010-11-16 Boot system

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Application Number Priority Date Filing Date Title
TW099126604A TWI456577B (zh) 2010-08-10 2010-08-10 反及閘快閃記憶體啓動裝置及使用方法

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TW201207860A TW201207860A (en) 2012-02-16
TWI456577B true TWI456577B (zh) 2014-10-11

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Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102237675B (zh) * 2010-04-26 2014-07-23 鸿富锦精密工业（深圳）有限公司 电子装置
TWI537826B (zh) * 2011-05-05 2016-06-11 聯詠科技股份有限公司 主晶片開機方法
US9933980B2 (en) 2014-02-24 2018-04-03 Toshiba Memory Corporation NAND raid controller for connection between an SSD controller and multiple non-volatile storage units
CN103995754A (zh) * 2014-04-23 2014-08-20 汉柏科技有限公司 一种控制power-pc中cpu启动切换的***及方法

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Publication number Priority date Publication date Assignee Title
US20050283598A1 (en) * 2004-06-22 2005-12-22 International Business Machines Corporation Method and system for loading processor boot code from serial flash memory
US20070174602A1 (en) * 2006-01-23 2007-07-26 Rom-Shen Kao Method of system booting with a direct memory access in a new memory architecture
US20070239977A1 (en) * 2006-04-10 2007-10-11 Stephen Wu Direct boot arrangement using a NAND flash memory
US20080294838A1 (en) * 2007-05-25 2008-11-27 Agere Systems Inc. Universal boot loader using programmable on-chip non-volatile memory
US20090100307A1 (en) * 2004-08-30 2009-04-16 Silicon Storage Technology, Inc. Systems and methods for providing nonvolatile memory management in wireless phones
US20090113558A1 (en) * 2007-10-26 2009-04-30 Qualcomm Incorporated Progressive boot for a wireless device
TW200941491A (en) * 2008-03-25 2009-10-01 Genesys Logic Inc Storage device supporting boot code execution

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8443183B2 (en) * 2009-09-02 2013-05-14 Spashtop Inc. Pre-boot loader for reducing system boot time

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050283598A1 (en) * 2004-06-22 2005-12-22 International Business Machines Corporation Method and system for loading processor boot code from serial flash memory
US20090100307A1 (en) * 2004-08-30 2009-04-16 Silicon Storage Technology, Inc. Systems and methods for providing nonvolatile memory management in wireless phones
US20070174602A1 (en) * 2006-01-23 2007-07-26 Rom-Shen Kao Method of system booting with a direct memory access in a new memory architecture
US20070239977A1 (en) * 2006-04-10 2007-10-11 Stephen Wu Direct boot arrangement using a NAND flash memory
US20080294838A1 (en) * 2007-05-25 2008-11-27 Agere Systems Inc. Universal boot loader using programmable on-chip non-volatile memory
US20090113558A1 (en) * 2007-10-26 2009-04-30 Qualcomm Incorporated Progressive boot for a wireless device
TW200941491A (en) * 2008-03-25 2009-10-01 Genesys Logic Inc Storage device supporting boot code execution

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US20120042117A1 (en) 2012-02-16
US8370565B2 (en) 2013-02-05
TW201207860A (en) 2012-02-16

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