TWI453838B - 具有散熱器之無引線封裝 - Google Patents

具有散熱器之無引線封裝 Download PDF

Info

Publication number
TWI453838B
TWI453838B TW096106717A TW96106717A TWI453838B TW I453838 B TWI453838 B TW I453838B TW 096106717 A TW096106717 A TW 096106717A TW 96106717 A TW96106717 A TW 96106717A TW I453838 B TWI453838 B TW I453838B
Authority
TW
Taiwan
Prior art keywords
heat sink
integrated circuit
leads
circuit device
die contact
Prior art date
Application number
TW096106717A
Other languages
English (en)
Other versions
TW200741920A (en
Inventor
Mary Jean Bajacan Ramos
Antonio Romarico Santos San
Anang Subagio
Original Assignee
Unisem M Berhad
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Unisem M Berhad filed Critical Unisem M Berhad
Publication of TW200741920A publication Critical patent/TW200741920A/zh
Application granted granted Critical
Publication of TWI453838B publication Critical patent/TWI453838B/zh

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/34Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/42Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
    • H01L23/433Auxiliary members in containers characterised by their shape, e.g. pistons
    • H01L23/4334Auxiliary members in encapsulations
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561Batch processing
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568Temporary substrate used as encapsulation process aid
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49541Geometry of the lead-frame
    • H01L23/49548Cross section geometry
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49575Assemblies of semiconductor devices on lead frames
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/33Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/34Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L24/36Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L24/37Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/34Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L24/39Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L24/40Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/84Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93Batch processes
    • H01L24/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0555Shape
    • H01L2224/05552Shape in top view
    • H01L2224/05553Shape in top view being rectangular
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16245Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/291Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/29144Gold [Au] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/325Material
    • H01L2224/32505Material outside the bonding interface, e.g. in the bulk of the layer connector
    • H01L2224/32506Material outside the bonding interface, e.g. in the bulk of the layer connector comprising an eutectic alloy
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/36Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L2224/37Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
    • H01L2224/37001Core members of the connector
    • H01L2224/3701Shape
    • H01L2224/37011Shape comprising apertures or cavities
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/36Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L2224/37Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
    • H01L2224/37001Core members of the connector
    • H01L2224/37099Material
    • H01L2224/371Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/36Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L2224/37Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
    • H01L2224/37001Core members of the connector
    • H01L2224/37099Material
    • H01L2224/371Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/37117Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/37124Aluminium [Al] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/36Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L2224/37Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
    • H01L2224/37001Core members of the connector
    • H01L2224/37099Material
    • H01L2224/371Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/37138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/37147Copper [Cu] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/36Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L2224/37Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
    • H01L2224/3754Coating
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/401Disposition
    • H01L2224/40151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/40221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/40245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/4501Shape
    • H01L2224/45012Cross-sectional shape
    • H01L2224/45014Ribbon connectors, e.g. rectangular cross-section
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4912Layout
    • H01L2224/49171Fan-out arrangements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73221Strap and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/84Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
    • H01L2224/848Bonding techniques
    • H01L2224/8485Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92Specific sequence of method steps
    • H01L2224/922Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222Sequential connecting processes
    • H01L2224/92242Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93Batch processes
    • H01L2224/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01013Aluminum [Al]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01029Copper [Cu]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01033Arsenic [As]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01047Silver [Ag]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01079Gold [Au]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01082Lead [Pb]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/0132Binary Alloys
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/0132Binary Alloys
    • H01L2924/01322Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/014Solder alloys
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161Cap
    • H01L2924/1615Shape
    • H01L2924/16152Cap comprising a cavity for hosting the device, e.g. U-shaped cap
    • H01L2924/16153Cap enclosing a plurality of side-by-side cavities [e.g. E-shaped cap]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • H01L2924/183Connection portion, e.g. seal
    • H01L2924/18301Connection portion, e.g. seal being an anchoring portion, i.e. mechanical interlocking between the encapsulation resin and another package part
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/301Electrical effects
    • H01L2924/3025Electromagnetic shielding

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Description

具有散熱器之無引線封裝
本發明係關於囊封一或多個半導器裝置之封裝,更特定言之,係關於一種具有優越熱效能之無引線封裝的組裝方法。
於具有引線架之半導體封裝中,電信號係藉由一導電的引線架在至少一半導體裝置(晶粒)與外部電路(例如,印刷電路板)之間傳送。該引線架包括複數個引線,每一個引線具有一內部引線端及一對立的外部引線端。內部引線端與晶粒上的輸入/輸出(I/O)觸點電互連,而外部引線端係作為外部端子,供封裝主體與外部電路互連。當外部引線端係端接在封裝主體表面時,該封裝即一般所習知的「無引線」封裝。若外部引線伸出至封裝主體周邊之外,則稱該封裝為「有引線」封裝。一般熟知的無引線封裝範例包括:四方扁平無引線(QFN)封裝,其具有四組環繞一方形封裝主體底部四周配置的引線;以及雙扁平無引線(DFN)封裝,其具有二組沿著封裝主體底部兩對立側配置的引線。晶粒與內部引線端之間的互連一般是採取線接合、捲帶式自動接合(TAB)或覆晶接合等方式。在採用線接合或TAB接合的情況中,內部引線端係端接在離晶粒一段距離之處,且利用小直徑的焊線或導電膠帶電互連到晶粒之一電作用面上的I/O觸點。晶粒可由一周圍被引線圍繞的晶粒觸點支撐。在覆晶接合的情況中,引線架的內部引線端從晶粒下面伸出,且晶粒翻轉使晶粒電作用面上的I/O觸點以直接電接觸的方式(例如焊料接合處)與內部引線端接觸。
美國專利申請案第10/563,712號(PCT國際申請案號為WO 2005/017968 A2,公開日期2005年2月24日)中更完整地揭示了一種代表性的QFN封裝及其製造方法。
無引線半導體封裝設計人員持續追求的目標是更良好的熱管理。亦即,移除電作用之半導體晶粒的熱量的能力。就熱管理與成本而言,QFN是最佳的引線架類型的封裝之一,但隨著積體電路裝置變得更為複雜,有必要改善熱其效能與電效能。業界的方法中,有些是使用粗焊線與金屬線帶來把積體電路晶粒的熱量傳導掉。
Mahulikar等人在美國專利第5,608,267號中揭示了一種在有引線的封裝中使用一散熱器的方法。Wang等人在美國專利第5,977,626號中以及Libres在美國專利第6,432,749號中揭示了在基板類型的封裝中使用散熱器的方法。
沒有任何先前技術的設計提出具有散熱器之無外引線的引線架類型的封裝。與QFN及目前已知之其他無引線類型的封裝比較,這種封裝將具有更強的熱效能。
本發明之一方面提供一種製造一無引線電子封裝的方法。該方法包括步驟:提供一具有所要特徵之引線架,該等特徵包括複數個端接於一中心孔周圍的引線;放置一積體電路裝置於在該中心孔內,並將該積體電路裝置電互連至該等引線;放置一散熱器於該積體電路裝置附近不與之接觸的位置,使該積體電路裝置位在該等引線與該散熱器之間;以及,將該半導體裝置及該散熱器之至少一部分與該等引線囊封於一模塑樹脂中。
本發明之另一方面提供一種半導體封裝,其包含:具有內部引線端及外部引線端之複數個引線,該等引線係圍繞一位於中心的晶粒觸點予以配置,該晶粒觸點具有從其向外延伸的複數個晶粒觸點繫條;一積體電路裝置,其具有一接合至該晶粒觸點之電無作用面及利用線接合或TAB接合電互連至該等內部引線端之電作用面;一散熱器,其位在該電作用面附近不與之接觸的位置,使該積體電路裝置位在該晶粒觸點與該散熱器之間;以及一模塑樹脂,其囊封該積體電路裝置、該散熱器之至少一部分以及該晶粒觸點與該等外部引線端除了一平面以外之全部的部分。
本發明另一方面提供一半導體封裝,其包含:具有內部引線端及外部引線端之複數個引線,該等引線係圍繞一位在中心的孔予以配置;一積體電路裝置,其跨過該孔且具有一藉由一焊料直接與該複數個引線之內部引線端接合的電作用面;一散熱器,其位在輔助積體電路裝置之一電無作用面附近不與之接觸的位置,使該積體電路裝置位在該複數個引線與該散熱器之間;以及一模塑樹脂,其囊封該積體電路裝置、該散熱器之至少一部分以及該晶粒觸點與該等外部引線端除了一平面以外之全部的部分。
圖1顯示先前技術中習知之一引線架矩陣10的俯視平面圖。一般而言,引線架係以經得起在控制下實施之化學蝕刻的導電材料做成。適合的材料包括銅與銅合金、鐵鎳合金以及鋁與鋁合金。蝕刻所形成的封裝特徵包括晶粒觸點14、引線16與晶粒繫條18。值得注意的是,針對每一種型式的封裝,並非全部的特徵都是必要的。例如,在一覆晶封裝中,晶粒觸點14是選擇性的。矩陣構成一重複的封裝特徵陣列,使得在組裝程序完成時,該陣列可被分割成(singulated)複數個個別的封裝。
圖2顯示一能夠改善QFN封裝之熱效能的散熱器的俯視平面圖,圖3為其剖面示意圖。以化學蝕刻或機械衝切的方式將一金屬板做成由散熱器34構成的矩陣32,各散熱器34之間以散熱器繫條36彼此互連。散熱器34與散熱器繫條36的厚度一般是在0.1公釐(mm)到1.0公釐(mm)的範圍。散熱器34係以具有延展性的高熱傳導金屬(例如銅、鋁及其合金)做成。可將散熱器塗布以賦予色彩來增強封裝標記的對比或提升其對環境腐蝕的耐受性。例如,當散熱器是以銅或銅質合金製造成時,可以利用電解液或無電鍍製程把它鍍鎳。當以鋁或鋁合金製造時,可以對它進行陽極處理,例如黑色陽極處理。蝕刻或衝切之後,對繫條36實施機械成型而形成部分38,使散熱器34提升到比繫條36高的位置,如圖3所示。此一上移把散熱器34提高到足夠的高度,以提供與線接合封裝之焊線隔開的間隙,且必要時使頂面40在封裝模塑之後能夠暴露出來。典型的上移量u為0.25 mm到0.7 mm。
可在蝕刻時使散熱器繫條36形成一厚度較薄的部分60,如圖2的局部放大圖所示,以促進分割。此種部分蝕刻亦可應用於在引線繫條上於分割期間要被切斷(cut)的部分。
然後如圖4所示,把散熱器34構成的陣列32附接在一特徵(例如引線16或繫條)上位於晶粒附近不與之接觸的位置。陣列32可以使用例如環氧膠或導電膠帶的黏著劑42附接。亦可不使用黏著劑42,而只把陣列32放到定位,以模塑樹脂穩固支撐。
圖5顯示以模塑樹脂46將一封裝囊封之後,封裝陣列44的剖面示意圖。被囊封的組件與特徵包括該晶粒、該散熱器之至少一部分以及除了一外部引線端47以外之全部引線端。模塑樹脂一般是使用介電聚合物。將圖4所示的組裝件放進一適當的模具中,注入高溫模塑樹脂至該模具中,成型後得到如圖5所示的封裝陣列44。囊封程序之後,以例如鋸開或衝切的方式分割該封裝陣列,得到如圖6所示的個別封裝48。
晶粒28位在兩塊金屬板、晶粒觸點14與散熱器34之間。如此提供對電敏感的裝置免於受電場及磁場影響的屏蔽。
圖7顯示一依據本發明之製造一線接合封裝70的製造程序。蝕刻一引線架72(其可為一引線架矩陣之一構件或一單一的引線架)使其具有需要的特徵(例如引線74及晶粒觸點76)。貼上背條78(例如膠帶),用以在蝕刻之後支撐該等特徵。
使用黏晶劑84把積體電路裝置80接合至晶粒觸點76之一內表面82。一般常用的黏晶劑材料包括金/錫共晶合金、金/銀共晶合金、各種銀質合金與含金屬填料的聚合物。然後以焊線86或TAB捲帶把引線74電互連至積體電路裝置80之一電作用面上的I/O觸點。該積體電路裝置80之電作用面包含電路與I/O觸點,其反面的電無作用面不具有這些特徵。
接下來把散熱器88放到引線74上面。可選擇性地使用例如環氧膠或導電膠帶等之黏著劑90把散熱器88貼附到引線74或引線架繫條上。然後以模塑樹脂91囊封積體電路裝置80、散熱器88之至少一部分及該等引線74之一部分。露出至少一外部引線表面92、92',且其與模塑樹脂之側壁94、94'一起構成一平面。散熱器88之一最外表面96亦可露出,且其與模塑樹脂之側壁94"一起構成一平面。
若該引線架及散熱器係做成一矩陣之構件,則最後一個步驟是分割。若該引線架及散熱器係做成單一的單元,則不需要分割。
圖8示意性放大顯示封裝70的剖面。該封裝包括散熱器繫條的一變薄部分60,以利用鋸開或衝切的方式促進分割。一第二變薄部分96將散熱器88機械式地固定在模塑樹脂91中。
圖9顯示一第一替代性封裝100。此封裝中,散熱器102包含複數個孔104,使得模塑樹脂91伸入這些孔中而將散熱器機械式地固定在模塑樹脂中。該複數個孔104可用來與在此所述之任何封裝組態結合。
圖10顯示一第二替代性封裝110。此封裝中,散熱器112具有一凹下的中央部分114。一散熱膏或例如環氧膠116之黏著劑或導電膠帶提供良好的熱傳導性。該散熱膏或環氧膠可為一介電質或導電材料,視應用而定。當其係用來代替焊線時,必須選擇導電材料。若只作為散熱用途且不打算電互連到I/O觸點,則應選擇介電質以防止短路。散熱器的周圍部分118與封裝110的側壁94"一起構成一平面,以促進以強制氣流、熱流體或與一外部散熱片接觸等方式把熱量移除掉。
圖11顯示一第三替代性封裝120,其與圖10之封裝類似,不同之處是,其散熱器112的周圍部分118並不形成封裝側壁94"的一部分。
圖12顯示一第四替代性封裝130。封裝130具有晶粒觸點132,其具有一凹下的中央部分134。一導電且導熱的黏著劑(例如散熱膏136、環氧膠或導電膠帶)提供積體電路裝置80之一電作用面與散熱器138之間良好的電與熱的連接性。一導電且導熱的散熱膏之示範例為把陶瓷或以例如銀、銅及/或鋁等為主的金屬顆粒混入一有機物或聚矽氧流體中所形成的乳狀物。或者,可使用導電且導熱的環氧膠(例如環氧銀膠(silver-filled epoxy))或可配給式(dispensable)焊錫膏來取代散熱膏136。
圖13顯示依據本發明另一具體實施例之一覆晶封裝150的組裝方法。封裝150之大部分組裝步驟與先前所述步驟相似。然而,積體電路裝置80之電作用面係以焊料凸塊152直接接合至引線74,且選擇性地接合至一中心晶粒觸點182(圖18)。請再參考圖13,焊料凸塊152一般具有0.07mm的高度,而且是以合適的焊料做成,例如以鉛質共晶合金、高鉛含量材料及支柱凸塊。突出部154、154'伸入到模塑樹脂91中,把引線74及散熱器88機械式地固定在適當位置。
圖14到17顯示本發明封裝之替代性覆晶封裝150、160、170、180的具體實施例。大部分特徵在先前已經說明。就覆晶而言,散熱膏136係導電且導熱,並且使散熱器102、112與積體電路裝置80的電無作用面電與熱互連。如前述,可以使用導熱環氧膠、焊錫膏與導電膠帶來代替散熱膏。一種適合的導熱環氧膠填充有超過60重量百分比的銀粉。
不論是使覆晶接合或是線接合/TAB接合的封裝,任何散熱器88之一散熱器表面158皆可暴露於環境中與模塑樹脂91之一側壁94"一起形成一平面。表面158除了可提供作為一標記面以外,亦可暴露於強制氣流、傳熱流體或一散熱片中,以改善熱管理。該暴露面的形狀可為正方形、矩形、圓形或其他任何形狀。
現在請參考圖19,散熱器繫條190可具有凸塊192,用以增加與線接合所使用焊線之間的凸出物間隙。凸塊192亦可用來對準散熱器以及把它固定到引線194上的適當位置。可在引線194中形成一孔196,進一步幫助對準及固定。
或者,如圖20所示,凸塊192可形成於封裝引線194或引線架繫條中。孔196可形成於散熱器繫條190中。同前,凸塊192提供對準(alignment)及固定(locking)的功能。凸塊一般是在化學蝕刻製程中形成,或在端壓(upset)程序中以鑄造/衝切的方式形成。
現在請參考圖21,在另一具體實施例中,封裝引線194可包括一凸塊192,且散熱器繫條190可包括一孔196。孔196與凸塊192係配置以提供對準與固定功能。
雖然在前述製程中係先將引線陣列與散熱器陣列模塑在一起後再加以分割,但在以模塑樹脂囊封以及將個別引線架組裝件與個別散熱器放進個別模穴中以便進行囊封的取置程序(pick and place)之前採取先分割的方式,並不超出本發明之範疇。
已說明本發明之一或多個具體實施例。但是,應瞭解,只要不背離本發明的精神與範疇,可進行各種修改。例如,可用此製程製造一DFN封裝,或例如在一混合式封裝的情況中,囊封一或多個半導體裝置或被動電子裝置。據此,其他具體實施例都屬於下列申請專利範圍的範疇內。
10...引線架矩陣
14...晶粒觸點
16...引線
18...晶粒繫條
28...晶粒
32...散熱器矩陣
34...散熱器
36...散熱器繫條
38...繫條部分
40...頂面
42...黏著劑
44...封裝陣列
46...模塑樹脂
47...外部引線端
48...個別封裝
60...變薄部分
70...線接合封裝
72...引線架
74...引線
76...晶粒觸點
78...背條
80...積體電路裝置
82...內表面
84...黏晶劑
86...焊線
88...散熱器
90...黏著劑
91...模塑樹脂
92、92'...外部引線表面
94、94'、94"...模塑樹脂側壁
96...散熱器最外表面/第二變薄部分
100...封裝
102...散熱器
104...孔
110...封裝
112...散熱器
114...中央部分
116...黏著劑
118...散熱器的周圍部分
120...封裝
130...封裝
132...晶粒觸點
134...中央部分
136...黏著劑
138...散熱器
150...覆晶封裝
152...焊料凸塊
154、154'...突出部
158...散熱器表面
160...覆晶封裝
170...覆晶封裝
180...覆晶封裝
182...晶粒觸點
190...散熱器繫條
192...凸塊
194...引線
196...孔
為了說明本發明之目的,各圖式顯示本發明目前之一較佳形式。不過應瞭解,本發明並不限於附圖中所示之特定配置及手段,其中:圖1為應用於本發明之習知先前技術之一引線架矩陣的俯視平面圖;圖2為用於引線架陣列及半導體晶粒組裝件之一散熱器矩陣的俯視平面圖;圖3為圖2所示散熱器陣列的剖視圖;圖4為接合至引線架陣列與半導體晶粒組裝件之散熱器陣列的剖面示意圖;圖5為以本發明製程所成型之一模塑封裝陣列的剖面示意圖;圖6為以本發明製程所成型之已分割線接合封裝的剖面示意圖;圖7為一依據本發明之線接合封裝的製造程序的剖面示意圖;圖8為依據本發明之方法所成型之一封裝的剖面示意圖;圖9為依據本發明之方法所成型之一封裝的剖面示意圖;圖10為依據本發明之方法所成型之一封裝的剖面示意圖;圖11為依據本發明之方法所成型之一封裝的剖面示意圖;圖12為依據本發明之方法所成型之一封裝的剖面示意圖;圖13顯示一依據本發明之製程所成型之一覆晶接合封裝的組裝方法;圖14為依據本發明之製程所成型之一覆晶接合封裝的剖面示意圖;圖15為依據本發明之製程所成型之另一覆晶接合封裝的剖面示意圖;圖16為依據本發明之製程所成型之另一覆晶接合封裝的剖面示意圖;圖17為依據本發明之製程所成型之另一覆晶接合封裝的剖面示意圖;圖18為依據本發明之製程所成型之另一覆晶接合封裝的剖面示意圖;圖19為一散熱器凸緣之一對準特徵的剖面示意圖;圖20為一散熱器凸緣之一替代性對準特徵的剖面示意圖;及圖21為一引線之一對準特徵的剖面示意圖。
16...引線
32...散熱器矩陣
34...散熱器
42...黏著劑

Claims (29)

  1. 一種製造一無引線電子封裝(70)的方法,包括步驟:提供一具有所要特徵的引線架(72),該等特徵包括端接於一中心孔周圍的複數個引線(74);放置一積體電路裝置(80)於在該中心孔內,並將該積體電路(80)電互連至該等引線(74);放置一散熱器(88)於該積體電路裝置(80)附近不與之接觸的位置,使該積體電路裝置(80)位在該等引線(74)與該散熱器(88)之間,該散熱器(88)藉由複數個繫條(tie bars)形成一非平面的關係,且該複數個繫條由該等封裝特徵支撐;以及將該半導體裝置(80)及該散熱器(88)之至少一部分與引線囊封於一模塑樹脂(91)中。
  2. 如請求項1之方法,其中該散熱器(88)被完全囊封於該模塑樹脂(91)內。
  3. 如請求項1之方法,其中該散熱器(88)之一表面(92、92')暴露出來且與該模塑樹脂(91)之一表面(94、94')在同一平面上。
  4. 如請求項3之方法,其中該散熱器(88)係選自由銅、鋁、銅質合金及鋁質合金所組成的群組。
  5. 如請求項3之方法,進一步包括在以模塑樹脂(91)囊封之前先將該散熱器(88)塗布的步驟。
  6. 如請求項5之方法,其中該散熱器(88)係選擇使用一鋁質合金且該塗布步驟係黑色陽極處理。
  7. 如請求項5之方法,其中該散熱器(88)係選擇使用一銅質合金且該塗布步驟包括塗敷一鎳塗層。
  8. 如請求項1之方法,進一步包括將該等繫條接合至該等特徵的步驟。
  9. 如請求項8之方法,其中該等特徵包括一配置於該中心孔內的晶粒觸點(132)及從該晶粒觸點向外伸出的晶粒觸點繫條,其中該等散熱器繫條黏著地接合至該等引線(74)中之至少一者及該等晶粒觸點繫條。
  10. 如請求項9之方法,其中該等散熱器繫條(190)係利用一環氧膠及一導電膠帶中之至少一者黏著地接合至該等引線(74)中之至少一者及該等晶粒觸點繫條。
  11. 如請求項9之方法,進一步包括將該積體電路裝置(80)之一電無作用面接合至該晶粒觸點(132)以及利用線接合或TAB接合將該積體電路裝置(80)之一電作用面電互連至該等引線(74)的步驟。
  12. 如請求項8之方法,其中該半導體裝置(80)之該電作用面係利用覆晶接合直接接合至該等引線。
  13. 如請求項12之方法,其中一導熱聚合物與該積體電路裝置(80)之該電無作用面接觸且與該散熱器(88)接觸。
  14. 如請求項8之方法,其中該等散熱器繫條(190)與其鄰近的散熱器繫條互連而形成一散熱器陣列。
  15. 如請求項14之方法,其中以模塑樹脂(91)囊封的該步驟係在該等散熱器繫條(190)分割之後執行。
  16. 如請求項14之方法,其中以模塑樹脂(91)囊封的該步驟 係在該等散熱器繫條(190)分割之前執行。
  17. 如請求項14之方法,其中該等散熱器繫條(190)具有一減小厚度的部分以促進分割。
  18. 一種半導體封裝,其包含:具有內部引線端及外部引線端之複數個引線(16),該等引線係圍繞一位於中心的晶粒觸點(14)予以配置,該晶粒觸點(14)具有從其向外延伸的複數個晶粒觸點繫條(18);一積體電路裝置,其具有一接合至該晶粒觸點(14)之電無作用面及一利用線接合或TAB接合電互連至該等內部引線端之電作用面;一散熱器(34),其位在該電作用面附近不與之接觸的位置,使該積體電路裝置位在該晶粒觸點(14)與該散熱器(34)之間,該散熱器(34)具有:一具有相對且實質上平行於該電作用面之一平面第一表面之中心部分,及一外部部分,該外部部分接觸下列至少一者:在該晶粒觸點之相對側上之該等引線之該等外部引線端,及在該晶粒觸點相對端上之該等晶粒觸點繫條之外部繫條端,其中該外部部分包括在接觸該等外部引線端或該等外部繫條端之一端點處之一第一薄部分,及該中心部分包括具有相對於該第一表面之一平面表面之一全厚部分,以及一第二薄部分,其與該晶粒觸點間隔開,且該第二薄部分具有一與該第一表面整合之較低 表面及平行於該第一表面之一上表面;及一模塑樹脂(46),其囊封該積體電路裝置、該散熱器(34)之至少一部分以及該晶粒觸點(14)與該等外部引線端除了一平面以外之全部的部分。
  19. 如請求項18之半導體封裝,其中該散熱器(34)係一塗布有鎳的銅質合金。
  20. 如請求項18之半導體封裝,其中該散熱器(88)為一塗布有黑色陽極處理的鋁質合金,且該散熱器(88)之一表面暴露出來而與該模塑樹脂(91)成為共平面的關係。
  21. 如請求項18之半導體封裝,其中該散熱器(88)係選自由銅、鋁、銅質合金及鋁質合金所組成的群組。
  22. 一種半導體封裝,其包含:具有內部引線端及外部引線端之複數個引線(16),該等引線係圍繞一位在中的孔予以配置;一積體電路裝置(80),其跨過該孔,且具有一藉由一焊料直接與該複數個引線(74)之該等內部引線端接合之電作用面;一散熱器(88),其位在輔助積體電路裝置(80)之一電無作用面附近不與之接觸的位置,使該積體電路裝置(80)位在該複數個引線(74)與該散熱器(88)之間,該散熱器(34)具有:一具有相對且實質上平行於該電作用面之一平面第一表面(96)之中心部分,及一外部部分,該外部部分接觸在該積體電路裝置(80)之相對側上之該等引線(74)之該 等外部引線端,及其中該外部部分包括在接觸該等外部引線端之一端點處之一第一薄部分(60),及該中心部分包括具有相對於該第一表面之一平面表面之一全厚部分,以及一第二薄部分(96),其與該積體電路裝置(80)間隔開,且該第二薄部分具有一與該第一表面整合之較低表面及平行於該第一表面之一上表面;及一模塑樹脂(91),其囊封該積體電路裝置(80)、該散熱器(88)之至少一部分以及該晶粒觸點(132)與該等外部引線端除了一平面以外之全部的部分。
  23. 如請求項22之半導體封裝,其中該散熱器(88)係選自由銅、鋁、銅質合金及鋁質合金所組成的群組。
  24. 如請求項22之半導體封裝,其中該散熱器(88)進一步包括一塗層,其係在以該模塑樹脂(91)囊封之前加至該散熱器(88)。
  25. 如請求項22之半導體封裝,其中該散熱器(88)為一塗布有黑色陽極處理的鋁質合金,且該散熱器(88)之一表面暴露出來而與該模塑樹脂(91)成為共平面的關係。
  26. 如請求項22之半導體封裝,其中有一導熱聚合物配置於該電無作用面與該散熱器(88)之間。
  27. 如請求項22之半導體封裝,其中有一晶粒觸點(132)配置於該中心孔內,且該積體電路裝置(80)直接接合至該晶粒觸點(132)。
  28. 如請求項22之半導體封裝,其進一步包括一黏著劑,用 於使該散熱器(88)接合於該複數個引線(74)之至少一部分。
  29. 如請求項28之半導體封裝,其中該黏著劑係一環氧膠及一導電膠帶中之一者。
TW096106717A 2006-02-28 2007-02-27 具有散熱器之無引線封裝 TWI453838B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US77731606P 2006-02-28 2006-02-28
US11/670,650 US8022512B2 (en) 2006-02-28 2007-02-02 No lead package with heat spreader

Publications (2)

Publication Number Publication Date
TW200741920A TW200741920A (en) 2007-11-01
TWI453838B true TWI453838B (zh) 2014-09-21

Family

ID=38443175

Family Applications (1)

Application Number Title Priority Date Filing Date
TW096106717A TWI453838B (zh) 2006-02-28 2007-02-27 具有散熱器之無引線封裝

Country Status (5)

Country Link
US (2) US8022512B2 (zh)
EP (1) EP1989735A2 (zh)
JP (1) JP2009528699A (zh)
TW (1) TWI453838B (zh)
WO (1) WO2007100642A2 (zh)

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI374525B (en) * 2004-05-11 2012-10-11 Taiwan Semiconductor Mfg Cut-out heat slug for integrated circuit device packaging
US8564124B2 (en) * 2006-03-07 2013-10-22 International Rectifier Corporation Semiconductor package
US7531383B2 (en) * 2006-10-31 2009-05-12 Freescale Semiconductor, Inc. Array quad flat no-lead package and method of forming same
US8018050B2 (en) * 2007-11-01 2011-09-13 National Semiconductor Corporation Integrated circuit package with integrated heat sink
US7923846B2 (en) 2007-11-16 2011-04-12 Stats Chippac Ltd. Integrated circuit package-in-package system with wire-in-film encapsulant
KR101463075B1 (ko) * 2008-02-04 2014-11-20 페어차일드코리아반도체 주식회사 히트 싱크 패키지
KR20100010747A (ko) * 2008-07-23 2010-02-02 삼성전자주식회사 반도체 소자 패키지
US20100103622A1 (en) * 2008-10-24 2010-04-29 Keihin Corporation Electronic control device
US8097489B2 (en) * 2009-03-23 2012-01-17 Stats Chippac, Ltd. Semiconductor device and method of mounting pre-fabricated shielding frame over semiconductor die
US8334584B2 (en) * 2009-09-18 2012-12-18 Stats Chippac Ltd. Integrated circuit packaging system with quad flat no-lead package and method of manufacture thereof
US8637981B2 (en) 2011-03-30 2014-01-28 International Rectifier Corporation Dual compartment semiconductor package with temperature sensor
WO2012137333A1 (ja) * 2011-04-07 2012-10-11 三菱電機株式会社 モールドモジュール、及び電動パワーステアリング装置
EP2608258A1 (en) * 2011-12-20 2013-06-26 STMicroelectronics (Grenoble 2) SAS A package
US9824958B2 (en) * 2013-03-05 2017-11-21 Infineon Technologies Austria Ag Chip carrier structure, chip package and method of manufacturing the same
US11291146B2 (en) 2014-03-07 2022-03-29 Bridge Semiconductor Corp. Leadframe substrate having modulator and crack inhibiting structure and flip chip assembly using the same
US9184120B1 (en) * 2014-08-07 2015-11-10 Texas Instruments Incorporated Nonleaded package and leadframe strip and method
DE102015120396A1 (de) 2015-11-25 2017-06-01 Infineon Technologies Austria Ag Halbleiterchip-Package umfassend Seitenwandkennzeichnung
WO2019059904A1 (en) * 2017-09-20 2019-03-28 Intel Corporation CONNECTION GRID OF INTEGRATED CIRCUIT BOXES
JP2022133486A (ja) * 2019-07-30 2022-09-14 株式会社デンソー 半導体パッケージおよび半導体装置

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6177718B1 (en) * 1998-04-28 2001-01-23 Kabushiki Kaisha Toshiba Resin-sealed semiconductor device
US6432749B1 (en) * 1999-08-24 2002-08-13 Texas Instruments Incorporated Method of fabricating flip chip IC packages with heat spreaders in strip format
WO2004032186A2 (en) * 2002-09-30 2004-04-15 Advanced Interconnect Technologies Limited Thermal enhanced package for block mold assembly

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5608267A (en) 1992-09-17 1997-03-04 Olin Corporation Molded plastic semiconductor package including heat spreader
US5650663A (en) 1995-07-03 1997-07-22 Olin Corporation Electronic package with improved thermal properties
US5977626A (en) 1998-08-12 1999-11-02 Industrial Technology Research Institute Thermally and electrically enhanced PBGA package
US6650663B1 (en) * 2000-05-19 2003-11-18 Ceramoptec Industries, Inc. Power-scaling of erbium 3/μ m-laser
US6432742B1 (en) 2000-08-17 2002-08-13 St Assembly Test Services Pte Ltd. Methods of forming drop-in heat spreader plastic ball grid array (PBGA) packages
US6482680B1 (en) 2001-07-20 2002-11-19 Carsem Semiconductor Sdn, Bhd. Flip-chip on lead frame
US6661087B2 (en) 2001-10-09 2003-12-09 Siliconware Precision Industries Co., Ltd. Lead frame and flip chip semiconductor package with the same
TW517365B (en) 2001-11-29 2003-01-11 Orient Semiconductor Elect Ltd Heat dissipation plate and its bonding process with substrate
US6979594B1 (en) 2002-07-19 2005-12-27 Asat Ltd. Process for manufacturing ball grid array package
JP2007509485A (ja) 2003-08-14 2007-04-12 アドバンスド インターコネクト テクノロジーズ リミテッド 半導体デバイス・パッケージおよびその製造方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6177718B1 (en) * 1998-04-28 2001-01-23 Kabushiki Kaisha Toshiba Resin-sealed semiconductor device
US6432749B1 (en) * 1999-08-24 2002-08-13 Texas Instruments Incorporated Method of fabricating flip chip IC packages with heat spreaders in strip format
WO2004032186A2 (en) * 2002-09-30 2004-04-15 Advanced Interconnect Technologies Limited Thermal enhanced package for block mold assembly

Also Published As

Publication number Publication date
JP2009528699A (ja) 2009-08-06
EP1989735A2 (en) 2008-11-12
US8022512B2 (en) 2011-09-20
US20070200207A1 (en) 2007-08-30
WO2007100642A2 (en) 2007-09-07
TW200741920A (en) 2007-11-01
WO2007100642A3 (en) 2008-05-22
US20110304032A1 (en) 2011-12-15

Similar Documents

Publication Publication Date Title
TWI453838B (zh) 具有散熱器之無引線封裝
US7741158B2 (en) Method of making thermally enhanced substrate-base package
US6790710B2 (en) Method of manufacturing an integrated circuit package
JP3170182B2 (ja) 樹脂封止型半導体装置及びその製造方法
US6294830B1 (en) Microelectronic assembly with conductive terminals having an exposed surface through a dielectric layer
US7439613B2 (en) Substrate based unmolded package
US6049125A (en) Semiconductor package with heat sink and method of fabrication
US7879653B2 (en) Leadless semiconductor package with electroplated layer embedded in encapsulant and the method for manufacturing the same
US7808084B1 (en) Semiconductor package with half-etched locking features
TWI419291B (zh) 引線框架結構、使用引線框架結構之進階四方扁平無引線封裝結構,以及其製造方法
JP2006501677A (ja) ブロック成形集成体用の耐熱強化パッケージ
US7847392B1 (en) Semiconductor device including leadframe with increased I/O
US7488623B2 (en) Integrated circuit chip packaging assembly
US20100193922A1 (en) Semiconductor chip package
US8089145B1 (en) Semiconductor device including increased capacity leadframe
KR101440933B1 (ko) 범프 기술을 이용하는 ic 패키지 시스템
US20020113325A1 (en) Semiconductor package and mounting structure on substrate thereof and stack structure thereof
KR20050109502A (ko) 내장형 수동 소자를 갖는 리드 프레임
CN213601865U (zh) 半导体封装件
US20090261461A1 (en) Semiconductor package with lead intrusions
US7102208B1 (en) Leadframe and semiconductor package with improved solder joint strength
JP3502377B2 (ja) リードフレーム、樹脂封止型半導体装置及びその製造方法
CN112216658A (zh) 具有适应各种管芯尺寸的引线框架的半导体器件
KR100370480B1 (ko) 반도체 패키지용 리드 프레임
WO2003017328A2 (en) Encapsulated integrated circuit package and method of manufacturing an integrated circuit package

Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees