TWI450260B - Power device of a thin film transistor liquid crystal display - Google Patents

Power device of a thin film transistor liquid crystal display Download PDF

Info

Publication number
TWI450260B
TWI450260B TW100131070A TW100131070A TWI450260B TW I450260 B TWI450260 B TW I450260B TW 100131070 A TW100131070 A TW 100131070A TW 100131070 A TW100131070 A TW 100131070A TW I450260 B TWI450260 B TW I450260B
Authority
TW
Taiwan
Prior art keywords
voltage
coupled
thin film
film transistor
pulse width
Prior art date
Application number
TW100131070A
Other languages
Chinese (zh)
Other versions
TW201310432A (en
Inventor
Chun Han Liu
Mei Chi Fu
Chien Wen Chen
Original Assignee
Chunghwa Picture Tubes Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Chunghwa Picture Tubes Ltd filed Critical Chunghwa Picture Tubes Ltd
Priority to TW100131070A priority Critical patent/TWI450260B/en
Publication of TW201310432A publication Critical patent/TW201310432A/en
Application granted granted Critical
Publication of TWI450260B publication Critical patent/TWI450260B/en

Links

Landscapes

  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Liquid Crystal Display Device Control (AREA)
  • Dc-Dc Converters (AREA)

Description

薄膜液晶顯示器的電源裝置Thin film liquid crystal display power supply unit

本發明係有關於一種電源裝置，尤指一種整合正電荷幫浦及負電荷幫浦至玻璃面板的薄膜液晶顯示器的電源裝置。The invention relates to a power supply device, in particular to a power supply device for a thin film liquid crystal display integrating a positive charge pump and a negative charge pump to a glass panel.

當操作薄膜液晶顯示器時，薄膜液晶顯示器的電源裝置需提供不同電壓給薄膜液晶顯示器。因此，電源裝置必須利用電源驅動單元，產生脈衝寬度調變控制訊號。然後，第一電壓產生電路根據輸入電壓和脈衝寬度調變控制訊號，產生第一電壓(VDDA)。When operating a thin film liquid crystal display, the power supply device of the thin film liquid crystal display needs to supply different voltages to the thin film liquid crystal display. Therefore, the power supply unit must use the power supply driving unit to generate a pulse width modulation control signal. Then, the first voltage generating circuit modulates the control signal according to the input voltage and the pulse width to generate a first voltage (VDDA).

第一電壓(VDDA)產生之後，電源裝置再利用正電荷幫浦與負電荷幫浦，產生並輸出第一電壓的倍壓(VDDG)及負電壓(VEEG)，以控制薄膜電晶體開關的開啟與關閉。然而，在先前技術中，電源裝置係由許多外部元件所組成，且電源裝置係形成於印刷電路板上。因此，電源裝置的成本高且需要較大面積的印刷電路板。After the first voltage (VDDA) is generated, the power supply device uses the positive charge pump and the negative charge pump to generate and output a voltage double voltage (VDDG) and a negative voltage (VEEG) of the first voltage to control the opening of the thin film transistor switch. With off. However, in the prior art, the power supply device is composed of a plurality of external components, and the power supply device is formed on the printed circuit board. Therefore, the power supply device is costly and requires a large area of printed circuit board.

本發明係有關於一種薄膜液晶顯示器的電源裝置。該電源裝置包含一印刷電路板、一第一電壓產生電路、一玻璃面板、一正電荷幫浦及一負電荷幫浦。該第一電壓產生電路，形成於該印刷電路板上，用以產生一第一電壓及一脈衝寬度調變訊號；該正電荷幫浦，形成於該玻璃面板上，用以接收該第一電壓及該脈衝寬度調變訊號，並據以輸出至少一該第一電壓的倍壓；該負電荷幫浦，形成於該玻璃面板上，用以接收該脈衝寬度調變訊號，並據以輸出一負電壓。The present invention relates to a power supply device for a thin film liquid crystal display. The power supply device comprises a printed circuit board, a first voltage generating circuit, a glass panel, a positive charge pump and a negative charge pump. The first voltage generating circuit is formed on the printed circuit board for generating a first voltage and a pulse width modulation signal; the positive charge pump is formed on the glass panel for receiving the first voltage And the pulse width modulation signal, and according to the output of at least one voltage of the first voltage; the negative charge pump is formed on the glass panel for receiving the pulse width modulation signal, and outputting a signal Negative voltage.

本發明提供一種薄膜液晶顯示器的電源裝置。該電源裝置係利用一第一電壓產生電路，產生一第一電壓及一脈衝寬度調變訊號。然後，一正電荷幫浦可根據該第一電壓及該脈衝寬度調變訊號，產生至少一該第一電壓的倍壓，以及一負電荷幫浦可根據該脈衝寬度調變訊號，產生一負電壓。另外，該正電荷幫浦和該負電荷幫浦係整合於一玻璃面板上。如此，本發明不僅可減少該電源裝置的外部元件數量，且因為該正電荷幫浦和該負電荷幫浦係整合於該玻璃面板上，所以該電源裝置的成本較低以及需要一較小面積的印刷電路板。The invention provides a power supply device for a thin film liquid crystal display. The power supply device generates a first voltage and a pulse width modulation signal by using a first voltage generating circuit. Then, a positive charge pump can generate at least one voltage double of the first voltage according to the first voltage and the pulse width modulation signal, and a negative charge pump can modulate the signal according to the pulse width to generate a negative Voltage. In addition, the positive charge pump and the negative charge pump are integrated on a glass panel. Thus, the present invention not only reduces the number of external components of the power supply device, but also because the positive charge pump and the negative charge pump are integrated on the glass panel, the power supply device is low in cost and requires a small area. A printed circuit board.

請參照第1圖，第1圖係為本發明的一實施例說明一種薄膜液晶顯示器的電源裝置100的示意圖。電源裝置100包含一印刷電路板102、一第一電壓產生電路104、一玻璃面板106、一正電荷幫浦108及一負電荷幫浦110。第一電壓產生電路104係形成於印刷電路板102上，用以產生一第一電壓VDDA及一脈衝寬度調變訊號PWM；正電荷幫浦108係形成於玻璃面板106上，用以接收第一電壓VDDA及脈衝寬度調變訊號PWM，並根據第一電壓VDDA及脈衝寬度調變訊號PWM，輸出二倍壓VDDG2X與三倍壓VDDG3X。正電荷幫浦108包含二倍壓電路1082與三倍壓電路1084，其中二倍壓電路1082係用以輸出二倍壓VDDG2X以及三倍壓電路1084係用以輸出三倍壓VDDG3X。但本發明並不受限於正電荷幫浦108僅輸出二倍壓VDDG2X與三倍壓VDDG3X。亦即正電荷幫浦108係用以輸出至少一第一電壓VDDA的倍壓。負電荷幫浦110係形成於玻璃面板106上，用以接收脈衝寬度調變訊號PWM，並根據脈衝寬度調變訊號PWM，輸出一負電壓VEEG。Please refer to FIG. 1. FIG. 1 is a schematic view showing a power supply device 100 of a thin film liquid crystal display according to an embodiment of the present invention. The power supply device 100 includes a printed circuit board 102, a first voltage generating circuit 104, a glass panel 106, a positive charge pump 108, and a negative charge pump 110. The first voltage generating circuit 104 is formed on the printed circuit board 102 for generating a first voltage VDDA and a pulse width modulation signal PWM. The positive charge pump 108 is formed on the glass panel 106 for receiving the first The voltage VDDA and the pulse width modulation signal PWM output a double voltage VDDG2X and a triple voltage VDDG3X according to the first voltage VDDA and the pulse width modulation signal PWM. The positive charge pump 108 includes a double voltage circuit 1082 and a triple voltage circuit 1084, wherein the double voltage circuit 1082 is used to output a double voltage VDDG2X and the triple voltage circuit 1084 is used to output a triple voltage VDDG3X. . However, the present invention is not limited to the positive charge pump 108 outputting only the double voltage VDDG2X and the triple voltage VDDG3X. That is, the positive charge pump 108 is used to output a voltage double of at least one first voltage VDDA. The negative charge pump 110 is formed on the glass panel 106 for receiving the pulse width modulation signal PWM, and outputs a negative voltage VEEG according to the pulse width modulation signal PWM.

如第1圖所示，第一電壓產生電路104包含一電源驅動單元1042、一電晶體1044、一電感1046、二極體1048、一電容1050及一負載1052。電源驅動單元1042係用以提供一脈衝寬度調變控制訊號PS；電晶體1044具有一第一端，一第二端，用以接收脈衝寬度調變控制訊號PS，及一第三端，耦接於一地端GND；電感1046具有一第一端，用以接收一輸入電壓VIN，及一第二端，耦接於電晶體1044的第一端，用以輸出脈衝寬度調變訊號PWM；二極體1048具有一第一端，耦接於電晶體1044的第一端，及一第二端，用以輸出輸入電壓VIN；電容1050具有一第一端，耦接於二極體1048的第二端，及一第二端，耦接於地端GND；負載1052具有一第一端，耦接於二極體1048的第二端，及一第二端，耦接於地端GND。如第1圖所示，第一電壓VDDA係為根據脈衝寬度調變訊號PWM與輸入電壓VIN，透過電感1046儲能與二極體1048箝位下，所得到的穩態直流電壓。另外，脈衝寬度調變訊號PWM的工作週期是由脈衝寬度調變控制訊號PS所控制。As shown in FIG. 1 , the first voltage generating circuit 104 includes a power driving unit 1042 , a transistor 1044 , an inductor 1046 , a diode 1048 , a capacitor 1050 , and a load 1052 . The power driving unit 1042 is configured to provide a pulse width modulation control signal PS. The transistor 1044 has a first end, a second end for receiving the pulse width modulation control signal PS, and a third end coupled. The inductor 1046 has a first end for receiving an input voltage VIN, and a second end coupled to the first end of the transistor 1044 for outputting a pulse width modulation signal PWM; The pole body 1048 has a first end coupled to the first end of the transistor 1044 and a second end for outputting an input voltage VIN. The capacitor 1050 has a first end coupled to the second body of the diode 1048. The second end and the second end are coupled to the ground GND. The load 1052 has a first end coupled to the second end of the diode 1048 and a second end coupled to the ground GND. As shown in FIG. 1, the first voltage VDDA is a steady-state DC voltage obtained by the energy storage of the inductor 1046 and the clamping of the diode 1048 according to the pulse width modulation signal PWM and the input voltage VIN. In addition, the duty cycle of the pulse width modulation signal PWM is controlled by the pulse width modulation control signal PS.

請參照第2圖和第3圖，第2圖係為說明二倍壓電路1082的示意圖，和第3圖係為說明產生二倍壓VDDG2X的時序的示意圖。如第2圖所示，二倍壓電路1082係用以接收第一電壓VDDA及脈衝寬度調變訊號PWM，並據以輸出二倍壓VDDG2X。二倍壓電路1082包含一第一充電電容10822、一第一薄膜電晶體10824、一第二薄膜電晶體10826及一第一穩壓電容10828，其中第一充電電容10822與第一穩壓電容10828係為玻璃面板106的耦合電容。第一充電電容10822具有一第一端，用以接收脈衝寬度調變訊號PWM，及一第二端；第一薄膜電晶體10824具有一第一端，用以接收第一電壓VDDA，一第二端，耦接於第一薄膜電晶體10824的第一端，及一第三端，耦接於第一充電電容10822的第二端；第二薄膜電晶體10826具有一第一端，耦接於第一充電電容10822的第二端，一第二端，耦接於第二薄膜電晶體10826的第一端，及一第三端，用以輸出二倍壓VDDG2X；第一穩壓電容10828具有一第一端，耦接於第二薄膜電晶體10826的第三端，及一第二端，耦接於地端GND。Please refer to FIG. 2 and FIG. 3, FIG. 2 is a schematic diagram illustrating the double voltage circuit 1082, and FIG. 3 is a schematic diagram illustrating the timing of generating the double voltage VDDG2X. As shown in FIG. 2, the double voltage circuit 1082 is configured to receive the first voltage VDDA and the pulse width modulation signal PWM, and output a double voltage VDDG2X accordingly. The double voltage circuit 1082 includes a first charging capacitor 10822, a first thin film transistor 10824, a second thin film transistor 10826 and a first stabilizing capacitor 10828, wherein the first charging capacitor 10822 and the first stabilizing capacitor 10828 is the coupling capacitance of the glass panel 106. The first charging capacitor 10822 has a first end for receiving the pulse width modulation signal PWM and a second end. The first thin film transistor 10824 has a first end for receiving the first voltage VDDA, and a second The first end of the first thin film transistor 10824 is coupled to the first end of the first thin film transistor 10824, and the third end is coupled to the second end of the first charging capacitor 10822. The second thin film transistor 10826 has a first end coupled to the first end. a second end of the first charging capacitor 10822, a second end coupled to the first end of the second thin film transistor 10826, and a third end for outputting a double voltage VDDG2X; the first stabilizing capacitor 10828 has The first end is coupled to the third end of the second thin film transistor 10826, and the second end is coupled to the ground end GND.

如第2圖和第3圖所示，當脈衝寬度調變訊號PWM係為一低電位(0V)時，第一薄膜電晶體10824開啟以及第二薄膜電晶體10826關閉。此時，第一電壓VDDA對第一充電電容10822充電，因此節點A(第一充電電容10822的第二端)的電位被提升至第一電壓VDDA。當脈衝寬度調變訊號PWM係為一高電位(VDDA)時，第一薄膜電晶體10824關閉以及第二薄膜電晶體10826開啟。此時，脈衝寬度調變訊號PWM對第一充電電容10822充電，因此節點A的電位由第一電壓VDDA再被提升至二倍壓VDDG2X，並持續維持在二倍壓VDDG2X。因為第二薄膜電晶體10826開啟，所以第二薄膜電晶體10826的第三端便可輸出二倍壓VDDG2X。另外，第一穩壓電容10828係用以穩定節點A的電位。As shown in FIGS. 2 and 3, when the pulse width modulation signal PWM is at a low potential (0 V), the first thin film transistor 10824 is turned on and the second thin film transistor 10826 is turned off. At this time, the first voltage VDDA charges the first charging capacitor 10822, and thus the potential of the node A (the second end of the first charging capacitor 10822) is boosted to the first voltage VDDA. When the pulse width modulation signal PWM is at a high potential (VDDA), the first thin film transistor 10824 is turned off and the second thin film transistor 10826 is turned on. At this time, the pulse width modulation signal PWM charges the first charging capacitor 10822, so the potential of the node A is further raised to the double voltage VDDG2X by the first voltage VDDA, and is continuously maintained at the double voltage VDDG2X. Because the second thin film transistor 10826 is turned on, the third end of the second thin film transistor 10826 can output a double voltage VDDG2X. In addition, the first voltage stabilizing capacitor 10828 is used to stabilize the potential of the node A.

請參照第4圖和第5圖，第4圖係為說明三倍壓電路1084的示意圖，和第5圖係為說明產生三倍壓VDDG3X的時序的示意圖。如第2圖所示，三倍壓電路1084係用以接收第一電壓VDDA及脈衝寬度調變訊號PWM，並據以輸出三倍壓VDDG3X。三倍壓電路1084包含一第二充電電容10842、一第三薄膜電晶體10844、一第四薄膜電晶體10846、一第二穩壓電容10848、一第三充電電容10850、一第五薄膜電晶體10852、一第六薄膜電晶體10854及一第三穩壓電容10856，其中第二充電電容10842、第二穩壓電容10848、第三充電電容10850及第三穩壓電容10856係為玻璃面板106的耦合電容。第二充電電容10842具有一第一端，用以接收脈衝寬度調變訊號PWM，及一第二端；第三薄膜電晶體10844具有一第一端，用以接收第一電壓VDDA，一第二端，耦接於第三薄膜電晶體10844的第一端，及一第三端，耦接於第二充電電容10842的第二端；第四薄膜電晶體10846具有一第一端，耦接於第二充電電容10842的第二端，一第二端，耦接於第四薄膜電晶體10846的第一端，及一第三端，用以輸出二倍壓VDDG2X；第二穩壓電容10848具有一第一端，耦接於第四薄膜電晶體10846的第三端，及一第二端，耦接於地端GND；第三充電電容10850具有一第一端，用以接收脈衝寬度調變訊號PWM，及一第二端；第五薄膜電晶體10852具有一第一端，用以接收二倍壓VDDG2X，一第二端，耦接於第五薄膜電晶體10852的第一端，及一第三端，耦接於第三充電電容10850的第二端；第六薄膜電晶體10854具有一第一端，耦接於第三充電電容10850的第二端，一第二端，耦接於第六薄膜電晶體10854的第一端，及一第三端，用以輸出三倍壓VDDG3X；第三穩壓電容10856具有一第一端，耦接於第六薄膜電晶體10854的第三端，及一第二端，耦接於地端GND。4 and 5, FIG. 4 is a schematic diagram illustrating the triple voltage circuit 1084, and FIG. 5 is a schematic diagram illustrating the timing of generating the triple voltage VDDG3X. As shown in FIG. 2, the triple voltage circuit 1084 is configured to receive the first voltage VDDA and the pulse width modulation signal PWM, and thereby output a triple voltage VDDG3X. The triple voltage circuit 1084 includes a second charging capacitor 10842, a third thin film transistor 10844, a fourth thin film transistor 10846, a second voltage stabilizing capacitor 10848, a third charging capacitor 10850, and a fifth thin film battery. The crystal 10852, the sixth thin film transistor 10854 and a third voltage stabilizing capacitor 10856, wherein the second charging capacitor 10842, the second stabilizing capacitor 10848, the third charging capacitor 10850 and the third stabilizing capacitor 10856 are glass panels 106 Coupling capacitor. The second charging capacitor 10842 has a first end for receiving the pulse width modulation signal PWM and a second end. The third thin film transistor 10844 has a first end for receiving the first voltage VDDA, and a second The first end of the third thin film transistor 10844 is coupled to the second end of the second charging capacitor 10842. The fourth thin film transistor 10846 has a first end coupled to the first end. a second end of the second charging capacitor 10842, a second end coupled to the first end of the fourth thin film transistor 10846, and a third end for outputting a double voltage VDDG2X; the second stabilizing capacitor 10848 has a first end is coupled to the third end of the fourth thin film transistor 10846, and a second end is coupled to the ground end GND; the third charging capacitor 10850 has a first end for receiving pulse width modulation The signal transistor PWM has a second end; the fifth thin film transistor 10852 has a first end for receiving a double voltage VDDG2X, a second end coupled to the first end of the fifth thin film transistor 10852, and a first end The third end is coupled to the second end of the third charging capacitor 10850; the sixth thin film transistor 10854 has a The first end is coupled to the second end of the third charging capacitor 10850, the second end is coupled to the first end of the sixth thin film transistor 10854, and the third end is configured to output a triple voltage VDDG3X; The voltage stabilizing capacitor 10856 has a first end coupled to the third end of the sixth thin film transistor 10854, and a second end coupled to the ground GND.

如第4圖和第5圖所示，當脈衝寬度調變訊號PWM係為低電位(0V)時，第三薄膜電晶體10844和第五薄膜電晶體10852開啟，以及第四薄膜電晶體10846和第六薄膜電晶體10854關閉。此時，第一電壓VDDA對第二充電電容10842充電，因此節點B(第二充電電容10842的第二端)的電位被提升至第一電壓VDDA。另外，因為第四薄膜電晶體10846關閉，所以第四薄膜電晶體10846的第三端的電位尚未被提升。因此，雖然第五薄膜電晶體10852開啟，但因為第四薄膜電晶體10846的第三端的電位尚未被提升，所以節點C(第三充電電容10850的第二端)的電位亦未被提升。當脈衝寬度調變訊號PWM係為高電位(VDDA)時，第四薄膜電晶體10846和第六薄膜電晶體10854開啟，以及第三薄膜電晶體10844和第五薄膜電晶體10852關閉。此時，脈衝寬度調變訊號PWM對第二充電電容10842充電，所以節點B的電位由第一電壓VDDA再被提升至二倍壓VDDG2X。因為第四薄膜電晶體10846開啟，所以第四薄膜電晶體10846的第三端的電位可被提升至二倍壓VDDG2X。另外，因為第二穩壓電容10848係用以穩定第四薄膜電晶體10846的第三端的電位，所以第四薄膜電晶體10846的第三端的電位可持續維持在二倍壓VDDG2X。As shown in FIGS. 4 and 5, when the pulse width modulation signal PWM is at a low potential (0 V), the third thin film transistor 10844 and the fifth thin film transistor 10852 are turned on, and the fourth thin film transistor 10846 and The sixth thin film transistor 10854 is turned off. At this time, the first voltage VDDA charges the second charging capacitor 10842, and thus the potential of the node B (the second end of the second charging capacitor 10842) is boosted to the first voltage VDDA. In addition, since the fourth thin film transistor 10846 is turned off, the potential of the third end of the fourth thin film transistor 10846 has not been elevated. Therefore, although the fifth thin film transistor 10852 is turned on, since the potential of the third end of the fourth thin film transistor 10846 has not been boosted, the potential of the node C (the second end of the third charging capacitor 10850) is also not boosted. When the pulse width modulation signal PWM is at a high potential (VDDA), the fourth thin film transistor 10846 and the sixth thin film transistor 10854 are turned on, and the third thin film transistor 10844 and the fifth thin film transistor 10852 are turned off. At this time, the pulse width modulation signal PWM charges the second charging capacitor 10842, so the potential of the node B is further boosted by the first voltage VDDA to the double voltage VDDG2X. Since the fourth thin film transistor 10846 is turned on, the potential of the third end of the fourth thin film transistor 10846 can be raised to the double voltage VDDG2X. In addition, since the second stabilizing capacitor 10848 is used to stabilize the potential of the third end of the fourth thin film transistor 10846, the potential of the third end of the fourth thin film transistor 10846 can be maintained at the double voltage VDDG2X.

如第4圖和第5圖所示，當脈衝寬度調變訊號PWM再次為低電位(0V)時，第三薄膜電晶體10844和第五薄膜電晶體10852開啟，以及第四薄膜電晶體10846和第六薄膜電晶體10854關閉。此時，二倍壓VDDG2X透過開啟的第五薄膜電晶體10852對第三充電電容10850充電，因此節點C的電位被提升至二倍壓VDDG2X。當脈衝寬度調變訊號PWM再次為高電位時，第四薄膜電晶體10846和第六薄膜電晶體10854開啟，以及第三薄膜電晶體10844和第五薄膜電晶體10852關閉。此時，脈衝寬度調變訊號PWM對第三充電電容10850充電，所以節點C的電位可由二倍壓VDDG2X再被提升至三倍壓VDDG3X。因為第六薄膜電晶體10854開啟，所以第六薄膜電晶體10854的第三端的電位可被提升至三倍壓VDDG3X，並輸出三倍壓VDDG3X。另外，因為第三穩壓電容10856係用以穩定第六薄膜電晶體10854的第三端的電位，所以第六薄膜電晶體10854的第三端的電位可持續維持在三倍壓VDDG3X。As shown in FIGS. 4 and 5, when the pulse width modulation signal PWM is again at a low potential (0 V), the third thin film transistor 10844 and the fifth thin film transistor 10852 are turned on, and the fourth thin film transistor 10846 and The sixth thin film transistor 10854 is turned off. At this time, the double voltage VDDG2X charges the third charging capacitor 10850 through the turned-on fifth thin film transistor 10852, so the potential of the node C is boosted to the double voltage VDDG2X. When the pulse width modulation signal PWM is again at a high potential, the fourth thin film transistor 10846 and the sixth thin film transistor 10854 are turned on, and the third thin film transistor 10844 and the fifth thin film transistor 10852 are turned off. At this time, the pulse width modulation signal PWM charges the third charging capacitor 10850, so the potential of the node C can be raised to the triple voltage VDDG3X by the double voltage VDDG2X. Since the sixth thin film transistor 10854 is turned on, the potential of the third end of the sixth thin film transistor 10854 can be raised to the triple voltage VDDG3X, and the triple voltage VDDG3X is output. In addition, since the third stabilizing capacitor 10856 is used to stabilize the potential of the third end of the sixth thin film transistor 10854, the potential of the third end of the sixth thin film transistor 10854 can be maintained at the triple voltage VDDG3X.

請參照第6圖和第7圖，第6圖係為說明負電荷幫浦110的示意圖，和第7圖係為說明產生負電壓VEEG的時序的示意圖。如第6圖所示，負電荷幫浦包含一第四充電電容1102、一第七薄膜電晶體1104、一第八薄膜電晶體1106及一第四穩壓電容1108，其中第四充電電容1102及第四穩壓電容1108係為玻璃面板106的耦合電容。第四充電電容1102具有一第一端，用以接收脈衝寬度調變訊號PWM，及一第二端；第七薄膜電晶體1104具有一第一端，耦接於第四充電電容1102的第二端，一第二端，耦接於第七薄膜電晶體1104的第一端，及一第三端，耦接於地端GND；第八薄膜電晶體1106具有一第一端，用以輸出負電壓VEEG，一第二端，耦接於第八薄膜電晶體1106的第一端，及一第三端，耦接於第四充電電容1102的第二端；第四穩壓電容1108具有一第一端，耦接於第八薄膜電晶體1106的第一端，及一第二端，耦接於地端GND。Please refer to FIG. 6 and FIG. 7. FIG. 6 is a schematic diagram illustrating the negative charge pump 110, and FIG. 7 is a schematic diagram illustrating the timing of generating a negative voltage VEEG. As shown in FIG. 6, the negative charge pump includes a fourth charging capacitor 1102, a seventh thin film transistor 1104, an eighth thin film transistor 1106, and a fourth voltage stabilizing capacitor 1108, wherein the fourth charging capacitor 1102 and The fourth voltage stabilizing capacitor 1108 is a coupling capacitor of the glass panel 106. The fourth charging capacitor 1102 has a first end for receiving the pulse width modulation signal PWM and a second end. The seventh thin film transistor 1104 has a first end coupled to the second charging capacitor 1102. The second end is coupled to the first end of the seventh thin film transistor 1104, and the third end is coupled to the ground end GND. The eighth thin film transistor 1106 has a first end for outputting a negative a voltage VEEG, a second end coupled to the first end of the eighth thin film transistor 1106, and a third end coupled to the second end of the fourth charging capacitor 1102; the fourth stabilizing capacitor 1108 has a first One end is coupled to the first end of the eighth thin film transistor 1106, and the second end is coupled to the ground end GND.

如第6圖和第7圖所示，當脈衝寬度調變訊號PWM係為低電位(0V)時，第七薄膜電晶體1104關閉和第八薄膜電晶體1106開啟。此時，第四充電電容1102的電位為0，以及節點D(第四充電電容1102的第二端)的電位亦為0。當脈衝寬度調變訊號PWM係為高電位(VDDA)時，第七薄膜電晶體1104開啟和第八薄膜電晶體1106關閉。此時，脈衝寬度調變訊號PWM對第四充電電容1102充電，因此，第四充電電容1102兩端的電壓差係為脈衝寬度調變訊號PWM的高電位(VDDA)，且節點D的電位還是為0。當脈衝寬度調變訊號PWM係為低電位(0V)時，第七薄膜電晶體1104關閉和第八薄膜電晶體1106開啟。此時，第四充電電容1102的第一端的電位係為0V，但因為要維持第四充電電容1102兩端的電壓差(VDDA)，所以節點D(第四充電電容1102的第二端)的電位會被往下箝位至負電壓VEEG。因為第八薄膜電晶體1106開啟，所以第八薄膜電晶體1106的第一端可輸出負電壓VEEG。另外，因為第四穩壓電容1108係用以穩定第八薄膜電晶體1106的第一端的電位，所以第八薄膜電晶體1106的第一端的電位可持續維持在負電壓VEEG。As shown in FIGS. 6 and 7, when the pulse width modulation signal PWM is at a low potential (0 V), the seventh thin film transistor 1104 is turned off and the eighth thin film transistor 1106 is turned on. At this time, the potential of the fourth charging capacitor 1102 is 0, and the potential of the node D (the second end of the fourth charging capacitor 1102) is also 0. When the pulse width modulation signal PWM is at a high potential (VDDA), the seventh thin film transistor 1104 is turned on and the eighth thin film transistor 1106 is turned off. At this time, the pulse width modulation signal PWM charges the fourth charging capacitor 1102. Therefore, the voltage difference between the fourth charging capacitor 1102 is the high potential (VDDA) of the pulse width modulation signal PWM, and the potential of the node D is still 0. When the pulse width modulation signal PWM is at a low potential (0 V), the seventh thin film transistor 1104 is turned off and the eighth thin film transistor 1106 is turned on. At this time, the potential of the first end of the fourth charging capacitor 1102 is 0V, but since the voltage difference (VDDA) across the fourth charging capacitor 1102 is to be maintained, the node D (the second end of the fourth charging capacitor 1102) The potential is clamped down to the negative voltage VEEG. Because the eighth thin film transistor 1106 is turned on, the first end of the eighth thin film transistor 1106 can output a negative voltage VEEG. In addition, since the fourth stabilizing capacitor 1108 is used to stabilize the potential of the first end of the eighth thin film transistor 1106, the potential of the first end of the eighth thin film transistor 1106 can be maintained at the negative voltage VEEG.

綜上所述，本發明所提供的薄膜液晶顯示器的電源裝置係利用第一電壓產生電路，產生第一電壓及脈衝寬度調變訊號。然後，正電荷幫浦可根據第一電壓及脈衝寬度調變訊號，產生至少一第一電壓的倍壓，以及負電荷幫浦可根據脈衝寬度調變訊號，產生負電壓。另外，正電荷幫浦和負電荷幫浦係整合於玻璃面板上。如此，本發明不僅可減少電源裝置的外部元件數量，且因為正電荷幫浦和負電荷幫浦係整合於玻璃面板上，所以電源裝置的成本較低以及需要較小面積的印刷電路板。In summary, the power supply device of the thin film liquid crystal display provided by the present invention generates a first voltage and a pulse width modulation signal by using a first voltage generating circuit. Then, the positive charge pump can generate a voltage multiplication of at least one first voltage according to the first voltage and the pulse width modulation signal, and the negative charge pump can generate a negative voltage according to the pulse width modulation signal. In addition, the positive charge pump and the negative charge pump are integrated on the glass panel. Thus, the present invention not only reduces the number of external components of the power supply device, but also because the positive charge pump and the negative charge pump are integrated on the glass panel, the power supply device is low in cost and requires a small area of the printed circuit board.

以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

100．．．電源裝置100. . . Power supply unit

102．．．印刷電路板102. . . A printed circuit board

104．．．第一電壓產生電路104. . . First voltage generating circuit

106．．．玻璃面板106. . . Glass panel

108．．．正電荷幫浦108. . . Positive charge pump

110．．．負電荷幫浦110. . . Negative charge pump

1082．．．二倍壓電路1082. . . Double voltage circuit

1084．．．三倍壓電路1084. . . Triple voltage circuit

1042．．．電源驅動單元1042. . . Power drive unit

1044．．．電晶體1044. . . Transistor

1046．．．電感1046. . . inductance

1048．．．二極體1048. . . Dipole

1050．．．電容1050. . . capacitance

1052．．．負載1052. . . load

1102．．．第四充電電容1102. . . Fourth charging capacitor

1104．．．第七薄膜電晶體1104. . . Seventh thin film transistor

1106‧‧‧第八薄膜電晶體1106‧‧‧ eighth film transistor

1108‧‧‧第四穩壓電容1108‧‧‧4th voltage regulator capacitor

10822‧‧‧第一充電電容10822‧‧‧First charging capacitor

10824‧‧‧第一薄膜電晶體10824‧‧‧First film transistor

10826‧‧‧第二薄膜電晶體10826‧‧‧Second thin film transistor

10828‧‧‧第一穩壓電容10828‧‧‧First Stabilized Capacitor

10842‧‧‧第二充電電容10842‧‧‧Second charging capacitor

10844‧‧‧第三薄膜電晶體10844‧‧‧ Third thin film transistor

10846‧‧‧第四薄膜電晶體10846‧‧‧fourth thin film transistor

10848‧‧‧第二穩壓電容10848‧‧‧Second voltage regulator

10850‧‧‧第三充電電容10850‧‧‧ Third charging capacitor

10852‧‧‧第五薄膜電晶體10852‧‧‧Film film transistor

10854‧‧‧第六薄膜電晶體10854‧‧‧6th film transistor

10856‧‧‧第三穩壓電容10856‧‧‧third voltage regulator

GND‧‧‧地端GND‧‧‧ ground

PS‧‧‧脈衝寬度調變控制訊號PS‧‧‧ pulse width modulation control signal

PWM‧‧‧脈衝寬度調變訊號PWM‧‧‧ pulse width modulation signal

VDDA‧‧‧第一電壓VDDA‧‧‧ first voltage

VDDG2X‧‧‧二倍壓VDDG2X‧‧‧ double pressure

VDDG3X‧‧‧三倍壓VDDG3X‧‧‧ three times pressure

VEEG‧‧‧負電壓VEEG‧‧‧negative voltage

VIN‧‧‧輸入電壓VIN‧‧‧ input voltage

第1圖係為本發明的一實施例說明一種薄膜液晶顯示器的電源裝置的示意圖。1 is a schematic view showing a power supply device of a thin film liquid crystal display according to an embodiment of the present invention.

第2圖係為說明二倍壓電路的示意圖。Figure 2 is a schematic diagram illustrating a double voltage circuit.

第3圖係為說明產生二倍壓的時序的示意圖。Figure 3 is a schematic diagram illustrating the timing of generating a double voltage.

第4圖係為說明三倍壓電路的示意圖。Figure 4 is a schematic diagram illustrating a triple voltage circuit.

第5圖係為說明產生三倍壓的時序的示意圖。Figure 5 is a schematic diagram illustrating the timing of generating triple voltage.

第6圖係為說明負電荷幫浦的示意圖。Figure 6 is a schematic diagram illustrating a negative charge pump.

第7圖係為說明產生負電壓的時序的示意圖。Figure 7 is a schematic diagram illustrating the timing of generating a negative voltage.

100．．．電源裝置100. . . Power supply unit

102．．．印刷電路板102. . . A printed circuit board

104．．．第一電壓產生電路104. . . First voltage generating circuit

106．．．玻璃面板106. . . Glass panel

108．．．正電荷幫浦108. . . Positive charge pump

110．．．負電荷幫浦110. . . Negative charge pump

1082．．．二倍壓電路1082. . . Double voltage circuit

1084．．．三倍壓電路1084. . . Triple voltage circuit

1042．．．電源驅動單元1042. . . Power drive unit

1044．．．電晶體1044. . . Transistor

1046．．．電感1046. . . inductance

1048．．．二極體1048. . . Dipole

1050．．．電容1050. . . capacitance

1052．．．負載1052. . . load

GND．．．地端GND. . . Ground end

PS．．．脈衝寬度調變控制訊號PS. . . Pulse width modulation control signal

PWM．．．脈衝寬度調變訊號PWM. . . Pulse width modulation signal

VDDA．．．第一電壓VDDA. . . First voltage

VDDG2X．．．二倍壓VDDG2X. . . Double pressure

VDDG3X．．．三倍壓VDDG3X. . . Triple pressure

VEEG．．．負電壓VEEG. . . Negative voltage

VIN．．．輸入電壓VIN. . . Input voltage

Claims (7)

一種薄膜液晶顯示器的電源裝置，包含：一印刷電路板；一第一電壓產生電路，形成於該印刷電路板上，用以產生一第一電壓及一脈衝寬度調變訊號；一玻璃面板；一正電荷幫浦，形成於該玻璃面板上，用以接收該第一電壓及該脈衝寬度調變訊號，並據以輸出至少一該第一電壓的倍壓，其中該正電荷幫浦包含：一二倍壓電路，用以接收該第一電壓及該脈衝寬度調變訊號，並據以輸出該第一電壓的一二倍壓，該二倍壓電路包含：一第一充電電容，具有一第一端，用以接收該脈衝寬度調變訊號，及一第二端；一第一薄膜電晶體，具有一第一端，用以接收該第一電壓，一第二端，耦接於該第一端，及一第三端，耦接於該第一充電電容的第二端；一第二薄膜電晶體，具有一第一端，耦接於該第一充電電容的第二端，一第二端，耦接於該第一端，及一第三端，用以輸出該二倍壓；及一第一穩壓電容，具有一第一端，耦接於該第二薄膜電晶體的第三端，及一第二端，耦接於一地端；及 一負電荷幫浦，形成於該玻璃面板上，用以接收該脈衝寬度調變訊號，並據以輸出一負電壓。 A power supply device for a thin film liquid crystal display, comprising: a printed circuit board; a first voltage generating circuit formed on the printed circuit board for generating a first voltage and a pulse width modulation signal; a glass panel; a positive charge pump formed on the glass panel for receiving the first voltage and the pulse width modulation signal, and outputting at least one voltage double of the first voltage, wherein the positive charge pump comprises: a voltage doubler circuit for receiving the first voltage and the pulse width modulation signal, and outputting a voltage double or a second of the first voltage, the voltage doubler circuit comprising: a first charging capacitor having a first end for receiving the pulse width modulation signal and a second end; a first thin film transistor having a first end for receiving the first voltage, and a second end coupled to the first end The first end and the third end are coupled to the second end of the first charging capacitor. The second thin film transistor has a first end coupled to the second end of the first charging capacitor. a second end coupled to the first end and a third end For outputting the voltage doubling; regulator and a first capacitor having a first terminal coupled to the third terminal of the second thin film transistor, and a second terminal coupled to a ground terminal; and A negative charge pump is formed on the glass panel for receiving the pulse width modulation signal and outputting a negative voltage accordingly. 如請求項1所述之電源裝置，其中該第一充電電容與該第一穩壓電容係為該玻璃面板的耦合電容。 The power supply device of claim 1, wherein the first charging capacitor and the first voltage stabilizing capacitor are coupling capacitances of the glass panel. 如請求項1所述之電源裝置，其中該正電荷幫浦另包含：一三倍壓電路，用以接收該第一電壓及該脈衝寬度調變訊號，並據以輸出該第一電壓的一三倍壓，該三倍壓電路包含：一第二充電電容，具有一第一端，用以接收該脈衝寬度調變訊號，及一第二端；一第三薄膜電晶體，具有一第一端，用以接收該第一電壓，一第二端，耦接於該第一端，及一第三端，耦接於該第二充電電容的第二端；一第四薄膜電晶體，具有一第一端，耦接於該第二充電電容的第二端，一第二端，耦接於該第一端，及一第三端，用以輸出該二倍壓；一第二穩壓電容，具有一第一端，耦接於該第四薄膜電晶體的第三端，及一第二端，耦接於該地端；一第三充電電容，具有一第一端，用以接收該脈衝寬度調變訊號，及一第二端；一第五薄膜電晶體，具有一第一端，用以接收該二倍壓，一第二端，耦接於該第一端，及一第三端，耦接於該 第三充電電容的第二端；一第六薄膜電晶體，具有一第一端，耦接於該第三充電電容的第二端，一第二端，耦接於該第一端，及一第三端，用以輸出該三倍壓；及一第三穩壓電容，具有一第一端，耦接於該第六薄膜電晶體的第三端，及一第二端，耦接於該地端。 The power supply device of claim 1, wherein the positive charge pump further comprises: a triple voltage circuit for receiving the first voltage and the pulse width modulation signal, and outputting the first voltage accordingly a triple voltage circuit, the triple voltage circuit includes: a second charging capacitor having a first end for receiving the pulse width modulation signal, and a second end; a third thin film transistor having a The first end is configured to receive the first voltage, the second end is coupled to the first end, and the third end is coupled to the second end of the second charging capacitor; a fourth thin film transistor The first end is coupled to the second end of the second charging capacitor, the second end is coupled to the first end, and the third end is configured to output the double voltage; The voltage stabilizing capacitor has a first end coupled to the third end of the fourth thin film transistor, and a second end coupled to the ground end; a third charging capacitor having a first end Receiving the pulse width modulation signal, and a second end; a fifth thin film transistor having a first end for receiving the double voltage a second end coupled to the first end and a third end coupled to the a second end of the third charging capacitor; a sixth thin film transistor having a first end coupled to the second end of the third charging capacitor, a second end coupled to the first end, and a first end The third end is configured to output the triple voltage; and a third voltage stabilizing capacitor has a first end coupled to the third end of the sixth thin film transistor, and a second end coupled to the third end Ground. 如請求項3所述之電源裝置，其中該第二充電電容、該第二穩壓電容、第三充電電容及該第三穩壓電容係為該玻璃面板的耦合電容。 The power supply device of claim 3, wherein the second charging capacitor, the second stabilizing capacitor, the third charging capacitor, and the third stabilizing capacitor are coupling capacitors of the glass panel. 如請求項1所述之電源裝置，其中該負電荷幫浦包含：一第四充電電容，具有一第一端，用以接收該脈衝寬度調變訊號，及一第二端；一第七薄膜電晶體，具有一第一端，耦接於該第四充電電容的第二端，一第二端，耦接於該第一端，及一第三端，耦接於一地端；一第八薄膜電晶體，具有一第一端，用以輸出該負電壓，一第二端，耦接於該第一端，及一第三端，耦接於該第四充電電容的第二端；及一第四穩壓電容，具有一第一端，耦接於該第八薄膜電晶體的第一端，及一第二端，耦接於該地端。 The power supply device of claim 1, wherein the negative charge pump comprises: a fourth charging capacitor having a first end for receiving the pulse width modulation signal, and a second end; a seventh film The transistor has a first end coupled to the second end of the fourth charging capacitor, a second end coupled to the first end, and a third end coupled to a ground end; The eighth film transistor has a first end for outputting the negative voltage, a second end coupled to the first end, and a third end coupled to the second end of the fourth charging capacitor; And a fourth voltage stabilizing capacitor having a first end coupled to the first end of the eighth thin film transistor and a second end coupled to the ground end. 如請求項5所述之電源裝置，其中該第四充電電容及該第四穩壓電容係為該玻璃面板的耦合電容。 The power supply device of claim 5, wherein the fourth charging capacitor and the fourth voltage stabilizing capacitor are coupling capacitors of the glass panel. 如請求項1所述之電源裝置，其中該第一電壓產生電路包含：一電源驅動單元，用以提供一脈衝寬度調變控制訊號；一電晶體，具有一第一端，一第二端，用以接收該脈衝寬度調變控制訊號，及一第三端，耦接於一地端；一電感，具有一第一端，用以接收一輸入電壓，及一第二端，耦接於該電晶體的第一端，用以輸出該脈衝寬度調變訊號；一二極體，具有一第一端，耦接於該電晶體的第一端，及一第二端，用以輸出該第一電壓；一電容，具有一第一端，耦接於該二極體的第二端，及一第二端，耦接於該地端；及一負載，具有一第一端，耦接於該二極體的第二端，及一第二端，耦接於該地端。The power supply device of claim 1, wherein the first voltage generating circuit comprises: a power driving unit for providing a pulse width modulation control signal; and a transistor having a first end and a second end. The first end of the inductor has a first end for receiving an input voltage, and a second end coupled to the ground end, and a third end coupled to the ground end; a first end of the transistor for outputting the pulse width modulation signal; a diode having a first end coupled to the first end of the transistor and a second end for outputting the first a capacitor having a first end coupled to the second end of the diode and a second end coupled to the ground; and a load having a first end coupled to the capacitor The second end of the diode and a second end are coupled to the ground end.
TW100131070A 2011-08-30 2011-08-30 Power device of a thin film transistor liquid crystal display TWI450260B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW100131070A TWI450260B (en) 2011-08-30 2011-08-30 Power device of a thin film transistor liquid crystal display

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW100131070A TWI450260B (en) 2011-08-30 2011-08-30 Power device of a thin film transistor liquid crystal display

Publications (2)

Publication Number Publication Date
TW201310432A TW201310432A (en) 2013-03-01
TWI450260B true TWI450260B (en) 2014-08-21

Family

ID=48482031

Family Applications (1)

Application Number Title Priority Date Filing Date
TW100131070A TWI450260B (en) 2011-08-30 2011-08-30 Power device of a thin film transistor liquid crystal display

Country Status (1)

Country Link
TW (1) TWI450260B (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101471601A (en) * 2007-12-24 2009-07-01 矽创电子股份有限公司 Electric charge assist pump for adding power efficiency and output voltage
US20110181346A1 (en) * 2010-01-22 2011-07-28 Himax Analogic, Inc. Charge Pump Driving Circuit and Charge Pump System
CN102158082A (en) * 2011-04-12 2011-08-17 杭州矽力杰半导体技术有限公司 Power supply management system with multipath output

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101471601A (en) * 2007-12-24 2009-07-01 矽创电子股份有限公司 Electric charge assist pump for adding power efficiency and output voltage
US20110181346A1 (en) * 2010-01-22 2011-07-28 Himax Analogic, Inc. Charge Pump Driving Circuit and Charge Pump System
TW201126883A (en) * 2010-01-22 2011-08-01 Himax Analogic Inc Charge pump driving circuit and charge pump system
CN102158082A (en) * 2011-04-12 2011-08-17 杭州矽力杰半导体技术有限公司 Power supply management system with multipath output

Also Published As

Publication number Publication date
TW201310432A (en) 2013-03-01

Similar Documents

Publication Publication Date Title
KR102222198B1 (en) DC voltage conversion circuit and DC voltage conversion method and liquid crystal display
US9552790B2 (en) Scan driving circuit for oxide semiconductor thin film transistors
US20120038610A1 (en) Gate pulse modulating circuit and method
CN103268749A (en) Phase inverter, AMOLED (Active Matrix/Organic Light Emitting Diode) compensating circuit and display panel
US8779684B2 (en) High gate voltage generator and display module including the same
CN102821511A (en) LED driver circuit
TWI508410B (en) Power management circuit
TWI514738B (en) Voltage converter
KR101262785B1 (en) Liquid crystal display and method of driving the same
WO2020124769A1 (en) Display panel driving circuit
CN104167186B (en) LED backlight and liquid crystal display for liquid crystal display
KR102229573B1 (en) DC voltage conversion circuit, DC voltage conversion method and liquid crystal display device
WO2022166467A1 (en) Gate turn-on voltage generation circuit, display panel drive apparatus and display apparatus
TWI546787B (en) Power supply module, display and related capacitance switching method
CN104518662A (en) Half-voltage ratio charge-pump circuit
TWI450260B (en) Power device of a thin film transistor liquid crystal display
WO2020140753A1 (en) Power supply circuit and display apparatus
TWI547922B (en) Power supply system and display apparatus
US20160358569A1 (en) Voltage output device, gate driving circuit and display apparatus
US20170006682A1 (en) Voltage boost driving circuit for led backlight and lcd device having same
CN103377631A (en) Liquid crystal display device
CN102361399B (en) Power supply device of thin film transistor liquid crystal display
TWI691946B (en) Charge pump circuit, drive circuit and display device
US7633238B2 (en) Lamp driving device and display apparatus having the same
CN114242015B (en) Control method of display panel circuit and display panel circuit

Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees