TWI449019B - Liquid crystal display panel and driving method thereof - Google Patents
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本發明是有關於一種像素準位多工(Pixel Level Multiplexing,PLM)架構的液晶顯示面板，且特別是有關於一種可減少所需的閘極驅動器(gate driver)和源極驅動器(source driver)數目的液晶顯示面板。 The invention relates to a liquid crystal display panel with a Pixel Level Multiplexing (PLM) architecture, and in particular to a gate driver and a source driver which can reduce the required requirements. The number of liquid crystal display panels.
目前的平面顯示器(FPD)種類繁多，如液晶顯示器(LCD)、有機電激發光顯示器(OLED)以及電漿顯示器(PDP)等。然而，不論是何種平面顯示器，其顯示面板的架構均相似，即在基板(substrate)上配置有縱橫交錯的掃描線路(scan line)與資料線路(data line)，且每一個掃描線路與資料線路交叉處即配置一像素(pixel)。像素經由掃描線路接收掃描訊號以決定是否被致能或導通，並在其被導通時經由資料線路接收資料訊號以顯示影像。 There are many types of flat panel displays (FPDs), such as liquid crystal displays (LCDs), organic electroluminescent displays (OLEDs), and plasma display devices (PDPs). However, regardless of the type of flat panel display, the structure of the display panel is similar, that is, a scan line and a data line are arranged on the substrate, and each scan line and data are arranged. A pixel is arranged at the intersection of the lines. The pixel receives the scan signal via the scan line to determine whether it is enabled or turned on, and receives the data signal via the data line to display the image when it is turned on.
液晶顯示面板的解析度越高，其所需的閘極驅動晶片和源極驅動晶片就要越多，且每一條掃描線和資料線均需要設置對應的焊墊(pad)以連接至閘極驅動晶片和源極驅動晶片，這不僅需要相當多的佈局面積，同時也會增加額外的製造成本。因此，如何在維持相同解析度的情況下減少所需的閘極驅動晶片和源極驅動晶片的元件數目和接腳數，便是目前液晶顯示面板驅動技術的重要發展方向之 一。因此有人提出一種PLM(像素準位多工，Pixel Level Multiplexing)的架構，利用較少的掃描線和資料線數目驅動液晶顯示面板的像素。 The higher the resolution of the liquid crystal display panel, the more gate drive and source drive wafers are required, and each scan line and data line needs to be provided with a corresponding pad to connect to the gate. Driving the wafer and source drive wafers requires not only a considerable amount of layout area, but also additional manufacturing costs. Therefore, how to reduce the number of components and the number of pins of the gate driving chip and the source driving chip required to maintain the same resolution is an important development direction of the current liquid crystal display panel driving technology. One. Therefore, a PLM (Pixel Level Multiplexing) architecture has been proposed to drive the pixels of the liquid crystal display panel with fewer scan lines and data lines.
圖1即為根據習知技術之液晶顯示面板之局部電路示意圖。液晶顯示面板100包括複數條資料線(如DL1、DL2)以及N條掃描線(如S1、S2、S3、S4)，其中掃描線S1對應於畫素列L1，掃描線S2對應於畫素列L2，並且畫素列L1及L2分別包括複數個畫素單元(如P11、P12、P21以及P22)，每一畫素單元中會包括電晶體、液晶電容以及儲存電容等元件，畫素單元可採用習知的畫素結構，圖1中之畫素單元(如P11、P12、P21以及P22)僅為示意。此外，掃描線S1及S3為用以說明其畫素列L1所接收的驅動信號一致，而非指實體上一定為直接連接的關係。 FIG. 1 is a partial circuit diagram of a liquid crystal display panel according to the prior art. The liquid crystal display panel 100 includes a plurality of data lines (such as DL 1 , DL 2 ) and N scan lines (such as S 1 , S 2 , S 3 , and S 4 ), wherein the scan line S 1 corresponds to the pixel column L 1 . The scan line S 2 corresponds to the pixel column L 2 , and the pixel columns L 1 and L 2 respectively include a plurality of pixel units (such as P 11 , P 12 , P 21 , and P 22 ), and each pixel unit Including components such as a transistor, a liquid crystal capacitor, and a storage capacitor, the pixel unit can adopt a conventional pixel structure, and the pixel units in FIG. 1 (such as P 11 , P 12 , P 21 , and P 22 ) are merely illustrative. In addition, the scan lines S1 and S3 are used to describe that the drive signals received by the pixel column L 1 are identical, and the relationship is not necessarily a direct connection.
以畫素P11及P21為例，畫素P21耦接於掃描線S2，而畫素列P11則耦接電晶體M1的一端以接收掃描線S1的驅動信號，而電晶體M1的另一端則耦接於掃描線S4，且電晶體M1的閘極耦接於掃描線S2。而畫素列L1上所有的畫素的結構會與畫素P11相同，而畫素列L2上所有的畫素的結構會與畫素P21相同。當掃描線S2與S4均致能時(即邏輯高電位時)，畫素列L1與L2均會開啟以便資料線(如DL1、DL2)寫入畫素資料至對應的畫素單元(如P11、P12)中。然後，當只有掃描線S2致能時，則畫素列L1關閉而剩下畫素列L2開啟以便資料線(如DL1、DL2)寫入畫素資料至畫素列L2的畫素單元(如P21、P22)中以更新畫素 列L2中的畫素電壓。其餘掃描線與對應的畫素單元的電路結構則以對偶方式類推，在此不加贅述。 Taking the pixels P 11 and P 21 as an example, the pixel P 21 is coupled to the scan line S 2 , and the pixel column P 11 is coupled to one end of the transistor M 1 to receive the driving signal of the scan line S 1 . The other end of the crystal M 1 is coupled to the scan line S 4 , and the gate of the transistor M 1 is coupled to the scan line S 2 . The structure of all the pixels on the pixel list L 1 will be the same as that of the pixel P 11 , and the structure of all the pixels on the pixel list L 2 will be the same as the pixel P 21 . When the scan lines S 2 and S 4 are both enabled (ie, when the logic is high), the pixel columns L 1 and L 2 are both turned on so that the data lines (such as DL 1 , DL 2 ) are written to the corresponding data. In the pixel unit (such as P 11 , P 12 ). Then, when only the scan line S 2 is enabled, the pixel column L 1 is turned off and the remaining pixel column L 2 is turned on so that the data lines (such as DL 1 , DL 2 ) are written to the pixel data to the pixel column L 2 . The pixel elements (such as P 21 , P 22 ) are used to update the pixel voltage in the pixel column L 2 . The circuit structure of the remaining scan lines and the corresponding pixel units is analogized in a dual manner, and will not be described herein.
掃描線S2與掃描線S4所接收的掃描信號(即閘極驅動器所須輸出的掃描信號)的波形則如圖2所示，圖2為根據圖1之掃描信號波形圖，其中在第二期間T2的前半週期中，掃描線S2與S4均致能，此時，畫素列L1與畫素列L2均會開啟。然後，在第二期間T2的後半週期中，掃描線S2維持致能，而掃描線S4則失能。此時，僅剩畫素列L2開啟，利用上述時序，便能依序更新畫素列L1與L2中的畫素資料。 The waveform of the scan signal received by the scan line S 2 and the scan line S 4 (ie, the scan signal to be output by the gate driver) is as shown in FIG. 2, and FIG. 2 is a waveform diagram of the scan signal according to FIG. During the first half of the second period T2, the scan lines S 2 and S 4 are both enabled, and at this time, both the pixel column L 1 and the pixel column L 2 are turned on. Then, in the latter half of the second period T2, the scanning line S 2 is maintained enabled, and the scanning line S 4 is disabled. At this time, only the remaining pixel sequence L 2 is turned on, and the pixel data in the pixel columns L 1 and L 2 can be sequentially updated by the above timing.
接著，掃描線S4在第三期間T3中致能以便更新所對應的畫素列L3、L4，而在第一期間T1中，掃描線S2則是配合上一條偶數的掃描線的掃描信號，在第一期間T1的前半週期中致能以便更新對應上一條奇數的掃描線的畫素列(如同掃描線S4在第二期間T2的前半週期配合掃描線S2而致能一般)。值得注意的是，上述第一期間T1、第二期間T2以及第三期間T3的週期相同，其餘掃描線的掃描信號則依此類推以更新整個面板的畫素。利用圖1之面板架構，僅需半數的掃描信號和資料線路來驅動所有的畫素單元即可，也就可以減少閘極驅動晶片和源極驅動晶片的使用數目。 Next, the scan line S 4 is enabled in the third period T3 to update the corresponding pixel columns L 3 , L 4 , and in the first period T1, the scan line S 2 is matched with an even number of scan lines. The scan signal is enabled in the first half of the first period T1 to update the pixel column corresponding to the previous odd-numbered scan line (as the scan line S 4 is coupled to the scan line S 2 during the first half of the second period T2) ). It should be noted that the periods of the first period T1, the second period T2, and the third period T3 are the same, and the scan signals of the remaining scan lines are updated to update the pixels of the entire panel. With the panel architecture of Figure 1, only half of the scan signal and data lines are required to drive all of the pixel units, and the number of gate drive and source drive wafers can be reduced.
在驅動的過程中，畫素單元會因掃描信號的電位變化而受影響，也就是所謂的饋通效應(feed through effect)。因此在第二期間T2中，畫素列L2僅會受到掃描線S2的下 降緣201所產生饋通效應的影響，而畫素列L1則會受到掃描線S2的掃描信號的下降緣201與下一條偶數掃描線S4的掃描信號的下降緣202所產生饋通效應的影響。因此，在驅動過程中，畫素列L1所受到的饋通效應會大於畫素列L2。若整個畫面給予相同灰階，則因為上述饋通效應的不同將造成畫面品質不均。 During the driving process, the pixel unit is affected by the potential change of the scanning signal, which is called the feed through effect. Therefore, in the second period T2, the pixel sequence L 2 is only affected by the feedthrough effect generated by the falling edge 201 of the scanning line S 2 , and the pixel sequence L 1 is subjected to the falling of the scanning signal of the scanning line S 2 . Effect feed-through edge 201 produces a falling edge 202 at the even-numbered scanning lines of the scanning signal S 4. Therefore, during the driving process, the pixel feed L 1 is subjected to a feedthrough effect that is larger than the pixel sequence L 2 . If the entire screen is given the same gray level, the picture quality will be uneven due to the difference in the feedthrough effect described above.
圖3為根據圖1之液晶顯示面板100之局部等效電路圖。其中畫素單元P11包括電晶體M111、液晶電容Clc2以及儲存電容Cst2，而電容Cgs2則是用來表示電晶體M111的閘極-源極間的等效寄生電容，而電容Cgsf則是用來表示電晶體M1的閘極-源極間的等效寄生電容。畫素單元P21的電路結構與畫素單元P11相同，在此不加累述。配合圖3中的等效電容與圖2之信號波形圖，可以計算出掃描信號的電壓變化(由高電壓Vgh至低電壓Vgl)對畫素單元P11與P21的畫素電壓(即液晶電容Clc2與Clc1上所儲存的畫素電壓)的影響。 FIG. 3 is a partial equivalent circuit diagram of the liquid crystal display panel 100 according to FIG. 1. The pixel unit P 11 includes a transistor M111, a liquid crystal capacitor Clc2, and a storage capacitor Cst2, and the capacitor Cgs2 is used to represent the equivalent parasitic capacitance between the gate and the source of the transistor M111, and the capacitor Cgsf is used. Indicates the equivalent parasitic capacitance between the gate and source of the transistor M1. The circuit structure of the pixel unit P 21 is the same as that of the pixel unit P 11 and will not be described here. With the equivalent capacitance in FIG. 3 and the signal waveform diagram of FIG. 2, the voltage variation of the scan signal (from high voltage Vgh to low voltage Vgl) to the pixel voltage of the pixel units P 11 and P 21 (ie, liquid crystal) can be calculated. The effect of the pixel voltage stored on the capacitors Clc2 and Clc1).
在第二期間T2中，畫素單元P21上的畫素電壓僅會受到掃描線S2的下降緣201(請參照圖2)的影響，也就是經由電容Cgs1所造成的電壓下降，其饋通電壓(feedthrough voltage)△V1可以表示如下：
畫素單元P11則會受到掃描線S2的掃描信號的下降緣
201與S4的掃描信號的下降緣202的影響，其饋通電壓(feed through voltage)△V2可以表示如下：
由上述公式(1)與(2)可知，畫素單元P11因掃描信號所造成的饋通電壓△V2會大於畫素單元P21因掃描信號所造成的饋通電壓△V1。因此，在驅動過程中，畫素單元P11與畫素單元P21上的畫素電壓會因掃描信號而有不同的電壓變化，這會影響顯示的品質與穩定性。 It can be seen from the above formulas (1) and (2) that the feedthrough voltage ΔV2 caused by the scanning signal of the pixel unit P 11 is larger than the feedthrough voltage ΔV1 of the pixel unit P 21 due to the scanning signal. Therefore, during the driving process, the pixel voltages on the pixel unit P 11 and the pixel unit P 21 may have different voltage changes due to the scanning signal, which may affect the quality and stability of the display.
此外，當掃描線S2失能時，掃描線S1會處於浮接(floating)的狀態，因為電晶體M111的閘極附近有許多電路線或電容等，會導致電晶體M111的閘極電壓受到這些電性耦合作用而飄移至共同電壓Vcom而影響液晶電容Clc2上的畫素電壓。 In addition, when the scan line S 2 is disabled, the scan line S 1 will be in a floating state, because there are many circuit lines or capacitors in the vicinity of the gate of the transistor M111, which may cause the gate voltage of the transistor M111. Due to these electrical coupling effects, it drifts to the common voltage Vcom and affects the pixel voltage on the liquid crystal capacitor Clc2.
本發明提供一種液晶顯示面板，將面板分為複數個顯示區域，並配合掃描信號及控制線來驅動面板中的掃描線，藉此減少液晶顯示面板所需的閘極驅動器(接腳)數目，並且調整控制線與掃描線的致能電壓大小來降低控制線及掃描線上的信號對畫素的饋通影響。 The invention provides a liquid crystal display panel, which divides the panel into a plurality of display areas, and drives the scan lines in the panel together with the scan signal and the control line, thereby reducing the number of gate drivers (pins) required for the liquid crystal display panel. And adjusting the enable voltage of the control line and the scan line to reduce the feedthrough effect of the signal on the control line and the scan line on the pixel.
本發明另提供一種液晶顯示面板，利用閘極信號線與控制線以間接的方式來驅動掃描線，藉此降低各別掃描線所受到的饋通效應的差異，使每一畫素單元的饋通效應相 同，以增加液晶顯示面板的顯示品質。 The invention further provides a liquid crystal display panel, which uses an gate signal line and a control line to drive the scan line in an indirect manner, thereby reducing the difference of the feedthrough effect of the respective scan lines, so that each pixel unit feeds Pass effect phase The same, to increase the display quality of the liquid crystal display panel.
本發明提供一種液晶顯示面板的驅動方法，在每個顯示區域中，第二掃描線搭配控制線來驅動面板中的掃描線，藉此減少閘極驅動器所需提供的信號的數目。 The present invention provides a driving method of a liquid crystal display panel in which a second scan line is used with a control line to drive a scan line in a panel in each display area, thereby reducing the number of signals required to be provided by the gate driver.
本發明亦提供一種液晶顯示面板的驅動方法，利用閘極信號線與控制線相互配合以驅動掃描線。 The present invention also provides a driving method of a liquid crystal display panel, which uses a gate signal line and a control line to cooperate to drive a scan line.
本發明提出一種液晶顯示面板，此液晶顯示面板包括複數個顯示區域及X條控制線，其中X為正整數。每一個顯示區域皆包括X個電晶體、X條第一掃描線及1條第二掃描線。每一條控制線分別對應於每一個顯示區域中所有第一掃描線的其中之一。其中，在每一個顯示區域中，這些電晶體會分別對應耦接於這些第一掃描線與這些控制線，其中在這些電晶體中的第i電晶體的汲極及源極分別耦接於這些第一掃描線中的第i掃描線及這些控制線中的第i控制線之間，且這些電晶體的閘極皆耦接第二掃描線，i為正整數且小於等於X。並且，各控制線係提供第一致能電壓，而各第二掃描線係提供第二致能電壓，其中第一致能電壓小於等於第二致能電壓。 The invention provides a liquid crystal display panel comprising a plurality of display areas and X control lines, wherein X is a positive integer. Each display area includes X transistors, X first scan lines, and one second scan line. Each control line corresponds to one of all the first scan lines in each display area. In each of the display regions, the transistors are respectively coupled to the first scan lines and the control lines, wherein the drains and the sources of the i-th transistors in the transistors are respectively coupled to the The i-th scan line in the first scan line and the i-th control line among the control lines, and the gates of the transistors are all coupled to the second scan line, i being a positive integer and less than or equal to X. Moreover, each control line provides a first enable voltage, and each second scan line provides a second enable voltage, wherein the first enable voltage is less than or equal to the second enable voltage.
本發明又提出一種液晶顯示面板，此液晶顯示面板包括複數個顯示區域及X條控制線。每一個顯示區域皆包括X個邏輯運算單元、X條第一掃描線及1條第二掃描線。每個邏輯運算單元皆具有第一輸入端、第二輸入端以及輸出端，且當第一輸入端與第二輸入端皆為邏輯高電位時，輸出端為邏輯高電位。每一條控制線分別對應於每一個顯 示區域中所有第一掃描線的其中之一。在每一個顯示區域中，這些邏輯運算單元會分別對應耦接於這些第一掃描線與這些控制線，其中在這些邏輯運算單元中的第i邏輯運算單元的輸出端及第一輸入端分別耦接於這些第一掃描線中的第i掃描線及這些控制線中的第i控制線之間，且這些邏輯運算單元的第二輸入端皆耦接第二掃描線，i為正整數且小於等於X。並且，各控制線係提供第一致能電壓，而各第二掃描線係提供第二致能電壓，其中第一致能電壓小於等於第二致能電壓。 The invention further provides a liquid crystal display panel comprising a plurality of display areas and X control lines. Each display area includes X logical operation units, X first scan lines, and one second scan line. Each logic operation unit has a first input terminal, a second input terminal, and an output terminal, and when the first input terminal and the second input terminal are both at a logic high level, the output terminal is at a logic high level. Each control line corresponds to each display One of all the first scan lines in the display area. In each display area, the logic operation units are respectively coupled to the first scan lines and the control lines, wherein the output ends of the ith logic operation units and the first input ends of the logic operation units are respectively coupled Connected between the ith scan line of the first scan lines and the ith control line of the control lines, and the second input ends of the logic operation units are coupled to the second scan line, where i is a positive integer and is less than Equal to X. Moreover, each control line provides a first enable voltage, and each second scan line provides a second enable voltage, wherein the first enable voltage is less than or equal to the second enable voltage.
在本發明之一實施例中，上述之第二掃描線在第一期間中呈現致能，而這些控制線會在第一期間中依序致能，且這些控制線致能的時間為第一期間的1/(X+1)。 In an embodiment of the invention, the second scan line is enabled in the first period, and the control lines are sequentially enabled in the first period, and the time of the control lines is first. 1/(X+1) of the period.
在本發明之一實施例中，上述之第一致能電壓為14伏特，且第二致能電壓為25伏特。 In one embodiment of the invention, the first enable voltage is 14 volts and the second enable voltage is 25 volts.
在本發明之一實施例中，上述之液晶顯示面板上所有的第一掃描線和所有的第二掃描線的總數為N，且X小於 等於。 In an embodiment of the invention, the total number of all the first scan lines and all the second scan lines on the liquid crystal display panel is N, and X is less than or equal to .
在本發明之一實施例中，上述之每一條第一掃描線及第二掃描線分別對應於一畫素列，且畫素列具有複數個畫素單元。 In an embodiment of the invention, each of the first scan lines and the second scan lines respectively correspond to a pixel column, and the pixel column has a plurality of pixel units.
在本發明之一實施例中，上述之液晶顯示面板更具有至少一閘極驅動器，這些閘極驅動器皆具有複數條訊號線，其中各訊號線係分別耦接各第二掃描線，並輸出第二致能電壓至各第二掃描線。 In an embodiment of the present invention, the liquid crystal display panel further has at least one gate driver, wherein each of the gate drivers has a plurality of signal lines, wherein each of the signal lines is coupled to each of the second scan lines, and outputs the first The two enable voltages to the respective second scan lines.
本發明另提出一種液晶顯示面板，此液晶顯示面板包括複數個顯示區域及Y條控制線。每一個顯示區域包括Y個電晶體、Y條掃描線及閘極信號線，Y為一正整數。這些控制線分別對應於每一個顯示區域中所有掃描線的其中之一。其中，每一個顯示區域中，這些電晶體分別對應耦接於這些掃描線與這些控制線之間，其中這些電晶體中的第j電晶體的汲極及源極分別耦接於第j掃描線及第j控制線，這些電晶體的閘極皆耦接閘極信號線，j為正整數且小於等於Y。並且，各控制線係提供第一致能電壓，各閘極信號線係提供第二致能電壓。 The invention further provides a liquid crystal display panel comprising a plurality of display areas and Y control lines. Each display area includes Y transistors, Y scan lines, and gate signal lines, and Y is a positive integer. These control lines correspond to one of all the scan lines in each display area. In each of the display regions, the transistors are respectively coupled between the scan lines and the control lines, wherein the drains and the sources of the jth transistors in the transistors are respectively coupled to the jth scan lines. And the jth control line, the gates of the transistors are all coupled to the gate signal line, and j is a positive integer and less than or equal to Y. Moreover, each control line provides a first enable voltage, and each gate signal line provides a second enable voltage.
本發明再提出一種液晶顯示面板，此液晶顯示面板包括複數個顯示區域及Y條控制線。每一個顯示區域包括Y個邏輯運算單元、Y條掃描線及閘極信號線，Y為一正整數。每個邏輯運算單元皆具有第一輸入端、第二輸入端以及輸出端，且當第一輸入端與第二輸入端皆為邏輯高電位時，輸出端為邏輯高電位。這些控制線分別對應於每一個顯示區域中所有掃描線的其中之一。其中，每一個顯示區域中，這些邏輯運算單元分別對應耦接於這些掃描線與這些控制線之間，其中這些邏輯運算單元中的第j邏輯運算單元的輸出端及第一輸入端分別耦接於第j掃描線及第j控制線，這些邏輯運算單元的第二輸入端皆耦接閘極信號線，j為正整數且小於等於Y。 The invention further provides a liquid crystal display panel comprising a plurality of display areas and Y control lines. Each display area includes Y logical operation units, Y scanning lines, and gate signal lines, and Y is a positive integer. Each logic operation unit has a first input terminal, a second input terminal, and an output terminal, and when the first input terminal and the second input terminal are both at a logic high level, the output terminal is at a logic high level. These control lines correspond to one of all the scan lines in each display area. In each display area, the logic operation units are respectively coupled between the scan lines and the control lines, wherein the output ends of the jth logic operation units and the first input ends of the logic operation units are respectively coupled In the jth scan line and the jth control line, the second input ends of the logic operation units are all coupled to the gate signal line, and j is a positive integer and less than or equal to Y.
在本發明之一實施例中，上述之閘極信號線在第一期間呈現致能，且這些控制線在第一期間中依序致能，且這 些控制線致能的時間等於第一期間的1/Y。 In an embodiment of the invention, the gate signal lines described above are enabled during the first period, and the control lines are sequentially enabled in the first period, and this The time required for these control lines is equal to 1/Y of the first period.
在本發明之一實施例中，上述之液晶顯示面板上所有的第一掃描線和所有的第二掃描線的總數為N，且Y小於等於。 In an embodiment of the invention, the total number of all the first scan lines and all the second scan lines on the liquid crystal display panel is N, and Y is less than or equal to .
在本發明之一實施例中，上述之每一條掃描線分別對應於一畫素列，且畫素列具有複數個畫素單元。 In an embodiment of the invention, each of the scan lines respectively corresponds to a pixel column, and the pixel column has a plurality of pixel units.
在本發明之一實施例中，上述每一電晶體係形成於扇出區，且每一電晶體皆為薄膜電晶體。 In an embodiment of the invention, each of the above electro-crystalline systems is formed in a fan-out region, and each of the transistors is a thin film transistor.
在本發明之一實施例中，上述之液晶顯示面板更具有至少一閘極驅動器，這些閘極驅動器皆具有複數條訊號線，其中各訊號線係分別耦接各閘極信號線，並輸出第二致能電壓至各閘極信號線。 In an embodiment of the present invention, the liquid crystal display panel further includes at least one gate driver, wherein the gate drivers each have a plurality of signal lines, wherein each of the signal lines is coupled to each of the gate signal lines, and outputs the first The two enable voltages to the gate signal lines.
在本發明之一實施例中，上述之邏輯運算單元包括一及閘。 In an embodiment of the invention, the logical operation unit includes a gate.
本發明提出一種液晶顯示面板的驅動方法，其中此液晶顯示面板包括多個顯示區域及多條控制線，而每一顯示區域包括至少一第一掃描線及第二掃描線，並且這些第一掃描線分別對應這些控制線。此驅動方法包括下列步驟。首先，輸出第二致能電壓至第二掃描線，以開啟第二掃描線。接著，依序提供第一致能電壓至這些控制線。最後，在這些控制線的其中之一接收到第一致能電壓時，則開啟對應控制線的第一掃描線。 The present invention provides a driving method of a liquid crystal display panel, wherein the liquid crystal display panel includes a plurality of display areas and a plurality of control lines, and each of the display areas includes at least a first scan line and a second scan line, and the first scans The lines correspond to these control lines. This driving method includes the following steps. First, the second enable voltage is outputted to the second scan line to turn on the second scan line. Then, the first enable voltage is sequentially supplied to the control lines. Finally, when one of the control lines receives the first enable voltage, the first scan line of the corresponding control line is turned on.
在本發明之一實施例中，上述之每條第一掃描線開啟的時間等於第二掃描線開啟的時間的1/(X+1)。 In an embodiment of the invention, the time that each of the first scan lines is turned on is equal to 1/(X+1) of the time when the second scan line is turned on.
本發明亦提出一種液晶顯示面板的驅動方法，其中此液晶顯示面板包括多個顯示區域及多條控制線，而每一顯示區域包括至多條掃描線及閘極信號線，並且這些掃描線分別對應這些控制線。此驅動方法包括下列步驟。首先，輸出第二致能電壓至閘極信號線。接著，依序提供第一致能電壓至這些控制線。最後，在這些控制線的其中之一接收到第一致能電壓時，則開啟對應控制線的掃描線。 The present invention also provides a driving method of a liquid crystal display panel, wherein the liquid crystal display panel includes a plurality of display areas and a plurality of control lines, and each of the display areas includes at most one of the scan lines and the gate signal lines, and the scan lines respectively correspond to These control lines. This driving method includes the following steps. First, the second enable voltage is output to the gate signal line. Then, the first enable voltage is sequentially supplied to the control lines. Finally, when one of the control lines receives the first enable voltage, the scan line of the corresponding control line is turned on.
在本發明之一實施例中，上述之每條掃描線開啟的時間等於第二致能電壓維持的時間的1/Y。 In an embodiment of the invention, each of the scan lines is turned on for a time equal to 1/Y of the time during which the second enable voltage is maintained.
本發明之液晶顯示面板，透過掃描線與控制線(或閘極信號線)相互搭配以驅動畫素單元以減少面板所需的閘極驅動器(接腳)數目，並且藉由調整控制線與掃描線的致能電壓大小來降低各別畫素所受到的饋通效應差異，使每一畫素單元的饋通效應相同，以增加液晶顯示面板的顯示品質。 The liquid crystal display panel of the present invention is matched with a control line (or a gate signal line) to drive a pixel unit to reduce the number of gate drivers (pins) required by the panel, and by adjusting the control line and scanning The enabling voltage of the line reduces the difference in feedthrough effects of the respective pixels, so that the feedthrough effect of each pixel unit is the same to increase the display quality of the liquid crystal display panel.
為讓本發明之上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式，作詳細說明如下。 The above described features and advantages of the present invention will be more apparent from the following description.
有鑑於此，為了改善畫素列饋通電壓不一致而導致畫面不均勻的問題，本發明於是提出一種液晶顯示面板。為了使本發明之內容更為明瞭，以下特舉實施例作為本發明確實能夠據以實施的範例。 In view of the above, in order to improve the problem of unevenness of the picture due to inconsistent pixel feedthrough voltage, the present invention proposes a liquid crystal display panel. In order to clarify the content of the present invention, the following specific examples are given as examples in which the present invention can be implemented.
圖4A為根據本發明第一實施例所述之液晶顯示面板之局部電路示意圖。請參照圖4A，在本實施方例中，液晶顯示面板400包括控制線SC1及多個顯示區域(如410、420)。每一顯示區域包括兩條掃描線，以顯示區域410為例，其包括第一掃描線S1、第二掃描線S2及電晶體M41，顯示區域420則包括第一掃描線S3、第二掃描線S4及電晶體M42。在顯示區域410中，掃描線S1對應掃描畫素列L1，掃描線S2對應掃描畫素列L2，電晶體M41的汲極與源極分別耦接於掃描線S1與控制線SC1，其閘極則耦接於掃描線S2。在顯示區域420中，電晶體M42的汲極與源極則分別耦接於掃描線S3與控制線SC1，其閘極則耦接掃描線S4，其餘顯示區域(未繪示)中的電路結構則類推，不再贅述。此外，電晶體M41、M42則可形成於扇出區或非可視區，藉此增加顯示區域可以利用的範圍。當然也可如圖1所示，將多個電晶體M41、M42...設置於各畫素中，惟此液晶顯示面板的顯示區開口率將相對較低。 4A is a partial circuit diagram of a liquid crystal display panel according to a first embodiment of the present invention. Referring to FIG. 4A, in the present embodiment embodiment, the liquid crystal display panel 400 includes a control line SC 1 and a plurality of display areas (e.g., 410, 420). Each display area includes two scan lines. The display area 410 is taken as an example. The display area 410 includes a first scan line S 1 , a second scan line S 2 , and a transistor M 41 . The display area 420 includes a first scan line S 3 . The second scan line S 4 and the transistor M 42 . In the display area 410, the scan line S 1 corresponds to the scan pixel column L 1 , the scan line S 2 corresponds to the scan pixel column L 2 , and the drain and source of the transistor M 41 are respectively coupled to the scan line S 1 and the control The line SC 1 has its gate coupled to the scan line S 2 . In the display area 420, the drain and the source of the transistor M 42 are respectively coupled to the scan line S 3 and the control line SC 1 , and the gate is coupled to the scan line S 4 , and the remaining display areas (not shown) The circuit structure in the case is analogous and will not be described again. Further, the transistors M 41 , M 42 may be formed in the fan-out area or the non-visible area, thereby increasing the range in which the display area can be utilized. Of course, as shown in FIG. 1, a plurality of transistors M 41 , M 42 can be disposed in each pixel, but the display area opening ratio of the liquid crystal display panel will be relatively low.
在驅動的過程中，由於控制線SC1會經由對應的電晶體耦接至個別顯示區域中的第一條掃描線，因此當顯示區域中的第二條掃描線與控制線SC1皆致能時，其對應的第一條掃描線便會開啟以便寫入對應的畫素電壓。然後，控制線SC1會失能，此時僅保留第二條掃描線致能以便更新第二條掃描線中的畫素資料。 During the driving process, since the control line SC 1 is coupled to the first scan line in the individual display areas via the corresponding transistor, the second scan line and the control line SC 1 in the display area are enabled. The corresponding first scan line is turned on to write the corresponding pixel voltage. Then, the control line SC 1 is disabled, at which time only the second scan line enable is retained to update the pixel data in the second scan line.
接下來，請參照圖4A及圖4B，圖4B為根據圖4A之掃描線與控制線的驅動波形圖。如圖4B所示，控制線SC1 會在掃描線S2的致能期間T4的前半週期T41中致能，此時掃描線S1會被開啟以便寫入畫素資料(畫素電壓)至畫素列L1中。然後，控制線SC1會在掃描線S2的致能期間的後半週期T41中失能，此時僅剩掃描線S2維持開啟狀態以便更新畫素列L2中的畫素資料。也就是說，掃描線S2的致能期間T4會被分為兩個週期，分別用來更新畫素列L1與L2中的畫素資料。其餘顯示區域中的掃描方式則類推，控制線SC1會與對應的掃描線相互配合以寫入畫素資料至所有畫素列。 Next, please refer to FIG. 4A and FIG. 4B, which is a driving waveform diagram of the scan line and the control line according to FIG. 4A. 4B, control line SC 1 will first half cycle T41 T4 of enabling a scan line during the enabling of the S 2, when the scan lines S 1 is turned on in order to write the pixel data (pixel voltage) to The picture is listed in L 1 . Then, the control line SC 1 will be half cycle S during 2 T41 enabling the disabling of the scanning lines, the scanning lines S 2 remaining at this time was maintained open so as to update the pixel data of the pixel row L 2. That is to say, the enable period T4 of the scan line S 2 is divided into two periods for updating the pixel data in the pixel columns L 1 and L 2 , respectively. The scanning method in the remaining display areas is analogous, and the control line SC 1 cooperates with the corresponding scanning lines to write the pixel data to all the pixel columns.
經由上述驅動方式可以推知，液晶顯示面板400在驅動的過程中，閘極驅動器僅需提供半數的掃描信號(僅需驅動個別顯示區域中的第二掃描線)，而另一半的掃描線則配合控制線SC1來驅動。再者，由於控制線SC1的致能電壓(亦即第一致能電壓)可分別控制，不需與第二掃描線的致能電壓(亦即第二致能電壓)相同，因此可藉由其控制線SC1的致能電壓大小來調整不同畫素列(如L1與L2)的饋通效應差異。 It can be inferred through the above driving manner that during the driving process of the liquid crystal display panel 400, the gate driver only needs to provide half of the scanning signals (only need to drive the second scanning line in the individual display areas), and the other half of the scanning lines cooperate. The control line SC 1 is driven. Furthermore, since the enable voltage of the control line SC 1 (ie, the first enable voltage) can be separately controlled, it is not required to be the same as the enable voltage of the second scan line (ie, the second enable voltage), so The feedthrough effect difference of different pixel columns (such as L 1 and L 2 ) is adjusted by the magnitude of the enable voltage of its control line SC 1 .
請同時參照圖1至圖4A及圖4B，由電路結構上比較可以得知，本實施例的部份等效電路會等同於圖3所示電路，其主要差異在於圖1的電晶體M1耦接下一條偶數掃描線，本實施的電晶體M41則耦接控制線SC1。因此，可以由圖3推導出本實施例各畫素單元的饋通效應(feed through effect)，並引用圖3中的標號以作說明，以畫素列L2上的畫素單元P21而言，其饋通電壓(feed through
voltage)△V3可以表示如下：
由於本實施例的控制線SC1所接收的信號並非來自閘極驅動器的掃描信號，所以控制線上的電壓準位(致能時的高電壓準位Vghs與失能時的低電壓準位Vgls)與掃描信號的不同，以畫素列L1上的畫素單元P11而言，其饋通電壓△V4可以表示如下：
其中，n表示本實施例畫素列L2中的畫素單元的數目，若是任二畫素(例如是P11和P21)皆配置一電晶體(例如是M41)，如圖1所示，則n=1；CX則表示Cgs2與(Clc2+Cst2)串聯的值。 Where n is the number of pixel units in the pixel column L 2 of the present embodiment. If any two pixels (for example, P 11 and P 21 ), a transistor (for example, M 41 ) is disposed, as shown in FIG. 1 . That is, n=1; CX indicates the value of Cgs2 in series with (Clc2+Cst2).
由公式(1)~(4)進行比較可得知，當電壓值Vghs-Vgls低於Vgh-Vgl時，饋通電壓△V4與△V3的差值會小於習知的饋通電壓△V1與△V2的差值。並且，可藉由公式(3)及(4)對Vghs、Vgls與Vgh、Vgl這兩組電壓作饋通電壓最佳化的運算，可以得知，當Vghs=14V,Vgls=-7V,Vgh=25V,Vgl=-7V時，饋通電壓△V3與△V4會幾乎相同。因此，本實施例藉由調整Vghs與Vgls兩個電壓值即可降低不同掃描線所受到的饋通效應差異，避免影響畫面顯示品質。 It can be known from the comparison of the formulas (1) to (4) that when the voltage value Vghs-Vgls is lower than Vgh-Vgl, the difference between the feedthrough voltages ΔV4 and ΔV3 is smaller than the conventional feedthrough voltage ΔV1 and ΔV2 difference. Moreover, the calculation of the feedthrough voltages of the two sets of voltages Vghs, Vgls, Vgh, and Vgl can be performed by equations (3) and (4), and it can be known that when Vghs=14V, Vgls=-7V, Vgh When the voltage is =25V and Vgl=-7V, the feedthrough voltages ΔV3 and ΔV4 will be almost the same. Therefore, in this embodiment, by adjusting the two voltage values of Vghs and Vgls, the difference in feedthrough effect between different scan lines can be reduced, thereby avoiding affecting the picture display quality.
同樣地，當顯示區域為三條掃描線時，亦可套用上述實施例的驅動方式來完成，以下再對此加以說明。圖5A為根據本發明第一實施例所述之液晶顯示面板之局部電路示意圖。請參照圖4A及圖5A，其主要差異在於液晶顯示面板500的控制線SC2，以及顯示區域中的掃描線數目，以顯示區域510為例，其包括第一掃描線S1、S2、第二掃描線S3與電晶體M51、M52。第一掃描線S1、S2分別經由電晶體M51、M52耦接至控制線SC1、SC2。同樣的，顯示區域520中的第一掃描線S4、S5則分別經由電晶體M53、M54耦接至控制線SC1、SC2。其餘顯示區域(未繪示)中的電路結構則類推，不再贅述。 Similarly, when the display area is three scanning lines, it can also be completed by applying the driving method of the above embodiment, which will be described below. FIG. 5A is a partial circuit diagram of a liquid crystal display panel according to a first embodiment of the present invention. Referring to FIG. 4A and FIG. 5A , the main difference is the control line SC 2 of the liquid crystal display panel 500 and the number of scan lines in the display area. Taking the display area 510 as an example, the first scan lines S 1 , S 2 , The second scan line S 3 and the transistors M 51 , M 52 . The first scan lines S 1 , S 2 are coupled to the control lines SC 1 , SC 2 via transistors M 51 , M 52 , respectively. Similarly, the first scan lines S 4 , S 5 in the display area 520 are coupled to the control lines SC 1 , SC 2 via the transistors M 53 , M 54 , respectively. The circuit structure in the remaining display areas (not shown) is analogous and will not be described again.
在驅動方法上則與上述圖4B相似，主要是將顯示區域中最後一條掃描線(如顯示區域510中的第二掃描線S3)的致能期間分為三個週期，在前兩個週期中分別開啟對應的前兩條畫素列(如L1、L2)以寫入畫素資料，然後在第三週期中則用來更新最後一個畫素列(如L3)。如圖5B所示，圖5B為根據圖5A之掃描線及控制線的驅動波形圖。掃描線S3的致能期間T5會被分為三個週期T51、T52以及T53，然後控制線SC1會在週期T51中致能，而控制線SC2會在週期T52中致能。因此，在週期T51中，畫素列L1開啟以便寫入畫素資料，在週期T52中，畫素列L2開啟以便寫入畫素資料。值得注意的是，畫素列L3會在整個致能週期T5開啟，因此在週期T53中，控制線SC1、SC2均會失能(表示畫素列L1與L2關閉)以便更新畫素列L3中的畫 素資料。 The driving method is similar to FIG. 4B described above, mainly in that the enabling period of the last scanning line in the display area (eg, the second scanning line S 3 in the display area 510) is divided into three periods, in the first two periods. The corresponding first two pixel columns (such as L 1 , L 2 ) are respectively opened to write the pixel data, and then used to update the last pixel column (such as L 3 ) in the third cycle. As shown in FIG. 5B, FIG. 5B is a driving waveform diagram of the scanning line and the control line according to FIG. 5A. Enabling period T5 of the scan lines S 3 is divided into three periods T51, T52 and T53, and the control line SC 1 will be enabled in the period T51, and the control line SC 2 will be enabled in the period T52. Therefore, in the period T51, the pixel column L 1 is turned on to write the pixel data, and in the period T52, the pixel column L 2 is turned on to write the pixel data. It is worth noting that the pixel sequence L 3 will be turned on during the entire enable period T5, so in the period T53, the control lines SC 1 , SC 2 are disabled (indicating that the pixel columns L 1 and L 2 are off) for updating. The pixel data in the L 3 is plotted.
由於本實施例可以由圖4的實施例演化而來，所以本實施例的電壓Vgh及Vgl與Vghs及Vgls同樣可以套用上述實施例計算出的最佳值，以使本實施例中的畫素單元P11及P21上的饋通電壓△V4與畫素單元P31上的饋通電壓△V3幾乎相同。 Since the present embodiment can be evolved from the embodiment of FIG. 4, the voltages Vgh and Vgl of the present embodiment can be applied to the optimum values calculated by the above embodiments in the same manner as Vghs and Vgls, so that the pixels in this embodiment are used. The feedthrough voltage ΔV4 on the cells P 11 and P 21 is almost the same as the feedthrough voltage ΔV3 on the pixel unit P 31 .
至此，可經由液晶顯示面板400及500的比較得知，當液晶顯示面板增加一條控制線時(如液晶顯示面板500中的控制線SC2)，顯示區域(如液晶顯示面板500中的顯示區域510)中最後一條掃描線(如液晶顯示面板500中的第二掃描線S3)則可以配合此控制線，再多驅動一條掃描線。藉此，閘極驅動器提供的掃描信號僅只需為掃描線數的三分之一，而同樣可以驅動液晶顯示面板中的所有掃描線。 So far, it can be seen from the comparison of the liquid crystal display panels 400 and 500 that when a control line is added to the liquid crystal display panel (such as the control line SC 2 in the liquid crystal display panel 500), the display area (such as the display area in the liquid crystal display panel 500) The last scan line in 510) (such as the second scan line S 3 in the liquid crystal display panel 500) can be matched with the control line to drive one more scan line. Thereby, the scan signal provided by the gate driver only needs to be one third of the number of scan lines, and can also drive all the scan lines in the liquid crystal display panel.
而從上述實施例可以發現，液晶顯示面板中顯示區域的掃描線可以增加至具有X條第一掃描線，請參照圖6A。圖6A為根據本發明第一實施例所述之液晶顯示面板之局部電路示意圖。請參照圖6A，在本實施例中，液晶顯示面板600包括N條掃描線(如S1~SX、SX+1...SN，其中N為正整數)、多個顯示區域(如610及620)及X條控制線(如SC1~SCX，其中X為正整數)。並且，每一個顯示區域皆包括X個電晶體(如M61~M6X)、X條第一掃描線(如S1~SX及SX+2~S2X+1)及1條第二掃描線(如SX+1及S2X+2)，且每一顯示區域中的X條第一掃描線會分別經由對應的X個電 晶體耦接至X條控制線。以顯示區域610而言，其第一掃描線S1~SX會分別經由電晶體M61~M6X耦接至控制線SC1~SCX。圖6A中的其餘顯示區域的電路結構可由上述說明類推，亦即第一掃描線SX+2~S2X+1可參照第一掃描線S1~SX的說明，第二掃描線S2X+2可參照第二掃描線SX+1的說明。並且，液晶顯示面板上所有畫素單元的饋通電壓同樣可由上述公式(3)、(4)得知，故不在此多作贅述。 It can be seen from the above embodiment that the scanning line of the display area in the liquid crystal display panel can be increased to have X first scanning lines, please refer to FIG. 6A. FIG. 6A is a partial circuit diagram of a liquid crystal display panel according to a first embodiment of the present invention. Referring to FIG. 6A, in the embodiment, the liquid crystal display panel 600 includes N scanning lines (such as S 1 ~S X , S X+1 ... S N , where N is a positive integer), and multiple display areas ( Such as 610 and 620) and X control lines (such as SC 1 ~ SC X , where X is a positive integer). Moreover, each display area includes X transistors (such as M 61 ~ M 6X ), X first scan lines (such as S 1 ~S X and S X+2 ~S 2X+1 ) and one second Scan lines (such as S X+1 and S 2X+2 ), and the X first scan lines in each display area are respectively coupled to the X control lines via the corresponding X transistors. In the display region 610, the first scan lines S 1 -S X are coupled to the control lines SC 1 -SC X via the transistors M 61 -M 6X , respectively. The circuit structure of the remaining display areas in FIG. 6A can be analogized by the above description, that is, the first scan lines S X+2 ~ S 2X+1 can refer to the description of the first scan lines S 1 -S X , and the second scan line S 2X +2 can refer to the description of the second scanning line S X+1 . Moreover, the feedthrough voltage of all the pixel units on the liquid crystal display panel can also be known from the above formulas (3) and (4), and therefore will not be further described herein.
在驅動方法上，本實施例則與上述實施例類似，同樣將顯示區域中第二掃描線(如顯示區域610中的掃描線SX+1)的致能期間分為X+1個週期，在前X個週期中分別開啟對應的前X條畫素列(如L1~LX)以寫入畫素資料，然後在第X+1週期中則用來更新最後一個畫素列(如LX+1)。如圖6B所示，圖6B為根據圖6A之掃描線及控制線的驅動波形圖。第二掃描線SX+1的致能期間T6會被分為X+1個週期T61~T6(X+1)，然後控制線SC1~SCX會分別在週期T61~T6X中依序致能，致使畫素列L1~LX依序開啟以便寫入畫素資料。值得注意的是，畫素列LX+1會在整個致能期間T6開啟，因此在週期T6(X+1)中，控制線SC1~SCX均會失能(表示畫素列L1~LX關閉)以便更新畫素列LX+1中的畫素資料。 In the driving method, the embodiment is similar to the above embodiment, and the enabling period of the second scanning line (such as the scanning line S X+1 in the display area 610) in the display area is also divided into X+1 periods. In the first X cycles, the corresponding first X pixel columns (such as L 1 ~L X ) are respectively opened to write the pixel data, and then in the X+1 cycle, the last pixel column is updated (eg, L X+1 ). As shown in FIG. 6B, FIG. 6B is a driving waveform diagram of the scanning line and the control line according to FIG. 6A. The enabling period T6 of the second scanning line S X+1 is divided into X+1 periods T61~T6(X+1), and then the control lines SC 1 ~SC X are sequentially sequenced in the period T61~T6X Yes, causing the pixel columns L 1 ~L X to be sequentially turned on to write pixel data. It is worth noting that the pixel sequence L X+1 will be turned on during the entire enable period T6, so in the period T6 (X+1), the control lines SC 1 ~SCX are disabled (representing the pixel column L 1 ~ L X is off) in order to update the pixel data in the pixel column L X+1 .
藉此，本實施例可利用增加控制線的條數，來減少閘極驅動器提供的掃描信號，並且可透過對掃描線及控制線作最佳化的運算，以求得接收掃描信號的掃描線條數及控制線條數的最小總和，使液晶顯示面板可以用最少的信號
源(包括掃描信號及控制線的信號)來驅動所有的掃描線。以具有N條掃描線液晶顯示面板為例，假設其控制線為X條，此液晶顯示面板所需的信號總數(閘極驅動器的接腳總數)可等於下式：
在本實施例中，可利用一次微分求取信號總數的最小解，推演過程如下：
以640×480的液晶顯示面板來說，對640作開根號可求得25.3，可得到X最小值為24，代表每一顯示區域的掃描線數則為24+1，所以此液晶顯示面板會分為25個完整的顯示區域，並將剩下15條掃描線歸為1個顯示區域。至此，可以得到此液晶顯示面板所需的最小信號總數為25+24+1=50。此外，可取掃描線總數的因數，用以代表每一顯示區域的掃描線數，藉此以提升液晶顯示面板解析度。同樣以640×480的液晶顯示面板來說，以其掃描線總數的因數32為例，以此代表每一顯示區域的掃描線數，致使顯示區域數會為20，則信號總數為32-1+20=51。而此液晶顯示面板掃描線總數的其餘因數可由上述說明推演，故不再贅述。 For a 640×480 liquid crystal display panel, the opening number of 640 can be obtained as 25.3, and the minimum value of X is 24, which means that the number of scanning lines per display area is 24+1, so this liquid crystal display panel It will be divided into 25 complete display areas, and the remaining 15 scan lines will be classified into one display area. At this point, the total number of minimum signals required to obtain the liquid crystal display panel is 25+24+1=50. In addition, a factor of the total number of scan lines can be taken to represent the number of scan lines per display area, thereby improving the resolution of the liquid crystal display panel. Similarly, in the case of a 640×480 liquid crystal display panel, taking the factor 32 of the total number of scanning lines as an example, the number of scanning lines of each display area is represented, so that the number of display areas is 20, and the total number of signals is 32-1. +20=51. The remaining factors of the total number of scanning lines of the liquid crystal display panel can be deduced from the above description, and therefore will not be described again.
此外，上述實施例中的電晶體的功能可利用邏輯運算單元來完成，下述依此再作說明。圖6C為根據本發明第一實施例所述之液晶顯示面板之局部電路示意圖。請參照 圖6A及圖6C，其最大的不同之處在於及閘A61~A6X(亦即邏輯運算單元)，並且參照圖6D來作說明。圖6D為圖6C的及閘A61的真值表示意圖。在此看到及閘A61，由真值表可以得知，當控制線SC1及第二掃描線SX+1的驅動信號皆為”1”(亦即致能)時，及閘A61的輸出端(亦即掃描線S1)的電壓準位會為”1”(亦即致能，例如為輸出邏輯高電壓準位)，使得畫素列L1上所有的畫素皆會被開啟。而及閘A62~A6X的運作方式會與及閘A61相同，故不再贅述。藉此，各顯示區域內的各畫素列同樣會依據第二掃描線及控制線的驅動信號而依序開啟，以寫入對應的畫素資料。 Further, the function of the transistor in the above embodiment can be performed by a logic operation unit, which will be further described below. FIG. 6C is a partial circuit diagram of a liquid crystal display panel according to a first embodiment of the present invention. Referring to FIG. 6A and FIG. 6C, the biggest difference is the gates A 61 to A 6X (that is, the logic operation unit), and is described with reference to FIG. 6D. FIG. 6D is a schematic diagram of the truth table of the gate A 61 of FIG. 6C. Here, the gate A 61 is seen. It can be known from the truth table that when the driving signals of the control line SC 1 and the second scanning line S X+1 are both "1" (ie, enabled), the gate A 61 The voltage level of the output (ie, scan line S 1 ) will be "1" (ie, enable, for example, output logic high voltage level), so that all pixels on the pixel column L 1 will be Open. The operation mode of the gate A 62 ~ A 6X will be the same as that of the gate A 61 , so it will not be described again. Thereby, each pixel column in each display area is also sequentially turned on according to the driving signals of the second scan line and the control line to write corresponding pixel data.
此外，可由上述實施例彙整為一種液晶顯示面板的驅動方法。圖6E為根據本發明第一實施例所述之液晶顯示面板的驅動方法的流程圖。請參照圖6E，首先，在步驟S601中，會輸出第二致能電壓至第二掃描線，以開啟第二掃描線。接著，在步驟S602中，依序輸出第一致能電壓至這些控制線。最後，在步驟S603中，在這些控制線的其中之一接收到第一致能電壓時，則開啟對應此控制線的第一掃描線。並且，步驟S604會判斷是否為還有控制線未接收過第一致能電壓。若步驟S604判斷結果為「是」，亦即有控制線未接收過第一致能電壓，則會再執行步驟S602及S603，以開啟另一條第一掃描線。若步驟S604判斷結果為「否」，亦即所有控制線皆接收過第一致能電壓，則結束此驅動方法。 Further, the above embodiment can be summarized as a driving method of a liquid crystal display panel. 6E is a flow chart of a driving method of a liquid crystal display panel according to a first embodiment of the present invention. Referring to FIG. 6E, first, in step S601, a second enable voltage is outputted to the second scan line to turn on the second scan line. Next, in step S602, the first enable voltage is sequentially output to the control lines. Finally, in step S603, when one of the control lines receives the first enable voltage, the first scan line corresponding to the control line is turned on. Moreover, step S604 determines whether there is still a control line that has not received the first enable voltage. If the result of the determination in step S604 is YES, that is, if the control line has not received the first enable voltage, steps S602 and S603 are performed again to turn on the other first scan line. If the result of the determination in step S604 is "NO", that is, all the control lines have received the first enable voltage, the driving method is ended.
由上述實施例的說明，可得知本實施例掃描線的驅動 方法。在每一顯示區域中，最後一條掃描線(亦即第二掃描線)會接收掃描信號，而所有的畫素例則會依據掃描信號的致能期間與對應的控制線的致能期間而依序開啟，以便分別寫入畫素資料，並藉由第二掃描線及控制線致能電壓的調整，以減少畫素單元間饋通電壓的差異。 According to the description of the above embodiment, the driving of the scan line of this embodiment can be known. method. In each display area, the last scan line (ie, the second scan line) receives the scan signal, and all of the pixel instances are based on the enable period of the scan signal and the enable period of the corresponding control line. The sequence is turned on to separately write the pixel data, and the second scan line and the control line enable voltage are adjusted to reduce the difference of the feedthrough voltage between the pixel units.
而不同的顯示區域中，其第二掃描線所接收掃描信號的來源及致能的時間會不一樣，並同時配合控制線的致能與否，使這些顯示區域中的畫素列都能寫入對應的畫素資料。當所有的顯示區域中的所有畫素列都寫入對應的畫素資料後，此液晶顯示面板就能提供使用者所需的影像。藉此，可減少面板所需的閘極驅動器(接腳)數目，並可增加液晶顯示面板的顯示品質。 In different display areas, the source and enable time of the scan signal received by the second scan line will be different, and at the same time, the enable or disable of the control line enables the pixel columns in these display areas to be written. Enter the corresponding pixel data. When all the pixel columns in all display areas are written to the corresponding pixel data, the liquid crystal display panel can provide the image desired by the user. Thereby, the number of gate drivers (pins) required for the panel can be reduced, and the display quality of the liquid crystal display panel can be increased.
圖7A為根據本發明第二實施例所述之液晶顯示面板之局部電路示意圖。請參照圖7A，在本實施例中，液晶顯示面板700包括控制線SC1、SC2及SC3，而每一顯示區域包括一條閘極信號線及三條掃描線。以顯示區域710為例，其包括閘極信號線SD1、掃描線S1、S2、S3及電晶體M71、M72、M73，顯示區域720則包括掃描線S4、S5、S6及電晶體M74、M75、M76。在顯示區域710中，掃描線S1對應掃描畫素列L1，掃描線S2對應掃描畫素列L2，掃描線S3對應掃描畫素列L3。電晶體M71的汲極與源極分別耦接於掃描線S1與控制線SC1，其閘極耦接閘極信號線SD1。電晶體M72的汲極與源極分別耦接於掃描線S2與控制線 SC2，其閘極耦接閘極信號線SD1。電晶體M73的汲極與源極分別耦接於掃描線S3與控制線SC3，其閘極耦接閘極信號線SD1。在顯示區域720中，掃描線S4、S5、S6分別經由電晶體M74、M75、M76耦接至控制線SC1、SC2及SC3，其餘顯示區域(未繪示)中的電路結構則類推，不再贅述。 FIG. 7A is a partial circuit diagram of a liquid crystal display panel according to a second embodiment of the present invention. Referring to Figure 7A, in the present embodiment, the liquid crystal display panel 700 includes a control line SC 1, SC 2 and SC 3, and each region includes a display gate signal line and three scan lines. Taking the display area 710 as an example, it includes a gate signal line SD 1 , scan lines S 1 , S 2 , S 3 and transistors M 71 , M 72 , M 73 , and the display area 720 includes scan lines S 4 , S 5 . , S 6 and transistors M 74 , M 75 , M 76 . In the display region 710, corresponding to the scan lines S 1 scan pixel column L 1, S 2 scan lines corresponding to the scanning pixel column L 2, S 3 corresponding to the scanning line scan pixel columns L 3. The drain and the source of the transistor M 71 are respectively coupled to the scan line S 1 and the control line SC 1 , and the gate thereof is coupled to the gate signal line SD 1 . The drain and the source of the transistor M 72 are respectively coupled to the scan line S 2 and the control line SC 2 , and the gate thereof is coupled to the gate signal line SD 1 . The drain and the source of the transistor M 73 are respectively coupled to the scan line S 3 and the control line SC 3 , and the gate thereof is coupled to the gate signal line SD 1 . In the display area 720, the scan lines S 4 , S 5 , and S 6 are coupled to the control lines SC 1 , SC 2 , and SC 3 via the transistors M 74 , M 75 , and M 76 , respectively, and the remaining display areas (not shown) The circuit structure in the case is analogous and will not be described again.
在驅動的過程中，由於控制線SC1~SC3會經由對應的電晶體耦接至個別顯示區域中的第一條至第三條掃描線，因此當顯示區域中的閘極信號線SD1與控制線SC1皆致能時，其對應的第一條掃描線便會開啟以便寫入對應的畫素電壓。同樣地，當顯示區域中的閘極信號線SD1與控制線SC2皆致能時，其對應的第二條掃描線便會開啟以便寫入對應的畫素電壓。然後，當顯示區域中的閘極信號線SD1與控制線SC3皆致能時，其對應的第三條掃描線便會開啟以便寫入對應的畫素電壓。其中，控制線SC1、SC2及SC3會依序致能，以致在同一顯示區域中，最多只有一條掃描線會被開啟。 During the driving process, since the control lines SC 1 to SC 3 are coupled to the first to third scanning lines in the individual display areas via the corresponding transistors, the gate signal line SD 1 in the display area is displayed. SC 1 and the control lines are enabled, the corresponding first scan line will open in order to write a voltage corresponding to the pixel. Similarly, when both the gate signal line SD 1 and the control line SC 2 in the display area are enabled, the corresponding second scanning line is turned on to write the corresponding pixel voltage. Then, when the display area of the gate signal line SD 1 and the control line when the SC 3 are enabled, the corresponding third scan lines will turn to write a voltage corresponding to the pixel. The control lines SC 1 , SC 2 , and SC 3 are sequentially enabled, so that at most one scan line is turned on in the same display area.
接下來，請參照圖7A及圖7B，圖7B為根據圖7A之閘極信號線與控制線的驅動波形圖。如圖7B所示，在顯示區域710中，控制線SC1會在閘極信號線SD1的致能期間T7的前1/3週期T71中致能，此時掃描線S1會被開啟以便寫入畫素資料(畫素電壓)至畫素列L1中。接著，控制線SC2會在閘極信號線SD1的致能期間T7的中間1/3週期T72中致能，此時掃描線S2會被開啟以便寫入畫素資料至畫素列L2中。最後，控制線SC3會在閘極信號線SD1的致 能期間T7的最後1/3週期T73中致能，此時掃描線S3會被開啟以便寫入畫素資料(畫素電壓)至畫素列L3中。也就是說，閘極信號線SD1的致能期間T7會被分為三個週期，分別用來更新畫素列L1~L3中的畫素資料。接著，在顯示區域720中，控制線SC1~SC3會在閘極信號線SD2的致能期間T7的中依序致能，以依序開啟掃描線S4~S6。接下來，其餘顯示區域中的掃描方式則參照上述說明類推，控制線SC1~SC3會與對應的掃描線相互配合以寫入畫素資料至所有畫素列。其中，致能期間T7為用以說明時間的長度，而非指特定時間區塊。 Next, please refer to FIG. 7A and FIG. 7B, which is a driving waveform diagram of the gate signal line and the control line according to FIG. 7A. 7B, in the display region 710, the SD control line SC 1 will be in the gate enabling signal line during the first 1/3 cycle of a T7-T71 are enabled, then the scan lines S 1 is turned on to Write the pixel data (pixel voltage) to the pixel column L 1 . Next, the control line SC 2 will be in the gate signal line SD during an enabling period of the T7-T72 in the third intermediate enabled, then the scan line S 2 is turned on in order to write the pixel data to the pixel rows L 2 in. Finally, the control line will be SC 3 SD signal in the gate enabling line 1 during the last third of the period T7 T73 enabled in this case the scan line S 3 is turned on to write the pixel data (pixel voltage) To the picture column L 3 . That is to say, the enable period T7 of the gate signal line SD 1 is divided into three periods for updating the pixel data in the pixel columns L 1 to L 3 , respectively. Next, in the display region 720, the control lines SC 1 to SC 3 are sequentially enabled in the enable period T7 of the gate signal line SD 2 to sequentially turn on the scan lines S 4 to S 6 . Next, the scanning manners in the remaining display areas are referred to the above description, and the control lines SC 1 to SC 3 cooperate with the corresponding scanning lines to write the pixel data to all the pixel columns. The enabling period T7 is a length for explaining the time, and does not refer to a specific time block.
經由上述驅動方式可以推知，液晶顯示面板700在驅動的過程中，閘極驅動器僅需提供掃描線數三分之一的閘極信號(僅需驅動個別顯示區域中的閘極信號線，閘極信號亦即習知之掃描信號)，而顯示區域中的掃描線則配合控制線SC1~SC3來個別驅動。再者，由於每一條掃描線的驅動方式相同，亦即同時依據閘極信號線及控制線致能時的致能電壓來驅動，因此可使每一個畫素列(如L1~L3)的饋通效應相同，其中控制線提供第一致能電壓，閘極信號線線提供第二致能電壓。 It can be inferred through the above driving manner that during the driving process of the liquid crystal display panel 700, the gate driver only needs to provide a gate signal of one third of the scanning line number (only need to drive the gate signal line in the individual display area, the gate The signal is also a conventional scanning signal), and the scanning lines in the display area are individually driven in conjunction with the control lines SC 1 to SC 3 . Furthermore, since each of the scanning lines is driven in the same manner, that is, simultaneously driven according to the enabling voltage of the gate signal line and the control line, each pixel column (eg, L 1 to L 3 ) can be used. The feedthrough effect is the same, wherein the control line provides a first enable voltage and the gate signal line provides a second enable voltage.
請同時參照圖4及圖7，由電路結構上比較可以得知，本實施例的每一顯示區域中所有掃描線所對應的畫素列(如L1~L3)，其饋通效應(feed through effect)皆會等同圖4實施例的畫素列L1，故每一畫素列的的饋通效應會如公式(4)所示。由於本實施例中的畫素列的饋通效應皆相 同，所以液晶顯示面板700中所有畫素單元的饋通電壓都會相同。 Referring to FIG. 4 and FIG. 7 simultaneously, it can be known from the circuit structure comparison that the pixel columns (such as L 1 ~ L 3 ) corresponding to all the scan lines in each display area of the embodiment have a feedthrough effect ( The feed through effect) is equivalent to the pixel column L 1 of the embodiment of FIG. 4, so the feedthrough effect of each pixel column is as shown in the formula (4). Since the feedthrough effects of the pixel columns in this embodiment are all the same, the feedthrough voltages of all the pixel units in the liquid crystal display panel 700 will be the same.
除此之外，顯示區域亦可延伸為Y條，以下再以此來作說明。圖8A為根據本發明第二實施例所述之液晶顯示面板之局部電路示意圖。請參照圖8A，在本實施例中，液晶顯示面板800包括N條掃描線(如S1~SY...SN，其中N為正整數)、多個顯示區域(如810及820)及Y條控制線(如SC1~SCY，其中Y為正整數)。並且，每一個顯示區域皆包括閘極信號線(如SD1、SD2...)、Y個電晶體(如M81~M8Y)及Y條掃描線(如S1~SY)，且每一顯示區域中所有的掃描線(如S1~SY)會分別經由對應的電晶體(如M81~M8Y)耦接至控制線SC1~SCY。以顯示區域810而言，其掃描線S1~SY會分別經由電晶體M81~M8Y耦接至控制線SC1~SCY。而圖8A中的其餘顯示區域的電路結構可由上述說明類推，且液晶顯示面板800上所有畫素列的饋通效應則參照圖7實施例所述，故不在此多作贅述。 In addition, the display area can also be extended to Y, which will be described below. FIG. 8A is a partial circuit diagram of a liquid crystal display panel according to a second embodiment of the present invention. Referring to FIG. 8A, in the embodiment, the liquid crystal display panel 800 includes N scan lines (such as S 1 ~S Y ... S N , where N is a positive integer), and multiple display areas (such as 810 and 820). And Y control lines (such as SC 1 ~ SC Y , where Y is a positive integer). Moreover, each display area includes a gate signal line (such as SD 1 , SD 2 ...), Y transistors (such as M 81 ~ M 8Y ), and Y scan lines (such as S 1 ~ S Y ), And all the scan lines (such as S 1 ~S Y ) in each display area are respectively coupled to the control lines SC 1 ~SC Y via corresponding transistors (such as M 81 ~ M 8Y ). In the display region 810, its scan line S 1 ~ S Y will be respectively connected via the transistor M 81 ~ M 8Y coupled to the control line SC 1 ~ SC Y. The circuit structure of the remaining display areas in FIG. 8A can be analogized by the above description, and the feedthrough effect of all the pixel columns on the liquid crystal display panel 800 is described with reference to the embodiment of FIG. 7, and therefore will not be further described herein.
在驅動方法上，本實施例則與上述實施例類似，同樣將顯示區域中閘極信號線(如顯示區域810中的閘極信號線SD1及顯示區域820中的閘極信號線SD2)的致能期間分為Y個週期，以分別開啟對應的Y條畫素列(如L1~LY)以寫入畫素資料。如圖8B所示，圖8B為根據圖8A之閘極信號線及控制線的驅動波形圖。在顯示區域810中，閘極信號線SD1的致能期間T8會被分為Y個週期T81~T8Y，然後控制線SC1~SCY會分別在週期T81~T8Y中依序致能， 致使畫素列L1~LY會依序開啟(亦即掃描線S1~SY依序致能)以便寫入畫素資料。接著，在顯示區域820中，閘極信號線SD2的致能期間T8同樣會被分為Y個週期T81~T8Y，然後控制線SC1~SCY一樣會分別在週期T81~T8Y中依序致能，以使掃描線SY+1~S2Y依序致能。而其餘顯示區域會在對應的閘極信號線致能時，才依序開啟顯示區域內的畫素列。其中，致能期間T8為用以說明時間的長度，而非指特定時間區塊。 In the driving method of this embodiment is the above-mentioned embodiment, the same display region in the gate signal lines (e.g., display area 810 the gate signal line SD 1 and the display area 820 of the gate signal line SD 2) The enabling period is divided into Y periods to respectively open the corresponding Y pixel columns (such as L 1 ~L Y ) to write pixel data. As shown in FIG. 8B, FIG. 8B is a driving waveform diagram of the gate signal line and the control line according to FIG. 8A. In the display region 810, during the enable gate signal line SD 1 will be divided into the Y T8 cycle T81 ~ T8Y, then control line SC 1 ~ SC Y 'respectively are sequentially enabled in cycle T81 ~ T8Y, resulting in The pixel columns L 1 ~L Y are sequentially turned on (that is, the scan lines S 1 -S Y are sequentially enabled) to write pixel data. Next, in the display area 820, the enable period T8 of the gate signal line SD 2 is also divided into Y periods T81 to T8Y, and then the control lines SC 1 to SC Y are sequentially in the periods T81 to T8Y, respectively. Enable to enable the scan lines S Y+1 ~S 2Y to be sequentially enabled. The remaining display areas will sequentially open the pixel columns in the display area when the corresponding gate signal lines are enabled. The enabling period T8 is used to describe the length of time, and does not refer to a specific time block.
藉此，本實施例可利用增加控制線的條數，來減少閘極驅動器提供的閘極信號，並且可透過對掃描線及控制線作最佳化的運算，以求得閘極信號線條數及控制線條數的最小總和，使液晶顯示面板可以用最少的信號源(包括閘極信號及控制線的信號)來驅動所有的掃描線。以具有N條掃描線液晶顯示面板為例，假設其控制線為Y條，此液晶顯示面板所需的信號總數(閘極驅動器的接腳總數)可等於下式：
在本實施例中，可利用一次微分求取信號總數的最小解，推演過程如下：
以640×480的液晶顯示面板來說，對640作開根號可求得25.3，可得到Y的最小值為25，則每一顯示區域的掃描線數則為25，所以此液晶顯示面板會分為25個完整的 顯示區域，並將剩下15條掃描線歸為1個顯示區域。至此，可以得到此液面板所需的最小信號總數為25+25+1=51。此外，可對掃描線總數取其因數，用以代表每一顯示區域的掃描線數，藉此以提升液晶顯示面板解析度。同樣以640×480的液晶顯示面板來說，以其掃描線總數的因數32為例，以此代表每一顯示區域的掃描線數，致使顯示區域數會為20，則信號總數為32+20=52。而此液晶顯示面板掃描線總數的其餘因數可由上述說明推演，故不再贅述。 For a 640×480 liquid crystal display panel, the opening number of 640 can be obtained as 25.3, and the minimum value of Y can be obtained as 25, and the number of scanning lines per display area is 25, so the liquid crystal display panel will Divided into 25 complete Display the area and divide the remaining 15 scan lines into one display area. At this point, the minimum number of signals required to obtain this liquid panel is 25+25+1=51. In addition, the total number of scan lines can be taken as a factor to represent the number of scan lines per display area, thereby improving the resolution of the liquid crystal display panel. Similarly, in the case of a 640×480 liquid crystal display panel, taking the factor 32 of the total number of scanning lines as an example, the number of scanning lines per display area is represented, so that the number of display areas is 20, and the total number of signals is 32+20. =52. The remaining factors of the total number of scanning lines of the liquid crystal display panel can be deduced from the above description, and therefore will not be described again.
此外，上述實施例中的電晶體的功能可利用邏輯運算單元來完成，下述依此再作說明。圖8C為根據本發明第二實施例所述之液晶顯示面板之局部電路示意圖。請參照圖8A及圖8C，其最大的不同之處在於及閘A81~A8Y(亦即邏輯運算單元)，並且參照圖8D來作說明。圖8D為圖8C的及閘A81的真值表示意圖。在此看到及閘A81，由真值表可以得知，當控制線SC1及閘極信號線SD1的驅動信號皆為”1”(亦即致能)時，及閘A81的輸出端(亦即掃描線S1)的電壓準位會為”1”(亦即致能，例如為輸出邏輯高電壓準位)，使得畫素列L1上所有的畫素皆會被開啟。而及閘A82~A8Y的運作方式會與及閘A81相同，故不再贅述。藉此，各顯示區域內的各畫素列同樣會依據閘極信號掃描線及控制線的驅動信號而依序開啟，以寫入對應的畫素資料。 Further, the function of the transistor in the above embodiment can be performed by a logic operation unit, which will be further described below. FIG. 8C is a partial circuit diagram of a liquid crystal display panel according to a second embodiment of the present invention. Referring to FIG. 8A and FIG. 8C, the biggest difference is the gates A 81 to A 8Y (that is, the logic operation unit), and will be described with reference to FIG. 8D. FIG. 8D is a schematic diagram of the truth table of the gate A 81 of FIG. 8C. Here, the gate A 81 is seen. It can be known from the truth table that when the drive signals of the control line SC 1 and the gate signal line SD 1 are both "1" (ie, enabled), the output of the gate A 81 is The voltage level of the terminal (ie, scan line S 1 ) will be "1" (ie, enabled, for example, output logic high voltage level), so that all pixels on pixel column L 1 will be turned on. The operation mode of the gate A 82 ~ A 8Y will be the same as that of the gate A 81 , so it will not be described again. Thereby, each pixel column in each display area is also sequentially turned on according to the driving signals of the gate signal scanning line and the control line to write corresponding pixel data.
此外，可由上述實施例彙整為一種液晶顯示面板的驅動方法。圖8E為根據本發明第二實施例所述之液晶顯示面板的驅動方法的流程圖。請參照圖8E，首先，在步驟 S801中，會輸出第二致能電壓至閘極信號線。接著，在步驟S802中，依序輸出第一致能電壓至這些控制線。最後，在步驟S803中，在這些控制線的其中之一接收到第一致能電壓時，則開啟對應此控制線的掃描線。並且，步驟S804會判斷是否為還有控制線未接收過第一致能電壓。若步驟S804判斷結果為「是」，亦即有控制線未接收過第一致能電壓，則會再執行步驟S802及S803，以開啟另一條掃描線。若步驟S804判斷結果為「否」，亦即所有控制線皆接收過第一致能電壓，則結束此驅動方法。由上述實施例的說明，可清楚了解本實施例的驅動方式。在顯示區域中，閘極信號線會接收來自閘極驅動器的閘極信號，以使掃描線配合閘極信號線及控制線的致能而依序開啟，以分別寫入畫素資料至對應的畫素單元。並且，藉由電路結構上的調整，可消除畫素單元間饋通電壓的差異。 Further, the above embodiment can be summarized as a driving method of a liquid crystal display panel. 8E is a flow chart of a driving method of a liquid crystal display panel according to a second embodiment of the present invention. Please refer to Figure 8E, first, at the step In S801, the second enable voltage is output to the gate signal line. Next, in step S802, the first enable voltage is sequentially outputted to the control lines. Finally, in step S803, when one of the control lines receives the first enable voltage, the scan line corresponding to the control line is turned on. Moreover, step S804 determines whether there is still a control line that has not received the first enable voltage. If the result of the determination in step S804 is YES, that is, if the control line has not received the first enable voltage, steps S802 and S803 are performed again to turn on another scan line. If the result of the determination in step S804 is "NO", that is, all the control lines have received the first enable voltage, the driving method is ended. The driving method of this embodiment can be clearly understood from the description of the above embodiment. In the display area, the gate signal line receives the gate signal from the gate driver, so that the scan line is sequentially turned on in conjunction with the enable of the gate signal line and the control line to respectively write the pixel data to the corresponding Pixel unit. Moreover, the difference in the feedthrough voltage between the pixel units can be eliminated by adjusting the circuit structure.
而不同的顯示區域中，其閘極信號線所接收閘極信號的來源及致能的時間會不一樣，並同時配合控制線的致能與否，使這些顯示區域中的畫素列能寫入對應的畫素資料。當所有的顯示區域中的畫素列都寫入對應的畫素資料後，此液晶顯示面板就能提供影像。藉此，可減少面板所需的閘極驅動器(接腳)數目，並可增加液晶顯示面板的顯示品質。 In different display areas, the source and enable time of the gate signal received by the gate signal line will be different, and at the same time, the enabling or not of the control line enables the pixel columns in these display areas to be written. Enter the corresponding pixel data. When all the pixel columns in the display area are written to the corresponding pixel data, the liquid crystal display panel can provide images. Thereby, the number of gate drivers (pins) required for the panel can be reduced, and the display quality of the liquid crystal display panel can be increased.
綜上所述，本發明實施例之液晶顯示面板，根據饋通效應的原理，分別利用以調整掃描信號及控制線的致能電壓，以及調整其驅動電路，來降低畫素列間的饋通電壓的 差異，藉以改善畫面品質不均的問題以及消除掃描信號間的電位變化對畫素電壓的影響。 In summary, the liquid crystal display panel of the embodiment of the present invention uses the principle of the feedthrough effect to adjust the enable voltage of the scan signal and the control line, and adjust the driving circuit thereof to reduce the feedthrough between the pixel columns. Voltage The difference is to improve the problem of uneven picture quality and to eliminate the influence of the potential change between the scanning signals on the pixel voltage.
雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作些許之更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。 Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.
100、400、500、600、700、800‧‧‧液晶顯示面板 100, 400, 500, 600, 700, 800‧‧‧ LCD panels
410、420、510、520、610、620、710、720、810、820‧‧‧顯示區域 410, 420, 510, 520, 610, 620, 710, 720, 810, 820‧‧‧ display area
L1、L2、L3、LX+1、LX、LY‧‧‧畫素列 L 1 , L 2 , L 3 , L X+1 , L X , L Y ‧‧‧ pixels
P11、P12、P21、P22、P31、P32、PX1、PX2、P(X+1)1、P(X+1)2、PY1、PY2‧‧‧畫素單元 P 11 , P 12 , P 21 , P 22 , P 31 , P 32 , P X1 , P X2 , P (X+1) 1 , P (X+1) 2 , P Y1 , P Y2 ‧ ‧ pixels unit
201、202‧‧‧下降緣 201, 202‧‧‧ falling edge
A61、A62、A6X、A81、A82、A8Y‧‧‧及閘 A 61 , A 62 , A 6X , A 81 , A 82 , A 8Y ‧ ‧ and gate
DL1、DL2‧‧‧資料線 DL 1 , DL 2 ‧‧‧ data line
S1~S6、SX、SX+1、SY、SY+1、SY+2、S2Y‧‧‧掃描線 S 1 ~S 6 , S X , S X+1 , S Y , S Y+1 , S Y+2 , S 2Y ‧‧‧ scan line
SC1、SC2、SC3、SCY、SCX‧‧‧控制線 SC 1 , SC 2 , SC 3 , SC Y , SC X ‧‧‧ control lines
SD1、SD2‧‧‧閘極信號線 SD 1 , SD 2 ‧‧ ‧ gate signal line
M111、M121、M1、M2、M41、M42、M51、M52、M53、M54、M61、M62、M6X、M71、M72、M73、M74、M75、M76、M81、M82、M8Y‧‧‧電晶體 M111, M121, M 1 , M 2 , M 41 , M 42 , M 51 , M 52 , M 53 , M 54 , M 61 , M 62 , M 6X , M 71 , M 72 , M 73 , M 74 , M 75 , M 76 , M 81 , M 82 , M 8Y ‧‧‧O crystal
T1、T2、T3、T4、T5、T6、T7、T8‧‧‧期間 During T1, T2, T3, T4, T5, T6, T7, T8‧‧
T41、T42、T51、T52、T53、T61、T62、T6(X+1)、T6X、T71、T72、T73、T81、T82、T8Y‧‧‧週期 T41, T42, T51, T52, T53, T61, T62, T6 (X+1), T6X, T71, T72, T73, T81, T82, T8Y‧‧ cycle
Clc1、Clc2‧‧‧液晶電容 Clc1, Clc2‧‧‧ liquid crystal capacitor
Cst1、Cst2‧‧‧儲存電容 Cst1, Cst2‧‧‧ storage capacitor
Cgs2‧‧‧電晶體M111的閘極-源極間的等效電容 Equivalent capacitance between the gate and source of Cgs2‧‧‧O crystal M111
Cgs1‧‧‧電晶體M121的閘極-源極間的等效電容 Equivalent capacitance between gate and source of Cgs1‧‧‧Optoelectronic M121
Cgsf‧‧‧電晶體M1的閘極-源極間的等效電容 Equivalent capacitance between the gate and source of Cgsf‧‧‧O crystal M 1
Vgh‧‧‧掃描信號及閘極信號的致能電壓值 Vgh‧‧‧Enable voltage value of scan signal and gate signal
Vgl‧‧‧掃描線及閘極信號線失能時的電壓值 Voltage value when Vgl‧‧ scan line and gate signal line are disabled
Vghs‧‧‧控制線的致能電壓值 Vghs‧‧‧ control line enable voltage value
Vgls‧‧‧控制線失能時的電壓值 Vgls‧‧‧ voltage value when the control line is disabled
S601~S604‧‧‧根據本發明第一實施例所述之液晶顯示面板的驅動方法的步驟 S601~S604‧‧‧ steps of the driving method of the liquid crystal display panel according to the first embodiment of the present invention
S801~S804‧‧‧根據本發明第二實施例所述之液晶顯示面板的驅動方法的步驟 S801~S804‧‧‧ steps of driving method of liquid crystal display panel according to second embodiment of the present invention
圖1即為根據習知技術之液晶顯示面板之局部電路示意圖。 FIG. 1 is a partial circuit diagram of a liquid crystal display panel according to the prior art.
圖2為根據圖1之掃描信號波形圖。 2 is a waveform diagram of a scan signal according to FIG. 1.
圖3為根據圖1之液晶顯示面板之局部等效電路圖。 3 is a partial equivalent circuit diagram of the liquid crystal display panel according to FIG. 1.
圖4A為根據本發明第一實施例所述之液晶顯示面板之局部電路示意圖。 4A is a partial circuit diagram of a liquid crystal display panel according to a first embodiment of the present invention.
圖4B為根據圖4A之掃描線與控制線的驅動波形圖。 4B is a driving waveform diagram of the scanning line and the control line according to FIG. 4A.
圖5A為根據本發明第一實施例所述之液晶顯示面板之局部電路示意圖。 FIG. 5A is a partial circuit diagram of a liquid crystal display panel according to a first embodiment of the present invention.
圖5B為根據圖5A之掃描線與控制線的驅動波形圖。 Fig. 5B is a driving waveform diagram of the scanning line and the control line according to Fig. 5A.
圖6A為根據本發明第一實施例所述之液晶顯示面板之局部電路示意圖。 FIG. 6A is a partial circuit diagram of a liquid crystal display panel according to a first embodiment of the present invention.
圖6B為根據圖6A之掃描線與控制線的驅動波形圖。 Fig. 6B is a driving waveform diagram of the scanning line and the control line according to Fig. 6A.
圖6C為根據本發明第一實施例所述之液晶顯示面板之局部電路示意圖。 FIG. 6C is a partial circuit diagram of a liquid crystal display panel according to a first embodiment of the present invention.
圖6D為圖6C的及閘A61的真值表示意圖。 FIG. 6D is a schematic diagram of the truth table of the gate A61 of FIG. 6C.
圖6E為根據本發明第一實施例所述之液晶顯示面板的驅動方法的流程圖。 6E is a flow chart of a driving method of a liquid crystal display panel according to a first embodiment of the present invention.
圖7A為根據本發明第二實施例所述之液晶顯示面板之局部電路示意圖。 FIG. 7A is a partial circuit diagram of a liquid crystal display panel according to a second embodiment of the present invention.
圖7B為根據圖7A之閘極信號線與控制線的驅動波形圖。 Fig. 7B is a driving waveform diagram of the gate signal line and the control line according to Fig. 7A.
圖8A為根據本發明第二實施例所述之液晶顯示面板之局部電路示意圖。 FIG. 8A is a partial circuit diagram of a liquid crystal display panel according to a second embodiment of the present invention.
圖8B為根據圖8A之閘極信號線與控制線的驅動波形圖。 Fig. 8B is a driving waveform diagram of the gate signal line and the control line according to Fig. 8A.
圖8C為根據本發明第二實施例所述之液晶顯示面板之局部電路示意圖。 FIG. 8C is a partial circuit diagram of a liquid crystal display panel according to a second embodiment of the present invention.
圖8D為圖8C的及閘A81的真值表示意圖。 FIG. 8D is a schematic diagram of the truth table of the gate A81 of FIG. 8C.
圖8E為根據本發明第二實施例所述之液晶顯示面板的驅動方法的流程圖。 8E is a flow chart of a driving method of a liquid crystal display panel according to a second embodiment of the present invention.
600‧‧‧液晶顯示面板 600‧‧‧LCD panel
610、620‧‧‧顯示區域 610, 620‧‧‧ display area
L1、L2、LX、LX+1‧‧‧畫素列 L 1 , L 2 , L X , L X+1 ‧‧‧ pixels
P11、P12、P21、P22、PX1、PX2、P(X+1)1、P(X+1)2‧‧‧畫素單元 P 11 , P 12 , P 21 , P 22 , P X1 , P X2 , P (X+1)1 , P (X+1) 2 ‧‧‧ pixel elements
DL1、DL2‧‧‧資料線 DL 1 , DL 2 ‧‧‧ data line
S1、S2、SX、SX+1‧‧‧掃描線 S 1 , S 2 , S X , S X+1 ‧‧‧ scan lines
SC1、SC2、SCX‧‧‧控制線 SC 1 , SC 2 , SC X ‧‧‧ control lines
M61、M62、M6X‧‧‧電晶體 M 61 , M 62 , M 6X ‧‧‧O crystal
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| US5365284A (en) * | 1989-02-10 | 1994-11-15 | Sharp Kabushiki Kaisha | Liquid crystal display device and driving method thereof |
| EP0911795A2 (en) * | 1997-10-23 | 1999-04-28 | Canon Kabushiki Kaisha | Liquid crystal display panel driving device and method |
| EP0949605A1 (en) * | 1998-04-10 | 1999-10-13 | Masaya Okita | High-speed driving method of a liquid crystal display panel |
| US7528815B2 (en) * | 2003-02-24 | 2009-05-05 | Hannstar Display Corporation | Driving circuit and method for liquid crystal display panel |
| TW200942933A (en) * | 2008-04-09 | 2009-10-16 | Chi Mei Optoelectronics Corp | Liquid crystal display apparatus, liquid crystal display panel and thin film transistor substrate |
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| US5365284A (en) * | 1989-02-10 | 1994-11-15 | Sharp Kabushiki Kaisha | Liquid crystal display device and driving method thereof |
| EP0911795A2 (en) * | 1997-10-23 | 1999-04-28 | Canon Kabushiki Kaisha | Liquid crystal display panel driving device and method |
| EP0949605A1 (en) * | 1998-04-10 | 1999-10-13 | Masaya Okita | High-speed driving method of a liquid crystal display panel |
| US7528815B2 (en) * | 2003-02-24 | 2009-05-05 | Hannstar Display Corporation | Driving circuit and method for liquid crystal display panel |
| TW200942933A (en) * | 2008-04-09 | 2009-10-16 | Chi Mei Optoelectronics Corp | Liquid crystal display apparatus, liquid crystal display panel and thin film transistor substrate |
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