TWI442849B - Circuit board having a circuit pattern and method of manufacturing the same - Google Patents
Circuit board having a circuit pattern and method of manufacturing the same Download PDFInfo
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- TWI442849B TWI442849B TW101122461A TW101122461A TWI442849B TW I442849 B TWI442849 B TW I442849B TW 101122461 A TW101122461 A TW 101122461A TW 101122461 A TW101122461 A TW 101122461A TW I442849 B TWI442849 B TW I442849B
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本發明是有關一種具有一電路圖案的電路基板及其製造方法，特別是提供一種具有一形成在一基材的一凹槽中之電路圖案的電路基板。The present invention relates to a circuit board having a circuit pattern and a method of fabricating the same, and more particularly to a circuit board having a circuit pattern formed in a recess of a substrate.
傳統上，在一絕緣基材上形成一具有一電路圖案的電路基板的方法可藉由在該絕緣基材中嵌入成型(insert molding)該電路圖案，或藉由以該絕緣基材積層化(laminating)該電路圖案。然而，前述的傳統方法會不良地增加電路基板的厚度。此外，所述傳統方法在電路圖案的修改或製造設備的改變及調整之製程步驟上是費時的。Conventionally, a method of forming a circuit substrate having a circuit pattern on an insulating substrate can be performed by insert molding the circuit pattern in the insulating substrate or by laminating the insulating substrate ( Laminating) the circuit pattern. However, the aforementioned conventional method may undesirably increase the thickness of the circuit substrate. Moreover, the conventional method is time consuming in the process of modifying the circuit pattern or changing and adjusting the manufacturing equipment.
美國專利4,865,873號揭示一種在一基材上製造具有一電路圖案的電路基板的方法，該方法包含在一基材上形成一絕緣層，在該絕緣層上形成一水溶性層，藉由雷射剝蝕(laser ablation)形成一延伸穿透該水溶性層及該絕緣層的圖案化孔，在該圖案化孔中及該水溶性層上形成一活性金屬層，並在該活性金屬層上無電沉積(electroless depositing)一基礎金屬層及同時在一水性電鍍液中溶解該水溶性層。由於該活性金屬層覆蓋了該圖案化孔壁與該水溶性層，該基礎金屬層的無電鍍覆(electroless plating)不只發生在該孔壁，亦不良地發生在該水溶性層的表面。雖然在無電鍍覆的過程中，該水溶性層會逐漸溶解於該水性電鍍液中，但此會對於無電鍍覆造成不利的影響。此外，如此形成的電路基板的厚度會大幅度地增加。No. 4,865,873 discloses a method of fabricating a circuit substrate having a circuit pattern on a substrate, the method comprising forming an insulating layer on a substrate, forming a water soluble layer on the insulating layer, by using a laser Laser ablation forms a patterned hole extending through the water soluble layer and the insulating layer, forming an active metal layer in the patterned hole and the water soluble layer, and electroless deposition on the active metal layer (electroless depositing) a base metal layer and simultaneously dissolving the water soluble layer in an aqueous plating solution. Since the active metal layer covers the patterned pore wall and the water-soluble layer, the electroless plating of the base metal layer not only occurs on the pore wall but also adversely occurs on the surface of the water-soluble layer. Although the water-soluble layer gradually dissolves in the aqueous plating solution during the electroless plating process, this may adversely affect the electroless plating. Further, the thickness of the circuit substrate thus formed is greatly increased.
因此，本發明之目的即在提供一種可以克服上述習知技術缺點的電路基板。Accordingly, it is an object of the present invention to provide a circuit substrate that overcomes the above-discussed shortcomings of the prior art.
於是，本發明提供一種電路基板，包含：一絕緣基材，包括一頂面，且自該頂面凹陷形成有一凹槽的圖案，該凹槽是藉由一凹槽定義壁所定義，該凹槽定義壁具有一底壁面及一自該底壁面向上延伸的圍繞壁面；一圖案化金屬層結構，包括至少一設置於該凹槽內的圖案化活性金屬層，該圖案化活性金屬層是形成在該凹槽定義壁的底壁面上，且與該凹槽定義壁的圍繞壁面間隔分離，該圖案化活性金屬層含有一能引發無電鍍覆的活性金屬，該圖案化活性金屬層的圖案在形狀上與該凹槽的圖案相對應；及一鍍覆在該圖案化金屬層結構上的基礎金屬層。Therefore, the present invention provides a circuit substrate comprising: an insulating substrate comprising a top surface, and a pattern of recesses formed by recessing the top surface, the recess being defined by a recess defining wall, the recess The groove defining wall has a bottom wall surface and a surrounding wall surface extending upward from the bottom wall; a patterned metal layer structure including at least one patterned active metal layer disposed in the groove, the patterned active metal layer is formed Separating from the bottom wall of the groove defining wall and spaced apart from the surrounding wall of the groove defining wall, the patterned active metal layer contains an active metal capable of inducing electroless plating, and the patterned active metal layer is patterned Correspondingly corresponding to the pattern of the groove; and a base metal layer plated on the patterned metal layer structure.
本發明之另一目的即在提供一種具有一電路圖案的電路基板的製造方法。該方法包含：(a)提供一具有一頂面的絕緣基材；(b)在該絕緣基材中形成一凹槽的圖案，以致該凹槽是凹陷自該頂面，該凹槽是藉由一具有一底壁面及一自該底壁面向上延伸之圍繞壁面的凹槽定義壁所定義；(c)在該凹槽的凹槽定義壁及該絕緣基材的頂面上形成一金屬層結構，該金屬層結構包括至少一含有一能引發無電鍍覆的活性金屬的活性金屬層；(d)將該金屬層結構中沿著該凹槽定義壁的底壁面之外周緣設置的部分移除，以使該金屬層結構形成一設置在該底壁面上的第一區及一與該第一區物理分離的第二區；及(e)在該金屬層結構的第一區上鍍覆一基礎金屬層。Another object of the present invention is to provide a method of manufacturing a circuit board having a circuit pattern. The method comprises: (a) providing an insulating substrate having a top surface; (b) forming a pattern of grooves in the insulating substrate such that the recess is recessed from the top surface, the recess is borrowed Defined by a groove defining wall having a bottom wall surface and a surrounding wall surface extending upward from the bottom wall; (c) forming a metal layer on the groove defining wall of the groove and the top surface of the insulating substrate a structure, the metal layer structure comprising at least one active metal layer containing an active metal capable of initiating electroless plating; (d) moving a portion of the metal layer structure disposed along a periphery of a bottom wall surface of the wall defining the groove In addition, the metal layer structure is formed into a first region disposed on the bottom wall surface and a second region physically separated from the first region; and (e) plating on the first region of the metal layer structure A base metal layer.
本發明將就以下實施例作進一步說明，但應瞭解的是，該等實施例僅為例示說明之用，而不應被解釋為本發明實施之限制。The invention is further described in the following examples, but it should be understood that these examples are for illustrative purposes only and are not to be construed as limiting.
圖8及圖9說明本發明第一較佳實施例之電路基板100。該電路基板100包含：一絕緣基材2，包括一頂面21，且自該頂面21凹陷形成有一凹槽20的一圖案，該凹槽20是藉由一凹槽定義壁20’所定義，該凹槽定義壁20’具有一底壁面201及一自該底壁面201向上延伸的圍繞壁面202；一圖案化金屬層結構5，包括至少一設置於該凹槽20內的圖案化活性金屬層3，該圖案化活性金屬層3是形成在該凹槽定義壁20’的底壁面201上，且與該凹槽定義壁20’的圍繞壁面202藉由一間隙203間隔分離，該圖案化活性金屬層3含有一能引發無電鍍覆的經還原的活性金屬，該圖案化活性金屬層3的圖案在形狀上與該凹槽20的圖案相對應；及一鍍覆在該圖案化金屬層結構5上的基礎金屬層4。該圖案化金屬層結構5與該基礎金屬層4共同形成一在形狀上與該凹槽20的圖案相對應的電路圖案10。較佳地，該電路圖案10具有一頂面101，該頂面101是大體上齊平於或略高地設置於該絕緣基材2的頂面21。8 and 9 illustrate a circuit substrate 100 according to a first preferred embodiment of the present invention. The circuit substrate 100 includes an insulating substrate 2 including a top surface 21, and a pattern of recesses 20 formed by recessing the top surface 21, the recess 20 being defined by a recess defining wall 20' The groove defining wall 20 ′ has a bottom wall surface 201 and a surrounding wall surface 202 extending upward from the bottom wall surface 201 ; a patterned metal layer structure 5 including at least one patterned active metal disposed in the groove 20 Layer 3, the patterned active metal layer 3 is formed on the bottom wall surface 201 of the groove defining wall 20', and is spaced apart from the surrounding wall surface 202 of the groove defining wall 20' by a gap 203, the patterning The active metal layer 3 comprises a reduced active metal capable of initiating electroless plating, the pattern of the patterned active metal layer 3 corresponding in shape to the pattern of the recess 20; and a plating on the patterned metal layer The base metal layer 4 on the structure 5. The patterned metal layer structure 5 and the base metal layer 4 together form a circuit pattern 10 that corresponds in shape to the pattern of the groove 20. Preferably, the circuit pattern 10 has a top surface 101 that is substantially flush or slightly disposed on the top surface 21 of the insulating substrate 2.
圖1至圖9說明本發明第一較佳實施例之電路基板100的製造方法的連續步驟。該方法包含以下步驟：(a)提供一具有一頂面21的絕緣基材2(參見圖1)；(b)在該絕緣基材2中形成一凹槽20的一圖案，以致該凹槽20是凹陷自該頂面21(參見圖2及圖3)，該凹槽20是藉由一具有一底壁面 201及一自該底壁面201向上延伸之圍繞壁面202的凹槽定義壁20’所定義；(c)在該凹槽20的凹槽定義壁20’及該絕緣基材2的頂面21上形成一金屬層結構5’，該金屬層結構5’包括至少一含有一能引發無電鍍覆的經還原的或非經還原的活性金屬的活性金屬層3’(參見圖4及圖5)；(d)將該金屬層結構5’的一沿著該凹槽定義壁20’的底壁面201之外周緣設置的閉環部分移除，以使該金屬層結構5’形成一設置在該底壁面201上的第一區51及一與該第一區51藉由一間隙203物理分離的第二區52(參見圖6)，該金屬層結構5’的第一區51定義出圖9中的圖案化金屬層結構5，該金屬層結構5’的第一區51的活性金屬層3’定義出圖9中的圖案化活性金屬層3；(e)在該金屬層結構5’的第一區51上鍍覆一基礎金屬層4(參見圖7)；及(f)藉由電解將該金屬層結構5’的第二區52自該絕緣基材2移除(參見圖8及圖9)。1 to 9 illustrate successive steps of a method of manufacturing the circuit substrate 100 of the first preferred embodiment of the present invention. The method comprises the steps of: (a) providing an insulating substrate 2 having a top surface 21 (see FIG. 1); (b) forming a pattern of a recess 20 in the insulating substrate 2 such that the recess 20 is recessed from the top surface 21 (see FIGS. 2 and 3), the groove 20 is formed by having a bottom wall surface 201 and a groove defining wall 20' extending from the bottom wall 201 upwardly surrounding the wall surface 202; (c) on the groove defining wall 20' of the groove 20 and the top surface 21 of the insulating substrate 2 Forming a metal layer structure 5' comprising at least one active metal layer 3' containing a reduced or non-reduced active metal capable of initiating electroless plating (see Figures 4 and 5); (d) removing a closed-loop portion of the metal layer structure 5' disposed along the outer periphery of the bottom wall surface 201 of the groove defining wall 20' such that the metal layer structure 5' is formed on the bottom wall surface a first region 51 on the 201 and a second region 52 (see FIG. 6) physically separated from the first region 51 by a gap 203, the first region 51 of the metal layer structure 5' defining the Patterning the metal layer structure 5, the active metal layer 3' of the first region 51 of the metal layer structure 5' defines the patterned active metal layer 3 in Fig. 9; (e) the first in the metal layer structure 5' A base metal layer 4 is plated on the region 51 (see FIG. 7); and (f) the second region 52 of the metal layer structure 5' is removed from the insulating substrate 2 by electrolysis (see FIG. 8). FIG. 9).
在本實施例中，該金屬層結構5’是藉由在該步驟(c)中將該絕緣基材2浸入一活性金屬溶液中所形成(圖未示)，以在該凹槽20的凹槽定義壁20’及該絕緣基材2的頂面21上形成一含有非經還原的活性金屬的非經還原的活性金屬層(可為活性金屬膠體粒子或離子)，並接續還原該非經還原的活性金屬層的非經還原的活性金屬，以在該凹槽20的凹槽定義壁20’及該絕緣基材2的頂面21上形成該含有經還原的活性金屬的活性金屬層3’，該金屬層結構5’是形成在該凹槽20的凹槽定義壁20’及該絕緣基材2的頂面21上。該基礎金屬層4是藉由電鍍而形成在該金屬層結構5’的第一區51上。In this embodiment, the metal layer structure 5' is formed by immersing the insulating substrate 2 in an active metal solution in the step (c) (not shown) to recess the groove 20. Forming a non-reduced active metal layer (which may be an active metal colloidal particle or an ion) containing a non-reduced active metal on the groove defining wall 20' and the top surface 21 of the insulating substrate 2, and subsequently reducing the non-reduced The non-reduced active metal of the active metal layer forms the active metal layer 3' containing the reduced active metal on the groove defining wall 20' of the groove 20 and the top surface 21 of the insulating substrate 2. The metal layer structure 5' is formed on the groove defining wall 20' of the groove 20 and the top surface 21 of the insulating substrate 2. The base metal layer 4 is formed on the first region 51 of the metal layer structure 5' by electroplating.
較佳地，該經還原的或非經還原的活性金屬是選自於由下列所構成之群組：鈀、銠、鉑、銥、鋨、金、鎳、鐵及其組合。Preferably, the reduced or non-reduced active metal is selected from the group consisting of palladium, rhodium, platinum, rhodium, iridium, gold, nickel, iron, and combinations thereof.
較佳地，該活性金屬溶液是鈀鹽溶液或鈀-錫膠體溶液。Preferably, the active metal solution is a palladium salt solution or a palladium-tin colloidal solution.
較佳地，該基礎金屬層4是以一選自於下列所構成之群組：銅、鎳、銀及金的金屬所製成。Preferably, the base metal layer 4 is made of a metal selected from the group consisting of copper, nickel, silver, and gold.
較佳地，該絕緣基材2是以一選自於下列所構成之群組：聚碳酸酯(polycarbonate)、丙烯酸樹脂(acryl resin)與丙烯腈-丁二烯-苯乙烯樹脂(ABS resin)之一組合及聚碳酸酯與丙烯腈-丁二烯-苯乙烯樹脂之一組合的材料所製成。Preferably, the insulating substrate 2 is a group selected from the group consisting of polycarbonate, acryl resin and acrylonitrile-butadiene-styrene resin (ABS resin). One combination and a polycarbonate are combined with a material of one of acrylonitrile-butadiene-styrene resins.
較佳地，該絕緣基材2中的凹槽20是藉由雷射或電漿剝蝕(ablation)所形成。Preferably, the recess 20 in the insulating substrate 2 is formed by laser or plasma ablation.
較佳地，該金屬層結構5’的閉環部分是藉由雷射剝蝕所移除。Preferably, the closed loop portion of the metal layer structure 5' is removed by laser ablation.
圖14說明本發明第二較佳實施例之電路基板100。該第二較佳實施例與先前的實施例不同處在於該圖案化活性金屬層3含有該非經還原的活性金屬，該圖案化金屬層結構5還包括一無電鍍覆在該圖案化活性金屬層3上且具有一與該圖案化活性金屬層3相對應之圖案的中間金屬層6，且該基礎金屬層4是被電鍍在該中間金屬層6上。該圖案化金屬層結構5與該基礎金屬層4共同形成該電路圖案10。Figure 14 illustrates a circuit substrate 100 in accordance with a second preferred embodiment of the present invention. The second preferred embodiment is different from the previous embodiment in that the patterned active metal layer 3 contains the non-reduced active metal, and the patterned metal layer structure 5 further comprises an electroless plating layer on the patterned active metal layer. The intermediate metal layer 6 has a pattern corresponding to the patterned active metal layer 3, and the base metal layer 4 is plated on the intermediate metal layer 6. The patterned metal layer structure 5 and the base metal layer 4 together form the circuit pattern 10.
圖10至圖14說明本發明第二較佳實施例之電路基板100的製造方法的連續步驟。該方法包含以下步驟：在該絕 緣基材2中形成一凹槽20的一圖案(參見圖10)；在該凹槽20的凹槽定義壁20’及該絕緣基材2的頂面21上形成一金屬層結構5’，該金屬層結構5’是藉由將該絕緣基材2浸入一活性金屬溶液中所形成(圖未示)，以在該凹槽20的凹槽定義壁20’及該絕緣基材2的頂面21上形成一含有非經還原的活性金屬的非經還原的活性金屬層3’(參見圖10)，並接續在該非經還原的活性金屬層3’上無電鍍覆一中間金屬層6(參見圖11)；將該金屬層結構5’的一沿著該凹槽定義壁20’的底壁面201之外周緣設置的部分移除，以使該金屬層結構5’形成一設置在該底壁面201上的第一區51及一與該第一區51藉由一間隙203物理分離的第二區52(參見圖12)，該金屬層結構5’的第一區51定義出圖14中的圖案化金屬層結構5，該金屬層結構5’的第一區51的非經還原的活性金屬層3’定義出圖14中的圖案化活性金屬層3；在該金屬層結構5’的第一區51的中間金屬層6上電鍍一基礎金屬層4(參見圖13)；及藉由電解將該金屬層結構5’的第二區52自該絕緣基材2移除(參見圖14)。10 to 14 illustrate successive steps of a method of manufacturing the circuit substrate 100 of the second preferred embodiment of the present invention. The method includes the following steps: Forming a groove 20 in the edge substrate 2 (see FIG. 10); forming a metal layer structure 5' on the groove defining wall 20' of the groove 20 and the top surface 21 of the insulating substrate 2, The metal layer structure 5' is formed by immersing the insulating substrate 2 in an active metal solution (not shown) to define a wall 20' and a top of the insulating substrate 2 in the groove of the groove 20. A non-reduced active metal layer 3' containing a non-reduced active metal is formed on the surface 21 (see FIG. 10), and an intermediate metal layer 6 is electrolessly plated on the non-reduced active metal layer 3' ( Referring to FIG. 11), a portion of the metal layer structure 5' disposed along the outer periphery of the bottom wall surface 201 of the groove defining wall 20' is removed, so that the metal layer structure 5' is formed at the bottom. a first region 51 on the wall 201 and a second region 52 (see FIG. 12) physically separated from the first region 51 by a gap 203, the first region 51 of the metal layer structure 5' is defined in FIG. a patterned metal layer structure 5, the non-reduced active metal layer 3' of the first region 51 of the metal layer structure 5' defines the patterned active metal in FIG. 3; plating a base metal layer 4 on the intermediate metal layer 6 of the first region 51 of the metal layer structure 5' (see FIG. 13); and electrolyzing the second region 52 of the metal layer structure 5' from the The insulating substrate 2 is removed (see Figure 14).
圖19說明本發明第三較佳實施例之電路基板100。該第三較佳實施例與該第一較佳實施例不同處在於該圖案化活性金屬層3含有該非經還原的活性金屬，該基礎金屬層4是被無電鍍覆在該圖案化活性金屬層3上，且在該基礎金屬層4上形成一頂部金屬層7。雖然該第三較佳實施例的製法與該第二較佳實施例不同，但當該第三較佳實施例的基礎金屬層4與頂部金屬層7各自等同於該第二較佳實施例的中間金屬層6與基礎金屬層4時，該第三較佳實施例與 該第二較佳實施例在結構上近似。Figure 19 illustrates a circuit substrate 100 in accordance with a third preferred embodiment of the present invention. The third preferred embodiment is different from the first preferred embodiment in that the patterned active metal layer 3 contains the non-reduced active metal, and the base metal layer 4 is electrolessly plated on the patterned active metal layer. 3, and a top metal layer 7 is formed on the base metal layer 4. Although the manufacturing method of the third preferred embodiment is different from the second preferred embodiment, when the base metal layer 4 and the top metal layer 7 of the third preferred embodiment are respectively equivalent to the second preferred embodiment The third preferred embodiment and the intermediate metal layer 6 and the base metal layer 4 This second preferred embodiment is structurally approximate.
圖15至圖19說明本發明第三較佳實施例之電路基板100的經修改的製造方法的連續步驟。該方法包含以下步驟：在該絕緣基材2中形成一凹槽20的一圖案(參見圖15)；在該凹槽20的凹槽定義壁20’及該絕緣基材2的頂面21上形成一金屬層結構5’，該金屬層結構5’是藉由將該絕緣基材2浸入一活性金屬溶液中所形成(圖未示)，以在該凹槽20的凹槽定義壁20’及該絕緣基材2的頂面21上形成一含有非經還原的活性金屬的非經還原的活性金屬層3’(參見圖15)；將該金屬層結構5’的一沿著該凹槽定義壁20’的底壁面201之外周緣設置的部分移除，以使該金屬層結構5’形成一設置在該底壁面201上的第一區51及一與該第一區51藉由一間隙203物理分離的第二區52(參見圖16)，該金屬層結構5’的第一區51定義出圖19中的圖案化金屬層結構5，該金屬層結構5’的第一區51的非經還原的活性金屬層3’定義出圖19中的圖案化活性金屬層3；在該金屬層結構5’的第一區51的活性金屬層3’上無電鍍覆一基礎金屬層4(參見圖17)；該基礎金屬層4上電鍍一頂部金屬層7(參見圖18)；及藉由電解將該金屬層結構5’的第二區52自該絕緣基材2移除(參見圖19)。15 to 19 illustrate successive steps of a modified manufacturing method of the circuit substrate 100 of the third preferred embodiment of the present invention. The method comprises the steps of: forming a pattern of grooves 20 in the insulating substrate 2 (see FIG. 15); defining a wall 20' of the groove 20 and a top surface 21 of the insulating substrate 2 Forming a metal layer structure 5' formed by immersing the insulating substrate 2 in an active metal solution (not shown) to define a wall 20' in the groove of the groove 20. And a non-reduced active metal layer 3' containing a non-reduced active metal is formed on the top surface 21 of the insulating substrate 2 (see FIG. 15); one of the metal layer structures 5' is along the groove The portion of the outer wall surface 201 defining the wall 20' is provided with a portion removed so that the metal layer structure 5' forms a first region 51 disposed on the bottom wall surface 201 and a first region 51 is separated from the first region 51. The gap 203 is physically separated by a second region 52 (see FIG. 16), the first region 51 of the metal layer structure 5' defining the patterned metal layer structure 5 of FIG. 19, the first region 51 of the metal layer structure 5' The non-reduced active metal layer 3' defines the patterned active metal layer 3 in FIG. 19; the active metal in the first region 51 of the metal layer structure 5' a base metal layer 4 (see FIG. 17) is electrolessly plated on the layer 3'; the top metal layer 7 is plated on the base metal layer 4 (see FIG. 18); and the second metal layer structure 5' is electrolyzed by electrolysis. The region 52 is removed from the insulating substrate 2 (see Figure 19).
綜上所述，由於本發明是藉由在該絕緣基材2中形成一凹槽20，及在該凹槽20中形成一包括至少一活性金屬層3’的金屬層結構5’(該活性金屬層3’是藉由使該絕緣基材2與一活性金屬溶液接觸而形成)，並隨後將該金屬層結構5’的一部分自該絕緣基材2移除，因而可以減輕上述習知技 術所遭遇的缺點。In summary, the present invention is formed by forming a recess 20 in the insulating substrate 2, and forming a metal layer structure 5' including at least one active metal layer 3' in the recess 20. The metal layer 3' is formed by bringing the insulating substrate 2 into contact with an active metal solution, and then a part of the metal layer structure 5' is removed from the insulating substrate 2, thereby mitigating the above-mentioned conventional technique. The shortcomings encountered by the surgery.
惟以上所述者，僅為本發明之較佳實施例與具體例而已，當不能以此限定本發明實施之範圍，即大凡依本發明申請專利範圍及發明說明內容所作之簡單的等效變化與修飾，皆仍屬本發明專利涵蓋之範圍內。The above is only the preferred embodiment and the specific examples of the present invention, and the scope of the invention is not limited thereto, that is, the simple equivalent change according to the scope of the invention and the description of the invention. And modifications are still within the scope of the invention patent.
10‧‧‧電路圖案10‧‧‧ circuit pattern
100‧‧‧電路基板100‧‧‧ circuit board
101‧‧‧頂面101‧‧‧ top surface
2‧‧‧絕緣基材2‧‧‧Insulating substrate
20‧‧‧凹槽20‧‧‧ Groove
20’‧‧‧凹槽定義壁20'‧‧‧ Groove definition wall
201‧‧‧底壁面201‧‧‧ bottom wall
202‧‧‧圍繞壁面202‧‧‧ Around the wall
203‧‧‧間隙203‧‧‧ gap
21‧‧‧頂面21‧‧‧ top surface
3‧‧‧圖案化活性金屬層3‧‧‧ patterned active metal layer
3’‧‧‧活性金屬層3'‧‧‧Active metal layer
4‧‧‧基礎金屬層4‧‧‧Basic metal layer
5‧‧‧圖案化金屬層結構5‧‧‧ patterned metal layer structure
5’‧‧‧金屬層結構5'‧‧‧Metal layer structure
51‧‧‧第一區51‧‧‧First District
52‧‧‧第二區52‧‧‧Second District
6‧‧‧中間金屬層6‧‧‧Intermediate metal layer
7‧‧‧頂部金屬層7‧‧‧Top metal layer
圖1是一立體透視圖，說明本發明一種製造第一較佳實施例的電路基板的方法的第一步驟；圖2是一立體透視圖，說明該製造第一較佳實施例的方法的第二步驟；圖3是一沿著圖2的剖切線Ⅲ-Ⅲ的剖視圖；圖4是一立體透視圖，說明該製造第一較佳實施例的方法的第三步驟；圖5是一沿著圖4的剖切線V-V的剖視圖；圖6是一剖視圖，說明該製造第一較佳實施例的方法的第四步驟；圖7是一剖視圖，說明該製造第一較佳實施例的方法的第五步驟；圖8是一立體透視圖，說明該製造第一較佳實施例的方法的第六步驟；圖9是一沿著圖8的剖切線Ⅸ-Ⅸ的剖視圖；圖10是一剖視圖，說明本發明一種製造第二較佳實施例的電路基板的方法的第一步驟；圖11是一剖視圖，說明該製造第二較佳實施例的方法的第二步驟； 圖12是一剖視圖，說明該製造第二較佳實施例的方法的第三步驟；圖13是一剖視圖，說明該製造第二較佳實施例的方法的第四步驟；圖14是一剖視圖，說明該製造第二較佳實施例的方法的第五步驟；圖15是一剖視圖，說明本發明一種製造第三較佳實施例的電路基板的方法的第一步驟；圖16是一剖視圖，說明該製造第三較佳實施例的方法的第二步驟；圖17是一剖視圖，說明該製造第三較佳實施例的方法的第三步驟；圖18是一剖視圖，說明該製造第三較佳實施例的方法的第四步驟；及圖19是一剖視圖，說明該製造第三較佳實施例的方法的第五步驟。1 is a perspective perspective view showing a first step of a method of manufacturing a circuit substrate of a first preferred embodiment of the present invention; and FIG. 2 is a perspective perspective view showing the method of manufacturing the first preferred embodiment. 2 is a cross-sectional view along the line III-III of FIG. 2; FIG. 4 is a perspective view showing the third step of the method of manufacturing the first preferred embodiment; FIG. Figure 4 is a cross-sectional view showing a fourth step of the method of manufacturing the first preferred embodiment; Figure 7 is a cross-sectional view showing the method of manufacturing the first preferred embodiment Figure 5 is a perspective view showing a sixth step of the method of manufacturing the first preferred embodiment; Figure 9 is a cross-sectional view taken along line IX-IX of Figure 8; and Figure 10 is a cross-sectional view. The first step of the method for manufacturing the circuit substrate of the second preferred embodiment of the present invention; and FIG. 11 is a cross-sectional view showing the second step of the method for manufacturing the second preferred embodiment; Figure 12 is a cross-sectional view showing the third step of the method of manufacturing the second preferred embodiment; Figure 13 is a cross-sectional view showing the fourth step of the method of manufacturing the second preferred embodiment; Figure 14 is a cross-sectional view, The fifth step of the method for manufacturing the second preferred embodiment is illustrated. FIG. 15 is a cross-sectional view showing the first step of the method for manufacturing the circuit substrate of the third preferred embodiment of the present invention; FIG. 16 is a cross-sectional view illustrating The second step of the method of manufacturing the third preferred embodiment; FIG. 17 is a cross-sectional view showing the third step of the method of manufacturing the third preferred embodiment; FIG. 18 is a cross-sectional view showing the third preferred embodiment. The fourth step of the method of the embodiment; and Figure 19 is a cross-sectional view illustrating the fifth step of the method of manufacturing the third preferred embodiment.
10‧‧‧電路圖案10‧‧‧ circuit pattern
100‧‧‧電路基板100‧‧‧ circuit board
2‧‧‧絕緣基材2‧‧‧Insulating substrate
20‧‧‧凹槽20‧‧‧ Groove
20’‧‧‧凹槽定義壁20'‧‧‧ Groove definition wall
21‧‧‧頂面21‧‧‧ top surface
4‧‧‧基礎金屬4‧‧‧Basic Metals
Claims (18)
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| TW101122461A TWI442849B (en) | 2012-06-22 | 2012-06-22 | Circuit board having a circuit pattern and method of manufacturing the same |
| US14/933,616 US9474161B2 (en) | 2010-03-12 | 2015-11-05 | Circuit substrate having a circuit pattern and method for making the same |
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| TW101122461A TWI442849B (en) | 2012-06-22 | 2012-06-22 | Circuit board having a circuit pattern and method of manufacturing the same |
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| TW201401947A TW201401947A (en) | 2014-01-01 |
| TWI442849B true TWI442849B (en) | 2014-06-21 |
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| TW (1) | TWI442849B (en) |
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