TWI441336B - 帶有減小的擊穿電壓的金屬氧化物半導體場效應管裝置 - Google Patents

帶有減小的擊穿電壓的金屬氧化物半導體場效應管裝置 Download PDF

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TWI441336B
TWI441336B TW098142726A TW98142726A TWI441336B TW I441336 B TWI441336 B TW I441336B TW 098142726 A TW098142726 A TW 098142726A TW 98142726 A TW98142726 A TW 98142726A TW I441336 B TWI441336 B TW I441336B
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epitaxial
layer
contact
semiconductor device
channel
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TW098142726A
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TW201025609A (en
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Ji Pan
Anup Bhalla
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Alpha & Omega Semiconductor
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Description

帶有減小的擊穿電壓的金屬氧化物半導體場效應管裝置
本發明涉及一種半導體裝置,特別涉及一種帶有減小的擊穿電壓的金屬氧化物半導體場效應管裝置。
當今的半導體裝置,例如金屬氧化物半導體場效應管,一般都是特徵尺寸很小的高密度裝置。比如,現在使用的某些金屬氧化物半導體場效應管的壁-壁尺寸約為1到2微米。隨著裝置尺寸的減小,裝置內閘極氧化物的厚度也隨之減小,並且在使用過程中更易受到損壞。這種問題在經常傳導大電流、消耗大功率的功率金屬氧化物半導體場效應管裝置中將變得更加顯著。
本發明的目的在於提供一種半導體裝置,通過一個沉積在裝置的接觸溝道下面的磊晶層增強部分,減小了金屬氧化物半導體場效應管裝置的擊穿電壓。
為了達到上述目的,本發明的技術方案是提供一種半導體裝置,其特徵在於,包含一個汲極、一個覆蓋在汲極上的磊晶層、一個主動區;上述主動區包含:一個沉積在磊晶層中的主體、一個嵌入主體內的源極、一個延伸進磊晶層的閘極溝道、一個沉積在閘極溝道中的閘極、 一個沿源極和至少一部分主體延伸的接觸溝道、一個沉積在接觸溝道中的接觸電極、一個沉積在接觸溝道下面的外延增強部分;上述外延增強部分的載子類型與磊晶層的一致。
上述外延增強部分用於降低由接觸電極和汲極形成的肖特基二極體的擊穿電壓。
上述外延增強部分的載子濃度比磊晶層的載子濃度要高。
上述主動區還包括一個沉積在接觸溝道側壁上的主體接觸植入物。
上述主動區還包括一個沉積在接觸溝道側壁上的主體接觸植入物,上述主體接觸植入物的載子類型與磊晶層相反。
上述主動區還包括一個沉積在接觸溝道側壁上的主體接觸植入物和一個沿接觸溝道底部沉積的二極體增強層,而且在上述二極體增強層下面沉積外延增強部分。
上述主動區還包括沉積在接觸溝道下面和外延增強部分上面的香農植入物,上述香農植入物的載子類型與磊晶層的相反。
上述半導體裝置的壁-壁間距尺寸小於或等於1.4微米。
上述磊晶層和外延增強部分為N型。
上述磊晶層和外延增強部分為P型。
一種半導體裝置的製作方法,其特徵在於,包含以下步驟:在磊晶層中製造一個閘極溝道,覆蓋在半導體基底上;在閘極溝道內沉積閘極材料;在磊晶層中製造一個主體;製造一個源極嵌入主體;製造一個沿源極和至少一部分主體延伸的接觸溝道;在接觸溝道下面沉積一個外延增強部分,其中外延增強部分的載子類型與磊晶層的一致;在接觸溝道中沉積一個接觸電極。
上述外延增強部分用於降低由接觸電極和汲極形成的肖特基二極體的擊穿電壓。
上述外延增強部分的載子濃度要高於磊晶層的載子濃度。
上述一種半導體裝置的製作方法,還包括在接觸溝道的側壁 上沉積一個主體接觸植入物。
上述一種半導體裝置的製作方法,還包括在接觸溝道的側壁上沉積一個主體接觸植入物,上述主體接觸植入物的載子類型與磊晶層的相反。
上述一種半導體裝置的製作方法,還包括在接觸溝道的側壁上沉積一個主體接觸植入物,並沿接觸溝道底部形成一個二極體增強層;上述外延增強部分沉積在二極體增強層之下。
上述一種半導體裝置的製作方法,還包括在接觸溝道下面和外延增強部分上面沉積香農植入物,上述香農植入物的載子類型與磊晶層相反。
上述半導體裝置的壁-壁間距尺寸小於或等於1.4微米。
上述主體的製作包括製作一個光阻主體塊,並通過光阻主體塊在未遮罩區內植入主體。
上述主體的製作包括製作一個主體層,並進行接觸蝕刻。
本發明所述的帶有減小的擊穿電壓的金屬氧化物半導體場效應管裝置,與現有技術相比,其優點在於:本發明通過一個沉積在裝置的接觸溝道下面的磊晶層增強部分,減小了金屬氧化物半導體場效應管裝置的擊穿電壓。
100‧‧‧裝置
103‧‧‧N+型半導體基底
104‧‧‧N-型半導體的磊晶層
111、113、115、117‧‧‧閘極溝道
121‧‧‧閘極氧化層
131、133、135‧‧‧閘極
150a~150d‧‧‧源極區域
140a~140d‧‧‧主體區
160、160a~160c‧‧‧絕緣材料層
112a、112b‧‧‧絕緣區接觸溝道
172a、172b‧‧‧金屬層
180a、180b‧‧‧製備電極
182a、182b‧‧‧磊晶層增強部分
185a、185b‧‧‧P--材料
300‧‧‧N型基底
302‧‧‧SiO2
304‧‧‧感光層
310‧‧‧SiO2硬遮罩
330‧‧‧犧牲層SiO2
332‧‧‧SiO2
340‧‧‧沉積聚乙烯
342‧‧‧閘極
344‧‧‧閘極的頂面
346‧‧‧矽的頂面
348‧‧‧SiO2的頂面
350、372、472‧‧‧光阻層
360a~360d、477a、477b‧‧‧主體區域
364‧‧‧源極遮罩
365、465‧‧‧介電(例如含有硼磷的矽玻璃)層
368、370、468、470‧‧‧溝道
371a、371b‧‧‧源極區域
373、473‧‧‧植入物
374‧‧‧二極體增強層
376、476‧‧‧磊晶層
390、490‧‧‧裝置
378、478‧‧‧金屬層
380、480‧‧‧沉積鈍化層
466‧‧‧源極摻雜物
464‧‧‧源極阻塊
第1A圖至第1B圖是本發明所述帶有減小的擊穿電壓的雙擴散金屬氧化物半導體裝置實施例的橫截面示意圖;第2圖是本發明製作一個雙擴散金屬氧化物半導體裝置的實施例流程圖;第3A圖至第3S圖是本發明所述金屬氧化物半導體場效應管裝置的一 種製作過程橫截面示意圖;第4K圖至第4S圖是本發明所述金屬氧化物半導體場效應管裝置的另一種製作過程橫截面示意圖。
本發明具有多種應用形式,包括用於加工過程、裝置、系統、合成物質、嵌入電腦可讀存儲介質中的電腦程式產品,以及/或處理器,例如執行存儲指令和/或由耦合到處理器上的記憶體配置的處理器。本說明書中,這些實施例,或本發明的其他任意應用形式,都可能會作為技術內容所提及。一般而言,所述的加工過程的順序可能有所不同,但仍屬本發明的範圍。除非另加說明,用作其他用途的處理器或記憶體等元件,可以製作成通用元件,用於特定時間的臨時加工任務或用作其他用途的特殊元件。此處提到的名詞“處理器”涉及一種或多種裝置、電路與/或處理核,用於處理電腦程式指令等資料。
以下將詳細介紹本發明的一個或多個實施例,以及用於解釋說明的附圖。文中提出了本發明有關的多個實施例,但本發明並不局限於任一實施例。本發明的範圍僅由權利要求書和本發明涵蓋的各種變化、修改和等效的內容所決定。為了對本發明進行完整說明,以下還將詳細介紹多個具體示例。這些示例僅用作舉例說明,依據權利要求書,無需這些具體示例中的任何一個或全部示例,本發明仍可實施。
本發明提出了一種帶有減小的擊穿電壓的半導體裝置。在一些實例中,裝置包括一個沉積在裝置的接觸溝道下面的磊晶層增強部分,以便減小裝置的擊穿電壓。這個磊晶層增強部分具有和磊晶層相同的載子類型。可選擇包括體接觸植入物或香農植入物。
第1A圖表示帶有減小的擊穿電壓的雙擴散金屬氧化物半導體裝置的一個實施例的橫截面視圖,該裝置100包括一個在N+型半導體基底103背面的汲極。汲極區域延伸進入N-型半導體的磊晶層104,與基底103 重疊。在磊晶層104中蝕刻出111、113、115等閘極溝道。在閘極溝道內形成閘極氧化層121。閘極131、133和135分別沉積在閘極溝道111、113和115中,並通過氧化層與磊晶層隔絕。閘極由多晶矽等導電材料構成,氧化層由熱氧化物等絕緣材料構成。更確切地說,閘極溝道111位於終止區,並帶有閘極引線131用於連接閘極的接觸金屬。正因如此,閘極溝道111可以比有源閘極溝道113和115更寬、更深。另外,閘極溝道111與它旁邊的有源溝道113之間的距離,要比有源閘極溝道113和115之間的距離大。
源極區域150a到150d被分別埋入主體區140a到140d內。源極區域從主體上表面一直向下延伸到主體內。當主體區沿所有的閘極溝道的邊緣植入時,源極區域僅僅在有源閘極溝道的鄰近位置植入,而不是閘極溝道的附近。在所給出的實施例中,閘極,比如133,具有一個閘極頂面,這個頂面超出了帶有源極嵌入的主體頂面。這種結構保證了閘極和源極重疊,使得源極區域比具有凹陷閘極裝置的源極區域淺,增加了裝置效率和性能。閘極多晶矽頂面延伸至源極-主體接面上方的量,對於不同的實施例,可能有所不同。在某些實施例中,裝置的閘極並沒有延伸至源極-主體區域的頂面上方。
在製備過程中,汲極區域和主體區域都是一個二極體,稱為體二極體。絕緣材料層160沉積在閘極上,使得閘極與源極-主體接觸區絕緣。絕緣材料在閘極的頂部以及主體和源極區域的頂部,形成了類似於160a到160c的絕緣區。熱氧化物、低溫氧化物(LTO)、硼磷矽玻璃(BPSG)等都可作為這種絕緣材料。
在源極附近的有源閘極溝道和主體區域之間,形成了多個接觸溝道112a到112b。由於這些溝道鄰近裝置源極和主體區形成的主動區,因此它們也被稱為主動區接觸溝道。例如,接觸溝道112a延伸穿過源極和主體,在溝道附近形成了源極區域150a到150b和主體區域140a到140b。與之相反,在閘極引線131頂部形成的溝道117,並不鄰近主動區,因此它就不是主動區接觸溝道。又因為連接閘極信號的金屬層172a沉積在溝道117內,因此溝道117被稱為閘極接觸溝道或閘極引線接觸溝道。通過溝道111、113和115之間的三維互聯(圖中沒有給出),閘極信號被送往有源閘極 133和135。金屬層172a與金屬層172b分離,172b通過接觸溝道112a到112b將源極和主體區域連接起來,作為功率源極。在本例中,主動區接觸溝道和閘極接觸溝道的深度大致相同。
在本例中,主體內的和沿主動區接觸溝道壁的區域,如170a到170d,都是重摻雜P型材料,形成P+型區域,也就是主體接觸植入物。之所以引入主體接觸植入物是為了保證在主體和源極金屬之間形成歐姆接觸,使得源極和主體之間的電勢一致。
將導電材料沉積在接觸溝道112a到112b和閘極接觸溝道117中,以便形成接觸電極。在主動區,接觸電極和汲極區域形成與主體二極體並聯的肖特基二極體。肖特基二極體降低了主體二極體的正向電壓降,並使累計電荷最少,這就使得金屬氧化物半導體二極體的效率更高。用於製備電極180a到180b的單一金屬礦石,可以形成N-汲極的肖特基接觸、同時對P+主體和N+源極有良好的歐姆接觸。可以使用金屬鈦(Ti)、鉑(Pt)、鈀(Pd)、鎢(W)等或其他合適的金屬。在某些實施例中,使用金屬鋁(Al)或Ti/TiN/Al堆疊來製備金屬層172。
傳統的功率金屬氧化物半導體場效應管裝置中,在接觸電極和汲極之間形成的肖特基二極體的擊穿電壓一般與體二極體的擊穿電壓一樣高。在擊穿之前,在裝置的閘極底部附近會形成一個很大的電場,對閘極氧化層造成損害。在裝置100中,通過在接觸溝道112a和112b下面,植入物和磊晶層具有相同載子類型的摻雜劑,降低了裝置的擊穿電壓。產生的磊晶層增強部分(也稱為擊穿電壓降低植入物)182a和182b具有與磊晶層相同的載子類型,但濃度更高。在本例中,磊晶層的載子類型為N型(也就是說,電子為多數載子,電洞為少數載子),磊晶層增強部分也為N型。在磊晶層載子類型為P型(也就是說,電子為少數載子,電洞為多數載子)的實施例中,磊晶層增強部分也為P型。磊晶層增強植入物降低了在接觸電極和汲極之間形成的肖特基二極體的擊穿電壓。由於肖特基二極體和體二極體並聯,並且肖特基二極體的擊穿電壓更低,因此裝置的總擊穿電壓將降低。如果建立起了大電場,肖特基二極體首先被擊穿,通過傳導電流消耗電荷,這就阻止了電場對閘極氧化層造成損害。下文將詳細討論磊晶 層增強植入物的形成。磊晶層增強植入物的厚度和濃度由所需的擊穿電壓決定,磊晶層增強植入物的厚度越大、濃度越濃,相應的擊穿電壓會越低。本例中,包含磊晶層增強部分後,裝置的擊穿電壓從38V降至22V。
第1B圖表示帶有減小的擊穿電壓的雙極金屬氧化物半導體裝置實施例的橫截面視圖,該裝置102與裝置100,除了P-材料185a和185b的薄層分別在接觸溝道112a和112b下面直接形成之外,其他方面均類似。在接觸溝道112a和112b的底面下方的體/汲極接面處形成低注入二極體,並不形成肖特基二極體。P--材料的上述薄層提高了低注入二極體的正向電壓降(Vfd),降低了漏電流,因此也稱為二極體增強層。下文將詳細介紹,在某些實施例中,二極體增強層的處理過程與體接觸植入的處理過程相同。二極體增強層的摻雜濃度遠低於體接觸植入區170a到170d的摻雜濃度,因此當反向偏置時,二極體增強層完全耗盡,空乏層相當高,使得當正向偏置時,二極體增強層沒有耗盡。二極體增強層的厚度由所需的低注入二極體正向電壓的變化量決定,層的厚度越大,正向電壓降越大。
與裝置100類似,裝置102也植入了具有和磊晶層一樣的載子類型的摻雜物。它所產生的磊晶層增強部分(也就是擊穿電壓降低植入物)182a和182b形成於二極體增強層185a和185b下麵,其載子類型也與磊晶層相同,但濃度更高,以減小低注入二極體的擊穿電壓,這就阻止了電場對閘極氧化層造成損害。
上述實施例是將N型基底(即在晶片上生成一層帶有N-磊晶層的N+矽片)作為裝置的汲極。在某些實施例中使用的是P型基底,並且裝置帶有N型體接觸植入物與P型磊晶層增強層。
第2圖表示製備一種雙極金屬氧化物半導體裝置的處理過程實施例的流程圖。在步驟202,在磊晶層中形成與半導體基底重疊的閘極溝道。在步驟204,將閘極材料沉積在閘極溝道中。在步驟206,形成主體。在步驟208,形成源極。在步驟210,形成接觸溝道。在步驟212,形成體接觸植入物。在步驟214,形成磊晶層增強層。在步驟216,在接觸溝道內沉積接觸電極。製程200及其步驟只要稍作修改,就能用於製備上述的100和102等不同的金屬氧化物半導體裝置。
第3A圖至第3S圖為裝置的橫截面示圖,說明用於製備金屬氧化物半導體場效應管裝置的一種製作過程。第3A圖至第3J圖表示閘極的形成。
在第3A圖中,在N型基底300上,通過沉積或熱氧化,形成了一個SiO2層302。根據不同的實施例中,二氧化矽層的厚度在100Å到30000Å之間變化。也可以使用其他的厚度值,這取決於閘極所需的高度。在氧化層上面旋塗一個感光層304,並用溝道遮罩形成圖案。
在第3B圖中,除去曝光區中的SiO2,剩餘的SiO2硬遮罩310用於矽蝕刻。第3C圖中,異向蝕刻矽。閘極材料沉積在溝道中。然後在溝道內形成的閘極,閘極的邊緣垂直於基底頂面。第3D圖中,適量回蝕SiO2硬遮罩310,蝕刻後,使溝道壁與硬遮罩的邊緣對齊。本實施例中,使用SiO2作為遮罩材料,是因為用SiO2硬遮罩蝕刻之後的溝道壁比較直,溝道壁與遮罩的邊緣相互對齊。也可以選用其他合適的材料。通常使用的Si3N4等其他類型的材料用於硬遮罩蝕刻,必定會使蝕刻後的溝道壁產生彎曲,這對於接下來形成閘極不利。
第3E圖中,異向蝕刻基底,使溝道的底部變得圓滑。在一些實施例中,溝道深約0.5到2.5μm、寬約0.2到1.5μm,也可選用其他尺寸。為了使表面平滑,便於生成閘極介電材料,要在溝道中生成一個犧牲層SiO2330。然後通過濕法蝕刻除去該層。第3G圖中,SiO2層332作為介電材料,在溝道中熱生成。
第3H圖中,沉積聚乙烯340填滿溝道。在這種情況下,通過摻雜聚乙烯,獲得合適的閘極阻抗。在一些實施例中,在(原位)沉積聚合物層時,開始摻雜。在另一些實施例中,沉積完聚合物後,開始摻雜聚乙烯。如第3I圖,回蝕SiO2頂部的聚乙烯層,形成類似於342的閘極。在這一點上,閘極的頂面344相對於SiO2的頂面348來說仍然是凹陷的;但是閘極的頂面344可能比矽的頂面346要高,這取決於硬遮罩層310的厚度。在一些實施例中,聚合物回蝕中並沒有使用遮罩。另一些實施例中,是在聚合物回蝕中使用遮罩,以便在接下來的主體植入過程中不再使用額外的遮罩。如第3J圖,除去SiO2硬遮罩。在一些實施例中,使用幹法蝕刻 除去硬遮罩。遇到矽的頂面時,停止蝕刻,使聚合物閘極在基底表面上延伸,源極和體摻雜物將被植入基底中。在另一些實施例中,閘極在基底表面上方延伸大概300Å到20000Å之間,也可以選用其他值。由於SiO2硬遮罩以一種可控的方式,提供所需的在矽表面上的閘極延伸量,因此在這些實施例中都使用SiO2硬遮罩。然後遮罩氧化層在晶片上生成。可以通過簡化上述製備過程,製造帶有減小的閘極聚合物的裝置。例如在一些實施例中,可使用光阻劑掩模或非常薄的SiO2硬遮罩製備溝道,於是生成的閘極聚合物並不在矽表面上延伸。
第3K圖至第3N圖表示源極和主體的形成。如第3K圖所示,光阻層350通過主體遮罩蝕刻在主體表面。由於光阻模組摻雜物從遮罩區中被植入,因此帶圖案的光阻層也稱為主體模組。未遮罩的區域同主體摻雜物一起植入。植入的摻雜物包括硼離子等。如第3L圖所示,除去光阻層,加熱晶片,以使植入的主體摻雜物熱擴散,這個過程有時也叫做主體驅動。形成主體區域360a到360d。在一些實施例中,用於植入主體摻雜物的能量約為30到600KeV,劑量約為每平方釐米2×1012到4×1013個離子,最終生成的主體厚度約為0.3到2.4微米。可以通過改變植入能量、劑量以及擴散溫度等參數,獲得不同的主體厚度。在擴散過程中,形成了氧化層362。
如第3M圖所示,使用源極遮罩在光阻層364上形成圖案。所給的實施例中,源極遮罩364並不阻塞有源溝道之間的任何區域。在一些實施例中,源極遮罩364阻塞了有源溝道之間的中心區域(圖中沒有給出)。未遮罩的區域366同源極摻雜物一起植入。在本例中,砷離子滲入矽中的未遮罩區,形成N+型源極。在另一些實施例中,用於植入源極摻雜物的能量約為10到100KeV,劑量約為每平方釐米1×1015到1×1016個離子,最終生成的主體厚度約為0.05到0.5微米。可以通過改變摻雜能量和劑量等參數進一步減薄厚度。也可以選用其他合適的植入工藝。如第3N圖所示,除去光阻層,加熱晶片,通過源極驅動過程,使植入的源極摻雜物熱擴散。源極驅動後,在裝置的頂面上沉積一層介電(例如含有硼磷的矽玻璃)層365,在某些實施例中還可以選擇性地增加介電層的密度。
第3O圖至第3T圖表示接觸溝道和各種植入物的形成。如第3O圖所示,光阻層372沉積在介電層上,使用接觸遮罩形成圖案。第一接觸蝕刻用於形成溝道368和370。由於溝道370穿過源極植入物,並形成獨立的源極區域371a和371b,因此溝道的深度至少部分取決於源極植入物的厚度。在一些實施例中,第一接觸溝道的深度約為0.2到2.5微米。
如第3P圖所示,除去光阻層,用植入離子轟擊溝道底部附近的區域,形成主體接觸植入物373。一些實施例中,植入了大約每平方釐米1到5×1015個離子的硼離子。相應的植入能量約為10到60keV。在另一些實施例中,使用大約每平方釐米1到5×1015個離子、植入能量40到100keV的BF2離子。還有一些實施例中,植入BF2和硼,形成主體接觸植入物。植入傾角約在0到45°之間。然後將植入物進行熱擴散。
如第3Q圖所示,進行第二接觸蝕刻。由於蝕刻過程並不影響介電層,第二接觸蝕刻也就不需要額外的遮罩。第二蝕刻的深度取決於溝道底部主體接觸植入物需要除去的量,這個量又進而取決於正向電壓降的增加量以及相應的漏電流的減少量。在一些實施例中(如第1A圖所示的裝置100),溝道底部所有的主體接觸植入物都被除去,僅剩餘側壁上的植入物。在另一些實施例中(如第1B圖所示的裝置102和第3Q圖所示的裝置),僅除去溝道底部的一部分主體接觸植入物,剩餘二極體增強層374。二極體增強層越厚,導致肖特基正向電壓降越大,漏電流卻越小。在某些實施例中,接觸溝道的深度增大了約0.2到0.5微米。
在一些實施例中,進行第二接觸蝕刻時,接觸溝道底面上所有的主體接觸植入物都被除去。可以選擇性地植入載子類型和磊晶層相反的摻雜物,在接觸溝道的底部區域,形成肖特基阻礙控制層(也被認為是香農植入)。香農植入屬於淺顯、小劑量的植入,因此無論是否偏置,都完全耗盡。香農植入用於控制肖特基阻礙高度,因此能夠更好地控制漏電流,並增強肖特基二極體的反向恢復特性。因此,沉積香農植入的步驟是可選的,圖表中並沒有給出。
如第3R圖所示,植入一個磊晶層376。本例中,使用N型摻雜物。在載子濃度為每立方釐米2×1016個離子的N型磊晶層的實施例中, 植入能量約為40keV、摻雜等級約為每平方釐米8×1012個離子的磷離子。在1050℃下熱擴散植入層30秒。生成的磊晶層厚度大約0.15到0.4微米,濃度約為每立方釐米5×1016到3×1017個離子。可以通過改變植入能量、劑量以及擴散溫度等參數獲得不同的厚度。外延增強層越厚或者其濃度越大,二極體擊穿電壓降低得越多。
也可選擇省去第二次接觸蝕刻。在一些實施例中,按照步驟3P進行接觸植入後,外延增強植入可通過使用不同能量和計量組合的植入物形成。只要接觸溝道側壁內的主體接觸植入物仍然不受影響,那麼接觸溝道底部的主體接觸植入物就可以完全補償肖特基二極體的形成,或部分補償低注入二極體的形成,留下一個薄二極體增強層。在一個實施例中,首先植入200keV的磷離子植入濃度每平方釐米6×1012個離子,隨後第二次植入100keV的磷離子植入濃度每平方釐米2×1012個離子,以補償一部分主體接觸植入物,並形成外延增強層。
如第3S圖,展示了一個完整的裝置390。金屬層378沉積、在適當的地方蝕刻,然後退火。沉積鈍化層380後,製作鈍化開口。還將進行晶片研磨、背墊金屬沉積等製作過程。
第4K圖至第4S圖為裝置的橫截面視圖,詳細介紹了另一種製造一個金屬氧化物半導體場效應管裝置的生產過程。此過程也經常用於製造小壁-壁間距尺寸的裝置。本例中,第3A圖到第3J圖所示的步驟已經用於形成閘極。如第4K圖所示,由於光阻主體塊的間距尺寸(pitch)很小,因此如第3K圖中的350很難形成,第4K圖到第4R圖所示的製作工藝中沒有使用光阻主體塊。
第4K圖中,植入一個沒有光阻主體塊的主體摻雜層。本例中裝置的壁-壁間距尺寸(pitch)在1.4微米的數量級上,甚至更小。如第4L圖,熱擴散主體摻雜物。如第4M圖所示,一層光阻劑形成源極阻塊464。植入一層源極摻雜物466。如第4N圖所示,除去光阻劑,並熱擴散源極摻雜物。源極驅動後,在裝置的頂面上沉積一個介電(例如含有硼磷的矽玻璃)層465,在某些實施例中,在某些實施例中還可以選擇性地增加介電層的密度。
第4O圖至第4S圖表示接觸溝道和各種植入物的形成。如第4O圖所示,在介電層上沉積一個光阻層472,並通過接觸遮罩形成圖案。通過第一次接觸蝕刻形成溝道468和470。蝕刻穿透源極層,形成獨立的源極區域。主體層的大部分也被除去。如第4P圖所示,除去光阻層,用植入離子轟擊溝道底部附近的側壁,以便形成主體接觸植入物473。在一些實施例中,植入的是劑量約為每平方釐米1到5×1015個離子的硼離子,植入能量約為10到60keV。在某些實施例中,也可使用劑量約為每平方釐米1到5×1015個離子、植入能量約為40到100keV的BF2離子。在另一些實施例中,BF2和硼都植入,以便形成主體接觸植入物。植入傾角約為0到45°。然後將植入物進行熱擴散。
如第4Q圖所示,進行第二次接觸蝕刻。根據二極體正向電壓降和漏電流的變化情況,除去溝道底部部分或全部的主體接觸植入物。如第4R圖所示,植入外延增強層476,並進行熱擴散。對於載子濃度為每立方釐米2×1016個離子的N型磊晶層的實施例,需植入能量約為40keV、劑量等級約為每平方釐米8×1012個離子的磷離子。在1050℃下熱擴散植入層30秒。生成的外延增強層厚度約為0.15到0.4微米,濃度約為每立方釐米5×1016到3×1017個離子。可以通過改變植入能量、劑量以及擴散溫度等參數獲得不同的厚度。選擇合適的溝道深度和外延增強植入物,以使主體區域477a和477b在主體區域底部分離。
也可以選擇省去第二次接觸蝕刻。在一些實施例中,按照步驟4P進行接觸植入後,外延增強植入可通過使用不同能量和計量組合的植入物形成。只要接觸溝道側壁內的主體接觸植入物仍然不受影響,那麼接觸溝道底部的主體接觸植入物就可以完全補償肖特基二極體的形成,或部分補償低注入二極體的形成,留下一個薄二極體增強層。在一個實施例中,首先植入200keV的磷離子植入濃度每平方釐米6×1012個離子,隨後第二次植入100keV的磷離子植入濃度每平方釐米2×1012個離子,以補償一部分主體接觸植入物,並形成外延增強層。
如第4S圖所示,展示了一個完整的裝置490。金屬層478沉積、在適當的地方蝕刻,然後退火。沉積鈍化層480後,製作鈍化開口。 還將進行晶片研磨、背墊金屬沉積等製作過程。
為了便於理解,上述實施例詳細闡述了各項細節,但並不能將本發明的範圍局限於此。本發明還有很多不同的實現方法。上述的實施例僅用作解釋說明,並不具有限制性。
100‧‧‧裝置
103‧‧‧N+型半導體基底
104‧‧‧N-型半導體的磊晶層
111、113、115、117‧‧‧閘極溝道
121‧‧‧閘極氧化層
131、133、135‧‧‧閘極
150a~150d‧‧‧源極區域
140a~140d‧‧‧主體區
160、160a~160c‧‧‧絕緣材料層
112a~112b‧‧‧絕緣區接觸溝道
172a、172b‧‧‧金屬層
180a~180b‧‧‧製備電極
182a、182b‧‧‧磊晶層增強部分

Claims (14)

  1. 一種半導體裝置,其特徵在於,包含一個汲極、一個覆蓋在汲極上的磊晶層、一個主動區;所述主動區包含:一個沉積在磊晶層中的主體、一個嵌入主體內的源極、一個延伸進磊晶層的閘極溝道、一個沉積在閘極溝道中的閘極、一個沿源極和至少一部分主體延伸的接觸溝道、一個沉積在接觸溝道中的接觸電極、一個沉積在接觸溝道下面的外延增強部分;所述外延增強部分的載子類型與磊晶層的一致;一個沉積在接觸溝道側壁上的主體接觸植入物;所述主體接觸植入物的載子類型與磊晶層相反;一個沿接觸溝道底部沉積的二極體增強層,而且在所述二極體增強層下面沉積所述外延增強部分。
  2. 如申請專利範圍第1項所述的半導體裝置,其中所述外延增強部分用於降低由接觸電極和汲極形成的肖特基二極體的擊穿電壓。
  3. 如申請專利範圍第1項所述的半導體裝置,其中所述外延增強部分的載子濃度比磊晶層的載子濃度要高。
  4. 如申請專利範圍第1項所述的半導體裝置,其中所述主動區還包括沉積在接觸溝道下面和外延增強部分上面的香農植入物,所述香農植入物的載子類型與磊晶層的相反。
  5. 如申請專利範圍第1項所述的半導體裝置,其中所述半導體裝置的壁-壁間距尺寸小於或等於1.4微米。
  6. 如申請專利範圍第1項所述的半導體裝置,其中所述磊晶層和外延增強部分為N型。
  7. 如申請專利範圍第1項所述的半導體裝置,其中所述磊晶層和外延增強部分為P型。
  8. 一種半導體裝置的製作方法,其特徵在於,包含以下步驟:在磊晶層中製造一個閘極溝道,覆蓋在半導體基底上;在閘極溝道內沉積閘極材料;在磊晶層中製造一個主體;製造一個源極嵌入主體;製造一個沿源極和至少一部分主體延伸的接觸溝道;在接觸溝道下面沉積一個外延增強部分,其中外延增強部分的載子類型與磊晶層的一致;還在接觸溝道的側壁上沉積一個主體接觸植入物,所述主體接觸植入物的載子類型與磊晶層相反;並沿接觸溝道底部形成一個二極體增強層;所述外延增強部分沉積在二極體增強層之下;在接觸溝道中沉積一個接觸電極。
  9. 如申請專利範圍第8項所述的半導體裝置的製作方法,其中所述外延增強部分用於降低由接觸電極和汲極形成的肖特基二極體的擊穿電壓。
  10. 如申請專利範圍第8項所述的半導體裝置的製作方法,其中,所述外延增強部分的載子濃度要高於磊晶層的載子濃度。
  11. 如申請專利範圍第8項所述的半導體裝置的製作方法,其中還包括在接觸溝道下面和外延增強部分上面沉積香農植入物,所述香農植入物的載子類型與磊晶層相反。
  12. 如申請專利範圍第8項所述的半導體裝置的製作方法,其中所述半導體裝置的壁-壁間距尺寸小於或等於1.4微米。
  13. 如申請專利範圍第8項所述的半導體裝置的製作方法,其中所述主體的製作包括製作一個光阻主體塊,並通過光阻主體塊在未遮罩區內植入主體。
  14. 如申請專利範圍第8項所述的半導體裝置的製作方法,其中所述主體的製作包括製作一個主體層,並進行接觸蝕刻。
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Families Citing this family (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8969950B2 (en) * 2008-12-23 2015-03-03 Alpha & Omega Semiconductor, Inc. Integrated MOSFET-Schottky diode device with reduced source and body Kelvin contact impedance and breakdown voltage
US8362552B2 (en) * 2008-12-23 2013-01-29 Alpha And Omega Semiconductor Incorporated MOSFET device with reduced breakdown voltage
JP5588670B2 (ja) 2008-12-25 2014-09-10 ローム株式会社 半導体装置
JP5588671B2 (ja) 2008-12-25 2014-09-10 ローム株式会社 半導体装置の製造方法
US8138605B2 (en) * 2009-10-26 2012-03-20 Alpha & Omega Semiconductor, Inc. Multiple layer barrier metal for device component formed in contact trench
US20110121387A1 (en) * 2009-11-23 2011-05-26 Francois Hebert Integrated guarded schottky diode compatible with trench-gate dmos, structure and method
JP2011134910A (ja) 2009-12-24 2011-07-07 Rohm Co Ltd SiC電界効果トランジスタ
US8492225B2 (en) * 2009-12-30 2013-07-23 Intersil Americas Inc. Integrated trench guarded schottky diode compatible with powerdie, structure and method
US20110156682A1 (en) * 2009-12-30 2011-06-30 Dev Alok Girdhar Voltage converter with integrated schottky device and systems including same
US20110156810A1 (en) * 2009-12-30 2011-06-30 Intersil Americas Inc. Integrated dmos and schottky
US8431470B2 (en) * 2011-04-04 2013-04-30 Alpha And Omega Semiconductor Incorporated Approach to integrate Schottky in MOSFET
US8502302B2 (en) 2011-05-02 2013-08-06 Alpha And Omega Semiconductor Incorporated Integrating Schottky diode into power MOSFET
US8507978B2 (en) 2011-06-16 2013-08-13 Alpha And Omega Semiconductor Incorporated Split-gate structure in trench-based silicon carbide power device
JP2013201268A (ja) * 2012-03-23 2013-10-03 Toshiba Corp 半導体装置
US8643071B2 (en) 2012-06-14 2014-02-04 Alpha And Omega Semiconductor Incorporated Integrated snubber in a single poly MOSFET
CN103839978B (zh) * 2012-11-23 2018-04-03 中国科学院微电子研究所 一种中高压沟槽型功率器件的终端结构及其制作方法
JP6297783B2 (ja) * 2013-03-08 2018-03-20 住友電気工業株式会社 炭化珪素半導体装置およびその製造方法
JP6763779B2 (ja) * 2014-11-18 2020-09-30 ローム株式会社 半導体装置および半導体装置の製造方法
KR101786668B1 (ko) * 2015-12-14 2017-10-18 현대자동차 주식회사 반도체 소자 및 그 제조 방법
JP6622611B2 (ja) * 2016-02-10 2019-12-18 ルネサスエレクトロニクス株式会社 半導体装置及びその製造方法
US10388781B2 (en) 2016-05-20 2019-08-20 Alpha And Omega Semiconductor Incorporated Device structure having inter-digitated back to back MOSFETs
US10103140B2 (en) 2016-10-14 2018-10-16 Alpha And Omega Semiconductor Incorporated Switch circuit with controllable phase node ringing
CN106328647B (zh) * 2016-11-01 2019-05-03 华羿微电子股份有限公司 高速的沟槽mos器件及其制造方法
CN110190135A (zh) * 2019-05-29 2019-08-30 西安电子科技大学芜湖研究院 一种浮结型肖特基二极管及其制备方法
US11145727B2 (en) * 2019-10-29 2021-10-12 Nanya Technology Corporation Semiconductor structure and method of forming the same
US11776994B2 (en) 2021-02-16 2023-10-03 Alpha And Omega Semiconductor International Lp SiC MOSFET with reduced channel length and high Vth
CN113410307B (zh) * 2021-04-16 2022-10-04 深圳真茂佳半导体有限公司 场效晶体管结构及其制造方法、芯片装置
CN113707545A (zh) * 2021-08-18 2021-11-26 深圳市美浦森半导体有限公司 一种改善mosfet雪崩特性的方法及其器件
CN114267739A (zh) * 2022-01-05 2022-04-01 北京昕感科技有限责任公司 一种双沟槽型SiC MOSFET元胞结构、器件及制造方法

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1558506A (en) * 1976-08-09 1980-01-03 Mullard Ltd Semiconductor devices having a rectifying metalto-semicondductor junction
US6110799A (en) * 1997-06-30 2000-08-29 Intersil Corporation Trench contact process
US6998678B2 (en) * 2001-05-17 2006-02-14 Infineon Technologies Ag Semiconductor arrangement with a MOS-transistor and a parallel Schottky-diode
JP4945055B2 (ja) * 2003-08-04 2012-06-06 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
JP2006049341A (ja) * 2004-07-30 2006-02-16 Renesas Technology Corp 半導体装置およびその製造方法
US8362547B2 (en) * 2005-02-11 2013-01-29 Alpha & Omega Semiconductor Limited MOS device with Schottky barrier controlling layer
US8283723B2 (en) * 2005-02-11 2012-10-09 Alpha & Omega Semiconductor Limited MOS device with low injection diode
US7948029B2 (en) * 2005-02-11 2011-05-24 Alpha And Omega Semiconductor Incorporated MOS device with varying trench depth
US8093651B2 (en) * 2005-02-11 2012-01-10 Alpha & Omega Semiconductor Limited MOS device with integrated schottky diode in active region contact trench
US7446374B2 (en) * 2006-03-24 2008-11-04 Fairchild Semiconductor Corporation High density trench FET with integrated Schottky diode and method of manufacture
US20080246082A1 (en) * 2007-04-04 2008-10-09 Force-Mos Technology Corporation Trenched mosfets with embedded schottky in the same cell
US8362552B2 (en) * 2008-12-23 2013-01-29 Alpha And Omega Semiconductor Incorporated MOSFET device with reduced breakdown voltage

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