TWI440088B - 非揮發性記憶體之第一層間介電堆疊 - Google Patents
非揮發性記憶體之第一層間介電堆疊 Download PDFInfo
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- TWI440088B TWI440088B TW097112428A TW97112428A TWI440088B TW I440088 B TWI440088 B TW I440088B TW 097112428 A TW097112428 A TW 097112428A TW 97112428 A TW97112428 A TW 97112428A TW I440088 B TWI440088 B TW I440088B
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- 239000011229 interlayer Substances 0.000 title claims description 13
- 239000010410 layer Substances 0.000 claims description 300
- 238000000034 method Methods 0.000 claims description 77
- 239000004065 semiconductor Substances 0.000 claims description 53
- 238000000151 deposition Methods 0.000 claims description 52
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims description 40
- 239000006096 absorbing agent Substances 0.000 claims description 26
- 150000002500 ions Chemical group 0.000 claims description 24
- 238000005498 polishing Methods 0.000 claims description 22
- 238000004519 manufacturing process Methods 0.000 claims description 15
- 230000004888 barrier function Effects 0.000 claims description 12
- 239000000126 substance Substances 0.000 claims description 11
- 238000010521 absorption reaction Methods 0.000 claims description 10
- 238000005530 etching Methods 0.000 claims description 9
- 229910052751 metal Inorganic materials 0.000 claims description 9
- 239000002184 metal Substances 0.000 claims description 9
- 239000010949 copper Substances 0.000 claims description 7
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 6
- 229910052802 copper Inorganic materials 0.000 claims description 6
- 239000003989 dielectric material Substances 0.000 claims description 6
- 238000009792 diffusion process Methods 0.000 claims description 5
- 150000004767 nitrides Chemical class 0.000 claims description 3
- 238000007517 polishing process Methods 0.000 claims description 3
- 229910000420 cerium oxide Inorganic materials 0.000 claims description 2
- BMMGVYCKOGBVEV-UHFFFAOYSA-N oxo(oxoceriooxy)cerium Chemical compound [Ce]=O.O=[Ce]=O BMMGVYCKOGBVEV-UHFFFAOYSA-N 0.000 claims description 2
- 230000000087 stabilizing effect Effects 0.000 claims 1
- 230000008569 process Effects 0.000 description 41
- 238000012545 processing Methods 0.000 description 17
- 239000000463 material Substances 0.000 description 16
- 239000000758 substrate Substances 0.000 description 16
- 230000008021 deposition Effects 0.000 description 12
- 239000010408 film Substances 0.000 description 12
- 230000015572 biosynthetic process Effects 0.000 description 10
- 230000008901 benefit Effects 0.000 description 8
- 238000007667 floating Methods 0.000 description 8
- 238000000137 annealing Methods 0.000 description 6
- 238000000231 atomic layer deposition Methods 0.000 description 6
- 230000006870 function Effects 0.000 description 6
- 230000005693 optoelectronics Effects 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 5
- 239000012535 impurity Substances 0.000 description 5
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 5
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 5
- 239000007789 gas Substances 0.000 description 4
- 238000013508 migration Methods 0.000 description 4
- 230000005012 migration Effects 0.000 description 4
- 230000036961 partial effect Effects 0.000 description 4
- 238000005240 physical vapour deposition Methods 0.000 description 4
- 125000006850 spacer group Chemical group 0.000 description 4
- 239000011800 void material Substances 0.000 description 4
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 3
- 230000002745 absorbent Effects 0.000 description 3
- 239000002250 absorbent Substances 0.000 description 3
- 238000013461 design Methods 0.000 description 3
- 238000002513 implantation Methods 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 239000011358 absorbing material Substances 0.000 description 2
- 238000004380 ashing Methods 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- 229910052715 tantalum Inorganic materials 0.000 description 2
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 2
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910000673 Indium arsenide Inorganic materials 0.000 description 1
- 229910003811 SiGeC Inorganic materials 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 238000004873 anchoring Methods 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- 230000000712 assembly Effects 0.000 description 1
- 238000000429 assembly Methods 0.000 description 1
- AJXBBNUQVRZRCZ-UHFFFAOYSA-N azanylidyneyttrium Chemical compound [Y]#N AJXBBNUQVRZRCZ-UHFFFAOYSA-N 0.000 description 1
- FFBGYFUYJVKRNV-UHFFFAOYSA-N boranylidynephosphane Chemical compound P#B FFBGYFUYJVKRNV-UHFFFAOYSA-N 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 125000004494 ethyl ester group Chemical group 0.000 description 1
- 239000000945 filler Substances 0.000 description 1
- 229910052731 fluorine Inorganic materials 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
- 229910052736 halogen Inorganic materials 0.000 description 1
- 150000002367 halogens Chemical class 0.000 description 1
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 230000000670 limiting effect Effects 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 230000014759 maintenance of location Effects 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000002159 nanocrystal Substances 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 230000001737 promoting effect Effects 0.000 description 1
- 230000002829 reductive effect Effects 0.000 description 1
- 238000012552 review Methods 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/314—Inorganic layers
- H01L21/316—Inorganic layers composed of oxides or glassy oxides or oxide based glass
- H01L21/31604—Deposition from a gas or vapour
- H01L21/31608—Deposition of SiO2
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- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
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- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
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- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
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- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
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- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
- H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
- H01L21/02362—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment formation of intermediate layers, e.g. capping layers or diffusion barriers
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- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
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Description
本發明概言之係關於半導體裝置領域。在一態樣中,本發明係關於用在浮動閘極或其它半導體裝置結構內之層間介電層之製造。
本申請案已於2007年4月5日在美國作為專利申請案第11/697,106號提出申請。
半導體裝置通常包括作為生產線前端(FEOL)處理部分形成於一基板上或基板內之裝置組件(諸如,電晶體及電容器)。此外,將該等裝置組件與外界連接在一起之互連特徵結構(例如,觸點、金屬線及通路)作為生產線後端(BEOL)整合製程之一部分而被包括,藉此在該等互連特徵結構內或其之間形成一個或多個介電層以電隔離該等互連特徵結構及裝置組件。為保護半導體裝置不受遷移離子及其他不期望雜質引起之電荷損耗/增益的影響,該等BEOL介電層通常包括一形成該第一層間介電(ILD0)質之全部或部分之硼磷原矽酸四乙酯(BPTEOS),該第一層間介電質有時亦被稱作前金屬介電質(PMD)。例如,該BPTEOS層提供吸收功能用於幫助保護非揮發記憶體(NVM)不受遷移離子(其能影響該(等)NVM單元之資料保持效能)影響。該BPTEOS層亦能幫助控制半導體電晶體(諸如形成於一電晶體陣列中之半導體電晶體)間之場洩露。
圖1圖解說明一此半導體裝置之實例,該圖繪示一半導
體裝置10,其中裝置組件(諸如電晶體12、13)形成於一基板11上或內部。以簡化示意形式顯示之所繪示裝置組件12、13可代表任一類型之電晶體裝置(諸如,一MOSFET、DRAM或NVM裝置),且其可用任一所需電晶體製造次序來形成,此種製造次序在基板11上形成一閘電極及一閘極介電層並使用該閘電極上之側壁間隔層形成基板11內之該(等)源極/汲極區域(未示出)之至少一部分。關於現有製作製程,藉由在裝置組件12、13上沈積一BPTEOS層14形成該吸收層。然而,當不等形沈積時,BPTEOS層14在裝置組件12、13頂部會形成得較厚且其壓緊開口,故而在BPTEOS層14內形成空隙區域15。該ILD0層內存在之空隙能陷獲到在隨後處理步驟過程中產生之遷移離子,諸如來自用在隨後的拋光步驟中之化學機械拋光劑材料中之離子或來自其他製程及/或清洗步驟中之離子。該裝置內存在之遷移離子會降低裝置良率及損害效能,對NVM裝置而言尤其如此。此外,隨後的觸點形成步驟能在該等空隙內形成導電桁條(例如,鎢桁條),藉此使兩個或更多個觸點短接在一起。
除引入遷移離子外,隨後拋光步驟亦能降低或消除由BPTEOS層14提供之保護功能。如圖2所圖解說明,當BPTEOS層14係包含在該ILD0堆疊內之薄膜堆疊物之部分且其被拋光掉以曝露該底層半導體裝置20之至少部分時,可在該ILD0層平坦化過程中發生上述情形。尤其當使用一化學機械拋光(CMP)步驟來拋光BPTEOS層14時,該CMP
拋光速率之變化(如在密集與絕緣區之間)能移除或削薄某些區之BPTEOS層14,從而移除彼等區域上之吸收保護功能。即使在該拋光僅移除部分BPTEOS層14之處,剩餘被曝露的BPTEOS層可能曝露於氣氛中的雜質,該BPTEOS層可陷獲該等雜質,故而降低該BPTEOS層之吸收效率。
因此,存在對一用於製造一無空隙ILD0層之改良型製程的需要。此外,存在對一如下無空隙ILD0堆疊之需要:其提供充足的吸收保護且可有效、高效且可靠地整合到該製造製程中,例如,整合到生產線製程中段。亦存在對一改良型ILD0堆疊形成製程之需要:其將提供對遷移離子之有效防護、改良裝置良率及/或消減桁條短路之形成。亦存在對一改良型半導體製程及裝置之需要,以克服諸如上文所概述之此項技術中之問題。參照附圖及下文之詳細說明,熟習此項技術者將在審閱本申請案之剩餘部分後更清楚瞭解習用製程及技術之進一步限制及缺點。
本文說明一種用於在一半導體裝置上形成一第一層間介電質(ILD0)的方法及設備,其中該ILD0層包括一厚度大致均勻之保護吸收層。在一被選實施例中,該ILD0層藉由在該等半導體裝置上沈積一蝕刻終止層(例如,電漿增強型氮化矽)形成,以在隨後的(若干)觸點蝕刻製程中保護該底層閘極堆疊及提供某些對遷移離子之防護。為消除該蝕刻終止層內之潛在缺陷,諸如能為離子路徑遷移提供路徑的接縫線,則需要更為強健的保護措施。在各個實施例中藉
由首先在該蝕刻終止層上形成一厚度可完全覆蓋該等閘極及可過填充該等位於半導體裝置間之區域的間隙填充層以減少或消除空隙或核心之形成,而在一ILD0堆疊內提供一強健吸收保護措施。該間隙填充層可藉由等形地沈積由次大氣壓原矽酸四乙酯(SATEOS)或高濃度電漿(HDP)氧化物構成之介電層,或藉由使用可完全填充該等間隙之任何介電質形成。若該間隙填充材料具有不合意之高拋光速率或不能經受住CMP處理,則可使用一適當介電材料(例如,經磷摻雜之TEOS(PTEOS))在該間隙填充材料上形成一穩定拋光層。在平坦化該間隙填充層或堆疊後,在該經平坦化之間隙填充層或堆疊上形成一吸收層,諸如藉由沈積一BPTEOS、PTEOS或經硼摻雜之TEOS(BTEOS)介電層來形成。此外,可藉由沈積一密集介電層(諸如,電漿增強型TEOS(PETEOS))在該吸收層上方形成一附加介電質。該附加介電層用作該吸收膜之罩以保護該吸收膜在隨後的處理中免於曝露在大氣雜質中。該密集介電層亦提供結構支撐以錨定隨後形成之金屬溝槽(例如,Cu),且亦可提供銅擴散阻障功能以阻止隨後形成的銅擴散穿透該ILD0層內。在使用一高濃度電漿(HDP)介電膜形成該間隙填充層的情形下,不太需要一附加密集介電層,乃因該HDP層提供該等保護及結構支撐功能。在再一實施例中,可使用一經HDP摻雜之介電膜(例如,HDP BPTEOS或HDP PTEOS)及一可選拋光罩層形成該間隙填充層,且然後使用一CMP製程拋光該間隙填充層,以便可在一平坦表面上形成一經隨後沈
積之TEOS金屬錨罩層。如將瞭解,可視需要使用一個或多個退火製程步驟使一個或多個的間隙填充層、吸收層及附加介電層密實。藉由揭示一用於形成一經整合ILD0堆疊之方法(其中在完成該ILD0平坦化步驟後形成該吸收層(及任何附加介電層)),該吸收膜以良好介面形成於一經平坦化之介電質上,且具有一大致均勻厚度且不會被拋光掉或曝露在外。在形成該等ILD0堆疊層後,蝕刻觸點開口以使該(等)底層半導體裝置曝露在外,然後可使用任何期望之後端生產線處理(例如,標準CMOS BEOL處理)完成該裝置。使用該所揭示之方法及設備可減少或消除該ILD0層內之空隙且可增強吸收保護,故而提高製造良率,對於具有侵略性觸點插頭縱橫比之NVM產品而言尤其如此,當然可將所揭示之技術用於任何其中空隙在插頭中限制良率之產品或技術中。
現將參照該等附圖詳細說明本發明之各種圖解說明性實施例。儘管下文說明中已列舉各種細節,但應瞭解,不藉助該等具體細節亦可實施本發明,且可針對本文所說明之發明做出各種實施方案特有之決策,以達成裝置設計者之具體目標,諸如依從製程技術或設計相關之約束(其將隨不同實施方案而變化)。儘管此一發展努力可能複雜且耗費時間,然而對於自此揭示內容中獲益之熟習此項技術者此將係例行事業。例如,應指出,將沈積及移除某些材料層以形成該等所繪示之半導體結構,此貫穿此詳細說明
中。若下文未詳細給出用於沈積或移除此等層之具體程序,則應傾向於使用對於熟習此項技術者而言用於沈積、移除或以其他方式以合適厚度形成該等層之習用技術。此種細節為眾所習知,且被認為不必教示熟習此項技術者如何製造或使用本發明。此外,將參照一半導體裝置之簡化截面視圖繪示所選擇態樣,但不包括每一裝置特徵或幾何結構以避免限制或模糊本發明。熟悉此技術者使用此等說明及表示形式以向熟悉此技術之其他人員說明及傳遞其工作內容。亦應指出,在此詳細說明中,出於簡潔及清晰之目的,圖解說明該等圖中之某些元件且未必按比例繪製該等元件。例如,該等圖式中某些元件之尺寸可相對於其他元件放大,以幫助更好地理解本發明之各實施例。
從圖3開始顯示一半導體裝置30之局部截面視圖,其中在基板31上形成電晶體裝置組件(諸如,MOS、NVM或DRAM裝置)32、33。相依於所製造之電晶體裝置32、33之類型,可將基板31構建為一塊狀矽基板、單晶矽(經摻雜或未經摻雜)、或任一包括例如Si、SiC、SiGe、SiGeC、Ge、GaAs、InAs、InP以及其他III-IV族組合物半導體或其任一組合在內之半導體材料,且可視需要形成為塊狀處理晶圓。此外,可將基板31構建為一絕緣半導體(SOI)結構之頂部半導體層或一由塊狀及/或具有不同晶體取向之SOI區域組成之混合基板。
在圖3所圖解說明之簡明裝置實例中,裝置組件32、33之每一者均係一具有一通道區域之非揮發性記憶體(NVM)
裝置,在該通道區域上所形成之NVM閘極堆疊包括第一絕緣或隧道介電層、一在該第一層上形成之浮動閘極34、一在浮動閘極34上形成之控制介電層35(例如,ONO層)及一在介電層35上形成之控制閘極36。此外,通常將在NVM閘極堆疊32、33一側形成之一個或多個側壁間隔層37用於形成基板31之源極及汲極區域(未示出)。雖將浮動閘極34圖解說明為自邊緣抬高而防止氧化侵蝕,但此非係本發明之所要求特徵。在操作中,浮動閘極層34用作一電荷儲存層,在控制閘極36及隧道介電之質控制下被充電。在形成裝置組件32、33中,可使用任一期望之前端生產線處理次序。要瞭解,除浮動閘極裝置外還有其他類型之NVM裝置,包括納米晶體裝置及SONOS(矽-氧-氮-氧矽)裝置。此外,應瞭解該等裝置組件可代表任一類型之半導體裝置組件,例如,一MOSFET電晶體、雙閘極全空乏絕緣半導體(FDSOI)電晶體、NVM電晶體、電容器、二極體或任一其他整合電路組件。
圖4圖解說明繼圖3後在蝕刻終止層42完成沈積後對半導體裝置40之處理,可藉由沈積氮化矽來形成用作第一遷移離子阻障層之蝕刻終止層42。可使用任一所需材料形成蝕刻終止層42,只要當打開該等觸點口時,該材料能保護底層裝置組件32、33不受蝕刻及/或灰化損害。依照各個實施例,可使用化學氣體沈積(CVD)、電漿增強型化學氣體沈積(PECVD)、物理氣體沈積(PVD)、原子層沈積(ALD)或其任一組合來沈積電漿增強型氮化矽(SiN)或碳氮化矽
(SiCN)層以形成蝕刻終止層42。在一被選實施例中,藉由將電漿增強型氮化矽沈積至約20-50納米之厚度來形成蝕刻終止層42,不過亦可使用其他厚度。如此形成之蝕刻終止層42可在隨後之觸點蝕刻製程中保護底層裝置32、33,且就氮化矽用作遷移離子之阻障而言,其亦可提供對遷移離子之防護。然而,就遷移離子能夠穿透接縫線44處之氮化矽蝕刻終止層來說,氮化矽層42僅為裝置32、33提供部分吸收保護功能。
圖5圖解說明繼圖4後在於蝕刻終止層42上沈積間隙填充層52後對半導體裝置50之處理。所沈積之間隙填充層52形成至少部分第一層間介電堆疊,該第一層間介電堆疊使形成於基板31上之裝置組件32、33相互電隔離“如本文所說明,可以一個或多個的介電前金屬層間介電層形成第一層間介電堆疊(ILD0),包括在裝置組件32、33上形成厚度約在500-10000埃間之間隙填充層52,不過亦可使用其他厚度。雖然依照各個實施例,間隙填充層52係使用CVD、PECVD、PVD、ALD或其任一組合沈積二氧化矽或其他介電材料的等形層形成,但也可使用任一合意介電材料形成間隙填充層52。在被選實施例中,選擇該用於形成間隙填充層52之材料來完全填滿該裝置組件32、33間之高縱橫比區域(尤其是與NVM陣列並存之區域),以避免形成空隙及金屬桁條短接(如上所說明)。除減少或消除在該等裝置組件上之大量地形變動或間隙縱橫比問題外,所沈積之間隙填充層52能夠經平坦化後形成ILD0基層,可在該ILD0基
層上形成一個或多個吸收介電層(例如,一BPTEOS層),如下文所說明。在一被選實施例中,可藉由將次大氣壓原矽酸四乙酯(SATEOS)沈積至至少約在1000-4000埃間之厚度以形成間隙填充層52,該厚度足以填充該等位於裝置組件間之區域,不過也可使用其他厚度。此外/或者,可使用低壓TEOS(LPTEOS)CVD、電漿增強型TEOS(PETEOS)、CVD及/或SiOx
Ny
、大氣壓力TEOS(APTEOS)CVD、HDP BPTEOS或HDP電漿增強型PTEOS形成間隙填充層52。此時,可使用一個或多個退火製程步驟使間隙填充層52密實,不過應瞭解亦可隨後在該製造製程中施加一退火製程。雖然未示出,但亦可使用一合適介電材料(例如,PETEOS)在間隙填充52上形成一穩定拋光層。無論用何種方法形成,間隙填充層52形成一可大致填滿該等位於裝置組件32、33間之區域之ILD0基層,藉此減少或消除空隙或核心之形成。此外/或在替代實施例中,將間隙填充層52沈積至足夠厚度以使隨後之拋光步驟將形成一大致平坦之表面,可在該表面上形成一BPTEOS、BTEOS及/或PTEOS材料之吸收層。
圖6圖解說明繼圖5後將間隙填充層52平坦化之後對半導體裝置60之處理。雖然可使用任一合意平坦化製程,但根據各個實施例,間隙填充層52係藉由一使用化學機械拋光步驟之ILD0平坦化製程加以平坦化以在間隙填充層52上形成大致平坦表面62。藉由一時控CMP製程,可移除間隙填充層52之上部區域之材料,此亦並不會移除或曝露蝕刻終
止層42。
圖7圖解說明繼圖6後在一第一吸收介電層72沈積後對一半導體裝置70之處理。可使用任一合意材料形成吸收介電層72,只要該材料可保護底層免受遷移離子影響。依照各個實施例,可使用CVD、PECVD、PVD、ALD或其任一組合沈積一BPTEOS、PTEOS、BTEOS或其任一組合之層以形成吸收介電層72。在一被選實施例中,吸收介電層72係藉由將BPTEOS之厚度沈積至約10-100納米形成,且其更佳係在20-50納米間,不過亦可使用其他厚度。因BPTEOS層72能陷獲遷移離子,所以吸收介電層72可用作高效吸收劑,吸收能影響裝置(例如,NVM記憶體)效能之遷移離子。此時,可用一個或多個退火製程步驟使吸收介電層72密實,不過應瞭解亦可隨後在該製造製程中施加一退火製程。如此形成之吸收介電層72可保護底層裝置32、33防護遷移離子。尤其,在完成該ILD0平坦化步驟後,藉由沈積吸收膜層72可將吸收膜層72形成為一能更加有效地吸收遷移離子之連續層。另外,亦改良該間隙填充材料與該吸收材料間之介面。此外,即使當該ILD0平坦化步驟過拋光該ILD0堆疊(且尤其是間隙填充層52)時,所揭示之方法亦形成一完整且連續的吸收材料層。
圖8圖解說明繼圖7後在沈積第二或介電罩層82後對半導體裝置80之處理。雖然可使用任一合意材料形成介電罩層82,但本發明各實施例係藉由使用CVD、PECVD、PVD、ALD或其任一組合沈積一TEOS層來形成介電罩層82。在
一被選實施例中,附加介電罩層82係藉由將PETEOS沈積至約500-5000埃之厚度形成,且其更佳係1000埃,不過亦可使用其他厚度。當使用一密集介電層(例如,TEOS)形成附加介電層82時,則附加介電層82可提供結構支撐以錨定隨後形成之金屬觸點區域,且亦可提供一銅擴散阻障功能以阻止隨後形成的銅擴散穿透該(等)下方ILD0層。此外,此TEOS罩保護該吸收膜免於曝露在可使其曝露於其他雜質(其可減少吸收膜作為吸收材料的效率)的氣氛中。
圖9圖解說明繼圖8後在形成使一個或多個裝置組件曝露之一個或多個觸點開口92、94及96後對半導體裝置90之處理。如所圖解說明,穿透該ILD0堆疊蝕刻出觸點開口92、94及96中之每一者以曝露在一底層裝置組件之預期觸點區域上之蝕刻終止層42,例如,一在基板31內形成之源極/汲極區域(未示出)或裝置組件32、33上之閘電極。就現有背景技術下之電路設計而言,該源極/汲極區域上之觸點開口94具有一約為500-3000埃、更佳地小於約2000埃之寬度。對於在裝置組件32、33間之區域具有約3000-8000埃、較佳地約5000埃之高度的典型ILD0堆疊,所得的此等裝置縱橫比(高:寬)大於約1.5至多於4:1,不過在未來生產製程技術下之縱橫比將更高。可使用任一微影及/或選擇性蝕刻技術形成觸點開口92、94及96。例如,可藉由以下方式形成觸點開口94:在吸收介電層72及/或附加介電層82上沈積及圖案化一其中界定一觸點口(未示出)之保護性遮罩或光阻層,然後各向異性蝕刻(例如,反應式離子蝕
刻)該經曝露之ILD0堆疊以形成觸點開口94。在另一實施例中,使用一三階段蝕刻製程,其移除第二介電層82之選擇部分、吸收層72、及間隙填充層52,然後到達形成於一選擇觸點區域(及/或閘電極)上之蝕刻終止層42。作為一預備步驟,可在第二介電層82上直接施加及圖案化一光阻層(未示出),不過亦可使用多層遮罩技術來界定觸點開口92、94及96之位置。然後,可使用合適蝕刻劑製程(諸如,一使用O2
,N2
或含氟氣體之各向異性反應式離子蝕刻(RIE)製程)移除第二介電層82、吸收介電層72及間隙填充層52之經曝露部分,以蝕刻出觸點開口92、94及96。例如,使用針對該等在ILD0堆疊層82、72及52內之介電材料(例如,用於蝕刻經碳摻雜的氧化物膜之氬、CHF3
或CF4
化學品)所選定之一個或多個蝕刻製程來蝕刻穿透至蝕刻終止層42之曝露部分。可使用一個或多個附加蝕刻及/或灰化製程以移除任何剩餘層。
雖然圖7-9繪示其中吸收膜層72及錨定層82形成於經拋光間隙填充層52上之選定實施例,但此等層可由形成於經平坦化之間隙填充層52上之單個PTEOS層(未示出)來取代。依照各實施例,該單個PTEOS層係藉由使用CVD、PECVD、PVD、ALD或其任一組合沈積經磷摻雜之TEOS等形層形成。因為此PTEOS層之相對密集,所以其能提供吸收及錨定兩種功能以錨定隨後形成之金屬觸點。
應瞭解,可使用附加處理步驟完成半導體裝置90進入一功能性NVM裝置之製造。除各個前端處理步驟(例如,犧
牲氧化物之形成、剝離、隔離區域之形成、閘極電極之形成、延展區植入、鹵素植入、間隔層之形成、源極/汲極之植入、退火、矽化物之形成及拋光步驟)外,也可實施附加後端處理步驟(例如,形成用於以合意方式連接該等裝置組件之觸點插頭及多層次互連器件)以獲取合意功能。如此一來,用於完成該等裝置組件之製造之具體步驟順序可相依於製程及/或設計要求而改變。
圖10係圖解說明實例製程100之流程圖,實例製程100用於形成一具有大致均勻厚度的吸收層之ILD0堆疊如圖示,該製程在生產線前端(FEOL)製程後繼續並藉由諸如藉由沈積一電漿增強型氮化物終止蝕刻層(PENESL)來形成一蝕刻終止層(步驟101)而開始。下一步,在步驟102中藉由沈積一間隙填充介電層(諸如SATEOS、HDP PTEOS等)形成一ILD0堆疊。此時,亦可沈積一CMP罩層。隨後,在步驟103上平坦化(例如,使用一CMP製程)該間隙填充介電層,在步驟104上沈積一吸收層(諸如BPTEOS),及在步驟105上沈積一阻障介電層(諸如PETEOS)。然而,如該位於步驟104與步驟106間之旁路線所指示,可跳過該阻障介電沈積步驟。一旦形成該ILD0堆疊,可穿透該ILD0堆疊蝕刻一個或多個觸點開口(步驟106),故而曝露預期觸點區域上之蝕刻終止層,此後可使用標準BEOL處理完成該裝置。
到目前為止,應瞭解,已提供一用於在一半導體結構上形成第一層間介電堆疊之方法。在一種形式中,藉由首先
在複數個在一半導體結構上形成之裝置組件(例如,NVM電晶體裝置)上形成一蝕刻終止層(例如,使用所沈積的電漿增強型氮化物)來形成第一層間介電堆疊。隨後,在該蝕刻終止層上形成一介電間隙填充層(例如,藉由沈積一SATEOS或HDP PTEOS層)以填充位於該等裝置組件間之區域。然後使該介電間隙填充層平坦化(例如,使用一CMP製程)成一大致平坦之表面。在該平坦化步驟之前,可在該介電間隙填充層上形成一穩定拋光罩層以便在平坦化該介電間隙填充層之同時,平坦化該穩定拋光罩層及介電間隙填充層。在該大致平坦之表面上,形成一介電吸收層,比如藉由沈積一BPTEOS、BTEOS或PTEOS層或其組合來形成。此外,可在該介電吸收層上形成一介電罩層(例如,PETEOS)。一旦形成該第一層間介電堆疊(ILD0),則可選擇性地蝕刻該介電吸收層及該介電間隙填充層以曝露在一個或多個裝置組件內之一個或多個觸點區域上之該蝕刻終止層,且然後選擇性地蝕刻該經曝露之蝕刻終止層以使該等觸點區域曝露。
在另一形式中,提供一用於製造一其上形成有複數個裝置組件之半導體裝置之方法及系統。如上所揭示,藉由在複數個裝置組件上沈積一介電層形成一間隙填充層以填充該複數個裝置組件之間的區域。為保護該等裝置組件,在形成該間隙填充層前可在該複數個裝置組件上形成一蝕刻終止層。該間隙填充層可藉由在複數個裝置組件上沈積一經SATEOS或HDP摻雜之TEOS層部分地形成以填充該複數
個裝置組件之間的區域,且亦可包括一位於該介電層上之經沈積的穩定拋光罩層。在將該間隙填充層拋光成一大致平坦表面後(例如,藉由使用一化學機械拋光製程平坦化該間隙填充層),在該間隙填充層之大致平坦表面上沈積一吸收層。可藉由在該間隙填充層之大致平坦表面上沈積一BPTEOS層、PTEOS層或BTEOS層或其組合來部分地形成該吸收層。舉例而言,可藉由如下作業形成該吸收層:在該間隙填充層之大致平坦表面上沈積一個或多個經摻雜之TEOS層,及然後在該一個或多個經摻雜之TEOS層上沈積一由TEOS或電漿增強型TEOS形成之錨定層。可選擇地蝕刻該如上所形成之吸收層及間隙填充層介電層以曝露一個或多個的裝置組件內之一個或多個的觸點區域。
在再一形式中,提供一用於形成第一層間介電堆疊之方法及系統,該方法及系統藉由首先在複數個裝置組件上形成一經平坦化之間隙填充層以覆蓋該複數個裝置組件及填充位於該複數個裝置組件之間的區域。在所選定實施例中,可藉由如下方式形成該經平坦化之間隙填充層:在該複數個裝置組件上沈積一經SATEOS或HDP摻雜之TEOS層以填充該複數個裝置組件之間的區域,然後將該經SATEOS或HDP摻雜之TEOS層拋光成一大致平坦表面。在該經平坦化之間隙填充層上,沈積一個或多個吸收層以便在該一個或多個吸收層及經平坦化之間隙填充層內有選擇地蝕刻一開口以使一個或多個裝置組件內之一個或多個觸點區域曝露。在所選實施例中,藉由如下作業形成該等吸
收層:在該經平坦之間隙填充層上沈積一個或多個經摻雜之TEOS層,然後在該一個或多個經摻雜之TEOS層上沈積一由TEOS或電漿增強型TEOS形成之錨定層。
儘管本文揭示之所說明實例性實施例著眼於各種半導體裝置結構及用於製備該等半導體裝置結構之方法,但本發明未必限定於圖解說明本發明之發明性態樣之實例性實施例,該等發明性態樣適用於各種各樣半導體製程及/或裝置。例如,可使用本發明之被選實施例填充高縱橫比(高度與間隔之比)特徵結構間之間隙及提供防污染保護,且本發明之被選實施例並不限於MOSFET、DRAM、NVM或雙極裝置,而是可用於半導體裝置之任一類型。因此,上文所揭示之具體實施例僅係說明性且不應被視為係對本發明之限定,因為受益於本文教示之熟習此項技術者可以其知曉之不同但等效方式修改及實行本發明。例如,可使用除在本文明確陳述以外的材料施用本發明之方法。此外,本發明並不限於本文所說明之特定類型之積體電路。因此,前述說明並不意欲將本發明限定於所陳述之具體形式,相反,其意欲涵蓋可包括於隨附申請專利範圍所界定之本發明精神及範疇內之替代、修改及等效物,以使熟習此項技術者應瞭解,其可在不背離本發明最廣闊形式之精神及範疇之前提下做出各種改變、替換及變更。
上文已針對特定實施例說明了本發明之益處、其他優點及解決問題之方案。然而,該等益處、優點及解決問題之方案及任何可導致任何益處、優點或解決方案發生或更突
出之元件皆不應被理解為係任何或所有請求項的一關鍵、必需或基本之特徵結構或元件。本文所用措詞「包含(comprise,comprising)」或其任一其他變化形式皆意欲涵蓋一非排他性包含,以使一包含一連串要素之製程、方法、製品或設備並非僅包含彼等要素,而是亦可包含其它未明確列出的要素或此製程、方法、製品或設備所固有的要素。
31‧‧‧基板
32‧‧‧電晶體裝置組件
33‧‧‧電晶體裝置組件
34‧‧‧浮動閘極
35‧‧‧控制介電層
36‧‧‧控制閘極
42‧‧‧蝕刻終止層
52‧‧‧間隙填充層
72‧‧‧吸收介電層
82‧‧‧介電罩層
90‧‧‧半導體裝置
92‧‧‧觸點開口
94‧‧‧觸點開口
96‧‧‧觸點開口
10‧‧‧半導體裝置
11‧‧‧基板
12‧‧‧電晶體/裝置組件
13‧‧‧電晶體/裝置組件
14‧‧‧BPTEOS層
15‧‧‧空隙區域
20‧‧‧下面半導體裝置
30‧‧‧半導體裝置
37‧‧‧側壁間隔層
40‧‧‧半導體裝置
44‧‧‧接縫線
50‧‧‧半導體裝置
60‧‧‧半導體裝置
62‧‧‧平坦表面
70‧‧‧半導體裝置
80‧‧‧半導體裝置
在結合下列圖式考量上文之詳細說明時,可理解本發明及其多種目的、特徵及所獲得優點,圖式中:圖1係一半導體裝置之局部截面視圖,在該半導體裝置上可形成有一具有空隙之單層BPTEOS層;圖2圖解說明繼圖1後在平坦化該BPTEOS層後之處理;圖3係一半導體裝置之局部截面視圖,其中在一基板上形成有NVM裝置組件;圖4圖解說明繼圖3後在沈積一蝕刻終止層後之處理;圖5圖解說明繼圖4後在沈積以一個或多個介電膜層形成之間隙充填層後之處理;圖6圖解說明繼圖5後在使用一化學機械拋光步驟平坦化該間隙填充層後之處理;圖7圖解說明繼圖6後在第一吸收介電層沈積後之處理;圖8圖解說明繼圖7後在第二介電層沈積後之處理;圖9圖解說明繼圖8後在形成用以曝露一個或多個裝置組件之觸點開口後之處理;及
圖10係一流程圖,用於圖解說明用於形成一具有厚度大致均勻的吸收層之ILD0堆疊之製程。
應瞭解,為圖解說明簡潔及清晰起見,該等圖式中所圖解說明之元件未並按比例繪製。舉例而言,出於促進及改良清晰性及理解性之目的,相對於其他元件誇大了某些元件之尺寸。此外,在認為適當之處,在該等圖式中重複使用參考編號用於代表對應或相似元件。
31‧‧‧基板
32‧‧‧電晶體裝置組件
33‧‧‧電晶體裝置組件
34‧‧‧浮動閘極
35‧‧‧控制介電層
36‧‧‧控制閘極
42‧‧‧蝕刻終止層
52‧‧‧間隙填充層
72‧‧‧吸收介電層
82‧‧‧介電罩層
90‧‧‧半導體裝置
92‧‧‧觸點開口
94‧‧‧觸點開口
96‧‧‧觸點開口
Claims (16)
- 一種在一半導體結構上形成一第一層間介電質之方法,其包含:在該半導體結構上形成具有一個或多個觸點區域之電晶體之複數個裝置組件;在該複數個裝置組件上形成一蝕刻終止層;在該蝕刻終止層上形成一未摻雜之介電材料之介電間隙填充層以填充該等電晶體間之區域;施用一化學機械拋光製程以將該介電間隙填充層平坦化成一實質平坦表面;藉由沈積一BPTEOS層、PTEOS層或BTEOS層或其組合而在該介電間隙填充層之該實質平坦表面上形成一介電吸收層以提供一遷移離子阻障層,該遷移離子阻障層有效地執行一吸收功能;及選擇地蝕刻該介電吸收層及該介電間隙填充層以於一個或多個之裝置組件內之該一個或多個觸點區域上曝露該蝕刻終止層。
- 如請求項1之方法,其中形成一蝕刻終止層包含在該複數個裝置組件上沈積一經電漿增強之氮化物層。
- 如請求項1之方法,其中形成一介電間隙填充層包含沈積二氧化矽、次大氣壓原矽酸四乙酯(SATEOS)、低壓TEOS(LPTEOS)、電漿增強型TEOS(PETEOS)、SiOx Ny 、大氣壓力TEOS(APTEOS)或高濃度電漿(HDP)氧化物之一層以填充該複數個裝置組件間之區域。
- 如請求項1之方法,其進一步包含在選擇性地蝕刻該介 電吸收層之前,在該介電吸收層上形成一介電罩層。
- 如請求項4之方法,其中形成一介電罩層包含在該介電吸收層上沈積一經電漿增強之原矽酸四乙酯(PETEOS)層。
- 如請求項1之方法,其進一步包含選擇性地蝕刻該經曝露之蝕刻終止層以曝露一個或多個裝置組件中之該一個或多個觸點區域。
- 如請求項1之方法,其進一步包含在介電間隙填充層上形成一穩定拋光罩層以便在平坦化該介電間隙填充層之同時,平坦化該穩定拋光罩層及介電間隙填充層。
- 一種製造一半導體裝置之方法,其包含:在一半導體結構上形成包含電晶體之複數個裝置組件;藉由在該複數個裝置組件上沈積一未摻雜之介電層形成一間隙填充層以填充該複數個裝置組件間之區域,其中所述形成該間隙填充層包含在該複數個裝置組件上沈積一經SATEOS或HDP摻雜的TEOS層以填充該複數個裝置組件間之區域;藉由以一化學機械拋光製程平坦化該間隙填充層而將該間隙填充層拋光成一實質平坦表面;及在該間隙填充層之該實質平坦表面上沈積一吸收層,其有效地執行一吸收功能。
- 如請求項8之方法,其中形成一間隙填充層包含在該未摻雜之介電層上形成一穩定拋光罩層。
- 如請求項8之方法,其中沈積一吸收層包含在該間隙填充層之該實質平坦表面上沈積一BPTEOS層、PTEOS層或BTEOS層或其組合。
- 如請求項8之方法,其中沈積一吸收層包含:在該間隙填充層之該實質平坦表面上沈積一個或多個經摻雜之TEOS層;及在該一個或多個經摻雜之TEOS層上沈積一由TEOS或經電漿增強之TEOS形成之錨定層。
- 如請求項8之方法,其進一步包含在形成該間隙填充層之前在該等電晶體上形成一蝕刻終止層。
- 如請求項8之方法,其進一步包含選擇性地蝕刻該吸收層及該間隙填充層介電層以曝露一個或多個裝置組件中之一個或多個觸點區域。
- 一種形成一第一層間介電堆疊之方法,其包含:在複數個裝置組件上形成一未摻雜之介電材料之經平坦化之間隙填充層及填充位於該複數個裝置組件間之區域;然後沈積一經摻雜之TEOS吸收層以在該經平坦化之間隙填充層上提供一遷移離子阻障層,該遷移離子阻障層有效地執行一吸收功能;然後選擇性地蝕刻在該經摻雜之TEOS吸收層及經平坦化之間隙填充層內之一開口以曝露在一個或多個裝置組件內之一個或多個觸點區域。
- 如請求項14之方法,其中形成一經平坦化之間隙填充層 包含:在該複數個裝置組件上沈積一未摻雜之SATEOS或HDP TEOS層以填充該複數個裝置組件間之區域;且將該SATEOS或HDP TEOS層拋光成一實質平坦表面。
- 如請求項14之方法,其進一步包含:在該經摻雜之TEOS吸收層上沈積一由TEOS或經電漿增強之TEOS形成之錨定層以錨定隨後形成之金屬觸點區域且提供一銅擴散阻障功能以阻止隨後形成之銅擴散穿過至該經摻雜之TEOS吸收層。
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US11/697,106 US8435898B2 (en) | 2007-04-05 | 2007-04-05 | First inter-layer dielectric stack for non-volatile memory |
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TWI440088B true TWI440088B (zh) | 2014-06-01 |
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Country Status (7)
Country | Link |
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US (1) | US8435898B2 (zh) |
EP (1) | EP2135274A4 (zh) |
JP (1) | JP2010524237A (zh) |
KR (1) | KR20100014714A (zh) |
CN (1) | CN101647105B (zh) |
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-
2007
- 2007-04-05 US US11/697,106 patent/US8435898B2/en active Active
-
2008
- 2008-03-12 EP EP08731927A patent/EP2135274A4/en not_active Withdrawn
- 2008-03-12 CN CN200880010706.9A patent/CN101647105B/zh active Active
- 2008-03-12 KR KR1020097020504A patent/KR20100014714A/ko not_active Application Discontinuation
- 2008-03-12 WO PCT/US2008/056562 patent/WO2008124240A1/en active Application Filing
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Also Published As
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JP2010524237A (ja) | 2010-07-15 |
KR20100014714A (ko) | 2010-02-10 |
US20080248649A1 (en) | 2008-10-09 |
TW200849386A (en) | 2008-12-16 |
CN101647105B (zh) | 2012-07-04 |
EP2135274A1 (en) | 2009-12-23 |
US8435898B2 (en) | 2013-05-07 |
EP2135274A4 (en) | 2011-07-27 |
WO2008124240A1 (en) | 2008-10-16 |
CN101647105A (zh) | 2010-02-10 |
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