TWI438907B - A printing method for making barrier in buried-contact solar cell fabrication and its resultant device - Google Patents

A printing method for making barrier in buried-contact solar cell fabrication and its resultant device Download PDF

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TWI438907B
TWI438907B TW098131013A TW98131013A TWI438907B TW I438907 B TWI438907 B TW I438907B TW 098131013 A TW098131013 A TW 098131013A TW 98131013 A TW98131013 A TW 98131013A TW I438907 B TWI438907 B TW I438907B
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semiconductor substrate
etched
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TW201110372A (en
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Li Karn Wang
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Nat Univ Tsing Hua
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    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy

Description

以印刷塗佈形成遮罩而製作埋藏式電極太陽能電池之方法以及該太陽能電池Method for forming a buried electrode solar cell by forming a mask by printing coating, and the solar cell

本發明係在矽晶圓基板上以化學濕式藥劑或以乾蝕刻製程，但不使用雷射、機械方式雕刻以及曝光、顯影等黃光製程，而製作出溝槽的技術方法。本發明亦包含使用此法在溝槽中鋪設金屬電極，以形成埋藏式電極，並製作矽半導體基板太陽能電池。The invention is a technical method for making a groove by using a chemical wet chemical or a dry etching process on a germanium wafer substrate, but without using a laser process such as laser, mechanical engraving, and exposure, development, and the like. The invention also encompasses the use of this method to lay metal electrodes in trenches to form buried electrodes and to fabricate germanium semiconductor substrate solar cells.

一般具有埋藏式電極之太陽能電池，係指在該太陽能電池之照光側表面製作溝槽陣列，並於溝槽內鍍製或鋪設金屬電極，如第一圖所示者，即為一個具有埋藏式電極15之P-N接面太陽能電池。該習式太陽能電池的製作一般係先在低摻雜濃度的矽晶圓基板(wafer)，例如P型矽半導體基板11，以磷擴散於其表面以下區域形成淺薄的第一N型層12(即n+ 層)，然後再成長鈍化層以及抗反射層(或兼具鈍化功能之抗反射層13，例如氮化矽層)。接著以雷射或機械方式在表面雕刻出複數條溝槽，亦即溝槽陣列，唯並不使用黃光製程技術(photolithography)。溝槽開口的表面以下薄薄一層區域以磷擴散方式形成摻雜濃度較高的第二N型層14(即n++ 層)，之後製作金屬電極於溝槽中，形成埋藏式電極15。習式金屬電極製作之另一例為使用含磷之銀膏塗於溝槽中，然後以快速高溫退火(即俗稱之firing)方式使磷擴散至溝槽表面以下區域形成第二N型層14。第一圖所示之習式太陽能電池亦含有背電極16，在電池背面處亦含有背表面場層(layer of back surface field;BSF layer)17，以及在前表面處具有表面粗化結構18(texture)以造成光線捕捉(light trapping)效果，增加光電轉換效率。上述習式技術以雷射或機械方式雕刻出寬數拾微米與數倍於寬度之深度的溝槽，所形成之埋藏式電極太陽能電池，其光電轉換效率在文獻已有超過22%的報導。A solar cell generally having a buried electrode means that an array of trenches is formed on the light-emitting side surface of the solar cell, and a metal electrode is plated or laid in the trench, as shown in the first figure, that is, a buried type The PN junction of the electrode 15 is a solar cell. The conventional solar cell is generally fabricated on a low doping concentration germanium wafer wafer, such as a P-type germanium semiconductor substrate 11, to form a shallow first N-type layer 12 with phosphorus diffused below the surface thereof ( That is, the n + layer), and then the passivation layer and the antireflection layer (or the antireflection layer 13 having a passivation function, such as a tantalum nitride layer) are grown. A plurality of trenches, ie, trench arrays, are then engraved on the surface by laser or mechanical means, but no photolithography is used. A thin layer of a region below the surface of the trench opening is formed by a phosphorus diffusion method to form a second N-type layer 14 having a higher doping concentration (ie, an n ++ layer), and then a metal electrode is formed in the trench to form a buried electrode 15. Another example of a conventional metal electrode fabrication is to apply a phosphorous-containing silver paste to a trench, and then diffuse phosphorus to a region below the surface of the trench to form a second N-type layer 14 in a rapid high temperature annealing (i.e., commonly known as firing). The conventional solar cell shown in the first figure also contains a back electrode 16 which also has a layer of back surface field (BSF layer) 17 at the back of the cell and a surface roughening structure 18 at the front surface ( Texture) to increase the photoelectric conversion efficiency by causing light trapping effect. The above-mentioned conventional technology laser or mechanically engraves a trench having a width of several micrometers and a depth several times the width, and the photoelectric conversion efficiency of the buried electrode solar cell formed has been reported in the literature by more than 22%.

使用埋藏式電極的好處有若干個：其一可大為減少金屬電極對光的遮罩。再者，埋藏式電極之線寬雖比較窄，但因深入晶圓內部，金屬的電阻值可與傳統覆蓋於晶圓表面的金屬電阻值相若。但由於金屬線寬較窄之故，前者電極的間距可以比後者電極的間距來的小很多，因此，埋藏式電極的太陽能電池，其內部因吸收光能而轉換產生的電子行進至電極處之平均路徑要比傳統式太陽能電池內部電子行進長度來的短。因此相較於傳統式太陽能電池，埋藏式電極電池的內阻便減少許多，此舉便可增加填充因子F.F.(fill factor)，對增加太陽能電池的光電轉換效率有不少助益。又，因為電極是從矽晶圓表面深入內部數拾微米乃至更深處，許多光能轉換成的電子在此直接移動至電極處，因而增加了電極收集電子的數量，提高了短流電流，亦增加開路電壓值，此舉對太陽能電池效率的提升十分有助益。而在埋藏式電極周邊製作低面電阻(sheet resistance)之n++ 層之目的，是為了減低金屬與半導體介面之接觸電阻，便利於達到高填充因子之目的。There are several advantages to using buried electrodes: one can greatly reduce the masking of light by metal electrodes. Moreover, although the line width of the buried electrode is relatively narrow, the resistance value of the metal can be similar to the metal resistance value conventionally covered on the surface of the wafer due to the depth of the inside of the wafer. However, since the width of the metal line is narrow, the pitch of the former electrode can be much smaller than the pitch of the latter electrode. Therefore, the solar cell of the buried electrode has electrons converted by the absorption of light energy to the electrode. The average path is shorter than the length of the electronic travel inside the conventional solar cell. Therefore, compared with the conventional solar cell, the internal resistance of the buried electrode battery is much reduced, which can increase the fill factor FF, which is helpful for increasing the photoelectric conversion efficiency of the solar cell. Moreover, since the electrodes are deeper and deeper from the surface of the germanium wafer, many electrons converted into light energy are directly moved to the electrodes, thereby increasing the amount of electrons collected by the electrodes and increasing the short-current current. Increasing the open circuit voltage value is very helpful for improving the efficiency of solar cells. The purpose of fabricating the n ++ layer of sheet resistance around the buried electrode is to reduce the contact resistance between the metal and the semiconductor interface, and to achieve a high fill factor.

目前以雷射或機械方式雕刻產生複數條溝槽，亦即溝槽陣列，在實務上恐怕尚不能達到真正量產化目的，尤其在大面積晶圓上欲雕刻出為數不少的溝槽，將面臨費時或製作良率不高的困境。其原因是，其一若使用雷射熔燒雕刻，則其雕刻速度不足以達高產能之快速需求。若使用複數個雷射機台，則又將面臨機具成本過高問題。另外，若使用機械刀具則亦將面臨雕刻速度緩慢問題。若使用機械排刀，其同時雕刻或可增加製作速度，然亦免不了刀具在矽晶圓表面來回研磨，其製作速度亦十分緩慢，而且因為晶圓上具有數量不少的溝槽孔洞，使得晶圓益加脆弱。研磨產生的應力將使得脆弱的晶圓破裂，造成良率不高。At present, laser or mechanical engraving produces a plurality of trenches, that is, trench arrays. In practice, it may not be possible to achieve mass production, especially in large-area wafers, where a large number of trenches are to be engraved. Will face time-consuming or low production yields. The reason is that if laser engraving is used for engraving, the engraving speed is not sufficient to meet the rapid demand for high productivity. If you use a plurality of laser machines, you will face the problem of excessive machine cost. In addition, if you use mechanical tools, you will also face the problem of slow engraving speed. If a mechanical row of knives is used, it can be engraved at the same time to increase the speed of production. However, it is inevitable that the tool will be ground back and forth on the surface of the enamel wafer. The fabrication speed is also very slow, and because there are a large number of groove holes on the wafer, the crystal is made. Round and fragile. The stress generated by the grinding will cause the fragile wafer to rupture, resulting in a low yield.

有鑑於此，本發明提出一個可以量產且能夠產生高製成良率的製程技術，便利於在晶圓上製作複數條溝槽，作為製作具有埋藏式電極之矽晶圓太陽能電池之重要方法。本發明所揭露之製程方法之一例，係以化學藥劑蝕刻出前述溝槽陣列，具體而言，係在具有N型半導體層和抗反射層(後者亦兼具鈍化效能)的P型半導體基板(亦即P型矽晶圓)上使用印刷方式塗佈具有圖樣(pattern)之遮罩層，其目的係阻擋化學藥劑溶液的侵蝕。在未塗佈遮罩處的半導體則裸露於化學藥劑溶液中遭受蝕刻而形成溝槽。本發明所揭露之溝槽製作方法，並不使用費時的黃光製程技術以及雷射或機械雕刻方式。In view of this, the present invention proposes a process technology that can be mass-produced and capable of producing high fabrication yield, and facilitates fabrication of a plurality of trenches on a wafer as an important method for fabricating a germanium wafer solar cell having buried electrodes. . An example of the process method disclosed in the present invention is to etch the trench array by a chemical agent, specifically, a P-type semiconductor substrate having an N-type semiconductor layer and an anti-reflection layer (the latter also having passivation efficiency) ( A mask layer having a pattern is applied by printing on a P-type wafer, the purpose of which is to block the attack of the chemical solution. The semiconductor at the uncoated mask is exposed to the chemical solution and is etched to form a trench. The trench fabrication method disclosed in the present invention does not use time-consuming yellow light process technology and laser or mechanical engraving.

由於本發明所揭露的方法係使用可藉網版或滾筒印刷技術達成適當遮罩圖樣於半導體基板上，旋又以化學藥劑溶液蝕刻出溝槽於其上，比前述傳統之黃光製程以及使用雷射或機械方式雕刻的技術較為方便與快速，可達量產化生產目的。此外，使用本發明所揭露的方法，其製作前述溝槽所需設備成本亦相較於前述傳統者為低。而所謂適當遮罩圖樣指的是可以使用印刷方式塗佈於前述半導體基板表面上的膏狀物質所形成的薄層圖樣。在半導體基板之受印刷面上所呈現的遮罩圖樣可由網版或滾筒印刷達成。該膏狀物質經冷卻或經由加溫燒結後成型，作為阻擋藥水之遮罩層。Since the method disclosed in the present invention uses a screen or roll printing technique to achieve a proper mask pattern on the semiconductor substrate, the liquid is etched onto the wafer by a chemical solution, which is more than the conventional yellow light process and use. The technology of laser or mechanical engraving is more convenient and fast, and can be used for mass production. Moreover, using the method disclosed by the present invention, the equipment cost required to fabricate the aforementioned trenches is also lower than previously described. The appropriate mask pattern refers to a thin layer pattern formed by using a paste-like substance applied to the surface of the semiconductor substrate by printing. The mask pattern presented on the printed surface of the semiconductor substrate can be achieved by screen printing or cylinder printing. The paste material is formed by cooling or sintering by heating, and serves as a mask layer for blocking the syrup.

本發明所揭露之方法係以印刷方式形成在半導體基板上且足以阻擋化學藥水之遮罩層，而蝕刻出所需的溝槽，此即以該遮罩層作為直接阻擋化學藥水的阻擋層。然而，本發明所揭露方法的另一例，係首先在矽基板上印刷塗佈與溝槽圖樣相合之遮罩層後，再全面塗佈一層不同材料之遮罩。然後，將原印刷之遮罩層清洗除去，而僅留下新的遮罩做為阻擋化學藥水的阻擋層。此新的遮罩層(阻擋層)圖樣與原遮罩層圖樣互補。新的遮罩層可由化學氣相沉積法、蒸鍍法、濺鍍法、印刷或濕式化學製程方式製作，唯不使用黃光製程技術。The method disclosed in the present invention is formed by printing on a semiconductor substrate and sufficient to block the mask layer of the chemical syrup, and etching the desired trench, that is, the mask layer is used as a barrier layer for directly blocking the chemical syrup. However, another example of the method disclosed in the present invention is to first apply a mask layer of a different material after printing a mask layer corresponding to the groove pattern on the ruthenium substrate. The original printed mask layer is then removed by cleaning, leaving only a new mask as a barrier to the blocking chemical. This new mask layer (barrier layer) pattern complements the original mask layer pattern. The new mask layer can be fabricated by chemical vapor deposition, evaporation, sputtering, printing or wet chemical processes, but without the use of yellow light process technology.

除了前述使用化學藥水進行蝕刻半導體未鋪設遮罩層之區域，以產生溝槽之外，本發明亦包括使用乾蝕刻法(dry etching)對未鋪設遮罩層之區域進行蝕刻，以產生所需要圖樣的溝槽。In addition to the foregoing use of a chemical syrup to etch regions of the semiconductor unmasked layer to create trenches, the present invention also includes etching the regions of the unmasked layer using dry etching to produce the desired The groove of the pattern.

本發明目的係使用一可量產化之製作方法在半導體基板表面處蝕刻複數條溝槽，以製作具有埋藏式電極之太陽能電池。以第二圖所示之結構為本發明實施方式之說明，亦即為本發明所欲製作太陽能電池之一例，其包括P型矽半導體基板21、第一N型層22、第二N型層24、抗反射層23、埋藏式電極25、背表面場層27以及背電極26。第二圖的抗反射層23可以單獨由氮化矽組成，兼具鈍化功能；亦可由二氧化矽與氮化矽先後成長組合而成。在後者的組合中，二氧化矽係以化學氣相沉積法、蒸鍍、濺鍍或經由浸泡半導體基板於化學溶液而產生，具表面鈍化(surface passivation)功能；氮化矽則由化學氣相沉積法、蒸鍍或濺鍍製成，同時兼具鈍化及抗反射功能。為造成光線捕捉效應，P型矽半導體基板21的表面係先以化學藥劑溶液蝕刻成粗化表面28(textured surface)，然後進行前述第一N型層22及抗反射層23的製作。前述第一N型層22及第二N型層24的N型摻雜濃度可以相同，例如在1019 至1021 1/cm3 之間，亦可以明顯不同，例如第一N型層22的摻雜濃度較低，一般命名為n+ 層，而第二N型層24的摻雜濃度較高，一般稱為n++ 層。SUMMARY OF THE INVENTION The object of the present invention is to etch a plurality of trenches at the surface of a semiconductor substrate using a mass production method to fabricate a solar cell having buried electrodes. The structure shown in the second figure is an illustration of an embodiment of the present invention, that is, an example of a solar cell to be fabricated according to the present invention, which includes a P-type germanium semiconductor substrate 21, a first N-type layer 22, and a second N-type layer. 24. Anti-reflective layer 23, buried electrode 25, back surface field layer 27, and back electrode 26. The anti-reflection layer 23 of the second figure may be composed of tantalum nitride alone and has a passivation function; it may also be formed by a combination of cerium oxide and tantalum nitride. In the latter combination, the cerium oxide is produced by chemical vapor deposition, evaporation, sputtering or by immersing a semiconductor substrate in a chemical solution, and has a surface passivation function; Made by deposition, evaporation or sputtering, with both passivation and anti-reflection. In order to cause a light trapping effect, the surface of the P-type germanium semiconductor substrate 21 is first etched into a textured surface by a chemical solution, and then the first N-type layer 22 and the anti-reflective layer 23 are formed. The N-type doping concentration of the first N-type layer 22 and the second N-type layer 24 may be the same, for example, between 10 19 and 10 21 1 /cm 3 , and may also be significantly different, for example, the first N-type layer 22 The doping concentration is lower, generally designated as the n + layer, while the second N-type layer 24 has a higher doping concentration, generally referred to as the n ++ layer.

本發明旨在提供一個在矽半導體基板表面製作複數條溝槽的方法，以利於製造具有埋藏式電極之太陽能電池，其具體實施方式之第一例係簡單如第三圖所示，詳細解說如下：首先矽基板經過化學蝕刻溶液之侵蝕處理形成有光線捕捉功能的表面粗化結構，具有粗化表面28，然後以N型掺雜物，在高溫至少800℃以上之爐管環境中經由擴散方式，在P型矽基板21照光側表面以下形成淺薄的第一N型層22，即n+ 層。N型掺雜物的選項包括三氯磷醯(POCl3 )、磷化氫(PH3 )、氧化磷(P2 O5 )或其他氣相、固相磷化合物，亦包括含有砷(As)或銻(Sb)之物質。其次，在第一N型層22之上方成長抗反射層23。接著以網版或滾筒印刷方式在矽基板上塗佈遮罩層，使耐化學藥水蝕刻，此即為直接遮罩層。視化學藥水種類而定，此遮罩層之材料可為二氧化矽或其他介電質材料，亦可以是金屬、金屬化合物或是含金屬之混合物，其在矽基板表面的分佈圖樣，係使未塗佈遮罩層的矽基板表面區域於浸泡化學藥水時受蝕刻而產生溝槽。本發明所揭露的方法，亦包含在印刷遮罩層於矽基板表面後，以化學氣相沉積法、蒸鍍、濺鍍、印刷或濕式化學製程全面於該矽基板表面塗佈另一種不同材料，唯不使用黃光製程。該另一種不同材料可為二氧化矽或其他介電質材料，亦可以是金屬、金屬化合物或是含金屬之混合物。然後，將原印刷之遮罩層清洗去除，留下新塗佈之材料於矽基板表面作為新的遮罩層，其在矽基板之分佈圖樣與原遮罩層圖樣互補，此處原遮罩層稱為暫時遮罩。於矽基板浸泡於適當化學藥水時，上述新的遮罩層將保護其下之抗反射層以及矽材質，而致使未覆蓋新遮罩層之區域受該化學藥水蝕刻而產生溝槽。產生溝槽後，將矽基板置于800℃以上之爐管中使用N型掺雜物，以擴散方式在溝槽內之表面形成淺薄之第二N型層24，其N型摻雜濃度大於或等於前述n+ 層濃度。N型掺雜物的選項包括三氯磷醯(POCl3 )、磷化氫(PH3 )、氧化磷(P2 O5 )或其他氣相、固相磷化合物，亦包括含有砷(As)或銻(Sb)之物質。進行此一步驟前，矽基板上的遮罩層若屬可耐高溫材料則不必清除，若屬不可耐高溫材料則必須事先清除。前者情況會導致第一N型層22與第二N型層24有不相同N型摻雜濃度，而後者情況將導致第一N型層22與第二N型層24必定有相同N型摻雜濃度。最後，以含有金屬成份之膏狀物塗佈於前述溝槽內，並經過高溫燒結而形成埋藏式電極25。至於背電極26的塗佈，以含金屬之膏狀物先後同時進行，並與埋藏式電極25一起同時燒結。並且，由於選擇背電極金屬的熔點較埋藏式電極金屬之熔點為低，兩者同時進行燒結時僅在背面形成背表面場層27，即P+ 層，而增加太陽能電池的開路電壓值。經燒結完成後，進行邊緣絕緣(edge isolation)程序即完成太陽能電池元件。The present invention aims to provide a method for fabricating a plurality of trenches on the surface of a germanium semiconductor substrate to facilitate the fabrication of a solar cell having a buried electrode. The first embodiment of the specific embodiment is as shown in the third figure, and is explained in detail as follows. First, the substrate is etched by a chemical etching solution to form a surface roughening structure having a light trapping function, having a roughened surface 28, and then diffused by a N-type dopant in a furnace tube environment having a temperature of at least 800 ° C or higher. A shallow first first N-type layer 22, that is, an n + layer, is formed below the light-emitting side surface of the P-type germanium substrate 21. Options for N-type dopants include chlorophosphonium (POCl 3 ), phosphine (PH 3 ), phosphorus oxide (P 2 O 5 ) or other gas phase, solid phase phosphorus compounds, and also include arsenic (As). Or the substance of sputum (Sb). Next, the anti-reflection layer 23 is grown above the first N-type layer 22. Then, a mask layer is applied on the ruthenium substrate by screen printing or roll printing to etch the chemical resistant syrup, which is a direct mask layer. Depending on the type of chemical syrup, the material of the mask layer may be cerium oxide or other dielectric material, or it may be a metal, a metal compound or a mixture of metals, and its distribution pattern on the surface of the ruthenium substrate is The surface area of the ruthenium substrate to which the mask layer is not applied is etched to form a groove when immersed in the chemical syrup. The method disclosed in the present invention also includes coating a mask layer on the surface of the ruthenium substrate, and applying a chemical vapor deposition method, an evaporation process, a sputtering process, a printing process or a wet chemical process to coat the surface of the ruthenium substrate with another difference. Material, only use the yellow light process. The other different material may be ceria or other dielectric material, or it may be a metal, a metal compound or a mixture of metals. Then, the original printed mask layer is cleaned and removed, leaving the newly coated material on the surface of the germanium substrate as a new mask layer, and the distribution pattern on the germanium substrate is complementary to the original mask layer pattern, where the original mask is The layer is called a temporary mask. When the germanium substrate is immersed in a suitable chemical solution, the new mask layer protects the anti-reflective layer and the germanium material underneath, so that the region not covered with the new mask layer is etched by the chemical solution to form a trench. After the trench is formed, the germanium substrate is placed in a furnace tube above 800 ° C using an N-type dopant, and a shallow second N-type layer 24 is formed on the surface of the trench in a diffusion manner, and the N-type doping concentration is greater than Or equal to the aforementioned n + layer concentration. Options for N-type dopants include chlorophosphonium (POCl 3 ), phosphine (PH 3 ), phosphorus oxide (P 2 O 5 ) or other gas phase, solid phase phosphorus compounds, and also include arsenic (As). Or the substance of sputum (Sb). Before performing this step, the mask layer on the substrate should not be removed if it is a high temperature resistant material. If it is not resistant to high temperature materials, it must be removed beforehand. The former case may cause the first N-type layer 22 and the second N-type layer 24 to have different N-type doping concentrations, and the latter case will cause the first N-type layer 22 and the second N-type layer 24 to have the same N-type doping. Miscellaneous concentration. Finally, a paste containing a metal component is applied to the trench and sintered at a high temperature to form the buried electrode 25. As for the coating of the back electrode 26, the metal-containing paste is simultaneously performed simultaneously and simultaneously sintered together with the buried electrode 25. Further, since the melting point of the back electrode metal is selected to be lower than the melting point of the buried electrode metal, the back surface field layer 27, that is, the P + layer, is formed only on the back surface when sintering, and the open circuit voltage value of the solar cell is increased. After the sintering is completed, an edge isolation process is performed to complete the solar cell element.

本發明所揭露製作溝槽之技術，除前述使用化學藥水進行蝕刻之外，亦包含另一種蝕刻方法，亦即使用乾蝕刻法將未覆蓋遮罩層之區域蝕刻而產生溝槽。然而，不論是濕蝕刻抑或乾蝕刻，對於不同的蝕刻劑(etchant)，將使用適當之遮罩材料，以阻擋蝕刻劑對遮罩下方之抗反射層與矽材質產生蝕刻，而僅對裸露之區域進行蝕刻。前述所謂適當之遮罩材料，係依使用蝕刻劑而定，例如使用氫氧化鉀為蝕刻劑時，遮罩材料可選擇二氧化矽；使用硝酸與氫氟酸混合溶液為蝕刻劑時，遮罩材料可選擇耐酸樹脂類聚合物；使用含四氟化碳、溴化氫和氯氣之混合物作為乾蝕刻劑時，光阻可作為遮罩。然而，不論作為濕蝕刻劑抑或作為乾蝕刻劑的種類，皆不勝枚舉。所列舉之蝕刻劑與遮罩材料雖屬有限種類，本發明所揭露之技術旨在闡述一項不使用黃光製程、雷射或機械雕刻而產生複數條溝槽的方法，應與使用何種蝕刻劑與遮罩材料無關。The technique for fabricating trenches disclosed in the present invention includes, in addition to the foregoing etching using a chemical syrup, another etching method, that is, etching a region where the mask layer is not covered by dry etching to form a trench. However, whether wet etching or dry etching, for different etchants, a suitable masking material will be used to block the etchant from etching the anti-reflective layer and the germanium material under the mask, but only for bare The area is etched. The above-mentioned suitable mask material is determined by using an etchant. For example, when potassium hydroxide is used as an etchant, the mask material may be selected from cerium oxide; when a mixed solution of nitric acid and hydrofluoric acid is used as an etchant, the mask is used. The material may be selected from an acid-resistant resin-based polymer; when a mixture containing carbon tetrafluoride, hydrogen bromide, and chlorine is used as a dry etchant, the photoresist may serve as a mask. However, the types that are either wet etchants or dry etchants are numerous. Although the etchant and mask materials listed are of a limited variety, the technology disclosed in the present invention aims to illustrate a method for generating a plurality of trenches without using a yellow light process, laser or mechanical engraving, which should be used. The etchant is independent of the mask material.

本發明具體實施方式之第二例係與前述具體實施方式之第一例大致相同，唯事先並不成長抗反射層，而是在製作完成第二N型層後始製作抗反射層於整個矽基板照光側之表面，其製程程序簡單如第四圖所示。另外，本發明具體實施方式之第三例係與前述第一例大致相同，唯事先並不製作表面粗化結構，且事先不成長第一N型層和抗反射層，而是在製作溝槽完成後始製作表面粗化結構，之後以N型掺雜物製作第一N型層與第二N型層，接著製作抗反射層於其上，製程程序簡單如第五圖所示。The second example of the specific embodiment of the present invention is substantially the same as the first example of the foregoing specific embodiment, except that the anti-reflection layer is not grown in advance, but the anti-reflection layer is formed after the second N-type layer is completed. The surface of the substrate is illuminated, and the process procedure is as shown in the fourth figure. In addition, the third example of the specific embodiment of the present invention is substantially the same as the first example described above, except that the surface roughening structure is not formed in advance, and the first N-type layer and the anti-reflection layer are not grown in advance, but the trench is formed. After completion, the surface roughening structure is formed, and then the first N-type layer and the second N-type layer are formed with N-type dopants, and then an anti-reflection layer is formed thereon, and the process procedure is as simple as shown in FIG.

另外，本發明所揭露之技術，其實施方式亦包含在N型矽半導體基板之照光側以網版或滾筒印刷方式形成直接遮罩或暫時遮罩，以利於製作乾、濕蝕刻之阻擋層進而產生溝槽。In addition, in the technology disclosed in the present invention, the embodiment also includes forming a direct mask or a temporary mask on the illumination side of the N-type germanium semiconductor substrate by screen printing or roller printing to facilitate the formation of a dry and wet etching barrier layer. A groove is created.

具體而言，本發明具體實施方式，乃係以適當遮罩材料阻擋化學藥水(即濕蝕刻劑)抑或乾蝕刻劑之侵蝕，而僅使未受遮罩層覆蓋之矽基板區域受上述乾、濕蝕刻劑蝕刻。本發明所揭露技術的重點在於以印刷塗佈作為開始，以取代雷射或機械雕刻以及黃光製程技術等較為費時程序。因此，凡屬以本實施方式所述之印刷而最終完成埋藏式電極之方法者，皆為本發明所揭露技術之範疇。Specifically, the specific embodiment of the present invention is to block the chemical syrup (ie, the wet etchant) or the dry etchant by a suitable mask material, and only the ruthenium substrate region not covered by the mask layer is subjected to the above drying, Wet etchant etching. The focus of the disclosed technology is to start with printing and coating to replace the more time consuming procedures such as laser or mechanical engraving and yellow light process technology. Therefore, all of the methods for finalizing the buried electrode by the printing described in the embodiment are within the scope of the disclosed technology.

另外，本發明所揭露之技術，其溝槽之剖面幾何形狀，因使用之蝕刻劑不同而具不同情況。例如，一般乾蝕刻劑較易形成較垂直塌陷之凹孔形狀，如第二圖所示者。若使用非等向性蝕刻劑，則視矽半導體之晶相結構而可蝕刻出凹孔形狀係向下漸寬，如第六圖所示者，或係向下漸窄，如第七圖所示者。若使用等向性蝕刻劑，則易形成類似第六圖所示之情況或第八圖類似碗形的結構。In addition, in the technique disclosed by the present invention, the cross-sectional geometry of the trenches may vary depending on the etchant used. For example, a general dry etchant is more likely to form a relatively collapsed recessed hole shape, as shown in the second figure. If an anisotropic etchant is used, the shape of the recessed holes can be etched downward depending on the crystal phase structure of the germanium semiconductor, as shown in the sixth figure, or gradually narrowed downward, as shown in the seventh figure. Shower. If an isotropic etchant is used, it is easy to form a structure similar to the case shown in the sixth figure or the bowl shape similar to the eighth figure.

11．．．P型矽半導體基板11. . . P-type germanium semiconductor substrate

12．．．第一N型層12. . . First N-type layer

13．．．抗反射層13. . . Antireflection layer

14．．．第二N型層14. . . Second N-type layer

15．．．埋藏式電極15. . . Buried electrode

16．．．背電極16. . . Back electrode

17．．．背表面場層17. . . Back surface field layer

18．．．表面粗化結構18. . . Surface roughening structure

21．．．P型矽半導體基板twenty one. . . P-type germanium semiconductor substrate

22．．．第一N型層twenty two. . . First N-type layer

23．．．抗反射層twenty three. . . Antireflection layer

24．．．第二N型層twenty four. . . Second N-type layer

25．．．埋藏式電極25. . . Buried electrode

26．．．背電極26. . . Back electrode

27．．．背表面場層27. . . Back surface field layer

28．．．粗化表面28. . . Roughened surface

第一圖　係習式之埋藏式電極太陽能電池的結構。The first figure is the structure of a buried electrode solar cell.

第二圖　係埋藏式電極太陽能電池剖面結構之第一例。The second figure is the first example of the cross-sectional structure of the buried electrode solar cell.

第三圖　係本發明以P型矽基板製作埋藏式電極太陽能電池程序之第一例。Third is a first example of a procedure for fabricating a buried electrode solar cell using a P-type germanium substrate.

第四圖　係本發明以P型矽基板製作埋藏式電極太陽能電池程序之第二例。The fourth figure is a second example of the procedure for fabricating a buried electrode solar cell using a P-type germanium substrate.

第五圖　係本發明以P型矽基板製作埋藏式電極太陽能電池程序之第三例。Fig. 5 is a third example of the procedure for fabricating a buried electrode solar cell using a P-type germanium substrate.

第六圖　係埋藏式電極太陽能電池剖面結構之第二例。The sixth figure is the second example of the cross-sectional structure of the buried electrode solar cell.

第七圖　係埋藏式電極太陽能電池剖面結構之第三例。The seventh figure is the third example of the cross-sectional structure of the buried electrode solar cell.

第八圖　係埋藏式電極太陽能電池剖面結構之第四例。The eighth figure is the fourth example of the cross-sectional structure of the buried electrode solar cell.

Claims (35)

一種毋須使用曝光、顯影等黃光製程以及雷射或機械雕刻而在矽半導體基板表面以化學藥水，即濕蝕刻劑蝕刻出複數條溝槽之技術；該技術係使用可耐濕蝕刻劑蝕刻之材料，以網版或滾筒印刷方式鋪設於該矽半導體基板表面上，經固化後作為遮罩使受遮罩阻擋之矽區域不受濕蝕刻劑侵蝕，且濕蝕刻劑僅對未受遮罩之矽區域進行蝕刻，而產生複數條溝槽；該印刷材料係一種含二氧化矽、高分子聚合物或其他介電質材料之膏狀物，亦可以是含金屬或金屬化合物之膏狀物。 A technique for etching a plurality of grooves on a surface of a germanium semiconductor substrate with a chemical syrup, that is, a wet etchant, using a yellow light process such as exposure, development, and laser or mechanical engraving; the technique is etched using a moisture-resistant etchant The material is laid on the surface of the germanium semiconductor substrate by screen printing or roller printing, and after curing, the masked area is shielded from the mask by the wet etchant, and the wet etchant is only unmasked. The germanium region is etched to produce a plurality of trenches; the printed material is a paste containing cerium oxide, a high molecular polymer or other dielectric material, or a paste containing a metal or a metal compound. 如申請專利範圍第1項所述之溝槽蝕刻技術，係以濕蝕刻方式對表面含有表面粗化結構與N型層之P型矽半導體基板進行蝕刻，而產生複數條溝槽。 The trench etching technique according to claim 1, wherein the P-type germanium semiconductor substrate having the surface roughened structure and the N-type layer is etched by wet etching to form a plurality of trenches. 如申請專利範圍第1項所述之溝槽蝕刻技術，係以濕蝕刻方式對表面含有表面粗化結構、N型層與鈍化層之P型矽半導體基板進行蝕刻，而產生複數條溝槽。 The trench etching technique according to claim 1, wherein the P-type germanium semiconductor substrate having the surface roughened structure, the N-type layer and the passivation layer is etched by wet etching to form a plurality of trenches. 如申請專利範圍第1項所述之溝槽蝕刻技術，係以濕蝕刻方式對表面含有表面粗化結構、N型層與抗反射層之P型矽半導體基板進行蝕刻，而產生複數條溝槽。 The trench etching technique according to claim 1, wherein the P-type germanium semiconductor substrate having the surface roughened structure, the N-type layer and the anti-reflective layer is etched by wet etching to generate a plurality of trenches. . 如申請專利範圍第1項所述之溝槽蝕刻技術，係以濕蝕刻方式對表面含有表面粗化結構、N型層、鈍化層與抗反射層之P型矽半導體基板進行蝕刻，而產生複數條溝槽。 The trench etching technique according to claim 1, wherein the P-type germanium semiconductor substrate having a surface roughened structure, an N-type layer, a passivation layer, and an anti-reflection layer is etched by wet etching to generate a plurality of Strip groove. 如申請專利範圍第1項所述之溝槽蝕刻技術，係以濕蝕刻方式對表面含有表面粗化結構與P型層之N型矽半導體基板進行蝕刻，而產生複 數條溝槽。 The trench etching technique according to claim 1, wherein the N-type germanium semiconductor substrate having a surface roughened structure and a P-type layer is etched by wet etching to generate a complex Several grooves. 如申請專利範圍第1項所述之溝槽蝕刻技術，係以濕蝕刻方式對表面含有表面粗化結構、P型層與鈍化層之N型矽半導體基板進行蝕刻，而產生複數條溝槽。 The trench etching technique according to claim 1, wherein the N-type germanium semiconductor substrate having a surface roughened structure, a P-type layer and a passivation layer is etched by wet etching to form a plurality of trenches. 如申請專利範圍第1項所述之溝槽蝕刻技術，係以濕蝕刻方式對表面含有表面粗化結構、P型層與抗反射層之N型矽半導體基板進行蝕刻，而產生複數條溝槽。 The trench etching technique according to claim 1, wherein the N-type germanium semiconductor substrate having a surface roughening structure, a P-type layer and an anti-reflection layer is etched by wet etching to generate a plurality of trenches. . 如申請專利範圍第1項所述之溝槽蝕刻技術，係以濕蝕刻方式對表面含有表面粗化結構、P型層、鈍化層與抗反射層之N型矽半導體基板進行蝕刻，而產生複數條溝槽。 The trench etching technique according to claim 1, wherein the N-type germanium semiconductor substrate having a surface roughening structure, a P-type layer, a passivation layer and an anti-reflection layer is etched by wet etching to generate a plurality of Strip groove. 一種毋須使用曝光、顯影等黃光製程以及雷射或機械雕刻而在矽半導體基板表面以乾蝕刻方式蝕刻出複數條溝槽之技術；該技術係使用可耐乾蝕刻劑蝕刻之材料，以網版或滾筒印刷方式鋪設於該矽半導體基板表面上，經固化後作為遮罩使受遮罩阻擋之矽區域不受乾蝕刻劑侵蝕，且乾蝕刻劑僅對未受遮罩之矽區域進行蝕刻，而產生複數條溝槽；該印刷材料係一種含二氧化矽、高分子聚合物或其他介電質材料之膏狀物，亦可以是含金屬或金屬化合物之膏狀物。 A technique for etching a plurality of trenches by dry etching on a surface of a germanium semiconductor substrate without using a yellow light process such as exposure, development, or laser or mechanical engraving; the technique uses a material resistant to dry etchant etching to screen Or roller printing is applied on the surface of the germanium semiconductor substrate, and after curing, the mask region is blocked by the dry etchant, and the dry etchant only etches the unmasked germanium region. A plurality of grooves are formed; the printing material is a paste containing cerium oxide, a high molecular polymer or other dielectric material, or a paste containing a metal or a metal compound. 如申請專利範圍第10項所述之溝槽蝕刻技術，係以乾蝕刻方式對表面含有表面粗化結構與N型層之P型矽半導體基板進行蝕刻，而產生複數條溝槽。 The trench etching technique according to claim 10, wherein the P-type germanium semiconductor substrate having the surface roughened structure and the N-type layer is etched by dry etching to form a plurality of trenches. 如申請專利範圍第10項所述之溝槽蝕刻技術，係以乾蝕刻方式對表面含有表面粗化結構、N型層與鈍化層之P型矽半導體基板進行蝕刻， 而產生複數條溝槽。 The trench etching technique according to claim 10, wherein the P-type germanium semiconductor substrate having a surface roughened structure, an N-type layer and a passivation layer is etched by dry etching. And a plurality of grooves are generated. 如申請專利範圍第10項所述之溝槽蝕刻技術，係以乾蝕刻方式對表面含有表面粗化結構、N型層與抗反射層之P型矽半導體基板進行蝕刻，而產生複數條溝槽。 The trench etching technique according to claim 10, wherein the P-type germanium semiconductor substrate having a surface roughening structure, an N-type layer and an anti-reflection layer is etched by dry etching to generate a plurality of trenches. . 如申請專利範圍第10項所述之溝槽蝕刻技術，係以乾蝕刻方式對表面含有表面粗化結構、N型層、鈍化層與抗反射層之P型矽半導體基板進行蝕刻，而產生複數條溝槽。 The trench etching technique according to claim 10, wherein the P-type germanium semiconductor substrate having a surface roughened structure, an N-type layer, a passivation layer and an anti-reflection layer is etched by dry etching to generate a plurality of Strip groove. 如申請專利範圍第10項所述之溝槽蝕刻技術，係以乾蝕刻方式對表面含有表面粗化結構與P型層之N型矽半導體基板進行蝕刻，而產生複數條溝槽。 The trench etching technique according to claim 10, wherein the N-type germanium semiconductor substrate having the surface roughened structure and the P-type layer is etched by dry etching to form a plurality of trenches. 如申請專利範圍第10項所述之溝槽蝕刻技術，係以乾蝕刻方式對表面含有表面粗化結構、P型層與鈍化層之N型矽半導體基板進行蝕刻，而產生複數條溝槽。 The trench etching technique according to claim 10, wherein the N-type germanium semiconductor substrate having the surface roughened structure, the P-type layer and the passivation layer is etched by dry etching to form a plurality of trenches. 如申請專利範圍第10項所述之溝槽蝕刻技術，係以乾蝕刻方式對表面含有表面粗化結構、P型層與抗反射層之N型矽半導體基板進行蝕刻，而產生複數條溝槽。 The trench etching technique according to claim 10, wherein the N-type germanium semiconductor substrate having a surface roughening structure, a P-type layer and an anti-reflection layer is etched by dry etching to generate a plurality of trenches. . 如申請專利範圍第10項所述之溝槽蝕刻技術，係以乾蝕刻方式對表面含有表面粗化結構、P型層、鈍化層與抗反射層之N型矽半導體基板進行蝕刻，而產生複數條溝槽。 The trench etching technique according to claim 10, wherein the N-type germanium semiconductor substrate having a surface roughening structure, a P-type layer, a passivation layer and an anti-reflection layer is etched by dry etching to generate a plurality of Strip groove. 一種毋須使用曝光、顯影等黃光製程以及雷射或機械雕刻，而在矽半導體基板表面，以濕蝕刻方式或乾蝕刻方式蝕刻出複數條溝槽之技術；該技術的特徵係首先使用網版或滾筒印刷方式將第一種膏狀材料 鋪設於該基板表面上，形成具有圖樣(pattern)之暫時遮罩，使該半導體基板表面之一部分受該膏狀材料覆蓋，且另一部分不受該膏狀物質覆蓋。該遮罩固化後，使用第二種材料以化學氣相沉積、蒸鍍、濺鍍、印刷或濕式化學製程鋪設於前述具有暫時遮罩之半導體基板表面上，之後將前述暫時遮罩清洗除去，而僅留下第二種材料，形成與暫時遮罩圖樣有互補型樣之新遮罩，接著，以濕蝕刻方式或乾蝕刻方式蝕刻，受新遮罩阻擋之矽區域不受乾、濕蝕刻劑侵蝕，而未覆蓋遮罩之矽區域則受蝕刻劑所蝕刻並產生溝槽。 A technique for etching a plurality of grooves by wet etching or dry etching on a surface of a germanium semiconductor substrate without using a yellow light process such as exposure, development, or laser or mechanical engraving; Or roller printing method will be the first paste material Laying on the surface of the substrate forms a temporary mask having a pattern such that one portion of the surface of the semiconductor substrate is partially covered by the paste material and the other portion is not covered by the paste material. After the mask is cured, the second material is deposited on the surface of the semiconductor substrate having the temporary mask by chemical vapor deposition, evaporation, sputtering, printing or wet chemical process, and then the temporary mask is removed by cleaning. And leaving only the second material, forming a new mask with a complementary pattern to the temporary mask pattern, and then etching by wet etching or dry etching, the area blocked by the new mask is not dry or wet The etchant erodes, while the unmasked area of the mask is etched by the etchant and creates trenches. 如申請專利範圍第19項所述之溝槽蝕刻技術，係對表面含有表面粗化結構與N型層之P型矽半導體基板進行蝕刻，而產生複數條溝槽。 The trench etching technique according to claim 19, wherein the P-type germanium semiconductor substrate having a surface roughened structure and an N-type layer is etched to form a plurality of trenches. 如申請專利範圍第19項所述之溝槽蝕刻技術，係對表面含有表面粗化結構、N型層與鈍化層之P型矽半導體基板進行蝕刻，而產生複數條溝槽。 The trench etching technique according to claim 19, wherein the P-type germanium semiconductor substrate having a surface roughened structure, an N-type layer and a passivation layer is etched to form a plurality of trenches. 如申請專利範圍第19項所述之溝槽蝕刻技術，係對表面含有表面粗化結構、N型層與抗反射層之P型矽半導體基板進行蝕刻，而產生複數條溝槽。 The trench etching technique according to claim 19, wherein the P-type germanium semiconductor substrate having a surface roughened structure, an N-type layer and an anti-reflective layer is etched to form a plurality of trenches. 如申請專利範圍第19項所述之溝槽蝕刻技術，係對表面含有表面粗化結構、N型層、鈍化層與抗反射層之P型矽半導體基板進行蝕刻，而產生複數條溝槽。 The trench etching technique according to claim 19, wherein the P-type germanium semiconductor substrate having a surface roughened structure, an N-type layer, a passivation layer, and an anti-reflection layer is etched to form a plurality of trenches. 如申請專利範圍第19項所述之溝槽蝕刻技術，係對表面含有表面粗化結構與P型層之N型矽半導體基板進行蝕刻，而產生複數條溝槽。 The trench etching technique according to claim 19, wherein the N-type germanium semiconductor substrate having a surface roughened structure and a P-type layer is etched to form a plurality of trenches. 如申請專利範圍第19項所述之溝槽蝕刻技術，係對表面含有表面粗 化結構、P型層與鈍化層之N型矽半導體基板進行蝕刻，而產生複數條溝槽。 The groove etching technique described in claim 19, the surface of the pair is rough. The N-type germanium semiconductor substrate of the chemical structure, the P-type layer and the passivation layer is etched to generate a plurality of trenches. 如申請專利範圍第19項所述之溝槽蝕刻技術，係對表面含有表面粗化結構、P型層與抗反射層之N型矽半導體基板進行蝕刻，而產生複數條溝槽。 The trench etching technique according to claim 19, wherein the N-type germanium semiconductor substrate having a surface roughened structure, a p-type layer and an anti-reflective layer is etched to form a plurality of trenches. 如申請專利範圍第19項所述之溝槽蝕刻技術，係對表面含有表面粗化結構、P型層、鈍化層與抗反射層之N型矽半導體基板進行蝕刻，而產生複數條溝槽。 The trench etching technique according to claim 19, wherein the N-type germanium semiconductor substrate having a surface roughened structure, a P-type layer, a passivation layer and an anti-reflection layer is etched to form a plurality of trenches. 一種矽基板太陽能電池，其基板為P型半導體，背光側包含背表面場層(BSF layer)與背電極，照光側則包含表面粗化結構、第一N型層、抗反射層、複數條溝槽與位於溝槽中的電極；該複數條溝槽係以第1項、第2項、第4項、第10項、第11項、第13項、第19項、第20項或第22項所述之溝槽蝕刻技術產生，且各溝槽中的電極於埋藏的部分之周邊具有第二N型層。 A germanium substrate solar cell, wherein the substrate is a P-type semiconductor, the backlight side comprises a back surface field layer (BSF layer) and a back electrode, and the illumination side comprises a surface roughening structure, a first N-type layer, an anti-reflection layer, and a plurality of trenches. a groove and an electrode located in the groove; the plurality of grooves are the first item, the second item, the fourth item, the tenth item, the eleventh item, the thirteenth item, the 19th item, the twenty item item, the twenty-second item or the twenty-second item The trench etching technique described in the article is produced, and the electrodes in each trench have a second N-type layer at the periphery of the buried portion. 一種矽基板太陽能電池，其基板為P型半導體，背光側包含背表面場層與背電極，照光側則包含表面粗化結構、第一N型層、鈍化層、抗反射層、複數條溝槽與位於溝槽中的電極；該複數條溝槽係以第1項、第2項、第3項、第5項、第10項、第11項、第12項、第14項、第19項、第20項、第21項或第23項所述之溝槽蝕刻技術產生，且各溝槽中的電極於埋藏的部分之周邊具有第二N型層。 A germanium substrate solar cell, wherein the substrate is a P-type semiconductor, the backlight side comprises a back surface field layer and a back electrode, and the illumination side comprises a surface roughening structure, a first N-type layer, a passivation layer, an anti-reflection layer, and a plurality of trenches And the electrode located in the groove; the plurality of grooves are the first item, the second item, the third item, the fifth item, the tenth item, the eleventh item, the twelfth item, the fourteenth item, the fourteenth item, the 19th item The trench etching technique of claim 20, 21 or 23, wherein the electrodes in each trench have a second N-type layer at the periphery of the buried portion. 如申請專利範圍第28項所述之矽基板太陽能電池，其照光側另含有在非溝槽區以印刷金屬膏方式、化學氣相沉積、蒸鍍、濺鍍抑或濕式 化學製程所鋪設之電極。 The ruthenium substrate solar cell according to claim 28, wherein the illuminating side is further included in the non-trench region by printing metal paste, chemical vapor deposition, evaporation, sputtering or wet Electrodes laid by chemical processes. 如申請專利範圍第29項所述之矽基板太陽能電池，其照光側另含有在非溝槽區以印刷金屬膏方式、化學氣相沉積、蒸鍍、濺鍍抑或濕式化學製程所鋪設之電極。 The substrate solar cell according to claim 29, wherein the illuminating side further comprises an electrode disposed in a non-trench region by a printing metal paste method, a chemical vapor deposition, an evaporation, a sputtering or a wet chemical process. . 一種矽基板太陽能電池，其基板為N型半導體，背光側包含背表面場層與背電極，照光側則包含表面粗化結構、第一P型層、抗反射層、複數條溝槽與位於溝槽中的電極；該複數條溝槽係以第1項、第6項、第8項、第10項、第15項、第17項、第19項、第24項或第26項所述之溝槽蝕刻技術產生，且各溝槽中的電極於埋藏的部分之周邊具有第二P型層。 A silicon substrate solar cell, wherein the substrate is an N-type semiconductor, the backlight side comprises a back surface field layer and a back electrode, and the illumination side comprises a surface roughening structure, a first P-type layer, an anti-reflection layer, a plurality of trenches and a trench An electrode in the slot; the plurality of grooves are as described in item 1, item 6, item 8, item 10, item 17, item 19, item 24, or item 26. A trench etch technique is produced and the electrodes in each trench have a second p-type layer at the periphery of the buried portion. 一種矽基板太陽能電池，其基板為N型半導體，背光側包含背表面場層與背電極，照光側則包含表面粗化結構、第一P型層、鈍化層、抗反射層、複數條溝槽與位於溝槽中的電極；該複數條溝槽係以第1項、第6項、第7項、第9項、第10項、第15項、第16項、第18項、第19項、第24項、第25項或第27項所述之溝槽蝕刻技術產生，且各溝槽中的電極於埋藏的部分之周邊具有第二P型層。 A silicon substrate solar cell, wherein the substrate is an N-type semiconductor, the backlight side comprises a back surface field layer and a back electrode, and the illumination side comprises a surface roughening structure, a first P-type layer, a passivation layer, an anti-reflection layer, and a plurality of trenches And the electrode located in the groove; the plurality of grooves are item 1, item 6, item 7, item 9, item 10, item 16, item 16, item 18, item The trench etching technique described in item 24, item 25 or item 27, wherein the electrodes in each of the trenches have a second p-type layer at the periphery of the buried portion. 如申請專利範圍第32項所述之矽基板太陽能電池，其照光側另含有在非溝槽區以印刷金屬膏方式、化學氣相沉積、蒸鍍、濺鍍抑或濕式化學製程所鋪設之電極。 The substrate solar cell of claim 32, wherein the illuminating side further comprises an electrode disposed in a non-trench region by a printed metal paste, chemical vapor deposition, evaporation, sputtering or wet chemical process. . 如申請專利範圍第33項所述之矽基板太陽能電池，其照光側另含有在非溝槽區以印刷金屬膏方式、化學氣相沉積、蒸鍍、濺鍍抑或濕式化學製程所鋪設之電極。The ruthenium substrate solar cell according to claim 33, wherein the illuminating side further comprises an electrode which is laid in a non-trench region by a printing metal paste method, a chemical vapor deposition, an evaporation, a sputtering or a wet chemical process. .
TW098131013A 2009-09-14 2009-09-14 A printing method for making barrier in buried-contact solar cell fabrication and its resultant device TWI438907B (en)

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TW098131013A TWI438907B (en) 2009-09-14 2009-09-14 A printing method for making barrier in buried-contact solar cell fabrication and its resultant device

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TWI455342B (en) * 2011-08-30 2014-10-01 Nat Univ Tsing Hua Solar cell with selective emitter structure and manufacturing method thereof
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TWI504006B (en) * 2013-07-09 2015-10-11 Neo Solar Power Corp Crystalline solar cell having doped sic layer and manufacturing method thereof
CN113013063A (en) * 2021-02-23 2021-06-22 绍兴同芯成集成电路有限公司 Front processing method of compound semiconductor wafer based on silicon-based carrier plate

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